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| author | Paul Burton <paul.burton@imgtec.com> | 2016-05-27 14:28:05 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-05-31 09:44:24 +0200 |
| commit | 372286217f050bfd57695001d59f618c52822f40 (patch) | |
| tree | e2d926d936e6d65f2a229b19a347435f9f1d8d56 /arch/mips/include | |
| parent | ace3be4f15875d74344336b9754c14274f940969 (diff) | |
| download | u-boot-imx-372286217f050bfd57695001d59f618c52822f40.zip u-boot-imx-372286217f050bfd57695001d59f618c52822f40.tar.gz u-boot-imx-372286217f050bfd57695001d59f618c52822f40.tar.bz2 | |
MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/include')
| -rw-r--r-- | arch/mips/include/asm/cache.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 806bd26..0cea581 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -12,4 +12,11 @@ #define ARCH_DMA_MINALIGN (L1_CACHE_BYTES) +/* + * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for + * DMA buffer alignment. Satisfy those drivers by providing it as a synonym + * of ARCH_DMA_MINALIGN for now. + */ +#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN + #endif /* __MIPS_CACHE_H__ */ |