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| author | Paul Burton <paul.burton@imgtec.com> | 2013-11-08 11:18:50 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2013-11-09 17:21:01 +0100 |
| commit | baf37f06c5cc51d2b9d71a2c83d5d92de60203a9 (patch) | |
| tree | 7ad3945d47de4c1b5a7a1594b45f3b623a46df8c /arch/mips/include/asm/malta.h | |
| parent | a257f6263b51321ecacc69ac1effbcbe2158fe15 (diff) | |
| download | u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.zip u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.tar.gz u-boot-imx-baf37f06c5cc51d2b9d71a2c83d5d92de60203a9.tar.bz2 | |
malta: support for coreFPGA6 boards
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/malta.h')
| -rw-r--r-- | arch/mips/include/asm/malta.h | 35 |
1 files changed, 29 insertions, 6 deletions
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d4d44a2..0b50a66 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -9,15 +9,38 @@ #ifndef _MIPS_ASM_MALTA_H #define _MIPS_ASM_MALTA_H -#define MALTA_IO_PORT_BASE 0x18000000 +#define MALTA_GT_BASE 0x1be00000 +#define MALTA_GT_PCIIO_BASE 0x18000000 +#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) -#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_MSC01_BIU_BASE 0x1bc80000 +#define MALTA_MSC01_PCI_BASE 0x1bd00000 +#define MALTA_MSC01_PBC_BASE 0x1bd40000 +#define MALTA_MSC01_IP1_BASE 0x1bc00000 +#define MALTA_MSC01_IP1_SIZE 0x00400000 +#define MALTA_MSC01_IP2_BASE1 0x10000000 +#define MALTA_MSC01_IP2_SIZE1 0x08000000 +#define MALTA_MSC01_IP2_BASE2 0x18000000 +#define MALTA_MSC01_IP2_SIZE2 0x04000000 +#define MALTA_MSC01_IP3_BASE 0x1c000000 +#define MALTA_MSC01_IP3_SIZE 0x04000000 +#define MALTA_MSC01_PCIMEM_BASE 0x10000000 +#define MALTA_MSC01_PCIMEM_SIZE 0x10000000 +#define MALTA_MSC01_PCIMEM_MAP 0x10000000 +#define MALTA_MSC01_PCIIO_BASE 0x1b000000 +#define MALTA_MSC01_PCIIO_SIZE 0x00800000 +#define MALTA_MSC01_PCIIO_MAP 0x00000000 +#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) -#define MALTA_GT_BASE 0x1be00000 +#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 -#define MALTA_RESET_BASE 0x1f000500 -#define GORESET 0x42 +#define MALTA_FLASH_BASE 0x1fc00000 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_REVISION 0x1fc00010 +#define MALTA_REVISION_CORID_SHF 10 +#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) +#define MALTA_REVISION_CORID_CORE_LV 1 +#define MALTA_REVISION_CORID_CORE_FPGA6 14 #endif /* _MIPS_ASM_MALTA_H */ |