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authorZhi-zhou Zhang <etou.zh@gmail.com>2012-10-16 15:02:08 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2012-10-16 15:02:08 +0200
commitcb0a6a1ecc8dfe4dbdad6f9376ef78879337b118 (patch)
tree6398daa7ee7188509950120a9377bfa91e9c478c /arch/mips/cpu
parentbd23b22badadcdc414a900828253961fc5ec6c39 (diff)
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MIPS: don't use camel-case style
Replace camel-case style with upper-case style globally. Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
Diffstat (limited to 'arch/mips/cpu')
-rw-r--r--arch/mips/cpu/mips32/cache.S10
-rw-r--r--arch/mips/cpu/mips32/cpu.c8
-rw-r--r--arch/mips/cpu/xburst/cpu.c12
-rw-r--r--arch/mips/cpu/xburst/start.S4
4 files changed, 17 insertions, 17 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..64dfad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_op Fill t0
+2: cache_op FILL t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b..50bb248 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
__asm__ __volatile__("sync");
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104..3a8280c 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
- cache Index_Writeback_Inv_D, 0(t0)
+ cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
@@ -106,7 +106,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
- cache Index_Invalidate_I, 0(t0)
+ cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE