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authorGabor Juhos <juhosg@openwrt.org>2013-02-12 22:22:13 +0100
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2013-02-12 22:22:13 +0100
commit04380c651a2ff0d1495822321d2b7668dcd02537 (patch)
treefd763e5b4f62d349cbcfde50e5e24292f9a1a18f /arch/mips/cpu
parent0ba8926e08bdabba681384ba3ea8476eda68c141 (diff)
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MIPS: add dynamic relocation support
The code handles relocation entries with the following relocation types only: mips32: R_MIPS_REL32 mips64: R_MIPS_REL+R_MIPS_64 xburst: R_MIPS_REL32 Other relocation entries are skipped without processing. The code must be extended if other relocation types must be supported. Add -pie to LDFLAGS_FINAL to generate the .rel.dyn fixup table, which will be applied to the relocated image before transferring control to it. The CONFIG_NEEDS_MANUAL_RELOC is not needed after the patch, so remove that as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/cpu')
-rw-r--r--arch/mips/cpu/mips32/start.S28
-rw-r--r--arch/mips/cpu/mips64/start.S36
-rw-r--r--arch/mips/cpu/xburst/start.S28
3 files changed, 92 insertions, 0 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
index 649c0bb..76abbaa 100644
--- a/arch/mips/cpu/mips32/start.S
+++ b/arch/mips/cpu/mips32/start.S
@@ -201,6 +201,8 @@ relocate_code:
jr t0
nop
+ .word __rel_dyn_end
+ .word __rel_dyn_start
.word __image_copy_end
.word _GLOBAL_OFFSET_TABLE_
.word num_got_entries
@@ -227,6 +229,32 @@ in_ram:
blt t2, t3, 1b
addi t4, 4
+ /* Update dynamic relocations */
+ lw t1, -16(t0) # t1 <-- __rel_dyn_start
+ lw t2, -20(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ addi t1, 8
+
+1:
+ lw t3, -4(t1) # t3 <-- relocation info
+
+ sub t3, 3
+ bnez t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ lw t3, -8(t1) # t3 <-- location to fix up in FLASH
+
+ lw t4, 0(t3) # t4 <-- original pointer
+ add t4, s1 # t4 <-- adjusted pointer
+
+ add t3, s1 # t3 <-- location to fix up in RAM
+ sw t4, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ addi t1, 8 # each rel.dyn entry is 8 bytes
+
/*
* Clear BSS
*
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
index 5c2c7b5..dc7ce07 100644
--- a/arch/mips/cpu/mips64/start.S
+++ b/arch/mips/cpu/mips64/start.S
@@ -31,6 +31,14 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
+#else
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
@@ -193,6 +201,8 @@ relocate_code:
jr t0
nop
+ .dword __rel_dyn_end
+ .dword __rel_dyn_start
.dword __image_copy_end
.dword _GLOBAL_OFFSET_TABLE_
.dword num_got_entries
@@ -219,6 +229,32 @@ in_ram:
blt t2, t3, 1b
daddi t8, 8
+ /* Update dynamic relocations */
+ ld t1, -32(t0) # t1 <-- __rel_dyn_start
+ ld t2, -40(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ daddi t1, 16
+
+1:
+ lw t8, -4(t1) # t8 <-- relocation info
+
+ dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+ bne t8, t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ ld t3, -16(t1) # t3 <-- location to fix up in FLASH
+
+ ld t8, 0(t3) # t8 <-- original pointer
+ dadd t8, s1 # t8 <-- adjusted pointer
+
+ dadd t3, s1 # t3 <-- location to fix up in RAM
+ sd t8, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ daddi t1, 16 # each rel.dyn entry is 16 bytes
+
/*
* Clear BSS
*
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index 6b30d3e..d2c064b 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -116,6 +116,8 @@ relocate_code:
jr t0
nop
+ .word __rel_dyn_end
+ .word __rel_dyn_start
.word __image_copy_end
.word _GLOBAL_OFFSET_TABLE_
.word num_got_entries
@@ -142,6 +144,32 @@ in_ram:
blt t2, t3, 1b
addi t4, 4
+ /* Update dynamic relocations */
+ lw t1, -16(t0) # t1 <-- __rel_dyn_start
+ lw t2, -20(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ addi t1, 8
+
+1:
+ lw t3, -4(t1) # t3 <-- relocation info
+
+ sub t3, 3
+ bnez t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ lw t3, -8(t1) # t3 <-- location to fix up in FLASH
+
+ lw t4, 0(t3) # t4 <-- original pointer
+ add t4, t6 # t4 <-- adjusted pointer
+
+ add t3, t6 # t3 <-- location to fix up in RAM
+ sw t4, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ addi t1, 8 # each rel.dyn entry is 8 bytes
+
/*
* Clear BSS
*