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authorDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>2012-04-02 02:57:55 +0000
committerMarek Vasut <marex@denx.de>2012-04-02 15:54:53 +0200
commit979cfeaf36bf8719d4a1a98f1e8a3e16ef3d1fba (patch)
tree2de67c3bedf4eaf71e6c4ea2449e4f8deab4a5bb /arch/mips/cpu
parent71919cf15337c62b9ab389875a6a0855f0ed4461 (diff)
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MIPS: fix inconsistency in config option for cache operation mode
Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch/mips/cpu')
-rw-r--r--arch/mips/cpu/mips32/cache.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 5ce0ec4..e683e8b 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -30,6 +30,10 @@
#include <asm/addrspace.h>
#include <asm/cacheops.h>
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
#define RA t8
/*
@@ -224,7 +228,7 @@ LEAF(dcache_enable)
mfc0 t0, CP0_CONFIG
ori t0, CONF_CM_CMASK
xori t0, CONF_CM_CMASK
- ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ ori t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
jr ra
END(dcache_enable)