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author | Xiangfu Liu <xiangfu@openmobilefree.net> | 2011-10-12 12:24:06 +0800 |
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committer | Shinya Kuribayashi <skuribay@pobox.com> | 2011-10-10 22:06:12 +0900 |
commit | 80421fcc3ed1843f62a4a463548a4f33cdde362f (patch) | |
tree | 0e17b489ca37e73be16fbc1f85fd8b8c63cb773b /arch/mips/cpu/xburst/jz_serial.c | |
parent | 0841ca90f22d73b0ea4642ef1ce33d879bb2f3ff (diff) | |
download | u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.zip u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.tar.gz u-boot-imx-80421fcc3ed1843f62a4a463548a4f33cdde362f.tar.bz2 |
MIPS: Ingenic XBurst Jz4740 processor support
Jz4740 is a multimedia application processor targeting for mobile
devices like e-Dictionary, eBook, portable media player (PMP) and
GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
(JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
provides high integration, high performance and low power consumption.
JzRISC incorporated in Jz4740 is the advanced and power-efficient
32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
D-Cache, and can operate at speeds up to 400 MHz.
On-chip modules such as LCD controller, embedded audio codec, multi-
channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
suite of peripherals for multimedia application. NAND controller
(SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
also available.
For more info about Ingenic XBurst Jz4740:
http://en.ingenic.cn/eng/
http://www.linux-mips.org/wiki/Ingenic
This patch introduces XBurst CPU support in U-Boot. It's compatible
with MIPS32, but requires a bit different cache maintenance, timer
routines, and boot mechanism using USB boot tool, so XBurst support
can go into a separate new home, cpu/xburst/.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips/cpu/xburst/jz_serial.c')
-rw-r--r-- | arch/mips/cpu/xburst/jz_serial.c | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c new file mode 100644 index 0000000..e6c48e0 --- /dev/null +++ b/arch/mips/cpu/xburst/jz_serial.c @@ -0,0 +1,114 @@ +/* + * Jz4740 UART support + * Copyright (c) 2011 + * Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/jz4740.h> + +/* + * serial_init - initialize a channel + * + * This routine initializes the number of data bits, parity + * and set the selected baud rate. Interrupts are disabled. + * Set the modem control signals if the option is selected. + * + * RETURNS: N/A + */ +struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE; + +int serial_init(void) +{ + /* Disable port interrupts while changing hardware */ + writeb(0, &uart->dlhr_ier); + + /* Disable UART unit function */ + writeb(~UART_FCR_UUE, &uart->iir_fcr); + + /* Set both receiver and transmitter in UART mode (not SIR) */ + writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr); + + /* + * Set databits, stopbits and parity. + * (8-bit data, 1 stopbit, no parity) + */ + writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr); + + /* Set baud rate */ + serial_setbrg(); + + /* Enable UART unit, enable and clear FIFO */ + writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS, + &uart->iir_fcr); + + return 0; +} + +void serial_setbrg(void) +{ + u32 baud_div, tmp; + + baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE; + + tmp = readb(&uart->lcr); + tmp |= UART_LCR_DLAB; + writeb(tmp, &uart->lcr); + + writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier); + writeb(baud_div & 0xff, &uart->rbr_thr_dllr); + + tmp &= ~UART_LCR_DLAB; + writeb(tmp, &uart->lcr); +} + +int serial_tstc(void) +{ + if (readb(&uart->lsr) & UART_LSR_DR) + return 1; + + return 0; +} + +void serial_putc(const char c) +{ + if (c == '\n') + serial_putc('\r'); + + /* Wait for fifo to shift out some bytes */ + while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60)) + ; + + writeb((u8)c, &uart->rbr_thr_dllr); +} + +int serial_getc(void) +{ + while (!serial_tstc()) + ; + + return readb(&uart->rbr_thr_dllr); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} |