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author | Stefano Babic <sbabic@denx.de> | 2015-02-13 11:17:01 +0100 |
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committer | Stefano Babic <sbabic@denx.de> | 2015-02-13 11:17:01 +0100 |
commit | e72d344386bf80738fab7a6bd37cb321f443093a (patch) | |
tree | d3e02055e6aa903ab80ef87c78d2f38e93981dcf /arch/mips/cpu/mips64/cpu.c | |
parent | 258c98f8d36ef35d7cb7604847ba73e64d702c2a (diff) | |
parent | bd2a4888b123713adec271d6c8040ca9f609aa2f (diff) | |
download | u-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.zip u-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.tar.gz u-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/mips/cpu/mips64/cpu.c')
-rw-r--r-- | arch/mips/cpu/mips64/cpu.c | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c deleted file mode 100644 index 9f45cfc..0000000 --- a/arch/mips/cpu/mips64/cpu.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <netdev.h> -#include <asm/mipsregs.h> -#include <asm/cacheops.h> -#include <asm/reboot.h> - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - " .set push\n" \ - " .set noreorder\n" \ - " .set mips64\n" \ - " cache %0, %1\n" \ - " .set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ - fprintf(stderr, "*** reset failed ***\n"); - - while (1) - /* NOP */; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - return 0; -} - -void flush_cache(ulong start_addr, ulong size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - /* aend will be miscalculated when size is zero, so we return here */ - if (size == 0) - return; - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - cache_op(HIT_INVALIDATE_I, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void flush_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_WRITEBACK_INV_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void invalidate_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - while (1) { - cache_op(HIT_INVALIDATE_D, addr); - if (addr == aend) - break; - addr += lsize; - } -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} |