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| author | Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> | 2011-07-27 13:22:38 +0200 |
|---|---|---|
| committer | Shinya Kuribayashi <skuribay@pobox.com> | 2011-07-31 23:26:41 +0900 |
| commit | ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 (patch) | |
| tree | f6d237d468eec036180a987fa99a8f58aa907e89 /arch/mips/cpu/mips32 | |
| parent | 7185adb48ef1e5b0f05263a7f791de340ddddeb2 (diff) | |
| download | u-boot-imx-ab2a98b11716364bc5a8c43cdfa7fee176cda1d8.zip u-boot-imx-ab2a98b11716364bc5a8c43cdfa7fee176cda1d8.tar.gz u-boot-imx-ab2a98b11716364bc5a8c43cdfa7fee176cda1d8.tar.bz2 | |
MIPS: make cache operation mode configurable
Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.
This patch makes the cache operation mode configurable via board config.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Diffstat (limited to 'arch/mips/cpu/mips32')
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index e829b02..9c1b2f7 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -27,6 +27,10 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -249,7 +253,7 @@ reset: nop /* ... and enable them */ - li t0, CONF_CM_CACHABLE_NONCOHERENT + li t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG #endif |