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| author | Gabor Juhos <juhosg@openwrt.org> | 2013-06-12 18:02:46 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-24 09:51:05 -0400 |
| commit | da84f33b046fe99c5fbb6f7d8f8b03c7333b260d (patch) | |
| tree | cae25d170f59261651ca5ff9f2b6aeb2501f94d2 /arch/mips/cpu/mips32/cache.S | |
| parent | b1a14c471cb4ea633746e7249e468a86a69f2495 (diff) | |
| download | u-boot-imx-da84f33b046fe99c5fbb6f7d8f8b03c7333b260d.zip u-boot-imx-da84f33b046fe99c5fbb6f7d8f8b03c7333b260d.tar.gz u-boot-imx-da84f33b046fe99c5fbb6f7d8f8b03c7333b260d.tar.bz2 | |
MIPS: mips32/cache.S: remove superfluous register assignment
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.
Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Diffstat (limited to 'arch/mips/cpu/mips32/cache.S')
| -rw-r--r-- | arch/mips/cpu/mips32/cache.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 117fc56..40bb46e 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -129,7 +129,6 @@ NESTED(mips_cache_reset, 0, ra) li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 li v0, MIPS_MAX_CACHE_SIZE @@ -164,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t5 + move a2, t4 PTR_LA t7, mips_init_dcache jalr t7 |