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| author | Ye.Li <B37916@freescale.com> | 2014-08-13 16:44:48 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-08-15 11:07:18 +0800 |
| commit | 01996acd7788c831fc06872c59af99f3bd6f6b03 (patch) | |
| tree | c27452e185444a6d34cd5563c9b06398c335a0a8 /arch/mips/config.mk | |
| parent | c3e9e81a4c6ae7306c273cbe4b5d96ef44222711 (diff) | |
| download | u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.zip u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.tar.gz u-boot-imx-01996acd7788c831fc06872c59af99f3bd6f6b03.tar.bz2 | |
ENGR00326994 iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before reset
u-boot v2014 upstream codes have a problem in pfd reset (s_init function)
that imx6 Dual is not applied for PLL2 PFD2 reset. It is originated by
using dynamical cpu type checking and introducing two cpu types:
MXC_CPU_MX6Q and MXC_CPU_MX6D for iMX6 Dual/Quad platform.
Fixed this problem by checking the pre_periph_clk_sel and pre_periph2_clk
of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock
source, do not reset this PFD to avoid system hang.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/mips/config.mk')
0 files changed, 0 insertions, 0 deletions