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| author | Andre Przywara <andre.przywara@linaro.org> | 2013-09-19 18:06:40 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-10-03 21:27:11 +0200 |
| commit | 45b940d6f9a9d4989452ea67480e299bfa51ee19 (patch) | |
| tree | 636e0c5d2d8b7bfce8b7927e56044e0b95862806 /arch/microblaze | |
| parent | d75ba503a972df09784f1a332ba356ef8b42a0a6 (diff) | |
| download | u-boot-imx-45b940d6f9a9d4989452ea67480e299bfa51ee19.zip u-boot-imx-45b940d6f9a9d4989452ea67480e299bfa51ee19.tar.gz u-boot-imx-45b940d6f9a9d4989452ea67480e299bfa51ee19.tar.bz2 | |
ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Diffstat (limited to 'arch/microblaze')
0 files changed, 0 insertions, 0 deletions