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author | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
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committer | Stefano Babic <sbabic@denx.de> | 2012-11-10 08:05:54 +0100 |
commit | 3e4d27b06d7484040355e22eec2cbce7335d6dab (patch) | |
tree | 9672a2bb2e4ce0edc0ab776ddf0e2ca8e39a5f62 /arch/microblaze | |
parent | bad05afe083eec0467220de21683443292c5012e (diff) | |
parent | 59852d03867108217fe88e3bfc3e1e9cedfe63c5 (diff) | |
download | u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.zip u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.gz u-boot-imx-3e4d27b06d7484040355e22eec2cbce7335d6dab.tar.bz2 |
Merge git://git.denx.de/u-boot
Diffstat (limited to 'arch/microblaze')
-rw-r--r-- | arch/microblaze/cpu/cache.c | 5 | ||||
-rw-r--r-- | arch/microblaze/cpu/start.S | 6 | ||||
-rw-r--r-- | arch/microblaze/cpu/u-boot.lds | 11 | ||||
-rw-r--r-- | arch/microblaze/include/asm/bitops.h | 3 | ||||
-rw-r--r-- | arch/microblaze/include/asm/byteorder.h | 23 | ||||
-rw-r--r-- | arch/microblaze/include/asm/global_data.h | 2 | ||||
-rw-r--r-- | arch/microblaze/include/asm/posix_types.h | 3 | ||||
-rw-r--r-- | arch/microblaze/include/asm/u-boot.h | 2 | ||||
-rw-r--r-- | arch/microblaze/lib/bootm.c | 5 |
9 files changed, 15 insertions, 45 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d258a69..ce066b9 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -61,12 +61,7 @@ void dcache_enable (void) { void dcache_disable(void) { #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8564c4e..3da711d 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,6 +132,12 @@ _start: rsubi r8, r10, 0x26 sh r6, r0, r8 + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE +flush: bralid r15, flush_cache + nop + /* enable instruction and data cache */ mfs r12, rmsr ori r12, r12, 0xa0 diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index d033a28..fe3d97d 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -45,17 +45,16 @@ SECTIONS .data ALIGN(0x4): { __data_start = .; +#ifdef CONFIG_OF_EMBED dts/libdts.o (.data) +#endif *(.data) __data_end = .; } - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; + . = ALIGN(4); + .u_boot_list : { + #include <u-boot.lst> } .bss ALIGN(0x4): diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h index e8c835f..eafa2b5 100644 --- a/arch/microblaze/include/asm/bitops.h +++ b/arch/microblaze/include/asm/bitops.h @@ -319,7 +319,8 @@ extern __inline__ int ext2_test_bit(int nr, const volatile void * addr) #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) -extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +static inline unsigned long ext2_find_next_zero_bit(void *addr, + unsigned long size, unsigned long offset) { unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h index b2757a4..f3a471d 100644 --- a/arch/microblaze/include/asm/byteorder.h +++ b/arch/microblaze/include/asm/byteorder.h @@ -20,29 +20,6 @@ #ifdef __GNUC__ -/* This is effectively a dupe of the arch-independent byteswap - code in include/linux/byteorder/swab.h, however we force a cast - of the result up to 32 bits. This in turn forces the compiler - to explicitly clear the high 16 bits, which it wasn't doing otherwise. - - I think this is a symptom of a bug in mb-gcc. JW 20040303 -*/ - - -static __inline__ __u16 ___arch__swab16 (__u16 half_word) -{ - /* 32 bit temp to cast result, forcing clearing of high word */ - __u32 temp; - - temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8); - - return (__u16) temp; -} - -#define __arch__swab16(x) ___arch__swab16(x) - -/* Microblaze has no arch-specific endian conversion insns */ - #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index de3b8db..2111c7c 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -35,7 +35,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long have_console; /* serial_init() was called */ #ifdef CONFIG_PRE_CONSOLE_BUFFER unsigned long precon_buf_idx; /* Pre-Console buffer index */ diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h index 9a2cc66..38dc5aa 100644 --- a/arch/microblaze/include/asm/posix_types.h +++ b/arch/microblaze/include/asm/posix_types.h @@ -16,9 +16,6 @@ #ifndef __MICROBLAZE_POSIX_TYPES_H__ #define __MICROBLAZE_POSIX_TYPES_H__ -#include <asm/bitops.h> - - typedef unsigned int __kernel_dev_t; typedef unsigned long __kernel_ino_t; typedef unsigned long long __kernel_ino64_t; diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index a0b1dbf..8d00658 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -40,7 +40,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_baudrate; /* Console Baudrate */ + unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 95cee50..66d21f4 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima #endif #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif /* * Linux Kernel Parameters (passing device tree): |