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| author | Michal Simek <monstr@monstr.eu> | 2012-09-25 10:13:35 +0200 |
|---|---|---|
| committer | Michal Simek <monstr@monstr.eu> | 2012-11-07 17:11:14 +0100 |
| commit | 5811830fae92cf0a3bb11ead54ef1267464a1280 (patch) | |
| tree | ecacfea7eef3f6792a56af11a74ae5bbb3bc5efb /arch/microblaze/cpu | |
| parent | ea0122816c6467c7ede80744363624c41822c93f (diff) | |
| download | u-boot-imx-5811830fae92cf0a3bb11ead54ef1267464a1280.zip u-boot-imx-5811830fae92cf0a3bb11ead54ef1267464a1280.tar.gz u-boot-imx-5811830fae92cf0a3bb11ead54ef1267464a1280.tar.bz2 | |
microblaze: Flush caches before enabling them
Flushing caches is necessary because of soft reset
which doesn't clear caches.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Reviewed-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/microblaze/cpu')
| -rw-r--r-- | arch/microblaze/cpu/cache.c | 5 | ||||
| -rw-r--r-- | arch/microblaze/cpu/start.S | 6 |
2 files changed, 6 insertions, 5 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d258a69..ce066b9 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -61,12 +61,7 @@ void dcache_enable (void) { void dcache_disable(void) { #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8564c4e..3da711d 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,6 +132,12 @@ _start: rsubi r8, r10, 0x26 sh r6, r0, r8 + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE +flush: bralid r15, flush_cache + nop + /* enable instruction and data cache */ mfs r12, rmsr ori r12, r12, 0xa0 |