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| author | Michal Simek <michal.simek@xilinx.com> | 2014-01-21 07:30:37 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-02-04 16:39:50 +0100 |
| commit | 9d24274509cdd463992dc1fb1a2820d6a4b6d21d (patch) | |
| tree | aa599f1c017ae0a597daf3394e8a45ed3192396d /arch/microblaze/cpu/u-boot-spl.lds | |
| parent | 22ff7f4d195b49ca7db5b2a0c3aa2c987ab88c34 (diff) | |
| download | u-boot-imx-9d24274509cdd463992dc1fb1a2820d6a4b6d21d.zip u-boot-imx-9d24274509cdd463992dc1fb1a2820d6a4b6d21d.tar.gz u-boot-imx-9d24274509cdd463992dc1fb1a2820d6a4b6d21d.tar.bz2 | |
microblaze: Add SPL support
Add support for U-BOOT SPL. NOR and RAM mode are supported.
There are 3 images in NOR flash. u-boot.img, dtb and kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze/cpu/u-boot-spl.lds')
| -rw-r--r-- | arch/microblaze/cpu/u-boot-spl.lds | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/microblaze/cpu/u-boot-spl.lds b/arch/microblaze/cpu/u-boot-spl.lds new file mode 100644 index 0000000..96353cd --- /dev/null +++ b/arch/microblaze/cpu/u-boot-spl.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2013 - 2014 Xilinx, Inc + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm-offsets.h> + +OUTPUT_ARCH(microblaze) +ENTRY(_start) + +SECTIONS +{ + .text ALIGN(0x4): + { + __text_start = .; + arch/microblaze/cpu/start.o (.text) + *(.text) + *(.text.*) + __text_end = .; + } + + .rodata ALIGN(0x4): + { + __rodata_start = .; + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + __rodata_end = .; + } + + .data ALIGN(0x4): + { + __data_start = .; + *(.data) + *(.data.*) + __data_end = .; + } + + .bss ALIGN(0x4): + { + __bss_start = .; + *(.sbss) + *(.scommon) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + } + __end = . ; +} + +#if defined(CONFIG_SPL_MAX_FOOTPRINT) +ASSERT(__end - _start < (CONFIG_SPL_MAX_FOOTPRINT), \ + "SPL image plus BSS too big"); +#endif |