x86: Rename i386 to x86

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

7 files changed, 0 insertions, 1081 deletions

diff --git a/arch/i386/cpu/sc520/Makefile b/arch/i386/cpu/sc520/Makefile
deleted file mode 100644
index 54260b6..0000000
--- a/arch/i386/cpu/sc520/Makefile
+++ /dev/null
@@ -1,57 +0,0 @@
-#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	:= $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_SYS_SC520) += sc520.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
-COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
-COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
-COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-
-SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
-
-SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
\ No newline at end of file
diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c
deleted file mode 100644
index edc1a5c..0000000
--- a/arch/i386/cpu/sc520/sc520.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
-
-int cpu_init_f(void)
-{
-	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		/* set it to 133 MHz and write back */
-		writeb(0x02, &sc520_mmcr->cpuctl);
-		gd->cpu_clk = 133000000;
-	} else {
-		/* set it to 100 MHz and write back */
-		writeb(0x01, &sc520_mmcr->cpuctl);
-		gd->cpu_clk = 100000000;
-	}
-
-	/* wait at least one millisecond */
-	asm("movl	$0x2000, %%ecx\n"
-	    "0:		pushl %%ecx\n"
-	    "popl	%%ecx\n"
-	    "loop 0b\n": : : "ecx");
-
-	return x86_cpu_init_f();
-}
-
-int cpu_init_r(void)
-{
-	/* Disable the PAR used for CAR */
-	writel(0x0000000, &sc520_mmcr->par[2]);
-
-	/* turn on the SDRAM write buffer */
-	writeb(0x11, &sc520_mmcr->dbctl);
-
-	return x86_cpu_init_r();
-}
-
-#ifdef CONFIG_SYS_SC520_RESET
-void reset_cpu(ulong addr)
-{
-	printf("Resetting using SC520 MMCR\n");
-	/* Write a '1' to the SYS_RST of the RESCFG MMCR */
-	writeb(0x01, &sc520_mmcr->rescfg);
-
-	/* NOTREACHED */
-}
-#endif
diff --git a/arch/i386/cpu/sc520/sc520_car.S b/arch/i386/cpu/sc520/sc520_car.S
deleted file mode 100644
index a33f94f..0000000
--- a/arch/i386/cpu/sc520/sc520_car.S
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
-
-.section .text
-
-.globl car_init
-car_init:
-	/*
-	 * How to enable Cache-As-RAM for the AMD Elan SC520:
-	 *  1. Turn off the CPU Cache (may not be strictly required)
-	 *  2. Set code execution PAR (usually the BOOTCS region) to be
-	 *     non-cachable
-	 *  3. Create a Cachable PAR Region for an area of memory which is
-	 *       a) NOT where the code is being executed
-	 *       b) NOT SDRAM (Controller not initialised yet)
-	 *       c) WILL response to read requests
-	 *     The easiest way to do this is to create a second BOOTCS
-	 *     PAR mappnig with an address != the PAR in step 2
-	 *  4. Issue a wbinvd to invalidate the CPU cache
-	 *  5. Turn on the CPU Cache
-	 *  6. Read 16kB from the cached PAR region setup in step 3
-	 *  7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
-	 *
-	 * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
-	 * are avoided as these are the only two PARs which can be used
-	 * as PCI BUS Memory regions which the board might require)
-	 *
-	 * The configuration of PAR2 must be set in the board configuration
-	 * file as CONFIG_SYS_SC520_CAR_PAR
-	 */
-
-	/* Configure Cache-As-RAM PAR */
-	movl	$CONFIG_SYS_SC520_CAR_PAR, %eax
-	movl	$SC520_PAR2, %edi
-	movl	%eax, (%edi)
-
-	/* Trash the cache then turn it on */
-	wbinvd
-	movl	%cr0, %eax
-	andl	$~(X86_CR0_NW | X86_CR0_CD), %eax
-	movl	%eax, %cr0
-
-	/*
-	 * The cache is now enabled and empty. Map a region of memory to
-	 * it by reading that region.
-	 */
-	movl	$CONFIG_SYS_CAR_ADDR, %esi
-	movl	$CONFIG_SYS_CAR_SIZE, %ecx
-	shrl	$2, %ecx			/* we are reading longs */
-	cld
-	rep	lodsl
-
-	/* Turn off the cache, but don't trash it */
-	movl	%cr0, %eax
-	orl	$(X86_CR0_NW | X86_CR0_CD), %eax
-	movl	%eax, %cr0
-
-	/* Clear the CAR region */
-	xorl	%eax, %eax
-	movl	$CONFIG_SYS_CAR_ADDR, %edi
-	movl	$CONFIG_SYS_CAR_SIZE, %ecx
-	shrl	$2, %ecx			/* we are writing longs */
-	rep	stosl
-
-	/*
-	 * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
-	 * Cache-As-RAM
-	 */
-	jmp	car_init_ret
diff --git a/arch/i386/cpu/sc520/sc520_pci.c b/arch/i386/cpu/sc520/sc520_pci.c
deleted file mode 100644
index 8cd7ffe..0000000
--- a/arch/i386/cpu/sc520/sc520_pci.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/ic/pci.h>
-#include <asm/ic/sc520.h>
-
-static struct {
-	u8 priority;
-	u16 level_reg;
-	u8 level_bit;
-} sc520_irq[] = {
-	{ SC520_IRQ0,  0, 0x01 },
-	{ SC520_IRQ1,  0, 0x02 },
-	{ SC520_IRQ2,  1, 0x02 },
-	{ SC520_IRQ3,  0, 0x08 },
-	{ SC520_IRQ4,  0, 0x10 },
-	{ SC520_IRQ5,  0, 0x20 },
-	{ SC520_IRQ6,  0, 0x40 },
-	{ SC520_IRQ7,  0, 0x80 },
-
-	{ SC520_IRQ8,  1, 0x01 },
-	{ SC520_IRQ9,  1, 0x02 },
-	{ SC520_IRQ10, 1, 0x04 },
-	{ SC520_IRQ11, 1, 0x08 },
-	{ SC520_IRQ12, 1, 0x10 },
-	{ SC520_IRQ13, 1, 0x20 },
-	{ SC520_IRQ14, 1, 0x40 },
-	{ SC520_IRQ15, 1, 0x80 }
-};
-
-/* The interrupt used for PCI INTA-INTD  */
-int sc520_pci_ints[15] = {
-	-1, -1, -1, -1, -1, -1, -1, -1,
-		-1, -1, -1, -1, -1, -1, -1
-};
-
-/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
-{
-	int i;
-	u8 tmpb;
-	u16 tmpw;
-
-	debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-
-	if (irq < 0 || irq > 15) {
-		return -1; /* illegal irq */
-	}
-
-	if (pci_pin < 0 || pci_pin > 15) {
-		return -1; /* illegal pci int pin */
-	}
-
-	/* first disable any non-pci interrupt source that use
-	 * this level */
-
-	/* PCI interrupt mapping (A through D)*/
-	for (i=0; i<=3 ;i++) {
-		if (readb(&sc520_mmcr->pci_int_map[i]) == sc520_irq[irq].priority)
-			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
-	}
-
-	/* GP IRQ interrupt mapping */
-	for (i=0; i<=10 ;i++) {
-		if (readb(&sc520_mmcr->gp_int_map[i]) == sc520_irq[irq].priority)
-			writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
-	}
-
-	/* Set the trigger to level */
-	tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
-	tmpb |= sc520_irq[irq].level_bit;
-	writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
-
-
-	if (pci_pin < 4) {
-		/* PCI INTA-INTD */
-		/* route the interrupt */
-		writeb(sc520_irq[irq].priority, &sc520_mmcr->pci_int_map[pci_pin]);
-	} else {
-		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
-		writeb(sc520_irq[irq].priority, &sc520_mmcr->gp_int_map[pci_pin - 4]);
-
-		/* also set the polarity in this case */
-		tmpw = readw(&sc520_mmcr->intpinpol);
-		tmpw |= (1 << (pci_pin-4));
-		writew(tmpw, &sc520_mmcr->intpinpol);
-	}
-
-	/* register the pin */
-	sc520_pci_ints[pci_pin] = irq;
-
-
-	return 0; /* OK */
-}
-
-void pci_sc520_init(struct pci_controller *hose)
-{
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->region_count = pci_set_regions(hose);
-
-	pci_setup_type1(hose,
-			SC520_REG_ADDR,
-			SC520_REG_DATA);
-
-	pci_register_hose(hose);
-
-	hose->last_busno = pci_hose_scan(hose);
-
-	/* enable target memory acceses on host brige */
-	pci_write_config_word(0, PCI_COMMAND,
-			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
diff --git a/arch/i386/cpu/sc520/sc520_sdram.c b/arch/i386/cpu/sc520/sc520_sdram.c
deleted file mode 100644
index f3623f5..0000000
--- a/arch/i386/cpu/sc520/sc520_sdram.c
+++ /dev/null
@@ -1,532 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/ic/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct sc520_sdram_info {
-	u8 banks;
-	u8 columns;
-	u8 rows;
-	u8 size;
-};
-
-static void sc520_sizemem(void);
-static void sc520_set_dram_timing(void);
-static void sc520_set_dram_refresh_rate(void);
-static void sc520_enable_dram_refresh(void);
-static void sc520_enable_sdram(void);
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-#endif
-
-int dram_init_f(void)
-{
-	sc520_sizemem();
-	sc520_set_dram_timing();
-	sc520_set_dram_refresh_rate();
-	sc520_enable_dram_refresh();
-	sc520_enable_sdram();
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-	sc520_enable_ecc();
-#endif
-
-	return 0;
-}
-
-static inline void sc520_dummy_write(void)
-{
-	writew(0x0000, CACHELINESZ);
-}
-static inline void sc520_issue_sdram_op_mode_select(u8 command)
-{
-	writeb(command, &sc520_mmcr->drcctl);
-	sc520_dummy_write();
-}
-
-static inline int check_long(u32 test_long)
-{
-	u8 i;
-	u8 tmp_byte = (u8)(test_long & 0x000000ff);
-
-	for (i = 1; i < 4; i++) {
-		if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
-				return -1;
-	}
-
-	return 0;
-}
-
-static inline int write_and_test(u32 data, u32 address)
-{
-	writel(data, address);
-	if (readl(address) == data)
-		return 0; /* Good */
-	else
-		return -1; /* Bad */
-}
-
-static void sc520_enable_sdram(void)
-{
-	u32 par_config;
-
-	/* Enable Writes, Caching and Code Execution to SDRAM */
-	par_config = readl(&sc520_mmcr->par[3]);
-	par_config &= ~(SC520_PAR_EXEC_DIS |
-			SC520_PAR_CACHE_DIS |
-			SC520_PAR_WRITE_DIS);
-	writel(par_config, &sc520_mmcr->par[3]);
-
-	par_config = readl(&sc520_mmcr->par[4]);
-	par_config &= ~(SC520_PAR_EXEC_DIS |
-			SC520_PAR_CACHE_DIS |
-			SC520_PAR_WRITE_DIS);
-	writel(par_config, &sc520_mmcr->par[4]);
-}
-
-static void sc520_set_dram_timing(void)
-{
-	u8 drctmctl = 0x00;
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
-	/* just have your hardware designer _GIVE_ you what you need here! */
-	drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
-#else
-	switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
-	case 2:
-		break;
-	case 3:
-		drctmctl |= 0x01;
-		break;
-	case 4:
-	default:
-		drctmctl |= 0x02;
-		break;
-	}
-
-	switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
-	case 2:
-		break;
-	case 3:
-		drctmctl |= 0x04;
-		break;
-	case 4:
-	default:
-		drctmctl |= 0x08;
-		break;
-
-	case 6:
-		drctmctl |= 0x0c;
-		break;
-	}
-
-	switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
-	case 2:
-		break;
-	case 3:
-	default:
-		drctmctl |= 0x10;
-		break;
-	}
-#endif
-	writeb(drctmctl, &sc520_mmcr->drctmctl);
-
-	/* Issue load mode register command */
-	sc520_issue_sdram_op_mode_select(0x03);
-}
-
-static void sc520_set_dram_refresh_rate(void)
-{
-	u8 drctl;
-
-	drctl = readb(&sc520_mmcr->drcctl);
-	drctl &= 0xcf;
-
-	switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
-	case 78:
-		break;
-	case 156:
-	default:
-		drctl |= 0x10;
-		break;
-	case 312:
-		drctl |= 0x20;
-		break;
-	case 624:
-		drctl |= 0x30;
-		break;
-	}
-
-	writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_enable_dram_refresh(void)
-{
-	u8 drctl;
-
-	drctl = readb(&sc520_mmcr->drcctl);
-	drctl &= 0x30; /* keep refresh rate */
-	drctl |= 0x08; /* enable refresh, normal mode */
-
-	writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
-{
-	u32 col_data;
-	u32 row_data;
-
-	u32 drcbendadr;
-	u16 drccfg;
-
-	u8 banks = 0x00;
-	u8 columns = 0x00;
-	u8 rows = 0x00;
-
-	bank_info->banks = 0x00;
-	bank_info->columns = 0x00;
-	bank_info->rows = 0x00;
-	bank_info->size = 0x00;
-
-	if ((bank < 0) || (bank > 3)) {
-		printf("Bad Bank ID\n");
-		return;
-	}
-
-	/* Save configuration */
-	drcbendadr = readl(&sc520_mmcr->drcbendadr);
-	drccfg = readw(&sc520_mmcr->drccfg);
-
-	/* Setup SDRAM Bank to largest possible size */
-	writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
-
-	/* Set ending address for this bank */
-	writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
-
-	/* write col 11 wrap adr */
-	if (write_and_test(COL11_DATA, COL11_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 10 wrap adr */
-	if (write_and_test(COL10_DATA, COL10_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 9 wrap adr */
-	if (write_and_test(COL09_DATA, COL09_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write col 8 wrap adr */
-	if (write_and_test(COL08_DATA, COL08_ADR) != 0)
-		goto restore_and_exit;
-
-	col_data = readl(COL11_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(col_data) < 0)
-		goto restore_and_exit;
-
-	if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
-		columns = (u8)(col_data & 0x000000ff);
-	else
-		goto restore_and_exit;
-
-	/* write row 14 wrap adr */
-	if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 13 wrap adr */
-	if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 12 wrap adr */
-	if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
-		goto restore_and_exit;
-
-	/* write row 11 wrap adr */
-	if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
-		goto restore_and_exit;
-
-	if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
-		goto restore_and_exit;
-
-	/*
-	 * read data @ row 12 wrap adr to determine number of banks,
-	 * and read data @ row 14 wrap adr to determine number of rows.
-	 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
-	 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
-	 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
-	 */
-	row_data = readl(ROW12_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(row_data) != 0)
-		goto restore_and_exit;
-
-	switch (row_data) {
-	case ROW10_DATA:
-		banks = 2;
-		break;
-
-	case ROW11_DATA:
-	case ROW12_DATA:
-		banks = 4;
-		break;
-
-	default:
-		goto restore_and_exit;
-	}
-
-	row_data = readl(ROW14_ADR);
-
-	/* All four bytes in the read long must be the same */
-	if (check_long(row_data) != 0)
-		goto restore_and_exit;
-
-	switch (row_data) {
-	case ROW11_DATA:
-	case ROW12_DATA:
-	case ROW13_DATA:
-	case ROW14_DATA:
-		rows = (u8)(row_data & 0x000000ff);
-		break;
-
-	default:
-		goto restore_and_exit;
-	}
-
-	bank_info->banks = banks;
-	bank_info->columns = columns;
-	bank_info->rows = rows;
-
-	if ((bank_info->banks != 0) &&
-	    (bank_info->columns != 0) &&
-	    (bank_info->rows != 0)) {
-		bank_info->size = bank_info->rows;
-		bank_info->size >>= (11 - bank_info->columns);
-		bank_info->size++;
-	}
-
-restore_and_exit:
-	/* Restore configuration */
-	writel(drcbendadr, &sc520_mmcr->drcbendadr);
-	writew(drccfg, &sc520_mmcr->drccfg);
-}
-
-static void sc520_setup_sizemem(void)
-{
-	u8 i;
-
-	/* Disable write buffer */
-	writeb(0x00, &sc520_mmcr->dbctl);
-
-	/* Disable ECC */
-	writeb(0x00, &sc520_mmcr->eccctl);
-
-	/* Set slowest SDRAM timing */
-	writeb(0x1e, &sc520_mmcr->drctmctl);
-
-	/* Issue a NOP to all SDRAM banks */
-	sc520_issue_sdram_op_mode_select(0x01);
-
-	/* Delay for 100 microseconds */
-	udelay(100);
-
-	/* Issue 'All Banks Precharge' command */
-	sc520_issue_sdram_op_mode_select(0x02);
-
-	/* Issue 2 'Auto Refresh Enable' command */
-	sc520_issue_sdram_op_mode_select(0x04);
-	sc520_dummy_write();
-
-	/* Issue 'Load Mode Register' command */
-	sc520_issue_sdram_op_mode_select(0x03);
-
-	/* Issue 8 more 'Auto Refresh Enable' commands */
-	sc520_issue_sdram_op_mode_select(0x04);
-	for (i = 0; i < 7; i++)
-		sc520_dummy_write();
-
-	/* Set control register to 'Normal Mode' */
-	writeb(0x00, &sc520_mmcr->drcctl);
-}
-
-static void sc520_sizemem(void)
-{
-	struct sc520_sdram_info sdram_info[4];
-	u8 bank_config = 0x00;
-	u8 end_addr = 0x00;
-	u16 drccfg = 0x0000;
-	u32 drcbendadr = 0x00000000;
-	u8 i;
-
-	/* Use PARs to disable caching of maximum allowable 256MB SDRAM */
-	writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
-	writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
-
-	sc520_setup_sizemem();
-
-	gd->ram_size = 0;
-
-	/* Size each SDRAM bank */
-	for (i = 0; i <= 3; i++) {
-		sc520_get_bank_info(i, &sdram_info[i]);
-
-		if (sdram_info[i].banks != 0) {
-			/* Update Configuration register */
-			bank_config = sdram_info[i].columns - 8;
-
-			if (sdram_info[i].banks == 4)
-				bank_config |= 0x08;
-
-			drccfg |= bank_config << (i * 4);
-
-			/* Update End Address register */
-			end_addr += sdram_info[i].size;
-			drcbendadr |= (end_addr | 0x80) << (i * 8);
-
-			gd->ram_size += sdram_info[i].size << 22;
-		}
-
-		/* Issue 'All Banks Precharge' command */
-		sc520_issue_sdram_op_mode_select(0x02);
-
-		/* Set control register to 'Normal Mode' */
-		writeb(0x00, &sc520_mmcr->drcctl);
-	}
-
-	writel(drcbendadr, &sc520_mmcr->drcbendadr);
-	writew(drccfg, &sc520_mmcr->drccfg);
-
-	/* Clear PARs preventing caching of SDRAM */
-	writel(0x00000000, &sc520_mmcr->par[3]);
-	writel(0x00000000, &sc520_mmcr->par[4]);
-}
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-static void sc520_enable_ecc(void)
-
-	/* A nominal memory test: just a byte at each address line */
-	movl	%eax, %ecx
-	shrl	$0x1, %ecx
-	movl	$0x1, %edi
-memtest0:
-	movb	$0xa5, (%edi)
-	cmpb	$0xa5, (%edi)
-	jne	out
-	shrl	$0x1, %ecx
-	andl	%ecx, %ecx
-	jz	set_ecc
-	shll	$0x1, %edi
-	jmp	memtest0
-
-set_ecc:
-	/* clear all ram with a memset */
-	movl	%eax, %ecx
-	xorl	%esi, %esi
-	xorl	%edi, %edi
-	xorl	%eax, %eax
-	shrl	$0x2, %ecx
-	cld
-	rep	stosl
-
-	/* enable read, write buffers */
-	movb	$0x11, %al
-	movl	$DBCTL, %edi
-	movb	%al, (%edi)
-
-	/* enable NMI mapping for ECC */
-	movl	$ECCINT, %edi
-	movb	$0x10, %al
-	movb	%al, (%edi)
-
-	/* Turn on ECC */
-	movl	$ECCCTL, %edi
-	movb	$0x05, %al
-	movb	%al,(%edi)
-
-out:
-	jmp	init_ecc_ret
-}
-#endif
-
-int dram_init(void)
-{
-	ulong dram_ctrl;
-	ulong dram_present = 0x00000000;
-
-	/*
-	 * We read-back the configuration of the dram
-	 * controller that the assembly code wrote
-	 */
-	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
-	gd->bd->bi_dram[0].start = 0;
-	if (dram_ctrl & 0x80) {
-		/* bank 0 enabled */
-		gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
-		dram_present = gd->bd->bi_dram[1].start;
-		gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
-	} else {
-		gd->bd->bi_dram[0].size = 0;
-		gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
-	}
-
-	if (dram_ctrl & 0x8000) {
-		/* bank 1 enabled */
-		gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
-		dram_present = gd->bd->bi_dram[2].start;
-		gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
-				gd->bd->bi_dram[1].start;
-	} else {
-		gd->bd->bi_dram[1].size = 0;
-		gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
-	}
-
-	if (dram_ctrl & 0x800000) {
-		/* bank 2 enabled */
-		gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
-		dram_present = gd->bd->bi_dram[3].start;
-		gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
-				gd->bd->bi_dram[2].start;
-	} else {
-		gd->bd->bi_dram[2].size = 0;
-		gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
-	}
-
-	if (dram_ctrl & 0x80000000) {
-		/* bank 3 enabled */
-		dram_present  = (dram_ctrl & 0x7f000000) >> 2;
-		gd->bd->bi_dram[3].size = dram_present -
-				gd->bd->bi_dram[3].start;
-	} else {
-		gd->bd->bi_dram[3].size = 0;
-	}
-
-	gd->ram_size = dram_present;
-
-	return 0;
-}
diff --git a/arch/i386/cpu/sc520/sc520_ssi.c b/arch/i386/cpu/sc520/sc520_ssi.c
deleted file mode 100644
index ac58d25..0000000
--- a/arch/i386/cpu/sc520/sc520_ssi.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/ic/ssi.h>
-#include <asm/ic/sc520.h>
-
-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
-{
-	u8 temp=0;
-
-	if (freq >= 8192) {
-		temp |= CTL_CLK_SEL_4;
-	} else if (freq >= 4096) {
-		temp |= CTL_CLK_SEL_8;
-	} else if (freq >= 2048) {
-		temp |= CTL_CLK_SEL_16;
-	} else if (freq >= 1024) {
-		temp |= CTL_CLK_SEL_32;
-	} else if (freq >= 512) {
-		temp |= CTL_CLK_SEL_64;
-	} else if (freq >= 256) {
-		temp |= CTL_CLK_SEL_128;
-	} else if (freq >= 128) {
-		temp |= CTL_CLK_SEL_256;
-	} else {
-		temp |= CTL_CLK_SEL_512;
-	}
-
-	if (!lsb_first) {
-		temp |= MSBF_ENB;
-	}
-
-	if (inv_clock) {
-		temp |= CLK_INV_ENB;
-	}
-
-	if (inv_phase) {
-		temp |= PHS_INV_ENB;
-	}
-
-	writeb(temp, &sc520_mmcr->ssictl);
-
-	return 0;
-}
-
-u8 ssi_txrx_byte(u8 data)
-{
-	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
-	writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
-
-	return readb(&sc520_mmcr->ssircv);
-}
-
-void ssi_tx_byte(u8 data)
-{
-	writeb(data, &sc520_mmcr->ssixmit);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
-	writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
-}
-
-u8 ssi_rx_byte(void)
-{
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
-	writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
-	while (readb(&sc520_mmcr->ssista) & SSISTA_BSY);
-
-	return readb(&sc520_mmcr->ssircv);
-}
diff --git a/arch/i386/cpu/sc520/sc520_timer.c b/arch/i386/cpu/sc520/sc520_timer.c
deleted file mode 100644
index 1bcfe67..0000000
--- a/arch/i386/cpu/sc520/sc520_timer.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/interrupt.h>
-#include <asm/ic/sc520.h>
-
-void sc520_timer_isr(void)
-{
-	/* Ack the GP Timer Interrupt */
-	writeb(0x02, &sc520_mmcr->gptmrsta);
-}
-
-int timer_init(void)
-{
-	/* Register the SC520 specific timer interrupt handler */
-	register_timer_isr (sc520_timer_isr);
-
-	/* Install interrupt handler for GP Timer 1 */
-	irq_install_handler (0, timer_isr, NULL);
-
-	/* Map GP Timer 1 to Master PIC IR0  */
-	writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
-
-	/* Disable GP Timers 1 & 2 - Allow configuration writes */
-	writew(0x4000, &sc520_mmcr->gptmr1ctl);
-	writew(0x4000, &sc520_mmcr->gptmr2ctl);
-
-	/* Reset GP Timers 1 & 2 */
-	writew(0x0000, &sc520_mmcr->gptmr1cnt);
-	writew(0x0000, &sc520_mmcr->gptmr2cnt);
-
-	/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
-	writew(83, &sc520_mmcr->gptmr2maxcmpa);
-	writew(0xc001, &sc520_mmcr->gptmr2ctl);
-
-	/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
-	writew(100, &sc520_mmcr->gptmr1maxcmpa);
-	writew(0xe009, &sc520_mmcr->gptmr1ctl);
-
-	unmask_irq (0);
-
-	/* Clear the GP Timer 1 status register to get the show rolling*/
-	writeb(0x02, &sc520_mmcr->gptmrsta);
-
-	return 0;
-}
-
-/* Allow boards to override udelay implementation */
-void __udelay(unsigned long usec)
-	__attribute__((weak, alias("sc520_udelay")));
-
-void sc520_udelay(unsigned long usec)
-{
-	int m = 0;
-	long u;
-	long temp;
-
-	temp = readw(&sc520_mmcr->swtmrmilli);
-	temp = readw(&sc520_mmcr->swtmrmicro);
-
-	do {
-		m += readw(&sc520_mmcr->swtmrmilli);
-		u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
-	} while (u < usec);
-}