Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	cpu/arm1176/cpu.c
	cpu/arm1176/start.S
	cpu/arm_cortexa8/s5pc1xx/Makefile
	cpu/arm_cortexa8/s5pc1xx/clock.c
	drivers/serial/serial_s5p.c
	include/asm-arm/arch-s5pc1xx/clk.h
	include/asm-arm/arch-s5pc1xx/gpio.h
	include/asm-arm/arch-s5pc1xx/uart.h

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

179 files changed, 71022 insertions, 0 deletions

diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk
new file mode 100644
index 0000000..137834e
--- /dev/null
+++ b/arch/blackfin/config.mk
@@ -0,0 +1,72 @@
+#
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?= bfin-uclinux-
+
+STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
+
+CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
+CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
+CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
+CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE)))
+
+PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
+PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
+
+LDFLAGS += --gc-sections -m elf32bfin
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
+ifneq (,$(CONFIG_BFIN_CPU))
+PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
+endif
+
+ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+ALL += $(obj)u-boot.ldr
+endif
+ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
+CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o
+else
+CREATE_LDR_ENV =
+endif
+
+SYM_PREFIX = _
+
+LDR_FLAGS-y :=
+LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
+
+LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
+LDR_FLAGS += --use-vmas
+LDR_FLAGS += --initcode $(obj)$(CPUDIR)/initcode.o
+ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
+LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
+	--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):$(obj)env-ldr.o
+endif
+ifneq (,$(findstring s,$(MAKEFLAGS)))
+LDR_FLAGS += --quiet
+endif
+
+LDR_FLAGS += $(LDR_FLAGS-y)
+
+ifeq ($(wildcard $(TOPDIR)/board/$(BOARD)/u-boot.lds*),)
+LDSCRIPT = $(obj)arch/$(ARCH)/lib/u-boot.lds.S
+endif
diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore
new file mode 100644
index 0000000..0ec9d56
--- /dev/null
+++ b/arch/blackfin/cpu/.gitignore
@@ -0,0 +1 @@
+bootrom-asm-offsets.[chs]
diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
new file mode 100644
index 0000000..211b8d5
--- /dev/null
+++ b/arch/blackfin/cpu/Makefile
@@ -0,0 +1,73 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Licensed under the GPL-2 or later.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).a
+
+EXTRA    :=
+CEXTRA   := initcode.o
+SEXTRA   := start.o
+SOBJS    := interrupt.o cache.o
+COBJS-y  += cpu.o
+COBJS-y  += interrupts.o
+COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
+COBJS-y  += os_log.o
+COBJS-y  += reset.o
+COBJS-y  += serial.o
+COBJS-y  += traps.o
+COBJS-$(CONFIG_HW_WATCHDOG)  += watchdog.o
+
+ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+COBJS-y  += initcode.o
+endif
+
+SRCS     := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS     := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+EXTRA    := $(addprefix $(obj),$(EXTRA))
+CEXTRA   := $(addprefix $(obj),$(CEXTRA))
+SEXTRA   := $(addprefix $(obj),$(SEXTRA))
+
+all:	$(obj).depend $(LIB) $(obj).depend $(EXTRA) $(CEXTRA) $(SEXTRA) check_initcode
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+$(OBJS): $(obj)bootrom-asm-offsets.h
+$(obj)bootrom-asm-offsets.c: bootrom-asm-offsets.c.in bootrom-asm-offsets.awk
+	echo '#include <asm/mach-common/bits/bootrom.h>' | $(CPP) $(CPPFLAGS) - | gawk -f ./bootrom-asm-offsets.awk > $@.tmp
+	mv $@.tmp $@
+$(obj)bootrom-asm-offsets.s: $(obj)bootrom-asm-offsets.c
+	$(CC) $(CFLAGS) -S $^ -o $@.tmp
+	mv $@.tmp $@
+$(obj)bootrom-asm-offsets.h: $(obj)bootrom-asm-offsets.s
+	sed -ne "/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}" $^ > $@
+
+# make sure our initcode (which goes into LDR) does not
+# have relocs or external references
+$(obj)initcode.o: CFLAGS += -fno-function-sections -fno-data-sections
+READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
+check_initcode: $(obj)initcode.o
+ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
+	@if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
+		echo "$< contains external references!" 1>&2 ; \
+		exit 1 ; \
+	fi
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk
new file mode 100755
index 0000000..1d61824
--- /dev/null
+++ b/arch/blackfin/cpu/bootrom-asm-offsets.awk
@@ -0,0 +1,41 @@
+#!/usr/bin/gawk -f
+BEGIN {
+	print "/* DO NOT EDIT: AUTOMATICALLY GENERATED"
+	print " * Input files: bootrom-asm-offsets.awk bootrom-asm-offsets.c.in"
+	print " * DO NOT EDIT: AUTOMATICALLY GENERATED"
+	print " */"
+	print ""
+	system("cat bootrom-asm-offsets.c.in")
+	print "{"
+}
+
+{
+	/* find a structure definition */
+	if ($0 ~ /typedef struct .* {/) {
+		delete members;
+		i = 0;
+
+		/* extract each member of the structure */
+		while (1) {
+			getline
+			if ($1 == "}")
+				break;
+			gsub(/[*;]/, "");
+			members[i++] = $NF;
+		}
+
+		/* grab the structure's name */
+		struct = $NF;
+		sub(/;$/, "", struct);
+
+		/* output the DEFINE() macros */
+		while (i-- > 0)
+			print "\tDEFINE(" struct ", " members[i] ");"
+		print ""
+	}
+}
+
+END {
+	print "\treturn 0;"
+	print "}"
+}
diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.c.in b/arch/blackfin/cpu/bootrom-asm-offsets.c.in
new file mode 100644
index 0000000..3146e46
--- /dev/null
+++ b/arch/blackfin/cpu/bootrom-asm-offsets.c.in
@@ -0,0 +1,12 @@
+/* A little trick taken from the kernel asm-offsets.h where we convert
+ * the C structures automatically into a bunch of defines for use in
+ * the assembly files.
+ */
+
+#include <linux/stddef.h>
+#include <asm/mach-common/bits/bootrom.h>
+
+#define _DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+#define DEFINE(s, m) _DEFINE(offset_##s##_##m, offsetof(s, m))
+
+int main(int argc, char *argv[])
diff --git a/arch/blackfin/cpu/cache.S b/arch/blackfin/cpu/cache.S
new file mode 100644
index 0000000..6ed655a
--- /dev/null
+++ b/arch/blackfin/cpu/cache.S
@@ -0,0 +1,87 @@
+/*
+ * Blackfin cache control code
+ *
+ * Copyright 2003-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/linkage.h>
+#include <config.h>
+#include <asm/blackfin.h>
+
+.text
+/* Since all L1 caches work the same way, we use the same method for flushing
+ * them.  Only the actual flush instruction differs.  We write this in asm as
+ * GCC can be hard to coax into writing nice hardware loops.
+ *
+ * Also, we assume the following register setup:
+ * R0 = start address
+ * R1 = end address
+ */
+.macro do_flush flushins:req optflushins optnopins label
+
+	R2 = -L1_CACHE_BYTES;
+
+	/* start = (start & -L1_CACHE_BYTES) */
+	R0 = R0 & R2;
+
+	/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
+	R1 += -1;
+	R1 = R1 & R2;
+	R1 += L1_CACHE_BYTES;
+
+	/* count = (end - start) >> L1_CACHE_SHIFT */
+	R2 = R1 - R0;
+	R2 >>= L1_CACHE_SHIFT;
+	P1 = R2;
+
+.ifnb \label
+\label :
+.endif
+	P0 = R0;
+	LSETUP (1f, 2f) LC1 = P1;
+1:
+.ifnb \optflushins
+	\optflushins [P0];
+.endif
+#if ANOMALY_05000443
+.ifb \optnopins
+2:
+.endif
+	\flushins [P0++];
+.ifnb \optnopins
+2:	\optnopins;
+.endif
+#else
+2:	\flushins [P0++];
+#endif
+
+	RTS;
+.endm
+
+/* Invalidate all instruction cache lines assocoiated with this memory area */
+ENTRY(_blackfin_icache_flush_range)
+	do_flush IFLUSH, , nop
+ENDPROC(_blackfin_icache_flush_range)
+
+/* Flush all cache lines assocoiated with this area of memory. */
+ENTRY(_blackfin_icache_dcache_flush_range)
+	do_flush FLUSH, IFLUSH
+ENDPROC(_blackfin_icache_dcache_flush_range)
+
+/* Throw away all D-cached data in specified region without any obligation to
+ * write them back.  Since the Blackfin ISA does not have an "invalidate"
+ * instruction, we use flush/invalidate.  Perhaps as a speed optimization we
+ * could bang on the DTEST MMRs ...
+ */
+ENTRY(_blackfin_dcache_flush_invalidate_range)
+	do_flush FLUSHINV
+ENDPROC(_blackfin_dcache_flush_invalidate_range)
+
+/* Flush all data cache lines assocoiated with this memory area */
+ENTRY(_blackfin_dcache_flush_range)
+	do_flush FLUSH, , , .Ldfr
+ENDPROC(_blackfin_dcache_flush_range)
diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
new file mode 100644
index 0000000..2c8fd86
--- /dev/null
+++ b/arch/blackfin/cpu/cpu.c
@@ -0,0 +1,112 @@
+/*
+ * U-boot - cpu.c CPU specific functions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/trace.h>
+
+#include "cpu.h"
+#include "serial.h"
+
+ulong bfin_poweron_retx;
+
+__attribute__ ((__noreturn__))
+void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
+{
+#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
+	/* Build a NOP slide over the LDR jump block.  Whee! */
+	char nops[0xC];
+	serial_early_puts("NOP Slide\n");
+	memset(nops, 0x00, sizeof(nops));
+	memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
+#endif
+
+	if (!loaded_from_ldr) {
+		/* Relocate sections into L1 if the LDR didn't do it -- don't
+		 * check length because the linker script does the size
+		 * checking at build time.
+		 */
+		serial_early_puts("L1 Relocate\n");
+		extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
+		memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
+		extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
+		memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
+	}
+#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+	/* The BF537 bootrom will reset the EBIU_AMGCTL register on us
+	 * after it has finished loading the LDR.  So configure it again.
+	 */
+	else
+		bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+#endif
+
+	/* Save RETX so we can pass it while booting Linux */
+	bfin_poweron_retx = bootflag;
+
+#ifdef CONFIG_DEBUG_DUMP
+	/* Turn on hardware trace buffer */
+	bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
+#endif
+
+#ifndef CONFIG_PANIC_HANG
+	/* Reset upon a double exception rather than just hanging.
+	 * Do not do bfin_read on SWRST as that will reset status bits.
+	 */
+	bfin_write_SWRST(DOUBLE_FAULT);
+#endif
+
+	serial_early_puts("Board init flash\n");
+	board_init_f(bootflag);
+}
+
+int exception_init(void)
+{
+	bfin_write_EVT3(trap);
+	return 0;
+}
+
+int irq_init(void)
+{
+#ifdef SIC_IMASK0
+	bfin_write_SIC_IMASK0(0);
+	bfin_write_SIC_IMASK1(0);
+# ifdef SIC_IMASK2
+	bfin_write_SIC_IMASK2(0);
+# endif
+#elif defined(SICA_IMASK0)
+	bfin_write_SICA_IMASK0(0);
+	bfin_write_SICA_IMASK1(0);
+#else
+	bfin_write_SIC_IMASK(0);
+#endif
+	bfin_write_EVT2(evt_default);	/* NMI */
+	bfin_write_EVT5(evt_default);	/* hardware error */
+	bfin_write_EVT6(evt_default);	/* core timer */
+	bfin_write_EVT7(evt_default);
+	bfin_write_EVT8(evt_default);
+	bfin_write_EVT9(evt_default);
+	bfin_write_EVT10(evt_default);
+	bfin_write_EVT11(evt_default);
+	bfin_write_EVT12(evt_default);
+	bfin_write_EVT13(evt_default);
+	bfin_write_EVT14(evt_default);
+	bfin_write_EVT15(evt_default);
+	bfin_write_ILAT(0);
+	CSYNC();
+	/* enable hardware error irq */
+	irq_flags = 0x3f;
+	local_irq_enable();
+	return 0;
+}
diff --git a/arch/blackfin/cpu/cpu.h b/arch/blackfin/cpu/cpu.h
new file mode 100644
index 0000000..0a13c28
--- /dev/null
+++ b/arch/blackfin/cpu/cpu.h
@@ -0,0 +1,38 @@
+/*
+ *  U-boot - cpu.h
+ *
+ *  Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#include <command.h>
+
+void board_reset(void) __attribute__((__weak__));
+void bfin_reset_or_hang(void) __attribute__((__noreturn__));
+void bfin_panic(struct pt_regs *reg);
+void dump(struct pt_regs *regs);
+
+asmlinkage void trap(void);
+asmlinkage void evt_default(void);
+
+#endif
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c
new file mode 100644
index 0000000..5f80ad6
--- /dev/null
+++ b/arch/blackfin/cpu/initcode.c
@@ -0,0 +1,687 @@
+/*
+ * initcode.c - Initialize the processor.  This is usually entails things
+ * like external memory, voltage regulators, etc...  Note that this file
+ * cannot make any function calls as it may be executed all by itself by
+ * the Blackfin's bootrom in LDR format.
+ *
+ * Copyright (c) 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#define BFIN_IN_INITCODE
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
+
+#include "serial.h"
+
+__attribute__((always_inline))
+static inline void serial_init(void)
+{
+#ifdef __ADSPBF54x__
+# ifdef BFIN_BOOT_UART_USE_RTS
+#  define BFIN_UART_USE_RTS 1
+# else
+#  define BFIN_UART_USE_RTS 0
+# endif
+	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		size_t i;
+
+		/* force RTS rather than relying on auto RTS */
+		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
+
+		/* Wait for the line to clear up.  We cannot rely on UART
+		 * registers as none of them reflect the status of the RSR.
+		 * Instead, we'll sleep for ~10 bit times at 9600 baud.
+		 * We can precalc things here by assuming boot values for
+		 * PLL rather than loading registers and calculating.
+		 *	baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
+		 *	EDB0    = 0
+		 *	Divisor = (SCLK / baud) / 16
+		 *	SCLK    = baud * 16 * Divisor
+		 *	SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
+		 *	CCLK    = (16 * Divisor * 5) * (9600 / 10)
+		 * In reality, this will probably be just about 1 second delay,
+		 * so assuming 9600 baud is OK (both as a very low and too high
+		 * speed as this will buffer things enough).
+		 */
+#define _NUMBITS (10)                                   /* how many bits to delay */
+#define _LOWBAUD (9600)                                 /* low baud rate */
+#define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
+#define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
+#define _NUMINS  (3)                                    /* how many instructions in loop */
+#define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
+		i = _CCLK;
+		while (i--)
+			asm volatile("" : : : "memory");
+	}
+#endif
+
+	if (BFIN_DEBUG_EARLY_SERIAL) {
+		int ucen = bfin_read16(&pUART->gctl) & UCEN;
+		serial_early_init();
+
+		/* If the UART is off, that means we need to program
+		 * the baud rate ourselves initially.
+		 */
+		if (ucen != UCEN)
+			serial_early_set_baud(CONFIG_BAUDRATE);
+	}
+}
+
+__attribute__((always_inline))
+static inline void serial_deinit(void)
+{
+#ifdef __ADSPBF54x__
+	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		/* clear forced RTS rather than relying on auto RTS */
+		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
+	}
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_putc(char c)
+{
+	if (!BFIN_DEBUG_EARLY_SERIAL)
+		return;
+
+	if (c == '\n')
+		serial_putc('\r');
+
+	bfin_write16(&pUART->thr, c);
+
+	while (!(bfin_read16(&pUART->lsr) & TEMT))
+		continue;
+}
+
+
+/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
+ * us a freq of 16MHz for SPI which should generally be
+ * slow enough for the slow reads the bootrom uses.
+ */
+#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
+    ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
+     (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
+#else
+# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
+#endif
+#ifndef CONFIG_SPI_BAUD_INITBLOCK
+# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
+#endif
+#ifdef SPI0_BAUD
+# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
+#endif
+
+/* PLL_DIV defines */
+#ifndef CONFIG_PLL_DIV_VAL
+# if (CONFIG_CCLK_DIV == 1)
+#  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
+# elif (CONFIG_CCLK_DIV == 2)
+#  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
+# elif (CONFIG_CCLK_DIV == 4)
+#  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
+# elif (CONFIG_CCLK_DIV == 8)
+#  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
+# else
+#  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
+# endif
+# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
+#endif
+
+#ifndef CONFIG_PLL_LOCKCNT_VAL
+# define CONFIG_PLL_LOCKCNT_VAL 0x0300
+#endif
+
+#ifndef CONFIG_PLL_CTL_VAL
+# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
+#endif
+
+#ifndef CONFIG_EBIU_RSTCTL_VAL
+# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
+#endif
+#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
+# error invalid EBIU_RSTCTL value: must not set reserved bits
+#endif
+
+#ifndef CONFIG_EBIU_MBSCTL_VAL
+# define CONFIG_EBIU_MBSCTL_VAL 0
+#endif
+
+#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
+# error invalid EBIU_DDRQUE value: must not set reserved bits
+#endif
+
+/* Make sure our voltage value is sane so we don't blow up! */
+#ifndef CONFIG_VR_CTL_VAL
+# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
+# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
+#  define CCLK_VLEV_120	400000000
+#  define CCLK_VLEV_125	533000000
+# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+#  define CCLK_VLEV_120	401000000
+#  define CCLK_VLEV_125	401000000
+# elif defined(__ADSPBF561__)
+#  define CCLK_VLEV_120	300000000
+#  define CCLK_VLEV_125	501000000
+# endif
+# if BFIN_CCLK < CCLK_VLEV_120
+#  define CONFIG_VR_CTL_VLEV VLEV_120
+# elif BFIN_CCLK < CCLK_VLEV_125
+#  define CONFIG_VR_CTL_VLEV VLEV_125
+# else
+#  define CONFIG_VR_CTL_VLEV VLEV_130
+# endif
+# if defined(__ADSPBF52x__)	/* TBD; use default */
+#  undef CONFIG_VR_CTL_VLEV
+#  define CONFIG_VR_CTL_VLEV VLEV_110
+# elif defined(__ADSPBF54x__)	/* TBD; use default */
+#  undef CONFIG_VR_CTL_VLEV
+#  define CONFIG_VR_CTL_VLEV VLEV_120
+# elif defined(__ADSPBF538__) || defined(__ADSPBF539__)	/* TBD; use default */
+#  undef CONFIG_VR_CTL_VLEV
+#  define CONFIG_VR_CTL_VLEV VLEV_125
+# endif
+
+# ifdef CONFIG_BFIN_MAC
+#  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
+# else
+#  define CONFIG_VR_CTL_CLKBUF 0
+# endif
+
+# if defined(__ADSPBF52x__)
+#  define CONFIG_VR_CTL_FREQ FREQ_1000
+# else
+#  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
+# endif
+
+# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
+#endif
+
+/* some parts do not have an on-chip voltage regulator */
+#if defined(__ADSPBF51x__)
+# define CONFIG_HAS_VR 0
+# undef CONFIG_VR_CTL_VAL
+# define CONFIG_VR_CTL_VAL 0
+#else
+# define CONFIG_HAS_VR 1
+#endif
+
+#if CONFIG_MEM_SIZE
+#ifndef EBIU_RSTCTL
+/* Blackfin with SDRAM */
+#ifndef CONFIG_EBIU_SDBCTL_VAL
+# if CONFIG_MEM_SIZE == 16
+#  define CONFIG_EBSZ_VAL EBSZ_16
+# elif CONFIG_MEM_SIZE == 32
+#  define CONFIG_EBSZ_VAL EBSZ_32
+# elif CONFIG_MEM_SIZE == 64
+#  define CONFIG_EBSZ_VAL EBSZ_64
+# elif CONFIG_MEM_SIZE == 128
+#  define CONFIG_EBSZ_VAL EBSZ_128
+# elif CONFIG_MEM_SIZE == 256
+#  define CONFIG_EBSZ_VAL EBSZ_256
+# elif CONFIG_MEM_SIZE == 512
+#  define CONFIG_EBSZ_VAL EBSZ_512
+# else
+#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
+# endif
+# if CONFIG_MEM_ADD_WDTH == 8
+#  define CONFIG_EBCAW_VAL EBCAW_8
+# elif CONFIG_MEM_ADD_WDTH == 9
+#  define CONFIG_EBCAW_VAL EBCAW_9
+# elif CONFIG_MEM_ADD_WDTH == 10
+#  define CONFIG_EBCAW_VAL EBCAW_10
+# elif CONFIG_MEM_ADD_WDTH == 11
+#  define CONFIG_EBCAW_VAL EBCAW_11
+# else
+#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
+# endif
+# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
+#endif
+#endif
+#endif
+
+/* Conflicting Column Address Widths Causes SDRAM Errors:
+ * EB2CAW and EB3CAW must be the same
+ */
+#if ANOMALY_05000362
+# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
+#  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
+# endif
+#endif
+
+__attribute__((always_inline)) static inline void
+program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
+{
+	serial_putc('a');
+
+	/* Save the clock pieces that are used in baud rate calculation */
+	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		serial_putc('b');
+		*sdivB = bfin_read_PLL_DIV() & 0xf;
+		*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+		*divB = serial_early_get_div();
+		serial_putc('c');
+	}
+
+	serial_putc('d');
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
+#  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
+# endif
+	/* Program the watchdog with an initial timeout of ~20 seconds.
+	 * Hopefully that should be long enough to load the u-boot LDR
+	 * (from wherever) and then the common u-boot code can take over.
+	 * In bypass mode, the start.S would have already set a much lower
+	 * timeout, so don't clobber that.
+	 */
+	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
+		serial_putc('e');
+		bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
+		bfin_write_WDOG_CTL(0);
+		serial_putc('f');
+	}
+#endif
+
+	serial_putc('g');
+
+	/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
+	 * fast read, so we need to slow down the SPI clock a lot more during
+	 * boot.  Once we switch over to u-boot's SPI flash driver, we'll
+	 * increase the speed appropriately.
+	 */
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
+		serial_putc('h');
+		if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
+			bs->dFlags |= BFLAG_FASTREAD;
+		bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
+		serial_putc('i');
+	}
+
+	serial_putc('j');
+}
+
+__attribute__((always_inline)) static inline bool
+maybe_self_refresh(ADI_BOOT_DATA *bs)
+{
+	serial_putc('a');
+
+	if (!CONFIG_MEM_SIZE)
+		return false;
+
+	/* If external memory is enabled, put it into self refresh first. */
+#ifdef EBIU_RSTCTL
+	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
+		serial_putc('b');
+		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
+		return true;
+	}
+#else
+	if (bfin_read_EBIU_SDBCTL() & EBE) {
+		serial_putc('b');
+		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
+		return true;
+	}
+#endif
+
+	serial_putc('c');
+
+	return false;
+}
+
+__attribute__((always_inline)) static inline u16
+program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
+{
+	u16 vr_ctl;
+
+	serial_putc('a');
+
+	vr_ctl = bfin_read_VR_CTL();
+
+	serial_putc('b');
+
+	/* If we're entering self refresh, make sure it has happened. */
+	if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+		while (!(bfin_read_EBIU_RSTCTL() & SRACK))
+#else
+		while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
+#endif
+			continue;
+
+	serial_putc('c');
+
+	/* With newer bootroms, we use the helper function to set up
+	 * the memory controller.  Older bootroms lacks such helpers
+	 * so we do it ourselves.
+	 */
+	if (!ANOMALY_05000386) {
+		serial_putc('d');
+
+		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
+		ADI_SYSCTRL_VALUES memory_settings;
+		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;
+		if (CONFIG_HAS_VR) {
+			actions |= SYSCTRL_VRCTL;
+			if (CONFIG_VR_CTL_VAL & FREQ_MASK)
+				actions |= SYSCTRL_INTVOLTAGE;
+			else
+				actions |= SYSCTRL_EXTVOLTAGE;
+			memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
+		} else
+			actions |= SYSCTRL_EXTVOLTAGE;
+		memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
+		memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
+		memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
+#if ANOMALY_05000432
+		bfin_write_SIC_IWR1(0);
+#endif
+		serial_putc('e');
+		bfrom_SysControl(actions, &memory_settings, NULL);
+		serial_putc('f');
+#if ANOMALY_05000432
+		bfin_write_SIC_IWR1(-1);
+#endif
+#if ANOMALY_05000171
+		bfin_write_SICA_IWR0(-1);
+		bfin_write_SICA_IWR1(-1);
+#endif
+		serial_putc('g');
+	} else {
+		serial_putc('h');
+
+		/* Disable all peripheral wakeups except for the PLL event. */
+#ifdef SIC_IWR0
+		bfin_write_SIC_IWR0(1);
+		bfin_write_SIC_IWR1(0);
+# ifdef SIC_IWR2
+		bfin_write_SIC_IWR2(0);
+# endif
+#elif defined(SICA_IWR0)
+		bfin_write_SICA_IWR0(1);
+		bfin_write_SICA_IWR1(0);
+#else
+		bfin_write_SIC_IWR(1);
+#endif
+
+		serial_putc('i');
+
+		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
+		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
+
+		serial_putc('j');
+
+		/* Only reprogram when needed to avoid triggering unnecessary
+		 * PLL relock sequences.
+		 */
+		if (vr_ctl != CONFIG_VR_CTL_VAL) {
+			serial_putc('?');
+			bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
+			asm("idle;");
+			serial_putc('!');
+		}
+
+		serial_putc('k');
+
+		bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
+
+		serial_putc('l');
+
+		/* Only reprogram when needed to avoid triggering unnecessary
+		 * PLL relock sequences.
+		 */
+		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
+			serial_putc('?');
+			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
+			asm("idle;");
+			serial_putc('!');
+		}
+
+		serial_putc('m');
+
+		/* Restore all peripheral wakeups. */
+#ifdef SIC_IWR0
+		bfin_write_SIC_IWR0(-1);
+		bfin_write_SIC_IWR1(-1);
+# ifdef SIC_IWR2
+		bfin_write_SIC_IWR2(-1);
+# endif
+#elif defined(SICA_IWR0)
+		bfin_write_SICA_IWR0(-1);
+		bfin_write_SICA_IWR1(-1);
+#else
+		bfin_write_SIC_IWR(-1);
+#endif
+
+		serial_putc('n');
+	}
+
+	serial_putc('o');
+
+	return vr_ctl;
+}
+
+__attribute__((always_inline)) static inline void
+update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
+{
+	serial_putc('a');
+
+	/* Since we've changed the SCLK above, we may need to update
+	 * the UART divisors (UART baud rates are based on SCLK).
+	 * Do the division by hand as there are no native instructions
+	 * for dividing which means we'd generate a libgcc reference.
+	 */
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+		serial_putc('b');
+		unsigned int sdivR, vcoR;
+		sdivR = bfin_read_PLL_DIV() & 0xf;
+		vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+		int dividend = sdivB * divB * vcoR;
+		int divisor = vcoB * sdivR;
+		unsigned int quotient;
+		for (quotient = 0; dividend > 0; ++quotient)
+			dividend -= divisor;
+		serial_early_put_div(quotient - ANOMALY_05000230);
+		serial_putc('c');
+	}
+
+	serial_putc('d');
+}
+
+__attribute__((always_inline)) static inline void
+program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
+{
+	serial_putc('a');
+
+	if (!CONFIG_MEM_SIZE)
+		return;
+
+	serial_putc('b');
+
+	/* Program the external memory controller before we come out of
+	 * self-refresh.  This only works with our SDRAM controller.
+	 */
+#ifndef EBIU_RSTCTL
+# ifdef CONFIG_EBIU_SDRRC_VAL
+	bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
+# endif
+# ifdef CONFIG_EBIU_SDBCTL_VAL
+	bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
+# endif
+# ifdef CONFIG_EBIU_SDGCTL_VAL
+	bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
+# endif
+#endif
+
+	serial_putc('c');
+
+	/* Now that we've reprogrammed, take things out of self refresh. */
+	if (put_into_srfs)
+#ifdef EBIU_RSTCTL
+		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
+#else
+		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
+#endif
+
+	serial_putc('d');
+
+	/* Our DDR controller sucks and cannot be programmed while in
+	 * self-refresh.  So we have to pull it out before programming.
+	 */
+#ifdef EBIU_RSTCTL
+# ifdef CONFIG_EBIU_RSTCTL_VAL
+	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
+# endif
+# ifdef CONFIG_EBIU_DDRCTL0_VAL
+	bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
+# endif
+# ifdef CONFIG_EBIU_DDRCTL1_VAL
+	bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
+# endif
+# ifdef CONFIG_EBIU_DDRCTL2_VAL
+	bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
+# endif
+# ifdef CONFIG_EBIU_DDRCTL3_VAL
+	/* default is disable, so don't need to force this */
+	bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
+# endif
+# ifdef CONFIG_EBIU_DDRQUE_VAL
+	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
+# endif
+#endif
+
+	serial_putc('e');
+}
+
+__attribute__((always_inline)) static inline void
+check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
+{
+	serial_putc('a');
+
+	if (!CONFIG_MEM_SIZE)
+		return;
+
+	serial_putc('b');
+
+	/* Are we coming out of hibernate (suspend to memory) ?
+	 * The memory layout is:
+	 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
+	 * 0x4: return address
+	 * 0x8: stack pointer
+	 *
+	 * SCKELOW is unreliable on older parts (anomaly 307)
+	 */
+	if (ANOMALY_05000307 || vr_ctl & 0x8000) {
+		uint32_t *hibernate_magic = 0;
+		__builtin_bfin_ssync(); /* make sure memory controller is done */
+		if (hibernate_magic[0] == 0xDEADBEEF) {
+			serial_putc('c');
+			bfin_write_EVT15(hibernate_magic[1]);
+			bfin_write_IMASK(EVT_IVG15);
+			__asm__ __volatile__ (
+				/* load reti early to avoid anomaly 281 */
+				"reti = %0;"
+				/* clear hibernate magic */
+				"[%0] = %1;"
+				/* load stack pointer */
+				"SP = [%0 + 8];"
+				/* lower ourselves from reset ivg to ivg15 */
+				"raise 15;"
+				"rti;"
+				:
+				: "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
+			);
+		}
+		serial_putc('d');
+	}
+
+	serial_putc('e');
+}
+
+__attribute__((always_inline)) static inline void
+program_async_controller(ADI_BOOT_DATA *bs)
+{
+	serial_putc('a');
+
+	/* Program the async banks controller. */
+	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
+	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
+	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+
+	serial_putc('b');
+
+	/* Not all parts have these additional MMRs. */
+#ifdef EBIU_MODE
+# ifdef CONFIG_EBIU_MBSCTL_VAL
+	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
+# endif
+# ifdef CONFIG_EBIU_MODE_VAL
+	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
+# endif
+# ifdef CONFIG_EBIU_FCTL_VAL
+	bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
+# endif
+#endif
+
+	serial_putc('c');
+}
+
+BOOTROM_CALLED_FUNC_ATTR
+void initcode(ADI_BOOT_DATA *bs)
+{
+	ADI_BOOT_DATA bootstruct_scratch;
+
+	serial_init();
+
+	serial_putc('A');
+
+	/* If the bootstruct is NULL, then it's because we're loading
+	 * dynamically and not via LDR (bootrom).  So set the struct to
+	 * some scratch space.
+	 */
+	if (!bs)
+		bs = &bootstruct_scratch;
+
+	serial_putc('B');
+	bool put_into_srfs = maybe_self_refresh(bs);
+
+	serial_putc('C');
+	uint sdivB, divB, vcoB;
+	program_early_devices(bs, &sdivB, &divB, &vcoB);
+
+	serial_putc('D');
+	u16 vr_ctl = program_clocks(bs, put_into_srfs);
+
+	serial_putc('E');
+	update_serial_clocks(bs, sdivB, divB, vcoB);
+
+	serial_putc('F');
+	program_memory_controller(bs, put_into_srfs);
+
+	serial_putc('G');
+	check_hibernation(bs, vr_ctl, put_into_srfs);
+
+	serial_putc('H');
+	program_async_controller(bs);
+
+#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
+	serial_putc('I');
+	/* tell the bootrom where our entry point is */
+	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
+		bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
+#endif
+
+	serial_putc('>');
+	serial_putc('\n');
+
+	serial_deinit();
+}
diff --git a/arch/blackfin/cpu/interrupt.S b/arch/blackfin/cpu/interrupt.S
new file mode 100644
index 0000000..69bba3f
--- /dev/null
+++ b/arch/blackfin/cpu/interrupt.S
@@ -0,0 +1,152 @@
+/*
+ * interrupt.S - trampoline default exceptions/interrupts to C handlers
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/entry.h>
+#include <asm/ptrace.h>
+#include <asm/deferred.h>
+#include <asm/mach-common/bits/core.h>
+
+.text
+
+/* default entry point for exceptions */
+ENTRY(_trap)
+	CONFIG_BFIN_SCRATCH_REG = sp;
+	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
+	SAVE_ALL_SYS
+
+	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
+	r1 = 3;		/* EVT3 space */
+	sp += -12;
+	call _trap_c;
+	sp += 12;
+
+#ifdef CONFIG_EXCEPTION_DEFER
+	CC = R0 == 0;
+	IF CC JUMP .Lexit_trap;
+
+	/* To avoid double faults, lower our priority to IRQ5 */
+	p4.l = lo(COREMMR_BASE);
+	p4.h = hi(COREMMR_BASE);
+
+	r7.h = _exception_to_level5;
+	r7.l = _exception_to_level5;
+	[p4 + (EVT5 - COREMMR_BASE)] = r7;
+
+	/*
+	 * Save these registers, as they are only valid in exception context
+	 *  (where we are now - as soon as we defer to IRQ5, they can change)
+	 */
+	p5.l = _deferred_regs;
+	p5.h = _deferred_regs;
+	r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
+	[p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
+
+	r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
+	[p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
+
+	/* Save the state of single stepping */
+	r6 = SYSCFG;
+	[p5 + (deferred_regs_SYSCFG * 4)] = r6;
+	/* Clear it while we handle the exception in IRQ5 mode
+	 * RESTORE_ALL_SYS will load it, so all we need to do is store it
+	 * in the right place
+	 */
+	BITCLR(r6, SYSCFG_SSSTEP_P);
+	[SP + PT_SYSCFG] = r6;
+
+	/* Since we are going to clobber RETX, we need to save it */
+	r6 = retx;
+	[p5 + (deferred_regs_retx * 4)] = r6;
+
+	/* Save the current IMASK, since we change in order to jump to level 5 */
+	cli r6;
+	[p5 + (deferred_regs_IMASK * 4)] = r6;
+
+	/* Disable all interrupts, but make sure level 5 is enabled so
+	 * we can switch to that level.
+	 */
+	r6 = 0x3f;
+	sti r6;
+
+	/* Clobber RETX so we don't end up back at a faulting instruction */
+	[sp + PT_RETX] = r7;
+
+	/* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
+	 * clear it (re-enabling interrupts again) by the special sequence of pushing
+	 * RETI onto the stack.  This way we can lower ourselves to IVG5 even if the
+	 * exception was taken after the interrupt handler was called but before it
+	 * got a chance to enable global interrupts itself.
+	 */
+	[--sp] = reti;
+	sp += 4;
+
+	RAISE 5;
+.Lexit_trap:
+#endif
+
+#if ANOMALY_05000257
+	R7  = LC0;
+	LC0 = R7;
+	R7  = LC1;
+	LC1 = R7;
+#endif
+
+	RESTORE_ALL_SYS
+	sp = CONFIG_BFIN_SCRATCH_REG;
+	rtx;
+ENDPROC(_trap)
+
+#ifdef CONFIG_EXCEPTION_DEFER
+/* Deferred (IRQ5) exceptions */
+ENTRY(_exception_to_level5)
+	SAVE_ALL_SYS
+
+	/* Now we have to fix things up */
+	p4.l = lo(EVT5);
+	p4.h = hi(EVT5);
+	r0.l = _evt_default;
+	r0.h = _evt_default;
+	[p4] = r0;
+	csync;
+
+	p4.l = _deferred_regs;
+	p4.h = _deferred_regs;
+	r0 = [p4 + (deferred_regs_retx * 4)];
+	[sp + PT_PC] = r0;
+
+	r0 = [p4 + (deferred_regs_SYSCFG * 4)];
+	[sp + PT_SYSCFG] = r0;
+
+	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
+	r1 = 5;	/* EVT5 space */
+	sp += -12;
+	call _trap_c;
+	sp += 12;
+
+	/* Restore IMASK */
+	r0 = [p4 + (deferred_regs_IMASK * 4)];
+	sti r0;
+
+	RESTORE_ALL_SYS
+
+	rti;
+ENDPROC(_exception_to_level5)
+#endif
+
+/* default entry point for interrupts */
+ENTRY(_evt_default)
+	SAVE_ALL_SYS
+	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
+	sp += -12;
+	call _bfin_panic;
+	sp += 12;
+	RESTORE_ALL_SYS
+	rti;
+ENDPROC(_evt_default)
diff --git a/arch/blackfin/cpu/interrupts.c b/arch/blackfin/cpu/interrupts.c
new file mode 100644
index 0000000..54a67b4
--- /dev/null
+++ b/arch/blackfin/cpu/interrupts.c
@@ -0,0 +1,159 @@
+/*
+ * U-boot - interrupts.c Interrupt related routines
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * This file is based on interrupts.c
+ * Copyright 1996 Roman Zippel
+ * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
+ * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
+ * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
+ * Copyright 2003 Metrowerks/Motorola
+ * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
+ *			BuyWays B.V. (www.buyways.nl)
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+static ulong timestamp;
+static ulong last_time;
+static int int_flag;
+
+int irq_flags;			/* needed by asm-blackfin/system.h */
+
+/* Functions just to satisfy the linker */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On Blackfin it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On Blackfin it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
+
+void enable_interrupts(void)
+{
+	local_irq_restore(int_flag);
+}
+
+int disable_interrupts(void)
+{
+	local_irq_save(int_flag);
+	return 1;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long delay, start, stop;
+	unsigned long cclk;
+	cclk = (CONFIG_CCLK_HZ);
+
+	while (usec > 1) {
+		WATCHDOG_RESET();
+
+		/*
+		 * how many clock ticks to delay?
+		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
+		 */
+		if (usec < 1000) {
+			delay = (usec * (cclk / 244)) >> 12;
+			usec = 0;
+		} else {
+			delay = (1000 * (cclk / 244)) >> 12;
+			usec -= 1000;
+		}
+
+		asm volatile (" %0 = CYCLES;" : "=r" (start));
+		do {
+			asm volatile (" %0 = CYCLES; " : "=r" (stop));
+		} while (stop - start < delay);
+	}
+
+	return;
+}
+
+#define MAX_TIM_LOAD	0xFFFFFFFF
+int timer_init(void)
+{
+	bfin_write_TCNTL(0x1);
+	CSYNC();
+	bfin_write_TSCALE(0x0);
+	bfin_write_TCOUNT(MAX_TIM_LOAD);
+	bfin_write_TPERIOD(MAX_TIM_LOAD);
+	bfin_write_TCNTL(0x7);
+	CSYNC();
+
+	timestamp = 0;
+	last_time = 0;
+
+	return 0;
+}
+
+/*
+ * Any network command or flash
+ * command is started get_timer shall
+ * be called before TCOUNT gets reset,
+ * to implement the accurate timeouts.
+ *
+ * How ever milliconds doesn't return
+ * the number that has been elapsed from
+ * the last reset.
+ *
+ * As get_timer is used in the u-boot
+ * only for timeouts this should be
+ * sufficient
+ */
+ulong get_timer(ulong base)
+{
+	ulong milisec;
+
+	/* Number of clocks elapsed */
+	ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());
+
+	/*
+	 * Find if the TCOUNT is reset
+	 * timestamp gives the number of times
+	 * TCOUNT got reset
+	 */
+	if (clocks < last_time)
+		timestamp++;
+	last_time = clocks;
+
+	/* Get the number of milliseconds */
+	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
+
+	/*
+	 * Find the number of millisonds that
+	 * got elapsed before this TCOUNT cycle
+	 */
+	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
+
+	return (milisec - base);
+}
+
+void reset_timer(void)
+{
+	timer_init();
+}
diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c
new file mode 100644
index 0000000..1cd619f
--- /dev/null
+++ b/arch/blackfin/cpu/jtag-console.c
@@ -0,0 +1,132 @@
+/*
+ * jtag-console.c - console driver over Blackfin JTAG
+ *
+ * Copyright (c) 2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <asm/blackfin.h>
+
+#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT
+# define CONFIG_JTAG_CONSOLE_TIMEOUT 500
+#endif
+
+/* The Blackfin tends to be much much faster than the JTAG hardware. */
+static void jtag_write_emudat(uint32_t emudat)
+{
+	static bool overflowed = false;
+	ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT;
+	while (bfin_read_DBGSTAT() & 0x1) {
+		if (overflowed)
+			return;
+		if (timeout < get_timer(0))
+			overflowed = true;
+	}
+	overflowed = false;
+	__asm__ __volatile__("emudat = %0;" : : "d"(emudat));
+}
+/* Transmit a buffer.  The format is:
+ * [32bit length][actual data]
+ */
+static void jtag_send(const char *c, uint32_t len)
+{
+	uint32_t i;
+
+	if (len == 0)
+		return;
+
+	/* First send the length */
+	jtag_write_emudat(len);
+
+	/* Then send the data */
+	for (i = 0; i < len; i += 4)
+		jtag_write_emudat((c[i] << 0) | (c[i+1] << 8) | (c[i+2] << 16) | (c[i+3] << 24));
+}
+static void jtag_putc(const char c)
+{
+	jtag_send(&c, 1);
+}
+static void jtag_puts(const char *s)
+{
+	jtag_send(s, strlen(s));
+}
+
+static size_t inbound_len, leftovers_len;
+
+/* Lower layers want to know when jtag has data */
+static int jtag_tstc_dbg(void)
+{
+	return (bfin_read_DBGSTAT() & 0x2);
+}
+
+/* Higher layers want to know when any data is available */
+static int jtag_tstc(void)
+{
+	return jtag_tstc_dbg() || leftovers_len;
+}
+
+/* Receive a buffer.  The format is:
+ * [32bit length][actual data]
+ */
+static uint32_t leftovers;
+static int jtag_getc(void)
+{
+	int ret;
+	uint32_t emudat;
+
+	/* see if any data is left over */
+	if (leftovers_len) {
+		--leftovers_len;
+		ret = leftovers & 0xff;
+		leftovers >>= 8;
+		return ret;
+	}
+
+	/* wait for new data ! */
+	while (!jtag_tstc_dbg())
+		continue;
+	__asm__("%0 = emudat;" : "=d"(emudat));
+
+	if (inbound_len == 0) {
+		/* grab the length */
+		inbound_len = emudat;
+	} else {
+		/* store the bytes */
+		leftovers_len = min(4, inbound_len);
+		inbound_len -= leftovers_len;
+		leftovers = emudat;
+	}
+
+	return jtag_getc();
+}
+
+int drv_jtag_console_init(void)
+{
+	struct stdio_dev dev;
+	int ret;
+
+	memset(&dev, 0x00, sizeof(dev));
+	strcpy(dev.name, "jtag");
+	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+	dev.putc = jtag_putc;
+	dev.puts = jtag_puts;
+	dev.tstc = jtag_tstc;
+	dev.getc = jtag_getc;
+
+	ret = stdio_register(&dev);
+	return (ret == 0 ? 1 : ret);
+}
+
+#ifdef CONFIG_UART_CONSOLE_IS_JTAG
+/* Since the JTAG is always available (at power on), allow it to fake a UART */
+void serial_set_baud(uint32_t baud) {}
+void serial_setbrg(void)            {}
+int serial_init(void)               { return 0; }
+void serial_putc(const char c)      __attribute__((alias("jtag_putc")));
+void serial_puts(const char *s)     __attribute__((alias("jtag_puts")));
+int serial_tstc(void)               __attribute__((alias("jtag_tstc")));
+int serial_getc(void)               __attribute__((alias("jtag_getc")));
+#endif
diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c
new file mode 100644
index 0000000..e1c8e29
--- /dev/null
+++ b/arch/blackfin/cpu/os_log.c
@@ -0,0 +1,30 @@
+/*
+ * functions for handling OS log buffer
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the 2-clause BSD.
+ */
+
+#include <common.h>
+
+#define OS_LOG_MAGIC       0xDEADBEEF
+#define OS_LOG_MAGIC_ADDR  ((unsigned long *)0x4f0)
+#define OS_LOG_PTR_ADDR    ((char **)0x4f4)
+
+bool bfin_os_log_check(void)
+{
+	if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
+		return false;
+	*OS_LOG_MAGIC_ADDR = 0;
+	return true;
+}
+
+void bfin_os_log_dump(void)
+{
+	char *log = *OS_LOG_PTR_ADDR;
+	while (*log) {
+		puts(log);
+		log += strlen(log) + 1;
+	}
+}
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c
new file mode 100644
index 0000000..e3be740
--- /dev/null
+++ b/arch/blackfin/cpu/reset.c
@@ -0,0 +1,106 @@
+/*
+ * reset.c - logic for resetting the cpu
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include "cpu.h"
+
+/* A system soft reset makes external memory unusable so force
+ * this function into L1.  We use the compiler ssync here rather
+ * than SSYNC() because it's safe (no interrupts and such) and
+ * we save some L1.  We do not need to force sanity in the SYSCR
+ * register as the BMODE selection bit is cleared by the soft
+ * reset while the Core B bit (on dual core parts) is cleared by
+ * the core reset.
+ */
+__attribute__ ((__l1_text__, __noreturn__))
+static void bfin_reset(void)
+{
+	/* Wait for completion of "system" events such as cache line
+	 * line fills so that we avoid infinite stalls later on as
+	 * much as possible.  This code is in L1, so it won't trigger
+	 * any such event after this point in time.
+	 */
+	__builtin_bfin_ssync();
+
+	/* The bootrom checks to see how it was reset and will
+	 * automatically perform a software reset for us when
+	 * it starts executing after the core reset.
+	 */
+	if (ANOMALY_05000353 || ANOMALY_05000386) {
+		/* Initiate System software reset. */
+		bfin_write_SWRST(0x7);
+
+		/* Due to the way reset is handled in the hardware, we need
+		 * to delay for 10 SCLKS.  The only reliable way to do this is
+		 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+		 * we'll assume worse case which is a 1:15 ratio.
+		 */
+		asm(
+			"LSETUP (1f, 1f) LC0 = %0\n"
+			"1: nop;"
+			:
+			: "a" (15 * 10)
+			: "LC0", "LB0", "LT0"
+		);
+
+		/* Clear System software reset */
+		bfin_write_SWRST(0);
+
+		/* The BF526 ROM will crash during reset */
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+		bfin_read_SWRST();
+#endif
+
+		/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+		 * though as the System state is all reset now.
+		 */
+		asm(
+			"LSETUP (1f, 1f) LC1 = %0\n"
+			"1: nop;"
+			:
+			: "a" (15 * 1)
+			: "LC1", "LB1", "LT1"
+		);
+	}
+
+	while (1)
+		/* Issue core reset */
+		asm("raise 1");
+}
+
+/* We need to trampoline ourselves up into L1 since our linker
+ * does not have relaxtion support and will only generate a
+ * PC relative call with a 25 bit immediate.  This is not enough
+ * to get us from the top of SDRAM into L1.
+ */
+__attribute__ ((__noreturn__))
+static inline void bfin_reset_trampoline(void)
+{
+	if (board_reset)
+		board_reset();
+	while (1)
+		asm("jump (%0);" : : "a" (bfin_reset));
+}
+
+__attribute__ ((__noreturn__))
+void bfin_reset_or_hang(void)
+{
+#ifdef CONFIG_PANIC_HANG
+	hang();
+#else
+	bfin_reset_trampoline();
+#endif
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	bfin_reset_trampoline();
+	return 0;
+}
diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c
new file mode 100644
index 0000000..901cb97
--- /dev/null
+++ b/arch/blackfin/cpu/serial.c
@@ -0,0 +1,193 @@
+/*
+ * U-boot - serial.c Blackfin Serial Driver
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Copyright (c) 2003	Bas Vermeulen <bas@buyways.nl>,
+ *			BuyWays B.V. (www.buyways.nl)
+ *
+ * Based heavily on:
+ * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
+ * Copyright(c) 2003	Metrowerks	<mwaddel@metrowerks.com>
+ * Copyright(c)	2001	Tony Z. Kou	<tonyko@arcturusnetworks.com>
+ * Copyright(c)	2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
+ *
+ * Based on code from 68328 version serial driver imlpementation which was:
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* Anomaly notes:
+ *  05000086 - we don't support autobaud
+ *  05000099 - we only use DR bit, so losing others is not a problem
+ *  05000100 - we don't use the UART_IIR register
+ *  05000215 - we poll the uart (no dma/interrupts)
+ *  05000225 - no workaround possible, but this shouldnt cause errors ...
+ *  05000230 - we tweak the baud rate calculation slightly
+ *  05000231 - we always use 1 stop bit
+ *  05000309 - we always enable the uart before we modify it in anyway
+ *  05000350 - we always enable the uart regardless of boot mode
+ *  05000363 - we don't support break signals, so don't generate one
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#ifdef CONFIG_UART_CONSOLE
+
+#include "serial.h"
+
+#ifdef CONFIG_DEBUG_SERIAL
+uint16_t cached_lsr[256];
+uint16_t cached_rbr[256];
+size_t cache_count;
+
+/* The LSR is read-to-clear on some parts, so we have to make sure status
+ * bits aren't inadvertently lost when doing various tests.  This also
+ * works around anomaly 05000099 at the same time by keeping a cumulative
+ * tally of all the status bits.
+ */
+static uint16_t uart_lsr_save;
+static uint16_t uart_lsr_read(void)
+{
+	uint16_t lsr = bfin_read16(&pUART->lsr);
+	uart_lsr_save |= (lsr & (OE|PE|FE|BI));
+	return lsr | uart_lsr_save;
+}
+/* Just do the clear for everyone since it can't hurt. */
+static void uart_lsr_clear(void)
+{
+	uart_lsr_save = 0;
+	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+}
+#else
+/* When debugging is disabled, we only care about the DR bit, so if other
+ * bits get set/cleared, we don't really care since we don't read them
+ * anyways (and thus anomaly 05000099 is irrelevant).
+ */
+static uint16_t uart_lsr_read(void)
+{
+	return bfin_read16(&pUART->lsr);
+}
+static void uart_lsr_clear(void)
+{
+	bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
+}
+#endif
+
+/* Symbol for our assembly to call. */
+void serial_set_baud(uint32_t baud)
+{
+	serial_early_set_baud(baud);
+}
+
+/* Symbol for common u-boot code to call.
+ * Setup the baudrate (brg: baudrate generator).
+ */
+void serial_setbrg(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	serial_set_baud(gd->baudrate);
+}
+
+/* Symbol for our assembly to call. */
+void serial_initialize(void)
+{
+	serial_early_init();
+}
+
+/* Symbol for common u-boot code to call. */
+int serial_init(void)
+{
+	serial_initialize();
+	serial_setbrg();
+	uart_lsr_clear();
+#ifdef CONFIG_DEBUG_SERIAL
+	cache_count = 0;
+	memset(cached_lsr, 0x00, sizeof(cached_lsr));
+	memset(cached_rbr, 0x00, sizeof(cached_rbr));
+#endif
+	return 0;
+}
+
+void serial_putc(const char c)
+{
+	/* send a \r for compatibility */
+	if (c == '\n')
+		serial_putc('\r');
+
+	WATCHDOG_RESET();
+
+	/* wait for the hardware fifo to clear up */
+	while (!(uart_lsr_read() & THRE))
+		continue;
+
+	/* queue the character for transmission */
+	bfin_write16(&pUART->thr, c);
+	SSYNC();
+
+	WATCHDOG_RESET();
+}
+
+int serial_tstc(void)
+{
+	WATCHDOG_RESET();
+	return (uart_lsr_read() & DR) ? 1 : 0;
+}
+
+int serial_getc(void)
+{
+	uint16_t uart_rbr_val;
+
+	/* wait for data ! */
+	while (!serial_tstc())
+		continue;
+
+	/* grab the new byte */
+	uart_rbr_val = bfin_read16(&pUART->rbr);
+
+#ifdef CONFIG_DEBUG_SERIAL
+	/* grab & clear the LSR */
+	uint16_t uart_lsr_val = uart_lsr_read();
+
+	cached_lsr[cache_count] = uart_lsr_val;
+	cached_rbr[cache_count] = uart_rbr_val;
+	cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
+
+	if (uart_lsr_val & (OE|PE|FE|BI)) {
+		uint16_t dll, dlh;
+		printf("\n[SERIAL ERROR]\n");
+		ACCESS_LATCH();
+		dll = bfin_read16(&pUART->dll);
+		dlh = bfin_read16(&pUART->dlh);
+		ACCESS_PORT_IER();
+		printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
+		do {
+			--cache_count;
+			printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
+				cached_rbr[cache_count], cached_lsr[cache_count]);
+		} while (cache_count > 0);
+		return -1;
+	}
+#endif
+	uart_lsr_clear();
+
+	return uart_rbr_val;
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc(*s++);
+}
+
+#endif
diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h
new file mode 100644
index 0000000..5f9be86
--- /dev/null
+++ b/arch/blackfin/cpu/serial.h
@@ -0,0 +1,263 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL_H__
+#define __BFIN_CPU_SERIAL_H__
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/uart.h>
+
+#ifndef CONFIG_UART_CONSOLE
+# define CONFIG_UART_CONSOLE 0
+#endif
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define BFIN_DEBUG_EARLY_SERIAL 1
+#else
+# define BFIN_DEBUG_EARLY_SERIAL 0
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct bfin_mmr_serial {
+#ifdef __ADSPBF54x__
+	__BFP(dll);
+	__BFP(dlh);
+	__BFP(gctl);
+	__BFP(lcr);
+	__BFP(mcr);
+	__BFP(lsr);
+	__BFP(msr);
+	__BFP(scr);
+	__BFP(ier_set);
+	__BFP(ier_clear);
+	__BFP(thr);
+	__BFP(rbr);
+#else
+	union {
+		u16 dll;
+		u16 thr;
+		const u16 rbr;
+	};
+	const u16 __spad0;
+	union {
+		u16 dlh;
+		u16 ier;
+	};
+	const u16 __spad1;
+	const __BFP(iir);
+	__BFP(lcr);
+	__BFP(mcr);
+	__BFP(lsr);
+	__BFP(msr);
+	__BFP(scr);
+	const u32 __spad2;
+	__BFP(gctl);
+#endif
+};
+#undef __BFP
+
+#ifndef UART_LSR
+# if (CONFIG_UART_CONSOLE == 3)
+#  define UART_BASE UART3_DLL
+# elif (CONFIG_UART_CONSOLE == 2)
+#  define UART_BASE UART2_DLL
+# elif (CONFIG_UART_CONSOLE == 1)
+#  define UART_BASE UART1_DLL
+# elif (CONFIG_UART_CONSOLE == 0)
+#  define UART_BASE UART0_DLL
+# endif
+#else
+# if CONFIG_UART_CONSOLE != 0
+#  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+# endif
+# define UART_BASE UART_DLL
+#endif
+#define pUART ((volatile struct bfin_mmr_serial *)UART_BASE)
+
+#ifdef __ADSPBF54x__
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+#else
+# define ACCESS_LATCH() \
+	bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB)
+# define ACCESS_PORT_IER() \
+	bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_do_portmux(void)
+{
+#if defined(__ADSPBF51x__)
+# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
+	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
+	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0: DO_MUX(G, 5, 5, 9, 10);  break;	/* Port G; mux 5; PG9 and PG10 */
+	case 1: DO_MUX(F, 2, 3, 14, 15); break;	/* Port H; mux 2/3; PH14 and PH15 */
+	}
+	SSYNC();
+#elif defined(__ADSPBF52x__)
+# define DO_MUX(port, mux, tx, rx) \
+	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
+	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0: DO_MUX(G, 2, 7, 8);   break;	/* Port G; mux 2; PG2 and PG8 */
+	case 1: DO_MUX(F, 5, 14, 15); break;	/* Port F; mux 5; PF14 and PF15 */
+	}
+	SSYNC();
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+# define DO_MUX(func, tx, rx) \
+	bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~(func)); \
+	bfin_write_PORTF_FER(bfin_read_PORTF_FER() | PF##tx | PF##rx);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0: DO_MUX(PFDE, 0, 1); break;
+	case 1: DO_MUX(PFTE, 2, 3); break;
+	}
+	SSYNC();
+#elif defined(__ADSPBF54x__)
+# define DO_MUX(port, tx, rx) \
+	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
+	bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
+	switch (CONFIG_UART_CONSOLE) {
+	case 0: DO_MUX(E, 7, 8); break;	/* Port E; PE7 and PE8 */
+	case 1: DO_MUX(H, 0, 1); break;	/* Port H; PH0 and PH1 */
+	case 2: DO_MUX(B, 4, 5); break;	/* Port B; PB4 and PB5 */
+	case 3: DO_MUX(B, 6, 7); break;	/* Port B; PB6 and PB7 */
+	}
+	SSYNC();
+#endif
+}
+
+__attribute__((always_inline))
+static inline void serial_early_init(void)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
+	bfin_write16(&pUART->gctl, UCEN);
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	bfin_write16(&pUART->lcr, WLS_8);
+
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write16(&pUART->dll, LOB(divisor));
+	bfin_write16(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	uint8_t dll = bfin_read16(&pUART->dll);
+	uint8_t dlh = bfin_read16(&pUART->dlh);
+	uint16_t divisor = (dlh << 8) | dll;
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+
+	return divisor;
+}
+
+/* We cannot use get_sclk() early on as it uses caches in external memory */
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t baud)
+{
+	/* Translate from baud into divisor in terms of SCLK.  The
+	 * weird multiplication is to make sure we over sample just
+	 * a little rather than under sample the incoming signals.
+	 */
+	serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
+}
+
+#ifndef BFIN_IN_INITCODE
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+	if (BFIN_DEBUG_EARLY_SERIAL) {
+		serial_puts("Early: ");
+		serial_puts(s);
+	}
+}
+#endif
+
+#else
+
+.macro serial_early_init
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+	call _serial_initialize;
+#endif
+.endm
+
+.macro serial_early_set_baud
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+	R0.L = LO(CONFIG_BAUDRATE);
+	R0.H = HI(CONFIG_BAUDRATE);
+	call _serial_set_baud;
+#endif
+.endm
+
+/* Since we embed the string right into our .text section, we need
+ * to find its address.  We do this by getting our PC and adding 2
+ * bytes (which is the length of the jump instruction).  Then we
+ * pass this address to serial_puts().
+ */
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define serial_early_puts(str) \
+	call _get_pc; \
+	jump 1f; \
+	.ascii "Early:"; \
+	.ascii __FILE__; \
+	.ascii ": "; \
+	.ascii str; \
+	.asciz "\n"; \
+	.align 4; \
+1: \
+	R0 += 2; \
+	call _serial_puts;
+#else
+# define serial_early_puts(str)
+#endif
+
+#endif
+
+#endif
diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S
new file mode 100644
index 0000000..7a3abba
--- /dev/null
+++ b/arch/blackfin/cpu/start.S
@@ -0,0 +1,238 @@
+/*
+ * U-boot - start.S Startup file for Blackfin u-boot
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * This file is based on head.S
+ * Copyright (c) 2003  Metrowerks/Motorola
+ * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
+ *                     Kenneth Albanowski <kjahds@kjahds.com>,
+ *                     The Silver Hammer Group, Ltd.
+ * (c) 1995, Dionne & Associates
+ * (c) 1995, DKG Display Tech.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
+#include "serial.h"
+
+/* It may seem odd that we make calls to functions even though we haven't
+ * relocated ourselves yet out of {flash,ram,wherever}.  This is OK because
+ * the "call" instruction in the Blackfin architecture is actually PC
+ * relative.  So we can call functions all we want and not worry about them
+ * not being relocated yet.
+ */
+
+.text
+ENTRY(_start)
+
+	/* Set our initial stack to L1 scratch space */
+	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
+
+#ifdef CONFIG_HW_WATCHDOG
+# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
+#  define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
+# endif
+	/* Program the watchdog with an initial timeout of ~5 seconds.
+	 * That should be long enough to bootstrap ourselves up and
+	 * then the common u-boot code can take over.
+	 */
+	P0.L = LO(WDOG_CNT);
+	P0.H = HI(WDOG_CNT);
+	R0.L = 0;
+	R0.H = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
+	[P0] = R0;
+	/* fire up the watchdog - R0.L above needs to be 0x0000 */
+	W[P0 + (WDOG_CTL - WDOG_CNT)] = R0;
+#endif
+
+	/* Turn on the serial for debugging the init process */
+	serial_early_init
+	serial_early_set_baud
+
+	serial_early_puts("Init Registers");
+
+	/* Disable self-nested interrupts and enable CYCLES for udelay() */
+	R0 = CCEN | 0x30;
+	SYSCFG = R0;
+
+	/* Zero out registers required by Blackfin ABI.
+	 * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
+	 */
+	r1 = 0 (x);
+	/* Disable circular buffers */
+	l0 = r1;
+	l1 = r1;
+	l2 = r1;
+	l3 = r1;
+	/* Disable hardware loops in case we were started by 'go' */
+	lc0 = r1;
+	lc1 = r1;
+
+	/* Save RETX so we can pass it while booting Linux */
+	r7 = RETX;
+
+#if CONFIG_MEM_SIZE
+	/* Figure out where we are currently executing so that we can decide
+	 * how to best reprogram and relocate things.  We'll pass below:
+	 *  R4: load address of _start
+	 *  R5: current (not load) address of _start
+	 */
+	serial_early_puts("Find ourselves");
+
+	call _get_pc;
+.Loffset:
+	r1.l = .Loffset;
+	r1.h = .Loffset;
+	r4.l = _start;
+	r4.h = _start;
+	r3 = r1 - r4;
+	r5 = r0 - r3;
+
+	/* Inform upper layers if we had to do the relocation ourselves.
+	 * This allows us to detect whether we were loaded by 'go 0x1000'
+	 * or by the bootrom from an LDR.  "R6" is "loaded_from_ldr".
+	 */
+	r6 = 1 (x);
+	cc = r4 == r5;
+	if cc jump .Lnorelocate;
+	r6 = 0 (x);
+
+	/* In bypass mode, we don't have an LDR with an init block
+	 * so we need to explicitly call it ourselves.  This will
+	 * reprogram our clocks, memory, and setup our async banks.
+	 */
+	serial_early_puts("Program Clocks");
+
+	/* if we're executing >=0x20000000, then we dont need to dma */
+	r3 = 0x0;
+	r3.h = 0x2000;
+	cc = r5 < r3 (iu);
+	if cc jump .Ldma_and_reprogram;
+#else
+	r6 = 1 (x);	/* fake loaded_from_ldr = 1 */
+#endif
+	r0 = 0 (x);	/* set bootstruct to NULL */
+	call _initcode;
+	jump .Lprogrammed;
+
+	/* we're sitting in external memory, so dma into L1 and reprogram */
+.Ldma_and_reprogram:
+	r0.l = LO(L1_INST_SRAM);
+	r0.h = HI(L1_INST_SRAM);
+	r1.l = __initcode_lma;
+	r1.h = __initcode_lma;
+	r2.l = __initcode_len;
+	r2.h = __initcode_len;
+	r1 = r1 - r4;	/* convert r1 from load address of initcode ... */
+	r1 = r1 + r5;	/* ... to current (not load) address of initcode */
+	p3 = r0;
+	call _dma_memcpy_nocache;
+	r0 = 0 (x);	/* set bootstruct to NULL */
+	call (p3);
+
+	/* Since we reprogrammed SCLK, we need to update the serial divisor */
+.Lprogrammed:
+	serial_early_set_baud
+
+#if CONFIG_MEM_SIZE
+	/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
+	 * monitor location in the end of RAM.  We know that memcpy() only
+	 * uses registers, so it is safe to call here.  Note that this only
+	 * copies to external memory ... we do not start executing out of
+	 * it yet (see "lower to 15" below).
+	 */
+	serial_early_puts("Relocate");
+	r0 = r4;
+	r1 = r5;
+	r2.l = LO(CONFIG_SYS_MONITOR_LEN);
+	r2.h = HI(CONFIG_SYS_MONITOR_LEN);
+	call _memcpy_ASM;
+#endif
+
+	/* Initialize BSS section ... we know that memset() does not
+	 * use the BSS, so it is safe to call here.  The bootrom LDR
+	 * takes care of clearing things for us.
+	 */
+	serial_early_puts("Zero BSS");
+	r0.l = __bss_vma;
+	r0.h = __bss_vma;
+	r1 = 0 (x);
+	r2.l = __bss_len;
+	r2.h = __bss_len;
+	call _memset;
+
+.Lnorelocate:
+
+	/* Setup the actual stack in external memory */
+	sp.h = HI(CONFIG_STACKBASE);
+	sp.l = LO(CONFIG_STACKBASE);
+	fp = sp;
+
+	/* Now lower ourselves from the highest interrupt level to
+	 * the lowest.  We do this by masking all interrupts but 15,
+	 * setting the 15 handler to ".Lenable_nested", raising the 15
+	 * interrupt, and then returning from the highest interrupt
+	 * level to the dummy "jump" until the interrupt controller
+	 * services the pending 15 interrupt.  If executing out of
+	 * flash, these steps also changes the code flow from flash
+	 * to external memory.
+	 */
+	serial_early_puts("Lower to 15");
+	r0 = r7;
+	r1 = r6;
+	p0.l = LO(EVT15);
+	p0.h = HI(EVT15);
+	p1.l = .Lenable_nested;
+	p1.h = .Lenable_nested;
+	[p0] = p1;
+	r7 = EVT_IVG15 (z);
+	sti r7;
+	raise 15;
+	p4.l = .LWAIT_HERE;
+	p4.h = .LWAIT_HERE;
+	reti = p4;
+	rti;
+
+	/* Enable nested interrupts before continuing with cpu init */
+.Lenable_nested:
+	cli r7;
+	[--sp] = reti;
+	jump.l _cpu_init_f;
+
+.LWAIT_HERE:
+	jump .LWAIT_HERE;
+ENDPROC(_start)
+
+LENTRY(_get_pc)
+	r0 = rets;
+#if ANOMALY_05000371
+	NOP;
+	NOP;
+	NOP;
+#endif
+	rts;
+ENDPROC(_get_pc)
diff --git a/arch/blackfin/cpu/traps.c b/arch/blackfin/cpu/traps.c
new file mode 100644
index 0000000..caaea94
--- /dev/null
+++ b/arch/blackfin/cpu/traps.c
@@ -0,0 +1,410 @@
+/*
+ * U-boot - traps.c Routines related to interrupts and exceptions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * This file is based on
+ * No original Copyright holder listed,
+ * Probabily original (C) Roman Zippel (assigned DJD, 1999)
+ *
+ * Copyright 2003 Metrowerks - for Blackfin
+ * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
+ * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <kgdb.h>
+#include <linux/types.h>
+#include <asm/traps.h>
+#include <asm/cplb.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <asm/mach-common/bits/trace.h>
+#include <asm/deferred.h>
+#include "cpu.h"
+
+#define trace_buffer_save(x) \
+	do { \
+		(x) = bfin_read_TBUFCTL(); \
+		bfin_write_TBUFCTL((x) & ~TBUFEN); \
+	} while (0)
+
+#define trace_buffer_restore(x) \
+	bfin_write_TBUFCTL((x))
+
+/* The purpose of this map is to provide a mapping of address<->cplb settings
+ * rather than an exact map of what is actually addressable on the part.  This
+ * map covers all current Blackfin parts.  If you try to access an address that
+ * is in this map but not actually on the part, you won't get an exception and
+ * reboot, you'll get an external hardware addressing error and reboot.  Since
+ * only the ends matter (you did something wrong and the board reset), the means
+ * are largely irrelevant.
+ */
+struct memory_map {
+	uint32_t start, end;
+	uint32_t data_flags, inst_flags;
+};
+const struct memory_map const bfin_memory_map[] = {
+	{	/* external memory */
+		.start = 0x00000000,
+		.end   = 0x20000000,
+		.data_flags = SDRAM_DGENERIC,
+		.inst_flags = SDRAM_IGENERIC,
+	},
+	{	/* async banks */
+		.start = 0x20000000,
+		.end   = 0x30000000,
+		.data_flags = SDRAM_EBIU,
+		.inst_flags = SDRAM_INON_CHBL,
+	},
+	{	/* everything on chip */
+		.start = 0xE0000000,
+		.end   = 0xFFFFFFFF,
+		.data_flags = L1_DMEMORY,
+		.inst_flags = L1_IMEMORY,
+	}
+};
+
+#ifdef CONFIG_EXCEPTION_DEFER
+unsigned int deferred_regs[deferred_regs_last];
+#endif
+
+/*
+ * Handle all exceptions while running in EVT3 or EVT5
+ */
+int trap_c(struct pt_regs *regs, uint32_t level)
+{
+	uint32_t ret = 0;
+	uint32_t trapnr = (regs->seqstat & EXCAUSE);
+	bool data = false;
+
+	switch (trapnr) {
+	/* 0x26 - Data CPLB Miss */
+	case VEC_CPLB_M:
+
+		if (ANOMALY_05000261) {
+			static uint32_t last_cplb_fault_retx;
+			/*
+			 * Work around an anomaly: if we see a new DCPLB fault,
+			 * return without doing anything. Then,
+			 * if we get the same fault again, handle it.
+			 */
+			if (last_cplb_fault_retx != regs->retx) {
+				last_cplb_fault_retx = regs->retx;
+				return ret;
+			}
+		}
+
+		data = true;
+		/* fall through */
+
+	/* 0x27 - Instruction CPLB Miss */
+	case VEC_CPLB_I_M: {
+		volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
+		uint32_t new_cplb_addr = 0, new_cplb_data = 0;
+		static size_t last_evicted;
+		size_t i;
+		unsigned long tflags;
+
+#ifdef CONFIG_EXCEPTION_DEFER
+		/* This should never happen */
+		if (level == 5)
+			bfin_panic(regs);
+#endif
+
+		/*
+		 * Keep the trace buffer so that a miss here points people
+		 * to the right place (their code).  Crashes here rarely
+		 * happen.  If they do, only the Blackfin maintainer cares.
+		 */
+		trace_buffer_save(tflags);
+
+		new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
+
+		for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
+			/* if the exception is inside this range, lets use it */
+			if (new_cplb_addr >= bfin_memory_map[i].start &&
+			    new_cplb_addr < bfin_memory_map[i].end)
+				break;
+		}
+		if (i == ARRAY_SIZE(bfin_memory_map)) {
+			printf("%cCPLB exception outside of memory map at 0x%p\n",
+				(data ? 'D' : 'I'), (void *)new_cplb_addr);
+			bfin_panic(regs);
+		} else
+			debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
+		new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
+
+		if (data) {
+			CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
+			CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
+		} else {
+			CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
+			CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
+		}
+
+		/* find the next unlocked entry and evict it */
+		i = last_evicted & 0xF;
+		debug("last evicted = %i\n", i);
+		CPLB_DATA = CPLB_DATA_BASE + i;
+		while (*CPLB_DATA & CPLB_LOCK) {
+			debug("skipping %i %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
+			i = (i + 1) & 0xF;	/* wrap around */
+			CPLB_DATA = CPLB_DATA_BASE + i;
+		}
+		CPLB_ADDR = CPLB_ADDR_BASE + i;
+
+		debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
+		last_evicted = i + 1;
+
+		/* need to turn off cplbs whenever we muck with the cplb table */
+#if ENDCPLB != ENICPLB
+# error cplb enable bit violates my sanity
+#endif
+		uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
+		bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
+		*CPLB_ADDR = new_cplb_addr;
+		*CPLB_DATA = new_cplb_data;
+		bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
+		SSYNC();
+
+		/* dump current table for debugging purposes */
+		CPLB_ADDR = CPLB_ADDR_BASE;
+		CPLB_DATA = CPLB_DATA_BASE;
+		for (i = 0; i < 16; ++i)
+			debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
+
+		trace_buffer_restore(tflags);
+		break;
+	}
+#ifdef CONFIG_CMD_KGDB
+	/* Single step
+	 * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
+	 */
+	case VEC_STEP:
+		if (level == 3) {
+			/* If we just returned from an interrupt, the single step
+			 * event is for the RTI instruction.
+			 */
+			if (regs->retx == regs->pc)
+				break;
+			/* we just return if we are single stepping through IRQ5 */
+			if (regs->ipend & 0x20)
+				break;
+			/* Otherwise, turn single stepping off & fall through,
+			 * which defers to IRQ5
+			 */
+			regs->syscfg &= ~1;
+		}
+		/* fall through */
+#endif
+	default:
+#ifdef CONFIG_CMD_KGDB
+		if (level == 3) {
+			/* We need to handle this at EVT5, so try again */
+			ret = 1;
+			break;
+		}
+		if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+			return 0;
+#endif
+		bfin_panic(regs);
+	}
+	return ret;
+}
+
+#ifdef CONFIG_DEBUG_DUMP
+# define ENABLE_DUMP 1
+#else
+# define ENABLE_DUMP 0
+#endif
+
+#ifndef CONFIG_KALLSYMS
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+{
+	*caddr = addr;
+	return "N/A";
+}
+#endif
+
+static void decode_address(char *buf, unsigned long address)
+{
+	unsigned long sym_addr;
+	void *paddr = (void *)address;
+	const char *sym = symbol_lookup(address, &sym_addr);
+
+	if (sym) {
+		sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
+		return;
+	}
+
+	if (!address)
+		sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
+	else if (address >= CONFIG_SYS_MONITOR_BASE &&
+	         address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+		sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
+	else
+		sprintf(buf, "<0x%p> /* unknown address */", paddr);
+}
+
+static char *strhwerrcause(uint16_t hwerrcause)
+{
+	switch (hwerrcause) {
+		case 0x02: return "system mmr error";
+		case 0x03: return "external memory addressing error";
+		case 0x12: return "performance monitor overflow";
+		case 0x18: return "raise 5 instruction";
+		default:   return "undef";
+	}
+}
+
+static char *strexcause(uint16_t excause)
+{
+	switch (excause) {
+		case 0x00 ... 0xf: return "custom exception";
+		case 0x10: return "single step";
+		case 0x11: return "trace buffer full";
+		case 0x21: return "undef inst";
+		case 0x22: return "illegal inst";
+		case 0x23: return "dcplb prot violation";
+		case 0x24: return "misaligned data";
+		case 0x25: return "unrecoverable event";
+		case 0x26: return "dcplb miss";
+		case 0x27: return "multiple dcplb hit";
+		case 0x28: return "emulation watchpoint";
+		case 0x2a: return "misaligned inst";
+		case 0x2b: return "icplb prot violation";
+		case 0x2c: return "icplb miss";
+		case 0x2d: return "multiple icplb hit";
+		case 0x2e: return "illegal use of supervisor resource";
+		default:   return "undef";
+	}
+}
+
+void dump(struct pt_regs *fp)
+{
+	char buf[150];
+	int i;
+	uint16_t hwerrcause, excause;
+
+	if (!ENABLE_DUMP)
+		return;
+
+#ifndef CONFIG_CMD_KGDB
+	/* fp->ipend is normally garbage, so load it ourself */
+	fp->ipend = bfin_read_IPEND();
+#endif
+
+	hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
+	excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
+
+	printf("SEQUENCER STATUS:\n");
+	printf(" SEQSTAT: %08lx  IPEND: %04lx  SYSCFG: %04lx\n",
+		fp->seqstat, fp->ipend, fp->syscfg);
+	printf("  HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
+	printf("  EXCAUSE   : 0x%x: %s\n", excause, strexcause(excause));
+	for (i = 6; i <= 15; ++i) {
+		if (fp->ipend & (1 << i)) {
+			decode_address(buf, bfin_read32(EVT0 + 4*i));
+			printf("  physical IVG%i asserted : %s\n", i, buf);
+		}
+	}
+	decode_address(buf, fp->rete);
+	printf(" RETE: %s\n", buf);
+	decode_address(buf, fp->retn);
+	printf(" RETN: %s\n", buf);
+	decode_address(buf, fp->retx);
+	printf(" RETX: %s\n", buf);
+	decode_address(buf, fp->rets);
+	printf(" RETS: %s\n", buf);
+	/* we lie and store RETI in "pc" */
+	decode_address(buf, fp->pc);
+	printf(" RETI: %s\n", buf);
+
+	if (fp->seqstat & EXCAUSE) {
+		decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
+		printf("DCPLB_FAULT_ADDR: %s\n", buf);
+		decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
+		printf("ICPLB_FAULT_ADDR: %s\n", buf);
+	}
+
+	printf("\nPROCESSOR STATE:\n");
+	printf(" R0 : %08lx    R1 : %08lx    R2 : %08lx    R3 : %08lx\n",
+		fp->r0, fp->r1, fp->r2, fp->r3);
+	printf(" R4 : %08lx    R5 : %08lx    R6 : %08lx    R7 : %08lx\n",
+		fp->r4, fp->r5, fp->r6, fp->r7);
+	printf(" P0 : %08lx    P1 : %08lx    P2 : %08lx    P3 : %08lx\n",
+		fp->p0, fp->p1, fp->p2, fp->p3);
+	printf(" P4 : %08lx    P5 : %08lx    FP : %08lx    SP : %08lx\n",
+		fp->p4, fp->p5, fp->fp, (unsigned long)fp);
+	printf(" LB0: %08lx    LT0: %08lx    LC0: %08lx\n",
+		fp->lb0, fp->lt0, fp->lc0);
+	printf(" LB1: %08lx    LT1: %08lx    LC1: %08lx\n",
+		fp->lb1, fp->lt1, fp->lc1);
+	printf(" B0 : %08lx    L0 : %08lx    M0 : %08lx    I0 : %08lx\n",
+		fp->b0, fp->l0, fp->m0, fp->i0);
+	printf(" B1 : %08lx    L1 : %08lx    M1 : %08lx    I1 : %08lx\n",
+		fp->b1, fp->l1, fp->m1, fp->i1);
+	printf(" B2 : %08lx    L2 : %08lx    M2 : %08lx    I2 : %08lx\n",
+		fp->b2, fp->l2, fp->m2, fp->i2);
+	printf(" B3 : %08lx    L3 : %08lx    M3 : %08lx    I3 : %08lx\n",
+		fp->b3, fp->l3, fp->m3, fp->i3);
+	printf("A0.w: %08lx   A0.x: %08lx   A1.w: %08lx   A1.x: %08lx\n",
+		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
+
+	printf("USP : %08lx  ASTAT: %08lx\n",
+		fp->usp, fp->astat);
+
+	printf("\n");
+}
+
+void dump_bfin_trace_buffer(void)
+{
+	char buf[150];
+	unsigned long tflags;
+	int i = 0;
+
+	if (!ENABLE_DUMP)
+		return;
+
+	trace_buffer_save(tflags);
+
+	printf("Hardware Trace:\n");
+
+	if (bfin_read_TBUFSTAT() & TBUFCNT) {
+		for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
+			decode_address(buf, bfin_read_TBUF());
+			printf("%4i Target : %s\n", i, buf);
+			decode_address(buf, bfin_read_TBUF());
+			printf("     Source : %s\n", buf);
+		}
+	}
+
+	trace_buffer_restore(tflags);
+}
+
+void bfin_panic(struct pt_regs *regs)
+{
+	if (ENABLE_DUMP) {
+		unsigned long tflags;
+		trace_buffer_save(tflags);
+	}
+
+	puts(
+		"\n"
+		"\n"
+		"\n"
+		"Ack! Something bad happened to the Blackfin!\n"
+		"\n"
+	);
+	dump(regs);
+	dump_bfin_trace_buffer();
+	puts("\n");
+	bfin_reset_or_hang();
+}
diff --git a/arch/blackfin/cpu/watchdog.c b/arch/blackfin/cpu/watchdog.c
new file mode 100644
index 0000000..1886bda
--- /dev/null
+++ b/arch/blackfin/cpu/watchdog.c
@@ -0,0 +1,23 @@
+/*
+ * watchdog.c - driver for Blackfin on-chip watchdog
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/blackfin.h>
+
+void hw_watchdog_reset(void)
+{
+	bfin_write_WDOG_STAT(0);
+}
+
+void hw_watchdog_init(void)
+{
+	bfin_write_WDOG_CNT(5 * get_sclk());	/* 5 second timeout */
+	hw_watchdog_reset();
+	bfin_write_WDOG_CTL(0x0);
+}
diff --git a/arch/blackfin/include/asm/bfin_logo_230x230.h b/arch/blackfin/include/asm/bfin_logo_230x230.h
new file mode 100644
index 0000000..3a79631
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_logo_230x230.h
@@ -0,0 +1,2377 @@
+/*
+ * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
+ *
+ * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
+ *
+ * Where:	'screen'	is the pointer to the frame buffer
+ *		'width'	is the screen width
+ *		'x'		is the horizontal position
+ *		'y'		is the vertical position
+ */
+
+#define EASYLOGO_ENABLE_GZIP 37470
+
+static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
+
+#include <video_easylogo.h>
+
+#define	DEF_BFIN_LOGO_WIDTH		230
+#define	DEF_BFIN_LOGO_HEIGHT		230
+#define	DEF_BFIN_LOGO_PIXELS		52900
+#define	DEF_BFIN_LOGO_BPP		24
+#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
+#define	DEF_BFIN_LOGO_SIZE		158700
+
+unsigned char DEF_BFIN_LOGO_DATA[] = {
+ 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7,
+ 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86,
+ 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b,
+ 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b,
+ 0xab, 0xd6, 0xd6, 0xb6, 0xee, 0x81, 0x5a, 0x95, 0xdb, 0xd6, 0x5d, 0x17, 0x52, 0x07, 0x60, 0xbc,
+ 0xc5, 0xf5, 0xbf, 0x4f, 0x38, 0x35, 0x0d, 0x43, 0x2a, 0xdc, 0xaa, 0xb7, 0xf1, 0x3c, 0x9f, 0xa8,
+ 0x90, 0x9c, 0x93, 0xf7, 0x3d, 0x9e, 0xef, 0x79, 0xde, 0xe7, 0xf7, 0xe6, 0x9c, 0x93, 0x41, 0x83,
+ 0x48, 0xfd, 0x31, 0x1a, 0xdc, 0x9b, 0x9e, 0x76, 0xa7, 0x48, 0x91, 0xd2, 0x8a, 0xa0, 0x71, 0x48,
+ 0xa7, 0x8c, 0x8d, 0x8d, 0x4d, 0x3a, 0x65, 0xd6, 0x43, 0xa6, 0xa6, 0xa6, 0x78, 0xde, 0xb8, 0x53,
+ 0x46, 0x46, 0x46, 0x24, 0xc3, 0xa4, 0x9e, 0xa4, 0x74, 0x94, 0x82, 0x3d, 0xa0, 0x68, 0x6e, 0x6e,
+ 0x6e, 0x61, 0x61, 0x61, 0x69, 0x69, 0x69, 0x6d, 0x6d, 0x6d, 0x63, 0x63, 0x63, 0x6b, 0x6b, 0x67,
+ 0x6f, 0x4f, 0x77, 0xe8, 0x2a, 0x7b, 0x7b, 0x7b, 0x5b, 0x5b, 0x5b, 0xbc, 0x6a, 0x65, 0x65, 0x85,
+ 0x25, 0xb1, 0x0a, 0x56, 0x24, 0xe8, 0xc5, 0xfb, 0x90, 0xf4, 0x92, 0x7a, 0x4c, 0x22, 0x40, 0x05,
+ 0x69, 0xb0, 0xcd, 0xa1, 0x43, 0x87, 0x5a, 0x59, 0x59, 0x83, 0x43, 0x00, 0xc9, 0x62, 0xb1, 0x79,
+ 0x3c, 0x9e, 0x48, 0x24, 0x92, 0x4a, 0xa5, 0xee, 0xee, 0xee, 0x5e, 0x5e, 0x5e, 0xde, 0xde, 0x0a,
+ 0x85, 0xc2, 0x87, 0x78, 0x78, 0x7b, 0x7b, 0xcb, 0xe5, 0x9e, 0x32, 0x99, 0xcc, 0xc5, 0xc5, 0x45,
+ 0x28, 0x14, 0x72, 0x38, 0x1c, 0x47, 0x47, 0x47, 0x80, 0x0d, 0xc2, 0x09, 0x7a, 0x61, 0xbf, 0x84,
+ 0xf1, 0x3e, 0xed, 0xed, 0x23, 0x65, 0x38, 0x02, 0x4e, 0x80, 0x0a, 0x68, 0xc1, 0x4e, 0x41, 0x9a,
+ 0x9d, 0x9d, 0x1d, 0x8b, 0xc5, 0x12, 0x08, 0x84, 0x6e, 0x6e, 0x6e, 0x00, 0x32, 0x30, 0x30, 0x30,
+ 0x3c, 0x5c, 0x15, 0x13, 0x13, 0x9b, 0x9c, 0x9c, 0x9c, 0x99, 0x99, 0x99, 0x97, 0x97, 0x57, 0x58,
+ 0x58, 0x58, 0xf4, 0x40, 0x05, 0x05, 0x05, 0xb9, 0xb9, 0xb9, 0x19, 0x19, 0x19, 0x89, 0x89, 0x89,
+ 0x51, 0x51, 0xd1, 0x21, 0x21, 0x4a, 0x1f, 0x1f, 0x1f, 0x00, 0x0c, 0xc2, 0xd9, 0x6c, 0x36, 0x9d,
+ 0x4e, 0xa7, 0x52, 0xa9, 0xe0, 0x1f, 0xae, 0x4b, 0x72, 0x4b, 0xea, 0xbf, 0x97, 0xce, 0x54, 0xe1,
+ 0x87, 0x18, 0xd6, 0x99, 0x4c, 0x96, 0x50, 0x28, 0xf2, 0xf0, 0xf0, 0x08, 0x0c, 0x0c, 0x8a, 0x8e,
+ 0x8e, 0x4e, 0x4d, 0x4d, 0xcd, 0xcf, 0xcf, 0x2f, 0x2f, 0x2f, 0xaf, 0xae, 0xae, 0xae, 0xa9, 0xa9,
+ 0xc1, 0x0f, 0x59, 0x59, 0x59, 0x49, 0x49, 0xc9, 0xb1, 0xb1, 0xb1, 0x11, 0x11, 0x11, 0xa1, 0xa1,
+ 0xa1, 0x51, 0x51, 0x51, 0x09, 0x09, 0x89, 0x19, 0x19, 0x99, 0xc5, 0xc5, 0x25, 0x58, 0xa6, 0xb6,
+ 0xb6, 0x76, 0xd8, 0xb0, 0xca, 0x82, 0x82, 0xc2, 0xf4, 0xf4, 0x0c, 0x2c, 0x13, 0x12, 0x12, 0xe2,
+ 0xe9, 0xe9, 0x29, 0x12, 0x39, 0x83, 0x7f, 0xd8, 0x35, 0x85, 0x42, 0x41, 0x43, 0x64, 0xd0, 0x25,
+ 0x35, 0x30, 0x11, 0xac, 0x62, 0xd4, 0x46, 0xf8, 0xa4, 0xd3, 0x1d, 0x9c, 0x9c, 0x78, 0x6e, 0x6e,
+ 0x32, 0x80, 0x0a, 0xd2, 0xb2, 0xb3, 0x73, 0x4a, 0x4a, 0x4a, 0x2b, 0x2a, 0x86, 0x95, 0x95, 0x95,
+ 0xc5, 0xc7, 0x27, 0x20, 0x06, 0xc0, 0x2a, 0x41, 0xda, 0xef, 0xbe, 0x27, 0x98, 0x94, 0x48, 0x24,
+ 0x6a, 0x75, 0x0c, 0xbc, 0xb7, 0xbc, 0xbc, 0xa2, 0xb4, 0xb4, 0x14, 0xc0, 0x27, 0x24, 0x24, 0x04,
+ 0x07, 0x07, 0x23, 0x4e, 0xf0, 0xf9, 0x7c, 0x64, 0x0c, 0x78, 0xb8, 0x8e, 0xdb, 0x27, 0xb0, 0x99,
+ 0xa4, 0x0c, 0x40, 0x44, 0x06, 0x00, 0x36, 0x60, 0x15, 0x08, 0x01, 0x24, 0xb9, 0x5c, 0x0e, 0xc3,
+ 0x4c, 0x4e, 0x4e, 0x01, 0xa8, 0x70, 0xcb, 0xac, 0xac, 0x6c, 0x95, 0x4a, 0xe5, 0xec, 0xec, 0x8c,
+ 0x9c, 0x30, 0xb0, 0x26, 0x70, 0x2c, 0x30, 0x99, 0xcc, 0x80, 0x80, 0x80, 0xf4, 0xf4, 0xf4, 0xa2,
+ 0xa2, 0xe2, 0x92, 0x92, 0x92, 0xb4, 0xb4, 0xb4, 0xb0, 0xb0, 0x30, 0x34, 0x84, 0xe6, 0x50, 0xa9,
+ 0xc1, 0xd2, 0x91, 0x13, 0xc8, 0xba, 0x8c, 0xd4, 0xef, 0x8a, 0xb0, 0x56, 0x04, 0x4b, 0x0c, 0xd3,
+ 0xa8, 0xa7, 0x80, 0x50, 0x78, 0x78, 0x38, 0x06, 0x71, 0x8c, 0xe6, 0x30, 0xc6, 0xc8, 0xc8, 0x48,
+ 0x57, 0x57, 0x57, 0x90, 0xfc, 0x47, 0x81, 0x04, 0x0f, 0x07, 0xf9, 0x88, 0x10, 0x88, 0xbe, 0x08,
+ 0x15, 0x00, 0x58, 0xa9, 0x0c, 0x45, 0x13, 0xa8, 0xe6, 0x10, 0x42, 0x10, 0x9b, 0xd1, 0x19, 0x12,
+ 0x5a, 0x52, 0x0f, 0x13, 0x70, 0x85, 0xb3, 0x61, 0xec, 0x86, 0xb5, 0x8a, 0xc5, 0x62, 0x0c, 0xd6,
+ 0x48, 0xaa, 0x95, 0x95, 0x95, 0xa5, 0xa5, 0x65, 0xf0, 0x58, 0x00, 0x3c, 0x60, 0x53, 0xed, 0x5b,
+ 0x78, 0x5b, 0x2e, 0x97, 0xab, 0x54, 0x2a, 0xcb, 0xca, 0x80, 0x6d, 0x39, 0x92, 0x86, 0xaf, 0xaf,
+ 0x2f, 0x4a, 0x33, 0x74, 0x03, 0x9d, 0x21, 0xcc, 0xf6, 0x71, 0xb4, 0x4b, 0xea, 0x4f, 0x2d, 0x02,
+ 0x57, 0xc4, 0x48, 0xd4, 0x41, 0xa8, 0xe5, 0x61, 0xa7, 0x18, 0xac, 0x47, 0x8d, 0x1a, 0x15, 0x1b,
+ 0x1b, 0x87, 0x67, 0xf0, 0xd2, 0xe3, 0xee, 0x00, 0x9a, 0x60, 0x30, 0x18, 0x28, 0xe8, 0xd0, 0x68,
+ 0x6e, 0x6e, 0x2e, 0x82, 0x07, 0xba, 0xc1, 0x66, 0xb3, 0xa9, 0x54, 0x2a, 0x99, 0x6c, 0x49, 0x75,
+ 0x13, 0x81, 0x2b, 0xd8, 0x70, 0x72, 0x72, 0x52, 0x28, 0x14, 0x89, 0x89, 0x89, 0x55, 0x55, 0x55,
+ 0x70, 0x3c, 0x81, 0x40, 0xf0, 0x18, 0xc7, 0xe5, 0xde, 0xde, 0x16, 0xcd, 0xc1, 0xcc, 0x8b, 0x8b,
+ 0x8b, 0x87, 0x0d, 0x1b, 0x96, 0x9c, 0x9c, 0xec, 0xe7, 0xe7, 0x2f, 0x14, 0x0a, 0x11, 0x51, 0xc8,
+ 0x84, 0x40, 0x4a, 0x27, 0xe0, 0x8a, 0x71, 0x19, 0xb8, 0x02, 0x15, 0x3f, 0x3f, 0x3f, 0x84, 0x49,
+ 0xe0, 0x9a, 0x91, 0x91, 0x01, 0x67, 0x7b, 0x5c, 0x4d, 0xa2, 0xb8, 0x33, 0x33, 0xb3, 0xa0, 0x52,
+ 0xcd, 0x29, 0x14, 0x23, 0x53, 0xd3, 0x9e, 0x1c, 0x22, 0x48, 0x87, 0x85, 0x85, 0x03, 0xda, 0xbc,
+ 0xbc, 0x7c, 0x04, 0x69, 0x89, 0x44, 0x82, 0x84, 0x80, 0x72, 0x0c, 0xfd, 0x24, 0xa1, 0x7d, 0xc6,
+ 0x05, 0x00, 0xe0, 0x5d, 0x88, 0x8b, 0x18, 0x7f, 0x7d, 0x7c, 0x7c, 0x80, 0x2b, 0x92, 0x24, 0xca,
+ 0x76, 0xd4, 0x44, 0x8f, 0xaf, 0x51, 0x54, 0x77, 0x34, 0x16, 0x53, 0x22, 0x97, 0x4b, 0xbd, 0xbd,
+ 0xb8, 0x62, 0x89, 0xb5, 0x9d, 0x9d, 0x09, 0x8e, 0x8e, 0xae, 0x28, 0xc2, 0xf3, 0x51, 0xf7, 0xa1,
+ 0x22, 0x2b, 0x2d, 0x2d, 0x45, 0x69, 0x86, 0x72, 0xcc, 0xd1, 0xd1, 0x11, 0xd0, 0x92, 0xf1, 0xe0,
+ 0x19, 0x17, 0x00, 0x80, 0xa1, 0xc1, 0xc1, 0x3c, 0x3c, 0x3c, 0x30, 0x0a, 0x23, 0x09, 0x04, 0x05,
+ 0x05, 0x61, 0x08, 0x7e, 0xac, 0x8d, 0x9a, 0x98, 0x9b, 0xf3, 0xa4, 0xd2, 0xb0, 0x98, 0x98, 0xf8,
+ 0xf4, 0xf4, 0xa8, 0xc4, 0x44, 0x45, 0x70, 0x30, 0x57, 0x2c, 0xa6, 0xd0, 0x68, 0x20, 0x59, 0x7f,
+ 0x31, 0x90, 0x89, 0x94, 0x92, 0x9d, 0x9d, 0x53, 0x51, 0x51, 0x81, 0x5c, 0xed, 0xe2, 0x22, 0xb5,
+ 0xb7, 0xa7, 0xa3, 0x6f, 0x8f, 0x32, 0xf7, 0x4b, 0xca, 0x20, 0x45, 0xc4, 0x57, 0xa4, 0x44, 0xb1,
+ 0x58, 0xac, 0x56, 0xab, 0x4b, 0x4b, 0xcb, 0x30, 0x04, 0x03, 0xe0, 0xc7, 0xdd, 0x2e, 0xc2, 0x80,
+ 0x1b, 0xfc, 0x3c, 0x37, 0xaf, 0xaa, 0xa6, 0x66, 0x04, 0xea, 0xac, 0x92, 0x92, 0xc8, 0x84, 0x04,
+ 0x99, 0x8f, 0x8f, 0x1d, 0x8b, 0x65, 0xd4, 0xa3, 0xc4, 0x03, 0xa5, 0x28, 0xc4, 0xca, 0xca, 0xb4,
+ 0x7d, 0x73, 0x76, 0x16, 0xa3, 0xb7, 0x88, 0x2b, 0xe4, 0xec, 0xc1, 0x33, 0x28, 0x22, 0x0f, 0x58,
+ 0x59, 0x59, 0x71, 0xb9, 0xdc, 0xc0, 0xc0, 0xc0, 0xa2, 0xa2, 0xe2, 0xcc, 0xcc, 0xcc, 0x27, 0x80,
+ 0x2b, 0x44, 0xb1, 0xb1, 0xf1, 0x0b, 0x0b, 0x2d, 0x19, 0x36, 0x6c, 0xca, 0xb4, 0xe9, 0xb3, 0x5e,
+ 0x9d, 0x3d, 0xe1, 0xc5, 0x29, 0xc3, 0x46, 0x8c, 0x48, 0xcc, 0xc8, 0x80, 0xd9, 0x32, 0xf8, 0x3c,
+ 0xa3, 0x1e, 0xf9, 0x19, 0x79, 0xa0, 0xa0, 0xa0, 0x00, 0x09, 0x21, 0x38, 0x38, 0x18, 0x61, 0x1b,
+ 0x91, 0x9b, 0x0c, 0xb4, 0xcf, 0xa0, 0x60, 0x53, 0x18, 0x61, 0x01, 0x03, 0xe2, 0x62, 0x5a, 0x5a,
+ 0x5a, 0x65, 0x65, 0xa5, 0x9d, 0x9d, 0xdd, 0x93, 0x68, 0x78, 0xf0, 0x60, 0xaa, 0x83, 0x03, 0x22,
+ 0x41, 0xcd, 0xe8, 0xd1, 0xaf, 0xce, 0x79, 0x6d, 0xfe, 0xc2, 0x45, 0xb3, 0x5f, 0x9b, 0x3b, 0x61,
+ 0xf2, 0xe4, 0x8a, 0xea, 0xea, 0xc4, 0x8c, 0x4c, 0xdf, 0x90, 0x10, 0x06, 0x9f, 0x6f, 0xd4, 0x35,
+ 0x45, 0x03, 0x4e, 0x0e, 0x87, 0x53, 0x5c, 0x5c, 0x92, 0x93, 0x93, 0xe3, 0xef, 0xef, 0xcf, 0x66,
+ 0x73, 0x10, 0x68, 0xc9, 0xa9, 0x83, 0x67, 0x4d, 0xd8, 0xe3, 0x30, 0x2b, 0x91, 0x48, 0x14, 0x11,
+ 0x11, 0x39, 0x7c, 0x78, 0x95, 0xa7, 0xa7, 0xe7, 0x93, 0x69, 0x77, 0xf0, 0x90, 0x21, 0xf6, 0x6c,
+ 0xb6, 0x3a, 0x29, 0xe9, 0xf9, 0xf1, 0xe3, 0xe7, 0xbe, 0xfe, 0xc6, 0xeb, 0xf3, 0xe6, 0xbf, 0x3c,
+ 0x6b, 0xd6, 0xd8, 0x09, 0x13, 0x2b, 0x47, 0x8e, 0xcc, 0x2a, 0x28, 0x50, 0xc5, 0xc6, 0xba, 0x29,
+ 0x14, 0x34, 0x16, 0x6b, 0x48, 0xd7, 0x78, 0x80, 0xe3, 0xcb, 0xdd, 0xdd, 0x1d, 0x55, 0x61, 0x4a,
+ 0x4a, 0x0a, 0x22, 0x37, 0x9d, 0x4e, 0x47, 0x6d, 0x48, 0x66, 0x83, 0x67, 0x47, 0xd8, 0xd7, 0xd8,
+ 0xe3, 0x30, 0x58, 0x6f, 0x6f, 0xef, 0xec, 0xec, 0xec, 0x92, 0x92, 0x92, 0x27, 0xf0, 0x19, 0xc1,
+ 0xaf, 0x4d, 0x1b, 0x19, 0x39, 0xf2, 0x78, 0xf1, 0xa9, 0x69, 0xcf, 0x8f, 0x1b, 0xff, 0x97, 0x99,
+ 0x33, 0x27, 0x4e, 0x99, 0x52, 0x3b, 0xe6, 0xb9, 0x92, 0xca, 0xca, 0xf4, 0xbc, 0x3c, 0x60, 0x1c,
+ 0xa0, 0x52, 0x49, 0xbd, 0xbd, 0xe9, 0x3c, 0x27, 0xe3, 0x1e, 0xf9, 0x04, 0x1d, 0x8e, 0x8a, 0x8a,
+ 0x2a, 0x2f, 0xd7, 0x56, 0x61, 0x42, 0xa1, 0xd0, 0xc6, 0xc6, 0xc6, 0xb4, 0xb7, 0x99, 0x31, 0x52,
+ 0x06, 0x29, 0x94, 0xdb, 0x48, 0xb0, 0x7c, 0x3e, 0x5f, 0xa5, 0x52, 0x21, 0x0f, 0x78, 0x78, 0xc8,
+ 0x9f, 0xd8, 0xae, 0x1f, 0x62, 0x6c, 0xcc, 0x12, 0x0a, 0xe3, 0xd3, 0xd2, 0x86, 0xd7, 0xd4, 0x54,
+ 0xd5, 0xd6, 0xe6, 0x97, 0x95, 0x25, 0x65, 0x66, 0xa9, 0xe2, 0xe2, 0x7c, 0x95, 0x4a, 0xed, 0x64,
+ 0x97, 0x44, 0x4c, 0x63, 0xb3, 0xcc, 0xa9, 0xd4, 0xc1, 0x5d, 0xe7, 0x0d, 0x08, 0xc1, 0x5a, 0x8b,
+ 0x8a, 0x8a, 0xf2, 0xf2, 0xf2, 0x14, 0x0a, 0x05, 0x93, 0xc9, 0x44, 0xea, 0x26, 0xe7, 0x0d, 0x9e,
+ 0x05, 0x01, 0x4e, 0xb8, 0x13, 0x52, 0xab, 0x4c, 0x26, 0x43, 0x82, 0xcd, 0xcf, 0x2f, 0xa0, 0xd1,
+ 0x68, 0x4f, 0xac, 0x75, 0x10, 0xcb, 0x14, 0x0a, 0x22, 0xe2, 0xe3, 0xd3, 0x73, 0xf3, 0x62, 0x53,
+ 0x52, 0x03, 0x23, 0x22, 0x64, 0xbe, 0x3e, 0x4e, 0x2e, 0x12, 0x5b, 0x0e, 0x7b, 0x28, 0xcd, 0xc6,
+ 0xc4, 0xc2, 0x42, 0xcb, 0xea, 0x43, 0x0e, 0x1f, 0xf4, 0x1c, 0x83, 0x42, 0x75, 0x75, 0xb5, 0x5a,
+ 0xad, 0x16, 0x8b, 0xc5, 0xe8, 0x36, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x51, 0x73, 0xb1, 0x58,
+ 0xac, 0x80, 0x80, 0x80, 0xd2, 0xd2, 0x32, 0xa5, 0x52, 0xf9, 0xc4, 0x22, 0xc1, 0xa0, 0xce, 0x54,
+ 0x40, 0x77, 0x72, 0x52, 0x84, 0x84, 0xf8, 0x84, 0x84, 0x88, 0xe5, 0x72, 0x3b, 0x27, 0xae, 0x85,
+ 0x0d, 0xd5, 0x18, 0xe0, 0xc1, 0x2d, 0x1f, 0x81, 0x3d, 0x13, 0x13, 0x13, 0xe2, 0xd2, 0x06, 0x3f,
+ 0x3f, 0x3f, 0x6c, 0x02, 0x69, 0xb3, 0xcf, 0x82, 0xb0, 0x8b, 0x29, 0x14, 0x8a, 0x40, 0x20, 0x8c,
+ 0x8e, 0x8e, 0x06, 0xb1, 0x02, 0x81, 0xe0, 0x49, 0xb6, 0x8e, 0xca, 0xcb, 0xd2, 0xd6, 0x96, 0x21,
+ 0xe0, 0x5b, 0x3b, 0x38, 0x18, 0x0d, 0xe8, 0x93, 0x35, 0x0e, 0x87, 0x53, 0x57, 0x37, 0x3a, 0x2e,
+ 0x2e, 0xce, 0xc5, 0xc5, 0x05, 0x36, 0x4b, 0xce, 0x74, 0x19, 0xb6, 0xb0, 0x73, 0xb1, 0x8b, 0x6d,
+ 0x6c, 0x68, 0xae, 0xae, 0xae, 0xa9, 0x5a, 0xa5, 0x3d, 0xa1, 0x49, 0xad, 0xae, 0x3d, 0xd0, 0x4e,
+ 0x05, 0x0c, 0x14, 0x33, 0x1c, 0x71, 0x59, 0x59, 0x59, 0x85, 0x85, 0x85, 0x84, 0xcd, 0x62, 0xbc,
+ 0x20, 0x27, 0x0d, 0x0c, 0x58, 0x44, 0x88, 0x45, 0x09, 0xe3, 0xed, 0xad, 0x40, 0x82, 0x8d, 0x88,
+ 0x88, 0x7c, 0x8c, 0x67, 0xbc, 0x3c, 0x1e, 0x61, 0x13, 0x24, 0x12, 0x49, 0x55, 0xd5, 0x08, 0x8c,
+ 0x11, 0x22, 0x91, 0x88, 0x4a, 0xa5, 0x1a, 0xf7, 0x56, 0xa6, 0x91, 0x32, 0x0c, 0x11, 0xf3, 0x5a,
+ 0xb0, 0xa6, 0xe0, 0xe0, 0xe0, 0xe2, 0xe2, 0x62, 0x5f, 0x5f, 0xdf, 0x3f, 0xe3, 0x90, 0x6a, 0x6d,
+ 0x6d, 0x9d, 0x9d, 0x9d, 0x0d, 0xa7, 0x95, 0xcb, 0xe5, 0x38, 0xfa, 0x70, 0xd0, 0xfd, 0x19, 0xb7,
+ 0x82, 0xd4, 0xa3, 0x08, 0xc4, 0x5a, 0x5a, 0x5a, 0xf2, 0x78, 0xbc, 0xc8, 0xc8, 0x28, 0x78, 0xac,
+ 0x44, 0xe2, 0xf2, 0xb4, 0x7b, 0x34, 0x10, 0xc1, 0x54, 0x71, 0xac, 0x55, 0x54, 0x54, 0xe0, 0xb8,
+ 0x43, 0xac, 0x45, 0xfd, 0x45, 0x06, 0x03, 0x43, 0x15, 0x31, 0x13, 0xeb, 0xec, 0xec, 0x9c, 0x90,
+ 0x90, 0x90, 0x93, 0x93, 0x03, 0xb3, 0x7d, 0xda, 0x3d, 0x1a, 0xa0, 0x9c, 0x9c, 0x9c, 0x0a, 0x0b,
+ 0x8b, 0x62, 0x63, 0xe3, 0x9c, 0x9d, 0xc5, 0xb0, 0x5c, 0x32, 0x18, 0x18, 0xaa, 0xb0, 0x67, 0x6d,
+ 0x6c, 0x6c, 0x50, 0x76, 0xa5, 0x77, 0xca, 0xca, 0xca, 0xfa, 0x69, 0xf7, 0x68, 0x80, 0xb2, 0xb4,
+ 0xa4, 0xc4, 0xc6, 0xc6, 0xe2, 0xa0, 0x23, 0x2e, 0x3f, 0x27, 0x27, 0x66, 0x0d, 0x52, 0xc4, 0x44,
+ 0x81, 0xad, 0xad, 0xad, 0x87, 0x87, 0x47, 0x4e, 0x4e, 0x6e, 0x62, 0x62, 0xe2, 0x9f, 0x77, 0x32,
+ 0x13, 0xdb, 0x82, 0x60, 0x80, 0x28, 0x1e, 0x12, 0x12, 0xc2, 0x66, 0xb3, 0xc9, 0x19, 0x03, 0x83,
+ 0x14, 0xf6, 0x32, 0x8a, 0x14, 0x7b, 0x7b, 0x7b, 0x85, 0x42, 0x51, 0x50, 0x50, 0x10, 0x1d, 0xad,
+ 0x7e, 0xda, 0x3d, 0xfa, 0xaf, 0x24, 0x14, 0x0a, 0xf3, 0xf2, 0xf2, 0x63, 0x62, 0x62, 0xf0, 0x03,
+ 0x85, 0x42, 0xf9, 0xf3, 0x1e, 0x7d, 0xa4, 0x1e, 0x26, 0x10, 0x4b, 0x9c, 0x00, 0xe3, 0xef, 0xef,
+ 0x0f, 0x77, 0x0a, 0x0f, 0x57, 0xfd, 0xce, 0x0a, 0x80, 0xc0, 0xc2, 0xc2, 0x94, 0x42, 0x31, 0xb6,
+ 0xb0, 0x18, 0xf4, 0xc7, 0x39, 0xd8, 0x60, 0x23, 0x23, 0x1b, 0x3a, 0xdd, 0x45, 0x26, 0xf3, 0x0b,
+ 0x0c, 0xf4, 0xf6, 0xf7, 0x67, 0x70, 0xb9, 0xc6, 0x03, 0xba, 0xae, 0x1c, 0xf1, 0x95, 0xc8, 0x36,
+ 0x08, 0x39, 0x88, 0x3a, 0xe4, 0x47, 0x09, 0x86, 0x27, 0xe2, 0x9c, 0x58, 0x26, 0x93, 0x85, 0x91,
+ 0xb4, 0xb4, 0xb4, 0x34, 0x28, 0x28, 0xa8, 0xef, 0xe5, 0x8d, 0xcd, 0xcd, 0xed, 0xb9, 0x5c, 0x81,
+ 0x9b, 0x9b, 0x58, 0xee, 0x21, 0x90, 0x4a, 0x81, 0xd9, 0x1f, 0xc2, 0x2d, 0xb8, 0xa2, 0xd0, 0x68,
+ 0x7e, 0xca, 0xd0, 0xca, 0xea, 0x91, 0x53, 0x67, 0xcc, 0x18, 0x3f, 0x71, 0x52, 0x4e, 0x41, 0x01,
+ 0x97, 0xcf, 0x1f, 0xdc, 0xcf, 0x37, 0xc7, 0xe6, 0xc0, 0x60, 0xf3, 0xf3, 0xf3, 0x31, 0x64, 0x90,
+ 0x73, 0x5c, 0x06, 0x29, 0xec, 0xe2, 0xa1, 0x43, 0x87, 0xb2, 0xd9, 0x9c, 0xb0, 0xb0, 0x30, 0x10,
+ 0x8b, 0x1d, 0xfd, 0x3b, 0xcb, 0x1b, 0x19, 0xd1, 0x1c, 0x1d, 0x65, 0x3e, 0xbe, 0x11, 0x71, 0xf1,
+ 0xa9, 0xd9, 0x39, 0xf1, 0x29, 0xa9, 0x52, 0x4f, 0x4f, 0xf3, 0x81, 0x5e, 0xa7, 0x40, 0xdc, 0x75,
+ 0x56, 0x77, 0xe7, 0x58, 0xf8, 0x2a, 0xde, 0x4a, 0x19, 0x19, 0x39, 0x79, 0xea, 0xd4, 0xd9, 0xaf,
+ 0xcd, 0x1d, 0x37, 0x61, 0x92, 0x4c, 0xee, 0x69, 0xd4, 0xcf, 0x92, 0xdf, 0xc7, 0xc7, 0x07, 0x83,
+ 0x85, 0x52, 0xa9, 0x64, 0xb1, 0xd8, 0xe4, 0x1c, 0x97, 0xe1, 0x89, 0x20, 0x96, 0xc3, 0xe1, 0x22,
+ 0x0f, 0x80, 0x58, 0x99, 0x4c, 0xf6, 0x28, 0x6b, 0x59, 0x52, 0xa9, 0x6e, 0x5e, 0x5e, 0x29, 0x59,
+ 0x59, 0xb5, 0x63, 0xc6, 0x0c, 0x1f, 0x39, 0x32, 0x20, 0x34, 0x74, 0xa8, 0x95, 0xd5, 0xa3, 0x7f,
+ 0xc6, 0x0a, 0x3e, 0xa9, 0x36, 0x36, 0x5c, 0x27, 0x27, 0x4f, 0x2f, 0x2f, 0x55, 0x44, 0x44, 0x4c,
+ 0x6c, 0x6c, 0x58, 0x78, 0xb8, 0xbb, 0xbb, 0x3b, 0x8f, 0xc7, 0x83, 0x31, 0x82, 0x5b, 0x3b, 0x3a,
+ 0xbd, 0xa8, 0xb4, 0x74, 0xd6, 0x9c, 0x39, 0xf5, 0x93, 0x5e, 0xe4, 0x8b, 0x44, 0xfd, 0xf2, 0x49,
+ 0xbc, 0x09, 0x36, 0x44, 0xad, 0x56, 0xf3, 0xf9, 0x02, 0x2b, 0x2b, 0x2b, 0x72, 0x8e, 0xcb, 0xc0,
+ 0xa4, 0x23, 0x56, 0xa5, 0x52, 0x95, 0x94, 0x94, 0xb8, 0xb8, 0x48, 0x7b, 0x5d, 0x0c, 0xcc, 0x58,
+ 0x53, 0xa9, 0x60, 0x4c, 0x20, 0x10, 0xa0, 0x0c, 0xb7, 0xb2, 0xb6, 0xc6, 0x8a, 0x0e, 0x6c, 0x76,
+ 0x74, 0x7c, 0xfc, 0xc8, 0xba, 0xba, 0xe1, 0x35, 0x35, 0x9e, 0xfe, 0xfe, 0x26, 0x8f, 0xf6, 0xd9,
+ 0x2e, 0x9a, 0x53, 0xf8, 0xfa, 0x96, 0x95, 0x57, 0xbc, 0xfc, 0xca, 0x5f, 0x5f, 0x7f, 0x7d, 0xde,
+ 0xc2, 0x85, 0x8b, 0x16, 0x2e, 0x5a, 0xbc, 0x60, 0xd1, 0xa2, 0x37, 0xe6, 0xcd, 0x7b, 0x75, 0xf6,
+ 0x9c, 0xb1, 0xe3, 0xc6, 0x85, 0x28, 0x95, 0x54, 0x2a, 0xd5, 0xd6, 0xde, 0x3e, 0xaf, 0xa8, 0x68,
+ 0xd6, 0xec, 0x39, 0x25, 0x95, 0x95, 0xfd, 0xf2, 0x70, 0x14, 0x5c, 0x20, 0x36, 0x25, 0x25, 0x45,
+ 0x22, 0x91, 0x10, 0x51, 0xf6, 0xd1, 0xd7, 0x25, 0xf5, 0xbf, 0x2f, 0x3d, 0x62, 0x23, 0x30, 0x98,
+ 0x3a, 0x3b, 0x3b, 0xf7, 0x5c, 0x06, 0x36, 0xe5, 0x21, 0x97, 0xe7, 0x17, 0x14, 0x00, 0xa7, 0x49,
+ 0x93, 0x26, 0x3f, 0xf7, 0xfc, 0x0b, 0x45, 0xc5, 0x25, 0xd1, 0xd1, 0x6a, 0x1a, 0x8d, 0x66, 0x6e,
+ 0x61, 0x11, 0x1c, 0x16, 0x56, 0x33, 0x7a, 0x74, 0x4e, 0x51, 0x11, 0x1b, 0xb1, 0xf3, 0xf7, 0xcc,
+ 0x10, 0x6d, 0x65, 0x66, 0x65, 0x81, 0xcc, 0xbf, 0x37, 0x34, 0xac, 0x5e, 0xb5, 0x7a, 0xfd, 0xba,
+ 0x0d, 0xff, 0xd4, 0xea, 0xff, 0xf0, 0x67, 0xc3, 0x86, 0x0f, 0xd7, 0xae, 0xfd, 0x60, 0xc5, 0x8a,
+ 0x15, 0x00, 0x38, 0x27, 0x27, 0xc7, 0xde, 0xde, 0xde, 0x91, 0xc1, 0x2c, 0x1f, 0x3e, 0x1c, 0x09,
+ 0x41, 0xda, 0x9f, 0xeb, 0x77, 0xd0, 0x87, 0xdc, 0xdc, 0xdc, 0xec, 0xec, 0x6c, 0x77, 0x77, 0x0f,
+ 0x3b, 0x3b, 0x7b, 0x72, 0x56, 0xd6, 0xc0, 0x44, 0x10, 0xcb, 0xe5, 0x3a, 0x81, 0xd8, 0xa2, 0xa2,
+ 0xa2, 0x9e, 0xe7, 0x19, 0x62, 0x77, 0x2b, 0x7c, 0x7c, 0xa6, 0x4e, 0x9b, 0xf6, 0xee, 0xdf, 0x1b,
+ 0x56, 0xaf, 0x5e, 0xb3, 0x4e, 0xab, 0xf5, 0xab, 0xd7, 0xac, 0x05, 0x72, 0x63, 0xc6, 0x8c, 0xe1,
+ 0x72, 0xb9, 0x14, 0x6b, 0x6b, 0x95, 0x5a, 0x9d, 0x55, 0x58, 0x24, 0xf7, 0xf7, 0x37, 0xea, 0xd3,
+ 0xd0, 0xcc, 0xcd, 0xcd, 0x73, 0xf3, 0xf2, 0x1a, 0x1a, 0xde, 0xfb, 0xe8, 0xa3, 0x7f, 0x6e, 0xdd,
+ 0xfa, 0xc5, 0xb7, 0xdf, 0x7c, 0xbb, 0x7b, 0xf7, 0xee, 0xbd, 0x7b, 0xf7, 0xee, 0xdb, 0xb7, 0x0f,
+ 0x7f, 0xef, 0xd9, 0xbd, 0x7b, 0xe7, 0x8e, 0x1d, 0xdb, 0xb7, 0x6f, 0xff, 0xf4, 0xb3, 0x4d, 0x0d,
+ 0x0d, 0x0d, 0x59, 0x59, 0x39, 0xe8, 0x18, 0x83, 0xc5, 0xca, 0x29, 0x2c, 0x8c, 0x4a, 0x4c, 0x34,
+ 0xeb, 0x8f, 0xcd, 0xaa, 0xd5, 0x31, 0x85, 0x85, 0x45, 0x08, 0xb4, 0x8e, 0x8e, 0x8e, 0x68, 0x94,
+ 0x24, 0xd6, 0x90, 0xa4, 0x4f, 0x6c, 0x01, 0xca, 0x73, 0x2e, 0xb7, 0xdb, 0x02, 0x70, 0xdd, 0x17,
+ 0xa7, 0x4c, 0x59, 0xbb, 0x76, 0xed, 0xd6, 0xad, 0x5b, 0x77, 0xee, 0xdc, 0x09, 0xb6, 0xf6, 0xef,
+ 0xd3, 0x6a, 0xe7, 0xae, 0x5d, 0x9b, 0x3f, 0xdf, 0x3c, 0x7d, 0xc6, 0x0c, 0x07, 0x07, 0x07, 0x3a,
+ 0x83, 0xe1, 0x19, 0x10, 0xe8, 0x2c, 0x93, 0x0d, 0xe9, 0xf3, 0x3c, 0xf0, 0xb4, 0xf4, 0xf4, 0xf7,
+ 0x97, 0x2f, 0xff, 0xfa, 0xeb, 0xaf, 0x0f, 0x35, 0x36, 0x36, 0x35, 0x35, 0x9d, 0x38, 0x71, 0xe2,
+ 0xf4, 0xe9, 0xd3, 0x67, 0xce, 0x9c, 0x39, 0x8b, 0x3f, 0xa7, 0xcf, 0x9c, 0x3a, 0x75, 0xea, 0xc4,
+ 0x89, 0x93, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0xc3, 0x87, 0x77, 0x7c, 0xfb, 0xed, 0xd2, 0x65, 0xcb,
+ 0x94, 0xca, 0x50, 0xc0, 0x66, 0x4b, 0xa7, 0xfb, 0x84, 0x84, 0xd8, 0x31, 0x99, 0x8f, 0xbe, 0x51,
+ 0x0a, 0x85, 0x4f, 0x59, 0x59, 0x79, 0x60, 0x60, 0x20, 0x71, 0x82, 0x37, 0x59, 0x7c, 0x19, 0x92,
+ 0xba, 0x11, 0x8b, 0x8c, 0xaa, 0xff, 0xea, 0x50, 0x4b, 0xcb, 0xbc, 0xfc, 0x7c, 0x8c, 0xda, 0xfb,
+ 0xf7, 0x1f, 0xf8, 0xe1, 0x87, 0x1f, 0xce, 0x9d, 0x3d, 0x77, 0xe1, 0xfc, 0x85, 0x4b, 0x17, 0x2f,
+ 0x35, 0x5f, 0x6e, 0xbe, 0x74, 0xe9, 0xd2, 0xb9, 0x33, 0x67, 0x41, 0xd7, 0xcc, 0x99, 0x33, 0x11,
+ 0x1d, 0x8d, 0xcd, 0xcd, 0x8d, 0x7a, 0xdc, 0x77, 0x48, 0x5f, 0x48, 0xa7, 0xcb, 0x97, 0x2f, 0xc7,
+ 0xf2, 0x17, 0x2e, 0x5c, 0xb8, 0x7a, 0xf5, 0x6a, 0x6b, 0x6b, 0x6b, 0xfb, 0xcd, 0x9b, 0x37, 0x35,
+ 0xd0, 0x2d, 0xfc, 0x7b, 0xb3, 0xfd, 0x66, 0x7b, 0x7b, 0x7b, 0x6b, 0x6b, 0xdb, 0xb5, 0x6b, 0xd7,
+ 0x5b, 0xae, 0x5c, 0x39, 0x7b, 0xf6, 0xec, 0xc1, 0x83, 0x07, 0x17, 0x2c, 0x58, 0x88, 0xe3, 0x45,
+ 0x7b, 0x17, 0x05, 0x33, 0x33, 0x53, 0x4b, 0xcb, 0x47, 0xdf, 0x28, 0x91, 0x48, 0x54, 0x55, 0x35,
+ 0x22, 0x3c, 0x3c, 0xdc, 0xc9, 0xc9, 0x89, 0xb8, 0xcd, 0xd1, 0xc0, 0xff, 0x83, 0x48, 0xfd, 0x8f,
+ 0xa9, 0x6f, 0x8f, 0x95, 0x48, 0x5c, 0xd6, 0xac, 0x5e, 0x7b, 0xfc, 0xd8, 0xf1, 0xcb, 0x97, 0x9b,
+ 0x5b, 0xdb, 0xda, 0x6f, 0xdd, 0xba, 0xd5, 0xd1, 0xd1, 0x71, 0xfb, 0xf6, 0xed, 0x3b, 0x9d, 0xc2,
+ 0x4f, 0x00, 0x0e, 0xdc, 0x8e, 0x1f, 0x37, 0xbe, 0xef, 0x1b, 0x71, 0xd0, 0x68, 0xb6, 0xd3, 0xa6,
+ 0x4f, 0x87, 0xa9, 0x02, 0xcb, 0x3b, 0x77, 0xef, 0xde, 0xbb, 0x7f, 0xff, 0xff, 0x7b, 0x08, 0x4f,
+ 0xdd, 0xbf, 0x7f, 0xff, 0xde, 0xbd, 0x7b, 0x78, 0xf7, 0x5b, 0x9a, 0x5b, 0x2d, 0x2d, 0x2d, 0xfb,
+ 0xf7, 0xef, 0x2f, 0x29, 0x29, 0x1d, 0xc0, 0x0d, 0x94, 0xe8, 0x74, 0x7a, 0x4d, 0x4d, 0x6d, 0x74,
+ 0x74, 0x34, 0x42, 0x8e, 0x95, 0x95, 0x15, 0x49, 0xac, 0x21, 0xa9, 0x8f, 0x1c, 0x8b, 0x82, 0x2b,
+ 0x2d, 0x2d, 0x0d, 0xc3, 0x74, 0x7b, 0xfb, 0xcd, 0x3b, 0x77, 0xee, 0xde, 0xef, 0x0d, 0x33, 0xe8,
+ 0xee, 0xbd, 0x7b, 0xf0, 0xc3, 0x90, 0x90, 0x90, 0x3e, 0x5a, 0x89, 0x8a, 0x8a, 0x3e, 0x78, 0xb0,
+ 0xf1, 0x97, 0x8e, 0x8e, 0x5e, 0xdf, 0xa1, 0x57, 0x01, 0xec, 0xab, 0x57, 0xaf, 0x6d, 0xde, 0xbc,
+ 0x05, 0x25, 0x7f, 0x7f, 0x37, 0xca, 0xcc, 0xcc, 0xac, 0xae, 0x6e, 0x74, 0x6c, 0x6c, 0x2c, 0x2c,
+ 0xda, 0xda, 0xda, 0x9a, 0x24, 0xd6, 0x90, 0xd4, 0x07, 0xb1, 0x54, 0x2a, 0x75, 0xe9, 0xd2, 0x65,
+ 0x9a, 0x5b, 0xb7, 0x08, 0x56, 0xf1, 0xf7, 0xc9, 0x93, 0x27, 0x8f, 0x1e, 0x3d, 0x8a, 0x31, 0xbd,
+ 0x1b, 0xbd, 0x77, 0xef, 0xde, 0x9d, 0x30, 0x71, 0xe2, 0xc3, 0x6c, 0x16, 0x2e, 0x37, 0x79, 0xf2,
+ 0xe4, 0xd6, 0xb6, 0xb6, 0x6e, 0xc4, 0xc3, 0x4e, 0x31, 0xfa, 0x6f, 0xdb, 0xb6, 0xed, 0xe3, 0x8f,
+ 0x3f, 0xfe, 0xf2, 0xcb, 0x2f, 0xcf, 0x9f, 0x3f, 0x8f, 0x67, 0xba, 0x1d, 0x0b, 0x97, 0x2f, 0x5f,
+ 0xae, 0xaf, 0xaf, 0x1f, 0x00, 0x72, 0xa8, 0x0a, 0xe3, 0xe3, 0xe3, 0xc5, 0x62, 0x31, 0x79, 0x3d,
+ 0x82, 0x81, 0xa9, 0x0f, 0x62, 0x51, 0x52, 0x1d, 0x39, 0x72, 0x84, 0x18, 0xc1, 0x7f, 0xfe, 0xf9,
+ 0xe7, 0x29, 0x53, 0xa6, 0x04, 0x05, 0x05, 0xf9, 0xf9, 0xf9, 0x25, 0x26, 0x26, 0xbe, 0xf3, 0xce,
+ 0x3b, 0xd7, 0xaf, 0x5f, 0xd7, 0xa7, 0xeb, 0xd0, 0xa1, 0x43, 0x52, 0x69, 0xef, 0x73, 0xb9, 0xc0,
+ 0x06, 0x56, 0x09, 0xaa, 0xf5, 0x97, 0xc7, 0xa0, 0x3f, 0x77, 0xee, 0x5c, 0x95, 0x4a, 0xe5, 0xea,
+ 0xea, 0x8a, 0xd8, 0xe9, 0xea, 0xe6, 0xa6, 0x56, 0xab, 0x97, 0x2e, 0x5d, 0x8a, 0xd8, 0xd0, 0xc5,
+ 0x69, 0xef, 0xdc, 0x39, 0x70, 0xe0, 0xc0, 0x00, 0xae, 0xe2, 0x19, 0x33, 0xe6, 0x39, 0x92, 0x58,
+ 0x83, 0x94, 0x3e, 0xb1, 0xdd, 0xe6, 0x63, 0x99, 0x4c, 0x26, 0x40, 0x05, 0x36, 0xbf, 0xfc, 0xf2,
+ 0xcb, 0xd8, 0xb1, 0x63, 0xb1, 0xeb, 0x75, 0xab, 0xd0, 0x68, 0xb4, 0x89, 0x13, 0x27, 0xa2, 0x60,
+ 0xd2, 0xa1, 0x85, 0x88, 0xeb, 0xe7, 0xe7, 0xdf, 0x6b, 0x13, 0x3e, 0x3e, 0xbe, 0x27, 0x4f, 0x9c,
+ 0xd4, 0xb7, 0x65, 0xa4, 0x5f, 0xe0, 0x6a, 0x6b, 0x6b, 0x4b, 0xcc, 0x3b, 0x71, 0xf9, 0xfc, 0x89,
+ 0x93, 0x27, 0x97, 0x57, 0x54, 0x48, 0x5d, 0x5d, 0x97, 0x2c, 0x59, 0x82, 0x9c, 0xac, 0x0f, 0x6d,
+ 0x5b, 0xdb, 0x4d, 0x77, 0x77, 0xf7, 0x7e, 0x6d, 0x14, 0x3c, 0xb9, 0x33, 0x15, 0x10, 0xa7, 0x76,
+ 0x53, 0xc9, 0x54, 0x60, 0x48, 0xd2, 0x27, 0xb6, 0xf3, 0x33, 0xaf, 0xdf, 0x2e, 0x99, 0x61, 0xb3,
+ 0xd9, 0x04, 0x93, 0x1b, 0x37, 0x6e, 0x84, 0x0d, 0x0e, 0xea, 0xcc, 0x09, 0x2f, 0xd4, 0x4f, 0x58,
+ 0xb0, 0x70, 0x71, 0x6a, 0x7a, 0x86, 0x25, 0x85, 0xb2, 0x72, 0xe5, 0x4a, 0x7d, 0x33, 0x0c, 0x08,
+ 0x08, 0x20, 0x56, 0x1c, 0xdc, 0x79, 0x86, 0x80, 0xf6, 0x86, 0x03, 0x9d, 0xd3, 0x4a, 0xc1, 0xc1,
+ 0xc1, 0x3f, 0xb7, 0xb4, 0xe8, 0x96, 0x04, 0xba, 0xc8, 0x00, 0x3c, 0x1e, 0x4f, 0xd7, 0x90, 0xc8,
+ 0xc5, 0x65, 0xd9, 0xfb, 0xcb, 0xd7, 0xad, 0x5f, 0x5f, 0x3f, 0x79, 0x32, 0x5f, 0x20, 0xd8, 0xb5,
+ 0x6b, 0x57, 0xb7, 0xf0, 0xf0, 0xe6, 0x9b, 0x4b, 0xfa, 0xb5, 0x51, 0x36, 0x36, 0x36, 0x64, 0xe5,
+ 0x65, 0xa8, 0x7a, 0x40, 0xac, 0xf6, 0x53, 0xda, 0xd2, 0xd2, 0x32, 0x7d, 0x37, 0x03, 0xb1, 0xa8,
+ 0xd9, 0x01, 0xd8, 0xf4, 0xe9, 0xd3, 0x89, 0x1b, 0x74, 0xdb, 0xd9, 0xdb, 0xbf, 0x31, 0x7f, 0xc1,
+ 0x86, 0x0f, 0x3f, 0x5a, 0xb9, 0x6a, 0x8d, 0x8f, 0xaf, 0x2f, 0x12, 0x02, 0xec, 0xb7, 0x1b, 0xb1,
+ 0x46, 0xc6, 0xc6, 0x0c, 0x2e, 0x57, 0xee, 0xe7, 0xe7, 0x15, 0x14, 0xc4, 0x15, 0x89, 0x2c, 0x28,
+ 0x94, 0xd0, 0xd0, 0xd0, 0xf6, 0xb6, 0xdf, 0xc6, 0x7a, 0x1c, 0x05, 0x33, 0x66, 0xcc, 0xd0, 0xef,
+ 0x03, 0x85, 0x62, 0x55, 0x56, 0x31, 0x6c, 0xe5, 0xaa, 0xd5, 0x6b, 0xd6, 0x7e, 0x10, 0xaa, 0x52,
+ 0xe5, 0xe6, 0xe6, 0xea, 0x47, 0x08, 0x74, 0x60, 0xcb, 0x96, 0x2d, 0xfd, 0xda, 0x28, 0x0e, 0x87,
+ 0xa3, 0x3f, 0xbb, 0x45, 0xce, 0xc7, 0x1a, 0x92, 0xf4, 0xcf, 0x2b, 0x28, 0x2b, 0x2b, 0xd3, 0xbf,
+ 0x9f, 0x21, 0xe1, 0xb1, 0x18, 0xa3, 0xeb, 0xea, 0xea, 0x88, 0x67, 0xc0, 0x6d, 0x76, 0x4e, 0x2e,
+ 0xc0, 0x5a, 0xbf, 0xe1, 0xc3, 0x9a, 0x51, 0xa3, 0x30, 0xac, 0x23, 0xe8, 0x76, 0x23, 0x76, 0x28,
+ 0x85, 0x12, 0x1e, 0x13, 0x53, 0x5e, 0x55, 0x35, 0xbc, 0xb6, 0xb6, 0xb0, 0xbc, 0x22, 0x28, 0x5c,
+ 0x15, 0x19, 0x1d, 0xad, 0x9f, 0x4e, 0x9b, 0x9b, 0x9b, 0x93, 0x92, 0x92, 0xba, 0x75, 0x83, 0xc1,
+ 0x64, 0xd6, 0x4f, 0x98, 0xf8, 0x8f, 0x7f, 0xac, 0x4a, 0xcb, 0xce, 0x41, 0x1a, 0x41, 0x89, 0xa7,
+ 0x6f, 0xb3, 0xfb, 0xf6, 0xef, 0xef, 0xd7, 0x46, 0x49, 0x24, 0x2e, 0x15, 0x15, 0xc3, 0xc8, 0x4b,
+ 0x14, 0x0d, 0x52, 0x7a, 0xe7, 0x6e, 0x85, 0x97, 0x97, 0x97, 0x2b, 0x14, 0x3e, 0xba, 0x97, 0x58,
+ 0x2c, 0x56, 0x5b, 0x5b, 0x7b, 0x47, 0x47, 0x47, 0x6d, 0x6d, 0xad, 0xee, 0x49, 0x07, 0x07, 0xc7,
+ 0xf1, 0xf5, 0x13, 0x40, 0xec, 0xe2, 0x25, 0x7f, 0xa3, 0xd3, 0xe9, 0x2b, 0x56, 0xac, 0x20, 0xa0,
+ 0xea, 0xe8, 0xb8, 0x4d, 0x10, 0x8b, 0x3c, 0xc0, 0xe1, 0xf3, 0xfd, 0x42, 0x42, 0x62, 0x53, 0x52,
+ 0xb2, 0x0a, 0x0b, 0xe3, 0x92, 0x53, 0xa2, 0xe2, 0xe2, 0x5a, 0x5b, 0x5b, 0x75, 0xf8, 0xfd, 0xf4,
+ 0xd3, 0x4f, 0xbd, 0xde, 0xe7, 0x53, 0x20, 0x10, 0xc6, 0xc4, 0xc6, 0x71, 0x9c, 0x78, 0x70, 0xc5,
+ 0x65, 0xcb, 0x96, 0xe9, 0x13, 0x7b, 0xf8, 0xf0, 0xe1, 0x7e, 0x6d, 0x94, 0xa7, 0xa7, 0x17, 0x12,
+ 0x8e, 0xbf, 0xbf, 0x3f, 0xe0, 0xb7, 0xb0, 0xb0, 0x20, 0x3f, 0xa5, 0x35, 0x24, 0xe9, 0x9f, 0x1f,
+ 0x5b, 0x51, 0x51, 0x11, 0x10, 0x10, 0xa8, 0x7b, 0x09, 0xbb, 0xfb, 0x4a, 0xf3, 0x15, 0x0c, 0xd0,
+ 0x63, 0xc6, 0x8c, 0xd1, 0xed, 0x74, 0x2c, 0x1f, 0x9f, 0x90, 0x00, 0x9b, 0x7d, 0xeb, 0xed, 0x77,
+ 0x41, 0xec, 0xbc, 0x79, 0xf3, 0x1e, 0x8c, 0xf5, 0x1a, 0x84, 0x84, 0x5f, 0xd7, 0xd4, 0x7e, 0x4a,
+ 0x65, 0x6a, 0x69, 0x65, 0x45, 0xb3, 0xb3, 0xa3, 0xd2, 0x68, 0x81, 0x41, 0x41, 0x17, 0x2f, 0x5c,
+ 0xd4, 0xe1, 0x77, 0xe6, 0xcc, 0x19, 0x22, 0x15, 0x77, 0x13, 0xf1, 0x5d, 0xa2, 0xc4, 0xed, 0x3e,
+ 0xea, 0xeb, 0xeb, 0xf5, 0x89, 0x6d, 0x6c, 0x6c, 0xec, 0xd7, 0x46, 0xe1, 0xb8, 0x2b, 0x2c, 0x2c,
+ 0x24, 0xcf, 0x2b, 0x30, 0x48, 0xe9, 0x5f, 0x83, 0x80, 0x54, 0xa0, 0x54, 0x2a, 0x75, 0x2f, 0x01,
+ 0xc8, 0xc3, 0x87, 0x0e, 0x23, 0x46, 0xce, 0x9c, 0x39, 0x53, 0xff, 0x83, 0x27, 0x17, 0x37, 0xb7,
+ 0x59, 0xb3, 0x67, 0x4f, 0x7f, 0xe9, 0x65, 0x1a, 0xcd, 0x76, 0xfe, 0xfc, 0xf9, 0x04, 0x54, 0x67,
+ 0xcf, 0x9e, 0xf3, 0xf2, 0xf2, 0x34, 0x31, 0x1a, 0x6c, 0x6a, 0x3c, 0xc4, 0x8c, 0x78, 0x98, 0x68,
+ 0x1f, 0xa6, 0xc6, 0x83, 0x79, 0x4e, 0x9c, 0x55, 0x2b, 0x57, 0xea, 0xe6, 0x0a, 0xce, 0x9d, 0x3b,
+ 0xe7, 0xea, 0xea, 0xda, 0x47, 0x97, 0x8c, 0x8d, 0x8d, 0xab, 0xab, 0xab, 0xf5, 0x89, 0x45, 0x2d,
+ 0xd6, 0xaf, 0x8d, 0x52, 0x28, 0x14, 0x3a, 0x62, 0xc9, 0xcb, 0x10, 0x0c, 0x4c, 0x7d, 0x5c, 0xe7,
+ 0x85, 0x2a, 0xfb, 0xcd, 0x25, 0x7f, 0x43, 0xa9, 0xbe, 0x7e, 0xfd, 0x7a, 0x3e, 0x9f, 0xaf, 0xbf,
+ 0x96, 0x4c, 0x2e, 0x77, 0x76, 0x75, 0xc5, 0x8a, 0x0d, 0x0d, 0x0d, 0x77, 0x7f, 0xd1, 0x68, 0x5a,
+ 0x4e, 0xbc, 0xbf, 0x64, 0xea, 0xa8, 0x34, 0xe1, 0xbc, 0x0a, 0xfe, 0xba, 0x71, 0x92, 0x2f, 0xfe,
+ 0xe2, 0xba, 0xe3, 0xaf, 0x6e, 0x7b, 0xe7, 0xb8, 0xef, 0x9e, 0x2d, 0xdb, 0x50, 0x2f, 0x99, 0x94,
+ 0xc1, 0x9a, 0x3d, 0xa5, 0xe8, 0xe6, 0xe5, 0x63, 0x1d, 0xad, 0x57, 0xee, 0xdf, 0xbf, 0x77, 0xfe,
+ 0xfc, 0xf9, 0xdf, 0xdc, 0xb8, 0x37, 0x81, 0xb1, 0x69, 0xd3, 0xa6, 0xe9, 0x57, 0x5e, 0xeb, 0xd7,
+ 0xad, 0xef, 0xd7, 0x46, 0xb9, 0xbb, 0x7b, 0x60, 0x5b, 0xd0, 0x0a, 0x83, 0xc1, 0x20, 0x53, 0x81,
+ 0x81, 0x89, 0xb8, 0x96, 0x16, 0x76, 0x0a, 0x5f, 0xca, 0xcf, 0x2f, 0x88, 0x8c, 0x8c, 0xd2, 0xbd,
+ 0x04, 0xfb, 0x4d, 0x4e, 0x4e, 0x46, 0xe5, 0x85, 0xe4, 0x19, 0x13, 0x13, 0xd3, 0xb3, 0x7e, 0x31,
+ 0x35, 0x35, 0xd9, 0xb8, 0xfa, 0x9d, 0x8b, 0x3b, 0x17, 0xfd, 0xb8, 0x2a, 0xa4, 0x79, 0xab, 0xa0,
+ 0x75, 0x1f, 0xa7, 0xed, 0x20, 0xab, 0xed, 0x00, 0xab, 0x6d, 0x3f, 0x5b, 0xfb, 0x38, 0xc8, 0xd6,
+ 0xfe, 0x7a, 0x90, 0x7d, 0x7d, 0x0f, 0xb7, 0x79, 0x9b, 0xe0, 0xd4, 0x5a, 0xe9, 0x4f, 0x5f, 0x54,
+ 0xb5, 0xfe, 0xf8, 0xd1, 0xc5, 0x73, 0xa7, 0x7b, 0x56, 0x5e, 0xfa, 0xa2, 0x50, 0x28, 0x9f, 0x7c,
+ 0xf2, 0x89, 0xfe, 0xec, 0xd6, 0x4b, 0x2f, 0xbd, 0xd4, 0xaf, 0x8d, 0x12, 0x8b, 0x25, 0xe5, 0xe5,
+ 0xda, 0x9b, 0xc3, 0xa0, 0x78, 0x24, 0x2b, 0x2f, 0x03, 0x93, 0xee, 0x7e, 0x05, 0x72, 0xb9, 0x3c,
+ 0x27, 0x27, 0x47, 0xad, 0xee, 0x72, 0xf5, 0x37, 0xa2, 0xc2, 0xb5, 0x6b, 0xd7, 0xe0, 0x72, 0x8b,
+ 0x17, 0x2f, 0xb6, 0xb1, 0xb1, 0xe9, 0xba, 0xe2, 0xa0, 0x24, 0x2f, 0x87, 0x03, 0x0d, 0x19, 0xe7,
+ 0x3e, 0x12, 0x5f, 0xdf, 0xc5, 0xbb, 0xb1, 0x87, 0xdb, 0xde, 0xc8, 0xd4, 0x7c, 0xe7, 0xa8, 0x7b,
+ 0xb4, 0x1e, 0x64, 0x5d, 0xda, 0x24, 0xf8, 0x71, 0x95, 0xe8, 0xe4, 0x1a, 0x51, 0xf3, 0x36, 0xa7,
+ 0xf6, 0x43, 0xcc, 0xb6, 0x83, 0xcc, 0xcb, 0x9b, 0x05, 0xe7, 0xf7, 0x4c, 0x7d, 0xa1, 0x24, 0xb6,
+ 0x8f, 0x2e, 0x85, 0x86, 0x86, 0xde, 0xb8, 0x71, 0x43, 0x47, 0xec, 0xed, 0xdb, 0x77, 0xfc, 0xfc,
+ 0x7b, 0xff, 0x6c, 0xe2, 0x61, 0xc2, 0x90, 0x51, 0x55, 0x55, 0xa5, 0x52, 0xa9, 0x78, 0x3c, 0x1e,
+ 0xf8, 0x27, 0x89, 0x35, 0x24, 0x11, 0xc4, 0xd2, 0x68, 0x34, 0x99, 0x4c, 0x96, 0x95, 0x95, 0x15,
+ 0x1b, 0xdb, 0x85, 0x25, 0x17, 0x17, 0x97, 0xaf, 0xbe, 0xda, 0x0e, 0x62, 0xaf, 0x5c, 0xb9, 0x82,
+ 0x64, 0xa8, 0x7b, 0x9e, 0x6a, 0x61, 0x5c, 0x11, 0xc6, 0xfc, 0xea, 0x15, 0xb7, 0x9f, 0x3e, 0x94,
+ 0x1c, 0x59, 0xe2, 0xba, 0xf7, 0x35, 0xb7, 0x43, 0x8b, 0x64, 0x2d, 0x5f, 0xf1, 0x35, 0x47, 0x7e,
+ 0x23, 0xf6, 0xc6, 0x3e, 0x4e, 0xd3, 0xdb, 0xb2, 0x4d, 0xa3, 0xbd, 0x37, 0xd5, 0x79, 0xef, 0x7a,
+ 0xc5, 0xfd, 0xd2, 0x16, 0x1e, 0xf1, 0x3c, 0x2c, 0x77, 0xd7, 0x7b, 0x92, 0xf2, 0x18, 0x7b, 0x5b,
+ 0xcb, 0x5e, 0x4e, 0xff, 0x46, 0xfc, 0xd8, 0xbc, 0x79, 0xb3, 0x7e, 0x88, 0x6d, 0x6d, 0x6d, 0xb3,
+ 0xec, 0xcf, 0xa9, 0x86, 0x83, 0x3a, 0x67, 0xe1, 0x6a, 0x6b, 0x6b, 0x31, 0x2e, 0x88, 0x44, 0xce,
+ 0xe4, 0xed, 0x8c, 0x0c, 0x4f, 0x0f, 0xee, 0x62, 0xe4, 0x96, 0x99, 0x99, 0xd9, 0xed, 0x9e, 0x30,
+ 0x08, 0x0c, 0xe3, 0xc7, 0xd7, 0x13, 0xf3, 0xf9, 0x67, 0xcf, 0x9e, 0xf5, 0xf0, 0xf0, 0xc0, 0x93,
+ 0x5c, 0x9a, 0xf9, 0x94, 0x14, 0xde, 0xee, 0xb9, 0xb2, 0x0b, 0x9f, 0x39, 0x9f, 0xd9, 0x20, 0xfe,
+ 0xb4, 0xd6, 0xfb, 0x93, 0x5a, 0xef, 0xa3, 0x6f, 0x4b, 0x6f, 0xec, 0x65, 0xff, 0x8a, 0xeb, 0x51,
+ 0x86, 0xe6, 0x18, 0xeb, 0xe6, 0x77, 0xac, 0xab, 0x5f, 0x73, 0x8e, 0xbe, 0xe5, 0xbe, 0xf5, 0x05,
+ 0xef, 0x2d, 0xcf, 0x7b, 0x9f, 0x5c, 0x23, 0xbe, 0x79, 0x98, 0x41, 0x2c, 0x00, 0x37, 0x3e, 0xbd,
+ 0x99, 0xbd, 0x69, 0x01, 0xef, 0xc5, 0x4c, 0x8e, 0xb5, 0xc5, 0xaf, 0x38, 0xe1, 0xd8, 0x09, 0x0a,
+ 0x0a, 0xda, 0xb8, 0x71, 0x63, 0x87, 0xde, 0x29, 0x5e, 0x88, 0x04, 0xab, 0x57, 0xaf, 0x31, 0x31,
+ 0xe9, 0xdf, 0x0d, 0xc3, 0xf1, 0x56, 0x23, 0x47, 0x8e, 0x4c, 0x4e, 0x4e, 0x91, 0x4a, 0xa5, 0xc4,
+ 0x0d, 0x90, 0xff, 0xc0, 0xff, 0x2e, 0x52, 0x4f, 0x5d, 0xc4, 0x97, 0x22, 0x75, 0xde, 0x77, 0x2b,
+ 0x23, 0x25, 0x25, 0xa5, 0xdb, 0xf9, 0xa8, 0x88, 0x0a, 0x2d, 0x0f, 0x3e, 0x63, 0x3d, 0xd4, 0xd8,
+ 0x58, 0x99, 0x11, 0xd5, 0x30, 0xdc, 0xf5, 0xd0, 0x22, 0xf7, 0x8b, 0x9f, 0x39, 0x23, 0xa6, 0xb6,
+ 0x7c, 0xe3, 0xd4, 0x38, 0xcf, 0xe3, 0xd4, 0x07, 0xa2, 0xb6, 0x46, 0xc6, 0x03, 0x5c, 0x99, 0x9a,
+ 0xe3, 0x42, 0x4d, 0x93, 0x54, 0xd3, 0x24, 0xd2, 0x7c, 0xc7, 0x6c, 0x3f, 0xc4, 0xb8, 0xb6, 0x8b,
+ 0x73, 0xfe, 0x53, 0xe7, 0xab, 0xdf, 0xf0, 0x34, 0x47, 0x18, 0xfa, 0xb1, 0xe1, 0xe6, 0x61, 0xe6,
+ 0xd5, 0x3d, 0xac, 0xd3, 0x9b, 0x38, 0x7b, 0x97, 0xb8, 0xac, 0x98, 0x18, 0xfe, 0xc1, 0xb2, 0x79,
+ 0xe7, 0xcf, 0xfc, 0xab, 0xe3, 0x56, 0x7b, 0xe7, 0xa9, 0xb2, 0xbf, 0x0a, 0xde, 0xee, 0xed, 0xed,
+ 0x3d, 0x80, 0x8d, 0x2a, 0x28, 0x28, 0xc8, 0xce, 0xce, 0x41, 0xd4, 0xb1, 0xb7, 0xb7, 0x27, 0xa7,
+ 0x0b, 0x0c, 0x4c, 0x04, 0xb1, 0x52, 0xa9, 0x96, 0x58, 0x08, 0xc3, 0xa8, 0xfe, 0xab, 0xa6, 0xa6,
+ 0xa6, 0xb3, 0xe7, 0xcc, 0x41, 0xfd, 0x75, 0xef, 0xce, 0xed, 0xcb, 0x8d, 0x9f, 0xef, 0x7c, 0x45,
+ 0x79, 0xfc, 0x6d, 0xf7, 0x4b, 0x9b, 0xc4, 0xad, 0x07, 0xd8, 0xfa, 0xf8, 0xfd, 0xf6, 0x38, 0xca,
+ 0xd6, 0x34, 0xb9, 0x6a, 0x9a, 0x64, 0x9a, 0x26, 0x89, 0x96, 0xde, 0x5e, 0x97, 0xe9, 0xf1, 0x80,
+ 0xeb, 0x5e, 0xdd, 0xc1, 0x3b, 0xb5, 0x46, 0x7a, 0xfa, 0xb3, 0x51, 0xff, 0xbe, 0xb2, 0x47, 0xd3,
+ 0xfc, 0xfd, 0x9d, 0x7f, 0x6b, 0x80, 0x6b, 0xf5, 0xc8, 0x91, 0x03, 0xfb, 0x4a, 0xdc, 0x88, 0x08,
+ 0xed, 0x69, 0x12, 0xc4, 0x74, 0x01, 0xf9, 0x3d, 0x5f, 0x06, 0xa6, 0x07, 0xc4, 0x4a, 0xd3, 0xd3,
+ 0xd3, 0xe1, 0xa8, 0x3d, 0x6f, 0x29, 0xaf, 0x8e, 0x56, 0xef, 0xdb, 0xf1, 0xf5, 0xb9, 0x1d, 0xeb,
+ 0x76, 0xbc, 0xa4, 0x68, 0x7a, 0x57, 0x76, 0x69, 0x93, 0x73, 0xeb, 0x7e, 0x8e, 0x7e, 0x64, 0xed,
+ 0x4a, 0x2c, 0x57, 0xd3, 0xe4, 0xd6, 0x49, 0xac, 0x73, 0x5f, 0xc4, 0x1e, 0x25, 0x1e, 0x8c, 0xce,
+ 0xc7, 0x83, 0x27, 0x8f, 0x30, 0xda, 0x1b, 0x59, 0x2d, 0x5f, 0x0a, 0x4e, 0xad, 0x0f, 0x6b, 0xde,
+ 0xbf, 0x70, 0xe9, 0xbc, 0x17, 0x79, 0x9c, 0x01, 0xde, 0x1a, 0x14, 0x43, 0xc6, 0x88, 0x11, 0x23,
+ 0x94, 0x4a, 0x25, 0x97, 0xcb, 0x25, 0x2f, 0x9c, 0x31, 0x30, 0x11, 0xc4, 0xa2, 0xc8, 0x4a, 0x4d,
+ 0x4d, 0xcd, 0xcf, 0xcf, 0x87, 0x29, 0x75, 0x5b, 0x80, 0x61, 0x6d, 0xf6, 0xd6, 0xd8, 0xb4, 0x5d,
+ 0xb3, 0x82, 0xbe, 0x7f, 0xcf, 0xfd, 0xd2, 0xe7, 0xc0, 0x95, 0xdd, 0x6d, 0x7c, 0xd7, 0x7b, 0x30,
+ 0x34, 0xc7, 0x05, 0x9d, 0xb8, 0xba, 0x69, 0x8e, 0xf3, 0xb4, 0xbf, 0x3e, 0x0c, 0xd7, 0x63, 0x08,
+ 0x0f, 0x6c, 0xcd, 0x71, 0x8e, 0xe6, 0x38, 0x57, 0xfb, 0x03, 0x7e, 0x3d, 0xaa, 0x67, 0xb9, 0x87,
+ 0x98, 0x2d, 0xdb, 0x79, 0x9b, 0x5e, 0xe3, 0x97, 0xa9, 0x1c, 0xac, 0xcc, 0x07, 0x02, 0x1b, 0x92,
+ 0x79, 0x5d, 0xdd, 0xe8, 0xe8, 0x68, 0xb5, 0x50, 0x28, 0x24, 0x8b, 0x2f, 0x03, 0x53, 0xe7, 0x1d,
+ 0x8f, 0xad, 0xc5, 0x62, 0x71, 0x52, 0x52, 0x52, 0xcf, 0x4b, 0xbd, 0xd8, 0x54, 0xb3, 0xfa, 0x38,
+ 0xa7, 0x6d, 0xd3, 0x3d, 0x9a, 0xde, 0x73, 0xbf, 0xbc, 0xc5, 0x59, 0x1b, 0x06, 0x1e, 0xe6, 0xae,
+ 0x04, 0x8a, 0x08, 0x03, 0x5a, 0x62, 0xa5, 0x9a, 0x63, 0x9c, 0x87, 0xe3, 0xca, 0xd6, 0xf2, 0x8c,
+ 0xa0, 0xdb, 0x24, 0xee, 0x7c, 0x08, 0x34, 0xc7, 0xb8, 0x5a, 0xb3, 0xed, 0xba, 0x64, 0xeb, 0x3e,
+ 0xf6, 0x77, 0x2b, 0x9c, 0x5f, 0x48, 0xe4, 0x18, 0x0f, 0xe9, 0x77, 0x0a, 0x45, 0x12, 0xa8, 0xaa,
+ 0xaa, 0x42, 0x2c, 0x87, 0xd9, 0x92, 0xdf, 0x3e, 0x63, 0x60, 0x22, 0xbe, 0x1a, 0x09, 0x5e, 0x14,
+ 0x17, 0x17, 0x57, 0x58, 0x58, 0x88, 0x1f, 0x74, 0x2f, 0x39, 0x5a, 0x9b, 0x4e, 0x4b, 0x12, 0x6c,
+ 0x9f, 0x21, 0xff, 0xd7, 0x7f, 0xd8, 0xbb, 0x0e, 0xb0, 0xa8, 0xae, 0x75, 0x7b, 0xef, 0x7d, 0xc9,
+ 0x0d, 0x49, 0x3e, 0x9f, 0x06, 0x91, 0x36, 0x74, 0x18, 0xca, 0x30, 0x0d, 0xa9, 0x62, 0x80, 0xa0,
+ 0x51, 0xaa, 0x82, 0x80, 0x28, 0x02, 0x22, 0xd5, 0xf2, 0x14, 0xa3, 0x48, 0x50, 0x6f, 0xf4, 0x25,
+ 0x7a, 0xed, 0x5e, 0x11, 0xa3, 0x80, 0x68, 0xac, 0x80, 0x05, 0xa5, 0x4a, 0x91, 0xde, 0x7b, 0x2f,
+ 0x43, 0x93, 0x3e, 0x94, 0x81, 0xa1, 0xce, 0x00, 0x22, 0xe8, 0x7b, 0xff, 0xcc, 0xd1, 0x09, 0xc2,
+ 0x00, 0x2a, 0x68, 0x84, 0xef, 0xac, 0xef, 0x7c, 0x80, 0x67, 0xce, 0x8c, 0x73, 0xf6, 0x59, 0x67,
+ 0xed, 0xf5, 0xff, 0xfb, 0x3f, 0x7b, 0xdf, 0xc0, 0xb7, 0x45, 0xc9, 0xb2, 0xd4, 0x75, 0x7a, 0x47,
+ 0x0a, 0x2c, 0x65, 0x59, 0x02, 0x10, 0x58, 0x69, 0xee, 0x96, 0xa0, 0x9c, 0x9f, 0x7d, 0x8c, 0x24,
+ 0x3b, 0x34, 0xc3, 0xbd, 0x56, 0x63, 0x20, 0x2d, 0x10, 0x98, 0xdb, 0xf1, 0x70, 0x83, 0x14, 0xf9,
+ 0x2a, 0x2c, 0xfe, 0xe6, 0xbd, 0x15, 0x12, 0xec, 0xf7, 0xc6, 0x8d, 0x1b, 0x37, 0x6f, 0xde, 0x4c,
+ 0x26, 0x2b, 0xf1, 0xf3, 0xf3, 0xa3, 0xc1, 0xd7, 0x42, 0xc2, 0xb8, 0x75, 0x10, 0x56, 0x81, 0xc6,
+ 0x72, 0x9e, 0x04, 0xfc, 0xfa, 0xcb, 0x7f, 0xec, 0xd4, 0x11, 0xc9, 0xf8, 0x8d, 0x5c, 0x79, 0x8d,
+ 0x40, 0x7d, 0x22, 0xdf, 0x9b, 0x23, 0x3a, 0x9d, 0xba, 0x22, 0x5b, 0xa5, 0x04, 0x9b, 0x84, 0x72,
+ 0x53, 0x0a, 0x2c, 0xa8, 0xeb, 0x6b, 0xba, 0x2a, 0x8e, 0xdb, 0xb0, 0x2c, 0x6f, 0xc0, 0xd1, 0xd8,
+ 0x52, 0x81, 0x9e, 0x6c, 0xe1, 0xee, 0x6c, 0x21, 0xf8, 0x83, 0x59, 0x2a, 0x08, 0x51, 0x9e, 0xdd,
+ 0xca, 0x89, 0x46, 0x65, 0x46, 0xc0, 0x6d, 0xa8, 0xa1, 0xa1, 0xe1, 0xe4, 0xe4, 0x8c, 0x8e, 0x7c,
+ 0x2d, 0x3c, 0x20, 0xc5, 0x30, 0x22, 0x22, 0x22, 0x5a, 0x5a, 0xda, 0x56, 0x56, 0x5b, 0x70, 0x38,
+ 0x1c, 0xb2, 0x5f, 0x62, 0xe9, 0xd7, 0x71, 0x07, 0x48, 0x25, 0x5e, 0xc4, 0x86, 0x87, 0x0a, 0x5d,
+ 0x29, 0x52, 0xcc, 0xe2, 0x99, 0x02, 0x7f, 0xf0, 0xa2, 0xac, 0x8e, 0x5e, 0x8e, 0x2d, 0x98, 0xdc,
+ 0x1c, 0x6c, 0x85, 0x30, 0x9b, 0xd2, 0x1c, 0x75, 0x45, 0x04, 0x56, 0x76, 0x90, 0x22, 0x36, 0x5e,
+ 0x60, 0x29, 0x0f, 0xc4, 0x02, 0x1c, 0x88, 0x8f, 0x5d, 0xe5, 0x98, 0x05, 0x2c, 0xf6, 0xd2, 0xe2,
+ 0xa5, 0x0f, 0x1b, 0x8a, 0x4f, 0x7f, 0x0a, 0x5c, 0x21, 0x26, 0x26, 0x86, 0x3c, 0x89, 0x20, 0x25,
+ 0x25, 0x8d, 0x3e, 0x51, 0xbb, 0x90, 0x80, 0xac, 0x8e, 0x24, 0x24, 0x24, 0x04, 0x72, 0xb4, 0x65,
+ 0x8b, 0x35, 0x91, 0xf8, 0xba, 0x78, 0xd5, 0x84, 0xc8, 0x9f, 0xf1, 0x2b, 0x99, 0x72, 0x8d, 0xd0,
+ 0x1a, 0x25, 0xd7, 0x97, 0x37, 0x85, 0x66, 0x8e, 0xdf, 0x28, 0xec, 0xee, 0x7e, 0x8a, 0xfe, 0x9d,
+ 0x1d, 0x6a, 0x49, 0xb0, 0xf8, 0xfc, 0xa7, 0xb4, 0x22, 0x74, 0xfd, 0x53, 0x5d, 0x1b, 0x63, 0x44,
+ 0x73, 0xae, 0x4a, 0x9e, 0xfa, 0x81, 0x78, 0xc9, 0x80, 0x90, 0xeb, 0x2d, 0x31, 0x58, 0x20, 0x08,
+ 0x1a, 0xdb, 0x16, 0x85, 0xdd, 0xaa, 0xf1, 0xde, 0x1a, 0x0b, 0xe0, 0xe3, 0x5b, 0x66, 0x67, 0x67,
+ 0x67, 0x62, 0x62, 0x0a, 0xf7, 0x20, 0x2f, 0x2f, 0x2f, 0x1a, 0x7c, 0x2d, 0x18, 0x20, 0xc5, 0x30,
+ 0x82, 0x82, 0x82, 0xea, 0xea, 0x1a, 0xe0, 0x63, 0x39, 0x53, 0xc8, 0xee, 0x5f, 0x25, 0x9e, 0x73,
+ 0x82, 0x54, 0x73, 0x07, 0x4f, 0x8b, 0x97, 0x61, 0x14, 0x09, 0xbf, 0x13, 0x63, 0x41, 0x2d, 0x2b,
+ 0xb8, 0xda, 0x57, 0x41, 0xd6, 0x4b, 0x6f, 0xd1, 0x15, 0x94, 0x56, 0x8a, 0x65, 0x1e, 0xde, 0xa4,
+ 0x08, 0xaa, 0x1e, 0x89, 0xdd, 0x72, 0x50, 0x3c, 0xa1, 0x43, 0x0a, 0x76, 0xc2, 0x97, 0xdd, 0x92,
+ 0x40, 0x76, 0x32, 0x4b, 0x04, 0x9b, 0x1e, 0xcb, 0x93, 0x45, 0x17, 0x7d, 0xc0, 0x79, 0x81, 0x39,
+ 0x37, 0x32, 0x32, 0xb2, 0xb1, 0xb1, 0x51, 0x51, 0x51, 0x81, 0xb3, 0x43, 0xad, 0xec, 0x82, 0x01,
+ 0xc2, 0x58, 0x01, 0x01, 0x41, 0x35, 0x35, 0x75, 0x5b, 0x5b, 0x56, 0xe9, 0x3e, 0xb2, 0xdf, 0xf5,
+ 0x07, 0xb1, 0xdc, 0x93, 0xa4, 0x67, 0xfe, 0x8a, 0x9d, 0x29, 0x52, 0x8c, 0x92, 0x99, 0x2c, 0x01,
+ 0x6b, 0x64, 0x16, 0x33, 0x58, 0x31, 0x45, 0x3a, 0x8b, 0x45, 0x57, 0xd9, 0x71, 0x66, 0x80, 0xed,
+ 0x1c, 0x38, 0xdc, 0x2e, 0x16, 0xac, 0x09, 0x94, 0xbc, 0x62, 0xa6, 0x78, 0x52, 0x8b, 0x94, 0xea,
+ 0x29, 0xd5, 0x19, 0x2f, 0xca, 0x79, 0x23, 0xa3, 0x50, 0xb8, 0xf2, 0x06, 0x9e, 0x33, 0x92, 0xfb,
+ 0x5e, 0x80, 0xbe, 0x43, 0x59, 0x59, 0xd9, 0xc5, 0xc5, 0x45, 0x47, 0x47, 0x07, 0x5c, 0x3a, 0x9a,
+ 0x95, 0x5d, 0x30, 0x78, 0xc3, 0x58, 0x01, 0x55, 0x55, 0x55, 0xa4, 0xa8, 0x1b, 0xd1, 0x22, 0x43,
+ 0x1c, 0x5f, 0xe6, 0x31, 0x96, 0xc6, 0x76, 0x26, 0x4a, 0x33, 0x8a, 0x67, 0xd2, 0x58, 0x64, 0x44,
+ 0x60, 0x66, 0xba, 0x22, 0x99, 0x81, 0x3f, 0xa5, 0x75, 0xa0, 0x48, 0xd0, 0xdf, 0x0e, 0xff, 0x1f,
+ 0x3d, 0xc2, 0x35, 0x4b, 0x62, 0xf9, 0x1d, 0xa9, 0xfe, 0xc2, 0xb7, 0x38, 0x4f, 0x4f, 0x97, 0xc8,
+ 0x3f, 0x87, 0xff, 0xea, 0xcb, 0x0f, 0x0c, 0x9a, 0xa4, 0xa5, 0xa5, 0xed, 0xed, 0xed, 0x8d, 0x8d,
+ 0x8d, 0xe5, 0xe4, 0xe4, 0x91, 0x89, 0x0b, 0x50, 0x99, 0x5d, 0x00, 0x78, 0xb3, 0x2e, 0x2d, 0x3f,
+ 0x32, 0x1f, 0xbb, 0xae, 0xae, 0x2e, 0x52, 0x3a, 0xc2, 0xbf, 0xe8, 0x9f, 0xd1, 0x6e, 0xa4, 0xb2,
+ 0x2b, 0x44, 0xe8, 0x97, 0x7b, 0xb3, 0x44, 0x99, 0x53, 0x8e, 0x1a, 0xbc, 0x61, 0x2c, 0xf7, 0x70,
+ 0x4c, 0x94, 0x9d, 0x71, 0x45, 0xb8, 0x2a, 0xc7, 0x0e, 0xb2, 0x5e, 0x7f, 0x0e, 0x3d, 0x53, 0xb8,
+ 0x22, 0x50, 0xee, 0xfc, 0x5a, 0xe2, 0x45, 0x3d, 0xc2, 0xd3, 0x23, 0x32, 0x93, 0xdf, 0x3b, 0x50,
+ 0x88, 0x69, 0x7c, 0x24, 0xf7, 0xdb, 0x06, 0x71, 0xae, 0xf9, 0xd8, 0x25, 0xbc, 0xbc, 0xfa, 0xeb,
+ 0x4d, 0x6c, 0xec, 0xed, 0xe5, 0x89, 0x04, 0x9e, 0x29, 0x46, 0x72, 0x21, 0xe0, 0x32, 0x31, 0x31,
+ 0xb1, 0xb6, 0x66, 0x19, 0x03, 0x34, 0xc7, 0xb5, 0x60, 0x80, 0x14, 0x1c, 0x2e, 0x5d, 0xca, 0x47,
+ 0x26, 0x93, 0xad, 0xac, 0xac, 0xd6, 0xac, 0x59, 0x83, 0x0c, 0xe5, 0x7f, 0xfd, 0xe5, 0x7f, 0xed,
+ 0xff, 0x51, 0x2c, 0xfd, 0x28, 0x39, 0xeb, 0x37, 0x72, 0xd5, 0x4d, 0x79, 0x5a, 0xa2, 0xd8, 0x0c,
+ 0xa4, 0xe5, 0x9e, 0x1c, 0x10, 0x63, 0x0d, 0xd7, 0xbe, 0x1e, 0x26, 0x78, 0x2d, 0xad, 0x6c, 0xae,
+ 0x4a, 0x04, 0x6e, 0xc7, 0x9d, 0x59, 0x4d, 0xba, 0xeb, 0xac, 0xd0, 0xfc, 0x40, 0x6a, 0xf2, 0x7b,
+ 0xc1, 0x39, 0x77, 0xc4, 0x49, 0xe7, 0x7b, 0x2a, 0x11, 0xc4, 0xb8, 0xaf, 0x88, 0x27, 0x2a, 0x2e,
+ 0xbe, 0xcb, 0xd5, 0xf5, 0xe7, 0x83, 0x07, 0xdd, 0xdc, 0xdd, 0x7f, 0xd4, 0xd7, 0x17, 0x14, 0x12,
+ 0xfa, 0x62, 0xd2, 0x5c, 0xa0, 0x70, 0x6a, 0x9a, 0x9a, 0x2b, 0x1d, 0x1d, 0x9d, 0xe0, 0x36, 0x44,
+ 0xe7, 0x39, 0x5c, 0x48, 0x80, 0xee, 0x12, 0xa2, 0x69, 0x3c, 0x1e, 0x6f, 0x61, 0x61, 0x61, 0x60,
+ 0x60, 0xb0, 0x68, 0xd1, 0xeb, 0x48, 0x47, 0x5e, 0x78, 0x71, 0xc0, 0xff, 0xa8, 0x64, 0x1c, 0x55,
+ 0x4a, 0xfa, 0x59, 0x29, 0xe3, 0x38, 0xb1, 0xee, 0x91, 0x34, 0x73, 0x46, 0x43, 0xfb, 0xa7, 0xea,
+ 0xf2, 0xb3, 0xeb, 0xb8, 0x44, 0x59, 0x1b, 0x58, 0x5c, 0xb6, 0xb4, 0x32, 0xf2, 0x84, 0xb3, 0xbc,
+ 0xa4, 0xc2, 0xdc, 0xe5, 0xce, 0xea, 0x92, 0xef, 0x3a, 0x29, 0xa4, 0x9c, 0xc7, 0xf6, 0xe5, 0x4f,
+ 0xfc, 0x40, 0xb8, 0x2f, 0x06, 0x0a, 0x85, 0x69, 0xf1, 0x52, 0x15, 0x7e, 0xf8, 0x47, 0xc7, 0x2c,
+ 0x56, 0xaa, 0x2a, 0x71, 0x15, 0x46, 0x21, 0x0c, 0xc6, 0x69, 0xc7, 0x0e, 0x60, 0x2c, 0x6c, 0x07,
+ 0x3c, 0x3c, 0xb6, 0x39, 0x39, 0xad, 0xd0, 0xd6, 0x96, 0x91, 0x95, 0xfd, 0xfa, 0xed, 0xe9, 0xbf,
+ 0x24, 0x25, 0x25, 0xed, 0xec, 0xb6, 0x99, 0x9a, 0x9a, 0x22, 0x95, 0x87, 0xe8, 0x94, 0xdd, 0x0b,
+ 0x03, 0xac, 0xa5, 0x34, 0xd8, 0xc5, 0x30, 0xeb, 0xd7, 0xaf, 0x07, 0xd7, 0x07, 0x57, 0x16, 0xd9,
+ 0x2f, 0x2c, 0xc8, 0x7f, 0x74, 0xbb, 0x79, 0xf4, 0x61, 0xed, 0xcc, 0x5f, 0xc9, 0x09, 0xee, 0x4a,
+ 0x31, 0x6e, 0xe4, 0x62, 0x5f, 0xb9, 0xb6, 0x58, 0xf1, 0xf7, 0x90, 0x59, 0x20, 0x2d, 0x9b, 0xab,
+ 0x1d, 0x29, 0x62, 0xc9, 0xe7, 0x64, 0x42, 0xf6, 0xc9, 0x9f, 0xd6, 0x26, 0xdd, 0xb4, 0xc1, 0xe7,
+ 0xf8, 0x48, 0xb6, 0xc6, 0x4f, 0x1a, 0x41, 0x2b, 0x15, 0x04, 0xc3, 0xdc, 0x93, 0x29, 0x4e, 0x7d,
+ 0x22, 0x5b, 0xea, 0x43, 0x8c, 0x3f, 0x6f, 0x79, 0xcb, 0xfb, 0xc2, 0x81, 0x03, 0xee, 0x5c, 0x13,
+ 0x53, 0xff, 0xbd, 0x64, 0xc9, 0x7a, 0x73, 0x73, 0x77, 0x0f, 0x0f, 0x84, 0xb4, 0x2c, 0xb1, 0xfd,
+ 0xf9, 0x67, 0x97, 0x5d, 0xbb, 0xbe, 0xd7, 0xd5, 0xfd, 0x7a, 0x5c, 0x05, 0x38, 0x0f, 0x0f, 0xcf,
+ 0x86, 0x0d, 0x66, 0x48, 0x1d, 0x17, 0xf2, 0x30, 0x38, 0x3a, 0x94, 0xb0, 0x00, 0x00, 0x8c, 0x05,
+ 0xcb, 0x87, 0xc5, 0x62, 0x0d, 0x0d, 0x0d, 0xc1, 0xf8, 0xf1, 0xf1, 0xf1, 0x21, 0xfb, 0x45, 0x44,
+ 0x45, 0x7f, 0x39, 0x7c, 0xe8, 0xfa, 0xb1, 0xdd, 0xb1, 0xff, 0xfa, 0x3e, 0xfb, 0x38, 0x39, 0xe7,
+ 0x24, 0x31, 0x7c, 0xb7, 0x52, 0xac, 0x07, 0xb1, 0xe1, 0xa1, 0x04, 0xb3, 0xe8, 0xdd, 0x18, 0x5b,
+ 0x2a, 0x40, 0x8d, 0x10, 0x7b, 0xbc, 0x13, 0x77, 0xd5, 0x4a, 0xf1, 0xf4, 0x2a, 0xe2, 0x1f, 0x66,
+ 0x4a, 0x55, 0x8f, 0x44, 0xa9, 0xb1, 0x13, 0xb3, 0xbb, 0xcc, 0x12, 0xc1, 0xfe, 0x7c, 0x0c, 0x3d,
+ 0x55, 0xb2, 0xf5, 0x89, 0x6c, 0xf5, 0x2d, 0x7c, 0xce, 0x39, 0xb5, 0xa4, 0x2b, 0xbb, 0x9f, 0x86,
+ 0xdc, 0x0b, 0x7e, 0xfc, 0xd8, 0xdb, 0xdb, 0x07, 0x33, 0x69, 0xe6, 0xf0, 0xbf, 0xb1, 0xd7, 0x69,
+ 0x52, 0x51, 0x57, 0xdf, 0x77, 0xe0, 0x00, 0x87, 0xb1, 0xc8, 0xb6, 0xfb, 0xa7, 0x9f, 0x88, 0x2a,
+ 0x2a, 0xff, 0x18, 0xd7, 0xfb, 0x83, 0x89, 0x75, 0x76, 0x76, 0x5e, 0xbd, 0x7a, 0x35, 0xa7, 0x2a,
+ 0x06, 0x95, 0xd9, 0xf9, 0x0e, 0x90, 0x1d, 0x64, 0xf9, 0x6f, 0xb0, 0x04, 0xa6, 0xa6, 0x1b, 0x20,
+ 0x48, 0x41, 0xf6, 0x8b, 0x89, 0x8b, 0x1f, 0x3f, 0x71, 0xc2, 0xcf, 0xc7, 0xe7, 0xd6, 0x69, 0x8f,
+ 0xa7, 0x07, 0xbf, 0xcf, 0x3b, 0x4d, 0xca, 0x3b, 0x43, 0x8c, 0xf9, 0x89, 0x18, 0xb2, 0x8b, 0x1c,
+ 0xba, 0x9b, 0x14, 0xe7, 0x41, 0x1c, 0xc8, 0xc6, 0x0c, 0x14, 0x0a, 0xb2, 0xb6, 0x22, 0x41, 0x06,
+ 0x7b, 0x83, 0xbf, 0xfb, 0xd9, 0x1b, 0x35, 0x59, 0x3a, 0x74, 0x1f, 0xd1, 0x6b, 0x1d, 0xde, 0xd3,
+ 0x00, 0x7f, 0x7e, 0x0d, 0x29, 0xd8, 0x95, 0x50, 0x1f, 0x26, 0x0e, 0x0e, 0x76, 0x12, 0x57, 0x85,
+ 0xfa, 0x72, 0x45, 0xdb, 0xe3, 0xb0, 0x75, 0x0f, 0x70, 0x65, 0x3e, 0xe4, 0xac, 0x93, 0x6a, 0x29,
+ 0x17, 0x1c, 0x72, 0x92, 0x22, 0x73, 0x32, 0xd2, 0x32, 0x33, 0x33, 0x13, 0x13, 0x13, 0x83, 0x82,
+ 0x1e, 0xd9, 0xda, 0xd9, 0x71, 0xfd, 0xda, 0x18, 0x31, 0x31, 0x5b, 0x7b, 0x7b, 0xf7, 0xb7, 0x19,
+ 0x0b, 0xdb, 0x8e, 0x5d, 0xbb, 0xbe, 0x5d, 0xf4, 0x67, 0x0a, 0x17, 0xec, 0xab, 0xa3, 0xa3, 0xa3,
+ 0xb9, 0xb9, 0x05, 0x91, 0x48, 0x84, 0x00, 0x13, 0x2d, 0x97, 0x5d, 0x00, 0x40, 0x34, 0x56, 0x56,
+ 0x56, 0xd6, 0xc8, 0xc8, 0xc8, 0xcc, 0xcc, 0x9c, 0xc3, 0x58, 0x71, 0x09, 0x89, 0x33, 0x67, 0xcf,
+ 0x05, 0x04, 0x04, 0xf8, 0xfb, 0x07, 0x5c, 0xbf, 0x78, 0xfa, 0x89, 0x87, 0x0e, 0x28, 0x6d, 0xb9,
+ 0x0f, 0xa1, 0xe1, 0x81, 0x62, 0xea, 0x71, 0x62, 0xf8, 0x4f, 0xc4, 0xd0, 0xbd, 0xc4, 0x20, 0x17,
+ 0xb2, 0xbf, 0xed, 0xf2, 0xc0, 0xad, 0xcb, 0x83, 0x5d, 0x94, 0x82, 0x77, 0x2b, 0xf9, 0x59, 0x2a,
+ 0x5d, 0x32, 0x22, 0x5f, 0x5e, 0x4f, 0xf2, 0xde, 0x48, 0xf0, 0xdd, 0x84, 0x0b, 0xda, 0xa3, 0x58,
+ 0x1d, 0x28, 0xcb, 0xa5, 0xec, 0x90, 0x5d, 0x0a, 0xdb, 0x93, 0x23, 0xd6, 0xfe, 0x54, 0xa6, 0xfa,
+ 0x0e, 0xbe, 0xd0, 0x4b, 0x3d, 0xe3, 0x9c, 0x69, 0x56, 0xe0, 0xf9, 0xb2, 0xc2, 0xbc, 0x4a, 0x0a,
+ 0xa5, 0xaa, 0xb2, 0x12, 0xb6, 0x8a, 0xf2, 0xf2, 0xc2, 0xc2, 0xc2, 0xe4, 0xe4, 0xe4, 0x33, 0x67,
+ 0xce, 0xfe, 0x73, 0x8a, 0x15, 0x16, 0x54, 0x34, 0x34, 0x5c, 0xf7, 0xed, 0x9b, 0xc0, 0x58, 0xb0,
+ 0x0a, 0xca, 0x2b, 0x34, 0xc7, 0x1f, 0xa6, 0xa6, 0xa6, 0x06, 0x32, 0xab, 0xad, 0xad, 0x23, 0x21,
+ 0x21, 0x81, 0x2c, 0xf2, 0x85, 0xca, 0xec, 0xbc, 0x06, 0x5c, 0x41, 0xf0, 0xae, 0x38, 0x1c, 0x0e,
+ 0x04, 0xd6, 0xcc, 0xcc, 0x8c, 0xe3, 0x0a, 0xe0, 0xfa, 0x9e, 0xff, 0xcf, 0x85, 0x90, 0xd0, 0xd0,
+ 0x88, 0x88, 0x27, 0xf7, 0xee, 0xdd, 0xbf, 0xee, 0x79, 0x2a, 0xe4, 0x90, 0x41, 0xc6, 0x6f, 0x4a,
+ 0x65, 0x97, 0x09, 0xf5, 0x0f, 0x70, 0x9d, 0x09, 0xd2, 0xbd, 0x39, 0xa2, 0x2d, 0xe1, 0xb2, 0xf9,
+ 0xbf, 0xcb, 0x27, 0x1c, 0x53, 0x88, 0xfa, 0x97, 0x7c, 0xe4, 0x61, 0xf9, 0xa8, 0xc3, 0xf2, 0x69,
+ 0xa7, 0xe4, 0xab, 0x02, 0xb0, 0xf4, 0x2c, 0xee, 0xf5, 0xb1, 0x4c, 0x36, 0x57, 0x7b, 0xb3, 0xc4,
+ 0x3a, 0x62, 0x65, 0xea, 0xef, 0xe3, 0x4a, 0x2e, 0x91, 0xb2, 0x3c, 0x4d, 0xb3, 0xfd, 0x4f, 0x94,
+ 0xe7, 0xe7, 0xd4, 0xd6, 0xd6, 0x36, 0x34, 0x34, 0x34, 0x35, 0x35, 0x53, 0x5b, 0xa8, 0xd4, 0x96,
+ 0x96, 0xc6, 0xc6, 0x46, 0xd8, 0x53, 0x54, 0x54, 0x14, 0x18, 0x78, 0x0f, 0x7a, 0x76, 0xae, 0xdf,
+ 0xfc, 0x9b, 0x45, 0x8b, 0xf4, 0x8d, 0x8d, 0xf7, 0xbf, 0xed, 0x0d, 0x80, 0xb1, 0x3a, 0x6b, 0xd6,
+ 0x8e, 0x3f, 0x0c, 0xec, 0x2b, 0x30, 0x16, 0xce, 0x8e, 0x40, 0x20, 0x2c, 0x5b, 0xb6, 0x0c, 0x95,
+ 0xd9, 0x79, 0x8d, 0x37, 0xf9, 0xd8, 0x65, 0x4a, 0x4a, 0x4a, 0x56, 0x56, 0x56, 0x20, 0xb3, 0x9c,
+ 0x5c, 0x01, 0x30, 0xf6, 0x82, 0xe7, 0xc5, 0xa8, 0xa8, 0xe8, 0xa4, 0xa4, 0xe4, 0xe8, 0xe8, 0xe8,
+ 0xc0, 0x80, 0x40, 0x20, 0xed, 0xa3, 0xc3, 0x26, 0x69, 0xff, 0xbb, 0xbc, 0xf4, 0x32, 0xb1, 0xfe,
+ 0x81, 0x22, 0x2d, 0x51, 0xba, 0x3f, 0x5f, 0xe4, 0x1d, 0xb3, 0x5e, 0x48, 0x12, 0x80, 0xc5, 0xd5,
+ 0x38, 0x99, 0xc6, 0x20, 0x05, 0x8a, 0x2f, 0x21, 0xfb, 0x94, 0x5a, 0xf6, 0xf5, 0xfd, 0x45, 0x89,
+ 0xe1, 0xb5, 0x35, 0xb5, 0x8d, 0x8d, 0x4d, 0x6d, 0xad, 0x6d, 0x9d, 0x9d, 0x9d, 0x74, 0x3a, 0xbd,
+ 0xa7, 0xa7, 0x17, 0xb6, 0x6e, 0x7a, 0x77, 0x47, 0x7b, 0x47, 0x7d, 0x5d, 0x7d, 0x6a, 0x4a, 0xca,
+ 0xee, 0xdd, 0x7b, 0xa6, 0x52, 0x45, 0xde, 0x65, 0xcb, 0xf4, 0xd6, 0xad, 0xdb, 0xef, 0xee, 0xce,
+ 0x61, 0xec, 0x5e, 0x37, 0x37, 0x99, 0x49, 0xd3, 0xce, 0x68, 0x6a, 0x6a, 0x3a, 0x39, 0x39, 0x69,
+ 0x69, 0x69, 0x89, 0x8b, 0x8b, 0xa3, 0x6b, 0x29, 0xce, 0x6b, 0x20, 0xb5, 0x5b, 0x18, 0x0c, 0x46,
+ 0x53, 0x73, 0xa5, 0x83, 0x83, 0xa3, 0x8e, 0xce, 0x0f, 0x9c, 0xab, 0x29, 0x21, 0x29, 0xe9, 0x75,
+ 0xe9, 0xf7, 0x84, 0xf8, 0x84, 0xdc, 0xdc, 0xdc, 0xf4, 0xf4, 0x8c, 0xc8, 0xc8, 0x28, 0xb0, 0x07,
+ 0x7e, 0x9e, 0xa7, 0xef, 0x1f, 0x32, 0x4b, 0x39, 0xaa, 0x5c, 0xfa, 0x3b, 0xb1, 0xe1, 0x01, 0x8e,
+ 0x16, 0x2f, 0xd3, 0x9b, 0x2b, 0x32, 0x4d, 0xd6, 0x8b, 0x25, 0xaa, 0xc5, 0x42, 0xfd, 0x05, 0x98,
+ 0x9e, 0x4c, 0x71, 0x38, 0xb8, 0xf1, 0xb1, 0x42, 0xe5, 0x75, 0x42, 0xde, 0x19, 0x72, 0xfa, 0x05,
+ 0x8b, 0xec, 0x20, 0xaf, 0x8a, 0xe2, 0xfc, 0xfa, 0xfa, 0xfa, 0x56, 0x6a, 0x6b, 0x67, 0x67, 0x57,
+ 0x6f, 0x6f, 0x2f, 0x83, 0xc1, 0x18, 0x1a, 0x1e, 0x7e, 0x3e, 0x32, 0x02, 0xdb, 0xf0, 0xf3, 0xe7,
+ 0x4c, 0x26, 0x93, 0x4e, 0xef, 0xae, 0xa4, 0x54, 0x42, 0xfc, 0x25, 0xcd, 0x6d, 0x75, 0x3c, 0x04,
+ 0x8b, 0x96, 0x2c, 0xd1, 0xd2, 0xd5, 0xdd, 0xbd, 0x77, 0xaf, 0x9b, 0xbb, 0xbb, 0xeb, 0xfe, 0xfd,
+ 0x6b, 0xd7, 0xad, 0x9b, 0x3c, 0xa6, 0xc0, 0xcb, 0xcb, 0xeb, 0xe8, 0xe8, 0x64, 0x6a, 0x6a, 0x8a,
+ 0xc7, 0x13, 0xd0, 0x45, 0x96, 0xe7, 0x2f, 0x58, 0x6b, 0x0f, 0x7d, 0xf1, 0x05, 0x98, 0x58, 0x08,
+ 0xbb, 0xf4, 0xf4, 0xf4, 0x41, 0x85, 0xc8, 0x64, 0x32, 0xe7, 0x55, 0x49, 0x49, 0xc9, 0xdf, 0x2f,
+ 0x5f, 0x49, 0x4d, 0x49, 0x2d, 0x2b, 0x2d, 0x2d, 0x29, 0x2e, 0x4e, 0x4d, 0x4b, 0x03, 0x7b, 0x70,
+ 0xe7, 0xce, 0x5d, 0x6f, 0xcf, 0xb3, 0x81, 0x1e, 0xe6, 0x40, 0xda, 0x32, 0x50, 0xda, 0xfb, 0xb8,
+ 0xb6, 0xa7, 0xd8, 0xee, 0x0c, 0x09, 0x10, 0x5b, 0x60, 0x26, 0xa3, 0x44, 0x88, 0xf5, 0x93, 0xb5,
+ 0x09, 0xf7, 0x17, 0x62, 0xfa, 0xf3, 0x44, 0x40, 0x54, 0xe9, 0x29, 0x92, 0xed, 0x31, 0xd8, 0xa6,
+ 0xc7, 0x0a, 0xd5, 0xb7, 0xf0, 0x45, 0x17, 0x48, 0x69, 0xbf, 0x6a, 0xa4, 0x5e, 0x75, 0x2b, 0x4c,
+ 0x8d, 0xa9, 0xa2, 0x54, 0x80, 0xb4, 0xd2, 0x3a, 0x68, 0x3d, 0x3d, 0x3d, 0x03, 0x4c, 0x26, 0xb0,
+ 0xf4, 0xe5, 0xcb, 0x97, 0xaf, 0xc6, 0x01, 0xfe, 0x35, 0x32, 0x32, 0x02, 0x07, 0xa4, 0x24, 0xa7,
+ 0x58, 0x5a, 0x5a, 0x4e, 0x73, 0x22, 0x5f, 0xf1, 0xf0, 0x08, 0x8b, 0x8a, 0xe2, 0x94, 0x94, 0x64,
+ 0x70, 0xb8, 0x45, 0x8b, 0x17, 0x4f, 0x66, 0x23, 0x9c, 0xe6, 0x1b, 0x99, 0xd5, 0x86, 0xbe, 0x03,
+ 0xa9, 0x3f, 0x44, 0x49, 0x3b, 0xef, 0x80, 0x94, 0x1a, 0x42, 0x04, 0x8d, 0x58, 0x02, 0x1b, 0x1b,
+ 0x1b, 0x01, 0x01, 0x01, 0xce, 0xab, 0xc0, 0x58, 0x6f, 0x1f, 0xdf, 0xac, 0xac, 0xac, 0xda, 0xda,
+ 0x67, 0x80, 0xe2, 0xa2, 0xa2, 0x94, 0x94, 0x94, 0xb0, 0xf0, 0x08, 0x20, 0xed, 0xe5, 0x4b, 0x5e,
+ 0xb7, 0x0f, 0x59, 0x25, 0xff, 0xa2, 0x52, 0x78, 0x81, 0x54, 0x73, 0x13, 0xdf, 0xf8, 0x08, 0x47,
+ 0x7d, 0x22, 0xd7, 0xf1, 0x54, 0x96, 0x16, 0x27, 0x43, 0x8b, 0x97, 0x86, 0x9f, 0x1d, 0xb1, 0xd8,
+ 0xb6, 0x68, 0x2c, 0x35, 0x42, 0x1e, 0x5e, 0xaa, 0xf5, 0xc7, 0x53, 0xfc, 0xf0, 0x70, 0x64, 0xe6,
+ 0x31, 0xd5, 0xf8, 0xe3, 0x66, 0xd9, 0x4f, 0x1f, 0x97, 0x15, 0x15, 0x82, 0x13, 0x68, 0x6e, 0x6e,
+ 0x01, 0x1b, 0x30, 0xd0, 0xdf, 0x3f, 0x34, 0xfc, 0x7c, 0xec, 0xed, 0x65, 0x3b, 0xc6, 0x03, 0x48,
+ 0xdb, 0xd4, 0xd8, 0x78, 0xc5, 0xdb, 0x5b, 0x06, 0x8b, 0x9d, 0xee, 0x64, 0xfe, 0xfe, 0x77, 0x38,
+ 0x9d, 0x69, 0x16, 0xb8, 0x07, 0x69, 0xb5, 0xb4, 0xdc, 0x64, 0x6e, 0x6e, 0x01, 0x27, 0x8b, 0x3e,
+ 0x63, 0x3b, 0x1f, 0x81, 0x8c, 0xcf, 0x82, 0xda, 0x00, 0x33, 0x57, 0xad, 0x5a, 0xb5, 0x7d, 0xfb,
+ 0xf6, 0x35, 0x6b, 0xd6, 0x8e, 0x97, 0x1d, 0x49, 0x29, 0x29, 0xbf, 0x6b, 0xd7, 0x21, 0x60, 0x87,
+ 0x38, 0x88, 0xd6, 0xde, 0x01, 0xa4, 0x45, 0x82, 0xf7, 0xb0, 0xd0, 0xb0, 0x3b, 0xb7, 0xef, 0x5c,
+ 0xb9, 0x7c, 0xf9, 0xfa, 0x2f, 0x4e, 0xd1, 0x07, 0xbf, 0xcf, 0x3a, 0xae, 0x04, 0x6c, 0x2c, 0xbb,
+ 0x42, 0xa8, 0xf0, 0x23, 0x52, 0xae, 0x11, 0x58, 0x9b, 0x1f, 0x9e, 0x72, 0x15, 0x5f, 0x7e, 0x95,
+ 0x50, 0x7a, 0x99, 0x50, 0x78, 0x81, 0x98, 0x7d, 0x42, 0x29, 0xf5, 0x98, 0x56, 0xdc, 0x71, 0xd3,
+ 0xa4, 0xbb, 0x9e, 0x05, 0xf9, 0xf9, 0x14, 0x0a, 0x05, 0xdc, 0x69, 0x1b, 0xb5, 0x15, 0x9c, 0x2a,
+ 0xd8, 0x80, 0x91, 0x17, 0x2f, 0xa6, 0x5a, 0x7a, 0x89, 0x83, 0xa1, 0xc1, 0xa1, 0xe2, 0xa2, 0x62,
+ 0x5b, 0x5b, 0x5b, 0x64, 0xb6, 0xf0, 0x0f, 0x03, 0xf0, 0x93, 0x44, 0x22, 0x39, 0x38, 0x38, 0xac,
+ 0x5d, 0xbb, 0x56, 0x56, 0x56, 0x6e, 0xc9, 0x12, 0xd6, 0x10, 0x18, 0x4a, 0xda, 0x79, 0x04, 0xc4,
+ 0xc1, 0x82, 0xa8, 0x92, 0x48, 0xe4, 0x8d, 0x1b, 0x2d, 0x5d, 0x5c, 0x5c, 0x26, 0x3c, 0x96, 0x28,
+ 0x25, 0x25, 0x7d, 0xf3, 0xd6, 0x2d, 0x20, 0x58, 0x57, 0x17, 0x7d, 0x60, 0x60, 0xa0, 0xa3, 0xa3,
+ 0xa3, 0xba, 0xba, 0x3a, 0x2f, 0x2f, 0x2f, 0x21, 0x21, 0x31, 0x24, 0x38, 0xf4, 0xce, 0xed, 0xbb,
+ 0x57, 0x2e, 0xff, 0xee, 0x7b, 0xdc, 0xfd, 0xde, 0x61, 0x8b, 0x90, 0x7f, 0xe9, 0x47, 0xff, 0xa2,
+ 0x1d, 0x7f, 0x64, 0x45, 0xd2, 0x11, 0xb5, 0xa4, 0x23, 0xea, 0xc9, 0x47, 0xd4, 0x92, 0x59, 0x7f,
+ 0x68, 0x24, 0x1e, 0xd5, 0x8e, 0x3f, 0xb1, 0x21, 0xf6, 0xbc, 0x4b, 0xdc, 0xcd, 0xb3, 0xe9, 0x89,
+ 0x71, 0x85, 0x05, 0x05, 0x95, 0x14, 0x4a, 0x43, 0x7d, 0x7d, 0x7b, 0x5b, 0x7b, 0x4f, 0x77, 0x0f,
+ 0x93, 0x39, 0x38, 0x3a, 0x3a, 0x3a, 0x03, 0x59, 0xdf, 0x4c, 0x0e, 0x03, 0xf4, 0x0e, 0x7e, 0x1c,
+ 0x8c, 0xc7, 0xe3, 0x67, 0xd3, 0x95, 0x2f, 0x59, 0xb2, 0xc4, 0xc4, 0xc4, 0xd4, 0xda, 0xda, 0x66,
+ 0xc5, 0x8a, 0x15, 0x18, 0x8c, 0x08, 0x6b, 0xb5, 0x47, 0x34, 0xd3, 0x35, 0x4f, 0x80, 0xa4, 0x08,
+ 0xe0, 0x0a, 0x82, 0x83, 0x05, 0x81, 0xdd, 0xb1, 0x63, 0xc7, 0xe4, 0x09, 0x0c, 0xe1, 0xa5, 0x7b,
+ 0xf7, 0xef, 0x83, 0xd5, 0x64, 0x0e, 0xb2, 0xa8, 0x35, 0xc0, 0x60, 0xb4, 0x52, 0xa9, 0x94, 0x0a,
+ 0x4a, 0x4e, 0x76, 0x4e, 0x7c, 0x7c, 0x7c, 0x48, 0x48, 0xc8, 0xed, 0xdb, 0x77, 0x7c, 0x7c, 0xaf,
+ 0x7a, 0x79, 0x7a, 0x5e, 0x3c, 0x7d, 0xec, 0xf2, 0x31, 0x37, 0xbf, 0x5f, 0xf7, 0xdc, 0xf8, 0x6d,
+ 0xf7, 0xed, 0x7f, 0xbb, 0x06, 0x9c, 0xdc, 0x77, 0xff, 0xec, 0x81, 0xc7, 0x9e, 0x87, 0xc2, 0xaf,
+ 0x9e, 0x8a, 0x0e, 0xba, 0x9b, 0x94, 0x98, 0x90, 0x9d, 0x9d, 0x0d, 0x22, 0x59, 0x55, 0x59, 0xd9,
+ 0xd8, 0xd8, 0x08, 0xcc, 0xef, 0xed, 0xe9, 0x1d, 0x1c, 0x1c, 0x1a, 0x7d, 0x7b, 0xc9, 0xa4, 0xe9,
+ 0x01, 0x5f, 0x00, 0x62, 0x34, 0x37, 0xb7, 0x03, 0x40, 0xb3, 0xd9, 0x9c, 0x35, 0x0e, 0x87, 0x73,
+ 0x74, 0x74, 0x64, 0x3f, 0x9b, 0xa0, 0x88, 0x66, 0xba, 0xe6, 0x0b, 0x90, 0x09, 0xb1, 0xe1, 0xd2,
+ 0x8b, 0x88, 0x88, 0xa8, 0xaa, 0xaa, 0x6e, 0xde, 0x6c, 0xe5, 0xe2, 0xb2, 0x7d, 0xc2, 0xec, 0x85,
+ 0x00, 0xb8, 0xb8, 0x71, 0x71, 0xf1, 0x3d, 0xbd, 0xbd, 0x88, 0xc9, 0x1c, 0x1b, 0x1b, 0xeb, 0xed,
+ 0xeb, 0x6b, 0x6a, 0x6a, 0x2a, 0x2f, 0x2b, 0x03, 0x73, 0x1b, 0x17, 0x17, 0x17, 0x12, 0x1c, 0xec,
+ 0xef, 0x1f, 0xf0, 0xc7, 0x1f, 0x37, 0x7c, 0x7d, 0xaf, 0xfa, 0x78, 0xfb, 0xf8, 0xf8, 0xf8, 0xfa,
+ 0xf9, 0xf9, 0xfd, 0x71, 0xe3, 0xe6, 0xdd, 0xbb, 0xfe, 0x0f, 0x1f, 0x06, 0x85, 0x87, 0x85, 0xc7,
+ 0xc6, 0xc6, 0xa6, 0xa6, 0xa6, 0xe6, 0xe4, 0xe6, 0x96, 0x96, 0x94, 0x54, 0x57, 0x55, 0xc3, 0x7b,
+ 0x69, 0xb4, 0xce, 0xbe, 0xbe, 0xfe, 0xe1, 0x69, 0x8d, 0xeb, 0x94, 0xde, 0x60, 0x68, 0x28, 0x2d,
+ 0x3d, 0x9d, 0xf3, 0x94, 0xc4, 0x87, 0x01, 0x28, 0x6a, 0x60, 0x60, 0x08, 0xa4, 0xd5, 0xd6, 0xd6,
+ 0x96, 0x92, 0x92, 0x5a, 0xbc, 0x78, 0x31, 0xfa, 0x6c, 0xf8, 0xe7, 0x0f, 0xc4, 0x0f, 0xf0, 0xf3,
+ 0xf3, 0x2b, 0x2a, 0xe2, 0x8d, 0x8c, 0x8c, 0x5c, 0x5d, 0xf7, 0x72, 0x9d, 0x37, 0x5b, 0x55, 0x45,
+ 0x05, 0xbc, 0x2b, 0x88, 0x1b, 0x87, 0x33, 0x10, 0x04, 0xd1, 0xbb, 0xe8, 0xe0, 0x42, 0x59, 0x2b,
+ 0x74, 0x67, 0x66, 0x02, 0x21, 0xc3, 0xc2, 0xc2, 0x81, 0x9c, 0xc0, 0x5b, 0x08, 0xc7, 0x80, 0xa8,
+ 0x81, 0x81, 0xf7, 0x82, 0x82, 0x82, 0xc0, 0xe8, 0x46, 0x47, 0x45, 0x27, 0xc4, 0x27, 0x64, 0x64,
+ 0x64, 0x80, 0x71, 0x2d, 0x2b, 0x2d, 0x43, 0x16, 0x62, 0xee, 0xa4, 0xd1, 0xfa, 0xfb, 0x07, 0x86,
+ 0x9f, 0x8f, 0x70, 0x5d, 0x9a, 0x76, 0x46, 0x80, 0xdd, 0xa5, 0xd3, 0xe9, 0x3e, 0xbe, 0xbe, 0xb3,
+ 0x3c, 0xfd, 0xef, 0xbe, 0xfb, 0x0e, 0x2c, 0x90, 0x85, 0xc5, 0xc6, 0xe5, 0xcb, 0x95, 0x85, 0x85,
+ 0x85, 0xbf, 0xfd, 0xf6, 0x5b, 0x34, 0x3d, 0xfb, 0x39, 0x03, 0xe8, 0x0a, 0x7e, 0x60, 0xe9, 0xd2,
+ 0xa5, 0xb2, 0xb2, 0xb2, 0xab, 0x57, 0xaf, 0x86, 0x6b, 0x07, 0x7e, 0x60, 0xf2, 0x04, 0x80, 0x20,
+ 0xb9, 0x40, 0xc1, 0xe1, 0xe1, 0xe1, 0x09, 0x9c, 0x19, 0x1a, 0x1e, 0xa6, 0xd1, 0x68, 0xc0, 0xe4,
+ 0x92, 0xe2, 0xe2, 0xcc, 0x0c, 0xd6, 0xd0, 0x7f, 0x4c, 0x74, 0x4c, 0x44, 0x78, 0x44, 0x58, 0x58,
+ 0x18, 0xfc, 0x8c, 0x8a, 0x8c, 0x7c, 0x1a, 0xf3, 0x14, 0xb8, 0x9a, 0x92, 0x9a, 0xca, 0x76, 0x02,
+ 0x45, 0x60, 0x83, 0xeb, 0x9e, 0xd5, 0x51, 0xa9, 0x54, 0x7a, 0x57, 0x17, 0xd0, 0xf5, 0xc5, 0x3b,
+ 0xc4, 0x59, 0xd3, 0x00, 0x94, 0xb9, 0xaa, 0xaa, 0x1a, 0x3a, 0xf4, 0x59, 0x36, 0x02, 0x44, 0x5e,
+ 0x7b, 0xf6, 0xb8, 0xc2, 0xdd, 0xaa, 0xa8, 0xa8, 0x08, 0x77, 0x2e, 0xdc, 0xbf, 0x68, 0xe9, 0xec,
+ 0xe7, 0x09, 0x4e, 0x7e, 0x40, 0x42, 0x42, 0x62, 0xe5, 0xca, 0x95, 0x10, 0x7d, 0x5b, 0x5b, 0x5b,
+ 0xf3, 0xf2, 0x4e, 0x9c, 0x6b, 0x0b, 0xa0, 0xa7, 0xa7, 0x07, 0x72, 0xca, 0x95, 0x33, 0x10, 0xe0,
+ 0xb7, 0xb5, 0xb5, 0xd5, 0xd6, 0xd4, 0x02, 0x69, 0xb3, 0xb3, 0x73, 0x80, 0x9c, 0x10, 0x8b, 0x01,
+ 0x4b, 0xe1, 0x67, 0x52, 0x52, 0x72, 0x5a, 0x5a, 0x1a, 0x78, 0x06, 0x96, 0xb4, 0xb2, 0x9d, 0x40,
+ 0x43, 0x43, 0x63, 0x5b, 0x5b, 0x7b, 0x77, 0x77, 0xf7, 0x00, 0x83, 0x39, 0x61, 0x3d, 0xc4, 0x0f,
+ 0x03, 0x18, 0x60, 0x2f, 0xaf, 0x4b, 0xb3, 0x27, 0xd8, 0xba, 0x75, 0xeb, 0x9d, 0x9c, 0x58, 0xc5,
+ 0xde, 0x58, 0x2c, 0x96, 0x97, 0x97, 0x17, 0x2d, 0x9d, 0xfd, 0x0c, 0x81, 0x8c, 0x17, 0x40, 0x27,
+ 0x08, 0x5d, 0xa1, 0x8a, 0x8a, 0x0a, 0x74, 0x8b, 0xdb, 0xb6, 0xd9, 0x83, 0xd2, 0x4e, 0x0e, 0x3d,
+ 0xe4, 0xe5, 0xe5, 0xb3, 0x73, 0x72, 0x5e, 0x4e, 0x61, 0x35, 0x81, 0x78, 0x10, 0x3a, 0xb5, 0xb4,
+ 0xb4, 0xd4, 0x54, 0x57, 0x83, 0x3d, 0xc8, 0xcf, 0xcf, 0xcf, 0xca, 0xce, 0xce, 0xcc, 0xcc, 0x04,
+ 0xa2, 0xe6, 0xe6, 0xe6, 0x16, 0x14, 0x14, 0x94, 0x16, 0x97, 0x40, 0x80, 0x56, 0x53, 0x53, 0xdb,
+ 0xd2, 0xdc, 0x4c, 0x63, 0xc7, 0x59, 0x10, 0xbb, 0xbd, 0x18, 0xe7, 0x2e, 0x66, 0x03, 0xf8, 0x56,
+ 0x19, 0xe9, 0x19, 0x38, 0xc5, 0xd9, 0xca, 0x2c, 0x1f, 0x1f, 0x9f, 0x9d, 0x9d, 0xdd, 0x96, 0x2d,
+ 0xd6, 0x1a, 0x1a, 0x1a, 0x62, 0x62, 0x62, 0x68, 0x85, 0xcc, 0x67, 0x08, 0xd0, 0x25, 0xe8, 0xfe,
+ 0x20, 0x40, 0x86, 0x90, 0xca, 0xd8, 0xd8, 0xd8, 0xc1, 0xc1, 0x51, 0x5d, 0x5d, 0x7d, 0x72, 0x59,
+ 0x14, 0x1c, 0xe0, 0x79, 0xf1, 0xe2, 0xf8, 0x65, 0x67, 0x27, 0x00, 0xba, 0x75, 0x08, 0x9d, 0x40,
+ 0x36, 0x9b, 0x9b, 0x9b, 0xc1, 0xa0, 0x56, 0x94, 0x57, 0x94, 0x00, 0x8a, 0x8b, 0x4b, 0x8b, 0x8b,
+ 0xcb, 0x4b, 0xcb, 0x28, 0x15, 0x15, 0xc0, 0x64, 0xf0, 0xba, 0xd4, 0x16, 0x6a, 0x57, 0x67, 0x17,
+ 0xc4, 0x59, 0x10, 0x31, 0xbd, 0x57, 0x5a, 0x60, 0x46, 0x74, 0x76, 0x76, 0xba, 0xb9, 0x1d, 0x98,
+ 0x7d, 0x6b, 0x10, 0x08, 0x04, 0x27, 0x27, 0x67, 0x13, 0x13, 0x13, 0x22, 0x91, 0x24, 0x20, 0x20,
+ 0x80, 0x7a, 0x83, 0xcf, 0x0a, 0x20, 0xa4, 0x5f, 0x7d, 0xf5, 0x15, 0x74, 0x7f, 0x32, 0x32, 0x32,
+ 0x3f, 0xfc, 0xa0, 0x0b, 0x74, 0x35, 0x30, 0x30, 0x98, 0x3c, 0x61, 0x3b, 0x5c, 0xb2, 0xad, 0x5b,
+ 0xb7, 0x56, 0x57, 0x57, 0x4f, 0xef, 0x36, 0x41, 0xe8, 0x06, 0x07, 0x07, 0xe9, 0x9d, 0x5d, 0x40,
+ 0x4b, 0x20, 0x27, 0xf0, 0x16, 0x0c, 0x00, 0xe0, 0x59, 0xed, 0xb3, 0x86, 0xfa, 0x86, 0x96, 0xe6,
+ 0x96, 0x8e, 0xf6, 0xf6, 0xee, 0xae, 0xee, 0x81, 0x01, 0x76, 0x9c, 0xf5, 0xfe, 0x69, 0x81, 0xe9,
+ 0x01, 0x01, 0xa0, 0xbf, 0xbf, 0x3f, 0x9c, 0xcb, 0x2c, 0xdb, 0x04, 0x28, 0x0a, 0x4e, 0x1e, 0xbc,
+ 0xc1, 0x8f, 0x3f, 0xfe, 0x28, 0x23, 0x83, 0x05, 0xeb, 0x8e, 0x8e, 0x29, 0x7c, 0x26, 0x40, 0xb2,
+ 0xaf, 0x8b, 0x17, 0x2f, 0x06, 0xfb, 0xba, 0x62, 0xc5, 0x0a, 0xf0, 0xae, 0x40, 0xcb, 0x09, 0x93,
+ 0x1b, 0x23, 0xd0, 0xd6, 0xd1, 0x89, 0x8d, 0x8b, 0x9b, 0x10, 0x70, 0x71, 0xc5, 0xd8, 0xd8, 0xd8,
+ 0x00, 0x83, 0x01, 0x5e, 0xb7, 0xbd, 0xad, 0x1d, 0x28, 0xda, 0xd4, 0xd8, 0x04, 0x3e, 0xa1, 0xb5,
+ 0xb5, 0x15, 0xb8, 0x0a, 0x41, 0x16, 0xab, 0xac, 0x85, 0xbd, 0x48, 0xe8, 0x6c, 0xe2, 0xac, 0xa9,
+ 0xf0, 0xf2, 0xd5, 0xab, 0xf2, 0x8a, 0x8a, 0xe9, 0xd7, 0xac, 0x79, 0x47, 0x40, 0x87, 0xb2, 0x69,
+ 0xd3, 0x66, 0x1b, 0x1b, 0x5b, 0xf0, 0x06, 0x22, 0x22, 0xe8, 0x98, 0xc2, 0xe7, 0x02, 0x24, 0xda,
+ 0x12, 0x15, 0x15, 0x55, 0x53, 0x53, 0xb3, 0xb4, 0xdc, 0xe4, 0xe2, 0xb2, 0x9d, 0xf3, 0x30, 0xd7,
+ 0x78, 0xc8, 0x60, 0xb1, 0xbe, 0xbe, 0xbe, 0x9d, 0x5d, 0x5d, 0xef, 0x48, 0x33, 0xe8, 0xeb, 0xc1,
+ 0x3c, 0x00, 0x39, 0xe9, 0x74, 0x20, 0x69, 0x17, 0xab, 0x50, 0xb0, 0xbb, 0xa7, 0xbf, 0xaf, 0x0f,
+ 0x76, 0x0e, 0x3f, 0xff, 0x90, 0x8c, 0xeb, 0xbb, 0xa3, 0xbf, 0xbf, 0xff, 0xe0, 0xc1, 0x83, 0x73,
+ 0xd2, 0x89, 0x43, 0xa7, 0x63, 0x6f, 0x6f, 0x6f, 0x6e, 0x6e, 0x4e, 0x22, 0x91, 0x04, 0x05, 0x05,
+ 0xbf, 0xf9, 0xe6, 0x1b, 0xd4, 0x1b, 0xfc, 0xb5, 0x80, 0xf6, 0x87, 0xde, 0x5f, 0x48, 0x48, 0x88,
+ 0x4c, 0x26, 0x9b, 0x98, 0x98, 0x02, 0x5d, 0x39, 0xd3, 0xc1, 0x8d, 0x07, 0x5c, 0xa9, 0x6d, 0xf6,
+ 0xf6, 0x15, 0x15, 0x94, 0xf7, 0x8a, 0xe8, 0x47, 0x47, 0x47, 0x07, 0x87, 0x87, 0x07, 0x18, 0x4c,
+ 0x30, 0x00, 0x8c, 0x01, 0xc6, 0xe0, 0xd0, 0x10, 0xd8, 0x00, 0x60, 0xf2, 0xc7, 0x90, 0xd6, 0x09,
+ 0xff, 0xef, 0xc3, 0xa0, 0x20, 0xc9, 0x71, 0x73, 0x87, 0x7e, 0x30, 0xd8, 0x8b, 0x86, 0x68, 0xba,
+ 0xb8, 0xb8, 0xe8, 0xe9, 0xe9, 0x29, 0x28, 0x28, 0xf0, 0xf1, 0x2d, 0xe3, 0xe1, 0x41, 0x1f, 0x60,
+ 0xfc, 0xcb, 0x80, 0xd8, 0x57, 0x24, 0xda, 0xd2, 0xd7, 0xd7, 0x47, 0xaa, 0x9a, 0x27, 0x67, 0x5f,
+ 0xe1, 0xaa, 0x41, 0x18, 0x12, 0x11, 0xf1, 0x04, 0x02, 0xa5, 0xf7, 0x25, 0x1b, 0xd8, 0xd4, 0x17,
+ 0xa3, 0xa3, 0x2f, 0x58, 0x00, 0xaa, 0x7e, 0x74, 0xae, 0x22, 0x80, 0xff, 0xa5, 0xee, 0xd9, 0x33,
+ 0x43, 0x43, 0xc3, 0x39, 0x69, 0x25, 0x68, 0x22, 0x88, 0xbf, 0xec, 0xed, 0x1d, 0xb4, 0xb5, 0xb5,
+ 0xa5, 0xa5, 0xa5, 0x91, 0xe7, 0xc4, 0x51, 0xd2, 0x7e, 0x7a, 0x70, 0xec, 0xab, 0xb4, 0xb4, 0x0c,
+ 0xb2, 0x1e, 0x3d, 0x78, 0x3f, 0xae, 0xf6, 0x15, 0x2e, 0x99, 0x87, 0x87, 0x47, 0x6d, 0x4d, 0xed,
+ 0xd8, 0x9c, 0x06, 0xf5, 0x1f, 0x15, 0x20, 0xe9, 0xae, 0x7b, 0xf6, 0xc0, 0x37, 0x9f, 0x93, 0xb6,
+ 0xe2, 0xe3, 0xe3, 0x83, 0x68, 0x74, 0xf3, 0xe6, 0xcd, 0x6a, 0x6a, 0xea, 0x48, 0xb2, 0x0b, 0x5d,
+ 0x56, 0xe9, 0x13, 0x03, 0xc9, 0xbe, 0x42, 0x28, 0x81, 0xc1, 0x60, 0xd4, 0xd5, 0x35, 0xac, 0xac,
+ 0xb6, 0x58, 0x59, 0x59, 0xc1, 0xdf, 0x5c, 0xc3, 0x0a, 0x49, 0x49, 0xc9, 0xa8, 0xa8, 0xa8, 0xf1,
+ 0xcb, 0xca, 0x7f, 0xfe, 0x80, 0x9b, 0x2b, 0x3c, 0x3c, 0x5c, 0x6a, 0x2e, 0x8c, 0xc1, 0xdf, 0xde,
+ 0x14, 0xc9, 0xec, 0xdc, 0xb9, 0x6b, 0xfd, 0x7a, 0x13, 0xc4, 0xd0, 0xa2, 0xc9, 0xae, 0x4f, 0x09,
+ 0xa4, 0xd6, 0x05, 0xac, 0xa9, 0x80, 0x80, 0x00, 0x74, 0xf7, 0xa6, 0xa6, 0xa6, 0x0e, 0x0e, 0x0e,
+ 0x8a, 0x8a, 0x78, 0xae, 0x3d, 0x1d, 0x1c, 0xec, 0xee, 0xee, 0x5e, 0x56, 0x5a, 0x36, 0x3a, 0x3a,
+ 0x6f, 0x04, 0xf6, 0xff, 0xd8, 0xc6, 0x80, 0x4a, 0xa5, 0x42, 0x8c, 0x3f, 0x57, 0x8d, 0x06, 0x72,
+ 0xad, 0xa3, 0xa3, 0xc3, 0xae, 0x13, 0x5e, 0x23, 0x27, 0x27, 0x87, 0x0e, 0x84, 0x7d, 0x4a, 0x20,
+ 0x0f, 0x17, 0x40, 0x4f, 0x27, 0x2f, 0x2f, 0x0f, 0xed, 0xef, 0xec, 0xec, 0xc2, 0x99, 0xb4, 0x70,
+ 0x32, 0x84, 0x31, 0x98, 0x1b, 0x7f, 0xdc, 0x6c, 0x6d, 0x6d, 0xfd, 0x34, 0x16, 0x74, 0x0e, 0x31,
+ 0x32, 0x32, 0xb2, 0xdf, 0xcd, 0x6d, 0x36, 0x65, 0xde, 0x13, 0x00, 0x0e, 0x16, 0xee, 0x6e, 0x3b,
+ 0x3b, 0x3b, 0x30, 0xb4, 0xc8, 0xc3, 0x35, 0x68, 0x65, 0xd7, 0x27, 0x00, 0xc7, 0xbe, 0x42, 0x5f,
+ 0x0f, 0x44, 0x05, 0xfb, 0x6a, 0x6a, 0xba, 0x61, 0x2a, 0xbf, 0x07, 0x07, 0x5b, 0x6d, 0xd9, 0xf2,
+ 0x24, 0x32, 0xaa, 0xbb, 0xbb, 0xfb, 0xaf, 0x26, 0xe0, 0x7b, 0x03, 0x82, 0xbe, 0xdc, 0xdc, 0x3c,
+ 0x88, 0x2b, 0xe7, 0xb0, 0xf5, 0xa0, 0xd1, 0xb6, 0x6e, 0xdd, 0x6a, 0x69, 0x69, 0xa9, 0xac, 0xac,
+ 0x2c, 0x24, 0x24, 0x84, 0x54, 0x76, 0xa1, 0xa4, 0xfd, 0xa8, 0x40, 0xd2, 0x59, 0xc2, 0xc2, 0xc2,
+ 0xcb, 0x97, 0x2b, 0x5b, 0x58, 0x58, 0xb8, 0xb8, 0x6c, 0x9f, 0xe6, 0x9a, 0x82, 0xaa, 0x1c, 0x3c,
+ 0x74, 0x38, 0x25, 0x25, 0xb5, 0xa7, 0xa7, 0xe7, 0xaf, 0x26, 0xe0, 0x87, 0xa0, 0xb7, 0xb7, 0x57,
+ 0x57, 0x57, 0x77, 0x6e, 0x5b, 0x4f, 0x45, 0x45, 0xc5, 0xc9, 0xc9, 0xc9, 0xd0, 0xd0, 0x50, 0x41,
+ 0x41, 0x01, 0x9a, 0x0e, 0x35, 0xb4, 0x1f, 0x15, 0x48, 0x3a, 0x0b, 0xfc, 0x80, 0x82, 0x02, 0x4e,
+ 0x5f, 0xdf, 0x60, 0xc7, 0x8e, 0x1d, 0xd3, 0x97, 0x40, 0xaf, 0xd0, 0xd4, 0xf4, 0xf2, 0xf2, 0xca,
+ 0xcc, 0xcc, 0xea, 0xea, 0xea, 0x9a, 0xf3, 0xe1, 0xd4, 0x59, 0xe3, 0xd5, 0xcb, 0x97, 0x63, 0x63,
+ 0xa3, 0xac, 0xdc, 0x19, 0x18, 0x80, 0xe7, 0x6c, 0xc0, 0x2f, 0xd8, 0xc5, 0x39, 0x62, 0x74, 0x6c,
+ 0xec, 0xe6, 0xcd, 0x9b, 0x73, 0xdb, 0x86, 0x40, 0x51, 0x23, 0x23, 0xa3, 0x09, 0xc9, 0x2e, 0x54,
+ 0x66, 0x3f, 0x06, 0x38, 0x4f, 0x73, 0x43, 0xd7, 0xa6, 0xa5, 0xa5, 0x05, 0x6d, 0x0e, 0x42, 0x31,
+ 0xcd, 0x6a, 0xef, 0x20, 0x1d, 0x66, 0xe6, 0xe6, 0x7e, 0x7e, 0xd7, 0xd2, 0x52, 0xd3, 0x9a, 0x9b,
+ 0x9b, 0xc7, 0xaf, 0xbb, 0xfd, 0x57, 0x01, 0xbc, 0x34, 0x50, 0x14, 0xbe, 0xc9, 0xd0, 0xd0, 0x10,
+ 0x93, 0xc9, 0xec, 0xef, 0xef, 0xef, 0xeb, 0xe9, 0x05, 0xc7, 0xd2, 0xd5, 0xd9, 0xd5, 0x49, 0xa3,
+ 0xd1, 0x3a, 0x3a, 0xba, 0x68, 0x9d, 0xbd, 0x3d, 0x3d, 0xe3, 0xbf, 0x6a, 0x5d, 0x5d, 0x1d, 0xd7,
+ 0x94, 0xdd, 0x6c, 0x00, 0x9e, 0xca, 0xd9, 0xd9, 0x79, 0xd3, 0xa6, 0xcd, 0xaa, 0xaa, 0xaa, 0x22,
+ 0x22, 0xa2, 0xe8, 0xe8, 0xed, 0xc7, 0x00, 0x92, 0x1f, 0x00, 0x7d, 0x10, 0x14, 0x14, 0x02, 0x5d,
+ 0xdd, 0xb8, 0xd1, 0xd2, 0xc6, 0xc6, 0x06, 0xbc, 0xc1, 0x34, 0x6f, 0x01, 0x9f, 0xb6, 0x7d, 0xe7,
+ 0xce, 0xab, 0x7e, 0xd7, 0x62, 0xa2, 0x63, 0x28, 0x15, 0x94, 0x9e, 0xee, 0x9e, 0x77, 0xcc, 0xc7,
+ 0xbe, 0x62, 0xa9, 0xdf, 0x4b, 0x64, 0x7a, 0x81, 0x09, 0x7c, 0xe3, 0xba, 0x7f, 0x46, 0x96, 0x82,
+ 0x94, 0x82, 0x7a, 0x32, 0x18, 0x8c, 0xbe, 0xbe, 0x3e, 0x7a, 0x17, 0x1d, 0x98, 0xd9, 0x4a, 0xa5,
+ 0x36, 0x37, 0x37, 0x35, 0x34, 0x34, 0x3c, 0x7b, 0x56, 0x57, 0x53, 0x53, 0x5b, 0x55, 0x55, 0x5d,
+ 0x49, 0xa9, 0x64, 0x6d, 0x95, 0x95, 0xb5, 0xb5, 0xcf, 0xda, 0xdb, 0xdb, 0x9f, 0xbf, 0x29, 0x7e,
+ 0x00, 0x6e, 0x1f, 0x39, 0x72, 0x64, 0xce, 0xdb, 0x13, 0x8b, 0xc5, 0xba, 0xba, 0xee, 0x5d, 0xb7,
+ 0x6e, 0x3d, 0x81, 0x40, 0xe0, 0xe7, 0x17, 0x40, 0x67, 0xf2, 0x9c, 0x73, 0x20, 0xd5, 0xda, 0xd0,
+ 0x85, 0xc9, 0xc9, 0xc9, 0xb1, 0x87, 0xb7, 0x9c, 0x21, 0x76, 0x98, 0xa6, 0x91, 0xe1, 0x78, 0x65,
+ 0x15, 0x95, 0x5f, 0x8e, 0x1e, 0xf5, 0xf1, 0xf1, 0x0d, 0x09, 0x09, 0xc9, 0x64, 0xcd, 0x4b, 0x50,
+ 0xdb, 0xdb, 0xd7, 0xf7, 0x2e, 0x95, 0x81, 0xd0, 0x4b, 0x77, 0xd3, 0xe9, 0xf5, 0xf5, 0xf5, 0x6d,
+ 0xad, 0xad, 0x83, 0x83, 0x83, 0xc0, 0x99, 0xa1, 0xc1, 0x41, 0xe0, 0x1b, 0x9d, 0x4e, 0x6f, 0x05,
+ 0x50, 0xa9, 0x7d, 0xbd, 0x7d, 0x33, 0x92, 0x9f, 0x4d, 0xef, 0x31, 0x20, 0xde, 0xc0, 0x40, 0x3f,
+ 0x7c, 0x5a, 0x47, 0x47, 0x07, 0x95, 0x4a, 0x85, 0xcf, 0xac, 0xae, 0xae, 0xa9, 0xa8, 0xa8, 0x28,
+ 0x66, 0x55, 0xde, 0x16, 0x40, 0x60, 0x95, 0x95, 0x95, 0x95, 0x9e, 0x91, 0x91, 0x96, 0x9e, 0x9e,
+ 0x9a, 0x9a, 0x9a, 0x02, 0x48, 0x4d, 0xcd, 0xc8, 0xc8, 0x28, 0x29, 0x29, 0x69, 0x6f, 0x6b, 0x43,
+ 0x94, 0x16, 0x6e, 0x90, 0xa4, 0xc4, 0xa4, 0xc9, 0x6b, 0x40, 0xcf, 0x12, 0x20, 0xaa, 0x7a, 0x7a,
+ 0x7a, 0xce, 0xce, 0x2e, 0xab, 0x57, 0xaf, 0x06, 0xf6, 0x7e, 0xf7, 0x1d, 0x9a, 0xec, 0x9a, 0x4b,
+ 0x70, 0x12, 0xb0, 0x20, 0xaa, 0x1a, 0x1a, 0x1a, 0xa0, 0xae, 0x66, 0x66, 0x66, 0x5c, 0xcb, 0x5d,
+ 0x38, 0xe0, 0xe1, 0xe1, 0xd1, 0xd3, 0xd7, 0xff, 0xf7, 0xc9, 0x93, 0x3e, 0xde, 0xbe, 0x0f, 0x1e,
+ 0x3c, 0x4c, 0x48, 0x48, 0x28, 0x28, 0x28, 0xa8, 0xab, 0xab, 0x87, 0x10, 0xec, 0x5d, 0xe6, 0x10,
+ 0x18, 0x1e, 0x1a, 0x06, 0x66, 0x56, 0x52, 0x28, 0x65, 0x65, 0x65, 0xe5, 0x00, 0xf8, 0x55, 0x5a,
+ 0x0a, 0x4c, 0x03, 0xca, 0x01, 0x6f, 0x47, 0x67, 0x2e, 0x4e, 0x78, 0xf5, 0xe2, 0xc5, 0x0b, 0x06,
+ 0x63, 0xa0, 0x9b, 0xde, 0xdd, 0xde, 0xde, 0xd6, 0xd8, 0xd8, 0x58, 0x53, 0x53, 0x03, 0x1f, 0x53,
+ 0x90, 0x5f, 0x90, 0x99, 0x91, 0x99, 0x94, 0x9c, 0x1c, 0x1b, 0x17, 0x1f, 0x1d, 0x1d, 0x13, 0x19,
+ 0x19, 0x19, 0x1e, 0xf1, 0x24, 0x2c, 0x3c, 0x02, 0xd9, 0x42, 0xd9, 0x1b, 0x20, 0x2e, 0x2e, 0xbe,
+ 0xa8, 0xa8, 0x08, 0x48, 0x8e, 0x3c, 0x86, 0x06, 0x92, 0x0b, 0x9d, 0xf8, 0x9c, 0xb7, 0x2a, 0x84,
+ 0x5d, 0xb6, 0xb6, 0x5b, 0xad, 0xad, 0x6d, 0xa0, 0x49, 0xd1, 0x65, 0xc4, 0xe7, 0x16, 0x48, 0x46,
+ 0x8b, 0x97, 0x97, 0x17, 0x04, 0xd6, 0xd8, 0xd8, 0xd8, 0xd1, 0xd1, 0x91, 0x6b, 0xb9, 0xcb, 0x78,
+ 0x2c, 0xe3, 0xe7, 0xdf, 0xba, 0x6d, 0xdb, 0xa9, 0x33, 0x67, 0x7c, 0x7d, 0x7c, 0x03, 0x03, 0xef,
+ 0x81, 0x31, 0x48, 0x4f, 0x4f, 0x07, 0xed, 0x02, 0xca, 0x75, 0xd1, 0xe9, 0x43, 0x43, 0xc3, 0x33,
+ 0x16, 0x5f, 0xbd, 0x18, 0x79, 0x01, 0xde, 0xb2, 0xaa, 0xb2, 0xb2, 0xb4, 0xb4, 0x14, 0xe8, 0x5a,
+ 0x5d, 0x5d, 0x0d, 0xe1, 0x1b, 0x04, 0x47, 0x33, 0x71, 0xf5, 0xb5, 0xc0, 0x02, 0xab, 0x99, 0x6c,
+ 0x59, 0x06, 0xa1, 0xae, 0xaf, 0xab, 0x07, 0x5b, 0x52, 0x54, 0x58, 0x04, 0x72, 0x1a, 0x1f, 0x17,
+ 0x1f, 0xf1, 0x24, 0x32, 0x24, 0x34, 0x3c, 0x38, 0x34, 0x2c, 0x38, 0x24, 0x94, 0xeb, 0x16, 0x12,
+ 0x1a, 0x16, 0xf3, 0x34, 0x16, 0x48, 0x0b, 0x16, 0x02, 0x3e, 0x0a, 0xc4, 0x36, 0x20, 0x20, 0x40,
+ 0x60, 0xd2, 0xc2, 0xe5, 0xb3, 0x04, 0xc8, 0x2c, 0x89, 0x44, 0x86, 0xde, 0x0a, 0xbc, 0x01, 0x1e,
+ 0x8f, 0x87, 0x78, 0x16, 0xa2, 0x5a, 0xd4, 0x1b, 0xcc, 0x09, 0x90, 0x8c, 0x16, 0x06, 0x83, 0x61,
+ 0x2f, 0xcb, 0x65, 0x0b, 0x2d, 0x3c, 0xe3, 0x80, 0xbb, 0x0c, 0x16, 0xeb, 0xee, 0xe1, 0x71, 0xee,
+ 0xfc, 0xff, 0xb3, 0x77, 0x25, 0x40, 0x51, 0x9e, 0x69, 0x5a, 0x9a, 0x86, 0x96, 0xa3, 0x81, 0x06,
+ 0x9b, 0xfb, 0xbe, 0x9b, 0x9b, 0x06, 0x69, 0xa0, 0x81, 0x46, 0x04, 0xb9, 0xef, 0x46, 0x6c, 0x4e,
+ 0xc5, 0x08, 0x1a, 0x9d, 0x8a, 0x3b, 0x9b, 0xaa, 0x71, 0xa6, 0x6a, 0x92, 0xad, 0x49, 0x25, 0x66,
+ 0x36, 0xd9, 0x35, 0xbb, 0xd9, 0x54, 0x8e, 0x29, 0x53, 0x93, 0x6c, 0x92, 0x9d, 0xac, 0x89, 0x07,
+ 0x20, 0x28, 0x5e, 0x89, 0x78, 0x83, 0x47, 0x88, 0x8e, 0x20, 0x97, 0x1c, 0xa2, 0x80, 0x0a, 0x8a,
+ 0x5c, 0x02, 0xba, 0x4f, 0xf7, 0x47, 0xff, 0x34, 0x88, 0xf4, 0x01, 0x6d, 0xd5, 0x2c, 0xfd, 0xd6,
+ 0x5f, 0x14, 0x45, 0xff, 0xdd, 0xfc, 0xfd, 0xfd, 0xcf, 0xff, 0x7c, 0xcf, 0x7b, 0x7c, 0xef, 0xf7,
+ 0x6f, 0x5f, 0xfc, 0xe5, 0x2f, 0xdf, 0x7f, 0xff, 0xfd, 0x91, 0x23, 0x47, 0x6b, 0x6b, 0x6b, 0xaf,
+ 0x5e, 0xb9, 0xd2, 0xd8, 0xd8, 0xd8, 0xd5, 0xd5, 0x05, 0x4d, 0x3b, 0x3c, 0x3a, 0x26, 0x37, 0x7a,
+ 0x00, 0xa8, 0x40, 0x05, 0x80, 0x69, 0xdb, 0x5a, 0x5a, 0x01, 0x3f, 0xe5, 0x72, 0x10, 0x70, 0xb2,
+ 0x20, 0x5f, 0xc7, 0xc6, 0x1e, 0x3f, 0x7e, 0x7c, 0xbf, 0xbf, 0x1f, 0x92, 0xa0, 0xb5, 0xa5, 0x55,
+ 0x4c, 0xb3, 0x97, 0x2f, 0x63, 0xde, 0x3f, 0x79, 0xf2, 0x27, 0x60, 0xb2, 0xf2, 0x70, 0x15, 0xa8,
+ 0xf5, 0xc0, 0xa1, 0xf2, 0x03, 0x2f, 0xa0, 0x97, 0x80, 0x16, 0x04, 0x8f, 0xb7, 0xe3, 0xff, 0x42,
+ 0xee, 0x0a, 0x85, 0x42, 0xd9, 0x2f, 0x48, 0xa3, 0xd3, 0x99, 0xa6, 0xa6, 0x46, 0x66, 0x66, 0xb4,
+ 0x97, 0xb4, 0x9f, 0x55, 0xc4, 0x30, 0xaa, 0x89, 0x89, 0x49, 0x9b, 0x36, 0x6d, 0x22, 0xfb, 0x82,
+ 0x91, 0x7a, 0x03, 0x8d, 0x36, 0x58, 0xa4, 0xc9, 0x12, 0x6c, 0x62, 0x62, 0x62, 0x69, 0x69, 0x99,
+ 0x6c, 0xfb, 0xac, 0x79, 0x0d, 0xc3, 0x1e, 0xce, 0xe7, 0xbf, 0xf3, 0xee, 0xbb, 0x9f, 0x7c, 0xf2,
+ 0xe9, 0x77, 0xdf, 0x7d, 0x87, 0xc9, 0x17, 0x2a, 0x11, 0x50, 0x01, 0x61, 0x76, 0xdc, 0xee, 0x00,
+ 0x73, 0x02, 0x06, 0xe3, 0x4f, 0x27, 0xe4, 0x22, 0x50, 0xb2, 0x82, 0x66, 0xf4, 0xd1, 0xe0, 0xa0,
+ 0x82, 0xd4, 0x3a, 0xff, 0x87, 0x4c, 0x89, 0xa1, 0x3b, 0x0e, 0xe8, 0x0e, 0x3e, 0xea, 0xef, 0xeb,
+ 0x03, 0x74, 0xdb, 0xdb, 0xda, 0x9b, 0x1a, 0x9b, 0x1a, 0x7e, 0xfd, 0xb5, 0xbe, 0xbe, 0x1e, 0x02,
+ 0xfb, 0xa7, 0x9f, 0x7f, 0x3e, 0x76, 0xfc, 0xf8, 0xe1, 0xaa, 0xaa, 0x83, 0x87, 0x2a, 0xe6, 0x82,
+ 0xb6, 0xa6, 0xe6, 0x56, 0x73, 0x33, 0x04, 0x06, 0x2e, 0xe3, 0xf3, 0x2f, 0xbe, 0xb0, 0x94, 0xf1,
+ 0x34, 0xe9, 0x0c, 0x86, 0xb3, 0xb7, 0x77, 0x4c, 0x62, 0x22, 0x3f, 0x26, 0xc6, 0xce, 0xd5, 0x95,
+ 0xa6, 0x6a, 0x65, 0x0b, 0x80, 0xba, 0x71, 0xe3, 0x46, 0x3c, 0x0e, 0x7e, 0x7e, 0x7e, 0x64, 0xe1,
+ 0xad, 0x86, 0x66, 0x17, 0x69, 0x84, 0x60, 0x6d, 0x6d, 0x6d, 0x21, 0xb7, 0x8a, 0x8b, 0x8b, 0x63,
+ 0x63, 0xe3, 0xe4, 0xbe, 0xc5, 0xd8, 0xd8, 0xf8, 0xb5, 0xd2, 0xd2, 0xcf, 0x3e, 0xfb, 0x7c, 0xff,
+ 0x8f, 0xfb, 0x4f, 0x9d, 0x3a, 0x75, 0xa5, 0xfe, 0x72, 0xf3, 0xad, 0x66, 0xf8, 0x32, 0x70, 0xd5,
+ 0x47, 0x46, 0x47, 0xc5, 0x05, 0xae, 0x2a, 0xe3, 0x6f, 0x71, 0x06, 0x67, 0x0c, 0xf0, 0x23, 0x85,
+ 0xe2, 0x7d, 0x12, 0xf4, 0xde, 0x6e, 0x6f, 0x6f, 0x6c, 0x6a, 0x82, 0x4c, 0xae, 0xaf, 0xab, 0x3f,
+ 0x5d, 0x5b, 0x7b, 0xf4, 0xd8, 0xb1, 0x43, 0x15, 0x15, 0x14, 0xe5, 0xe2, 0x17, 0x80, 0xb9, 0xbb,
+ 0xab, 0x73, 0x62, 0x62, 0xb2, 0xa3, 0xa3, 0x23, 0x2d, 0x2d, 0x4d, 0x16, 0x4e, 0x5a, 0x34, 0x9a,
+ 0xa7, 0x8f, 0x4f, 0x4a, 0x56, 0x96, 0x50, 0x24, 0x12, 0xac, 0x8b, 0xb7, 0xb4, 0xb7, 0xd3, 0x56,
+ 0xbe, 0x35, 0x01, 0x08, 0x41, 0x20, 0x88, 0x86, 0x0b, 0x16, 0x13, 0xb3, 0xd6, 0xc5, 0xc5, 0x85,
+ 0x2c, 0xae, 0xd1, 0xd0, 0xac, 0xca, 0x46, 0x08, 0x16, 0x9e, 0x32, 0x87, 0xc3, 0x49, 0x4e, 0x4e,
+ 0x2e, 0x2b, 0xdb, 0x0a, 0x34, 0xca, 0x7d, 0x17, 0x78, 0xe3, 0x3f, 0x3f, 0xfe, 0xb8, 0xbc, 0xbc,
+ 0xe2, 0xe2, 0x85, 0x8b, 0xd0, 0x9f, 0xbd, 0xf7, 0x7a, 0xe1, 0xe9, 0x3f, 0x9d, 0x90, 0x4f, 0xaa,
+ 0xaf, 0xcc, 0xc4, 0x42, 0x77, 0x62, 0x62, 0x6c, 0x64, 0xf4, 0xf1, 0x23, 0x68, 0x86, 0xfb, 0x3d,
+ 0x3d, 0x3d, 0xed, 0x80, 0x6e, 0x63, 0xe3, 0xd5, 0xab, 0xd7, 0xa0, 0xb7, 0x8f, 0x1c, 0xa9, 0x39,
+ 0x78, 0xa8, 0x9c, 0x02, 0x2d, 0xd4, 0xef, 0x7d, 0x89, 0x84, 0xde, 0xfb, 0xe5, 0x97, 0x96, 0x2f,
+ 0xa8, 0x59, 0x63, 0x33, 0xb3, 0xc8, 0xd8, 0x58, 0x61, 0x5e, 0x7e, 0xfa, 0xfa, 0xf5, 0xde, 0x5c,
+ 0xae, 0x9e, 0xa1, 0xe1, 0x0a, 0x25, 0xf1, 0x66, 0x64, 0x64, 0x04, 0x9a, 0x15, 0x89, 0x44, 0xc1,
+ 0xc1, 0xc1, 0xa4, 0x29, 0x87, 0xc6, 0x05, 0x53, 0xd9, 0x08, 0xc1, 0xc2, 0x93, 0x0d, 0x0b, 0x0b,
+ 0x2b, 0x2e, 0xde, 0xb8, 0x76, 0xed, 0xda, 0xb9, 0x73, 0x16, 0xee, 0xce, 0xec, 0x1b, 0x84, 0x13,
+ 0xd2, 0x33, 0x32, 0xf6, 0xef, 0x3f, 0x50, 0x5f, 0x57, 0x07, 0x27, 0xfd, 0xd1, 0xe0, 0xa3, 0xa7,
+ 0x62, 0x01, 0xb0, 0xa4, 0x78, 0x93, 0x1c, 0x52, 0xec, 0x4d, 0x1f, 0x2a, 0x7e, 0xd4, 0xd4, 0x14,
+ 0x7c, 0xb4, 0x91, 0x91, 0x91, 0xc1, 0xc1, 0x01, 0xc8, 0x95, 0xce, 0x8e, 0x4e, 0x48, 0x17, 0xa8,
+ 0x85, 0x93, 0x27, 0x4f, 0x96, 0x57, 0x54, 0x12, 0xd0, 0xc2, 0x53, 0xbb, 0x76, 0xed, 0xda, 0xd0,
+ 0xe3, 0x21, 0x70, 0x32, 0x1e, 0xdb, 0x17, 0xe1, 0xc4, 0xd0, 0xd7, 0x0b, 0x58, 0x1d, 0x92, 0x96,
+ 0x93, 0x03, 0xdc, 0x06, 0xf3, 0xf9, 0xcc, 0x17, 0x5a, 0x36, 0xc9, 0x35, 0x48, 0x82, 0xed, 0xdb,
+ 0xb7, 0x27, 0x24, 0x24, 0x78, 0x7a, 0x7a, 0x42, 0x80, 0x69, 0x7a, 0x26, 0xab, 0x66, 0x24, 0x06,
+ 0x8b, 0x01, 0x24, 0x04, 0x5b, 0x52, 0x52, 0x32, 0x27, 0x65, 0xa0, 0x45, 0xa7, 0xeb, 0xe8, 0xeb,
+ 0x6b, 0xcd, 0x76, 0x3d, 0xf0, 0x96, 0x8f, 0x3e, 0xfa, 0x8f, 0xf3, 0xe7, 0xcf, 0x77, 0x75, 0x76,
+ 0x0e, 0x3d, 0x79, 0xb2, 0x84, 0x0b, 0xb2, 0x9e, 0xcd, 0xb6, 0x29, 0x99, 0x63, 0x3e, 0x53, 0xee,
+ 0x93, 0x27, 0x27, 0x27, 0xc6, 0xc7, 0xc7, 0x40, 0xb9, 0xf7, 0xee, 0xde, 0x6d, 0x6b, 0x6b, 0x6d,
+ 0x68, 0x68, 0xf8, 0xf9, 0xf4, 0x69, 0x0a, 0xb4, 0x47, 0x6b, 0x8e, 0xb5, 0xb6, 0xb6, 0x0e, 0x0f,
+ 0x0f, 0xef, 0xdb, 0xb7, 0x6f, 0xde, 0x34, 0x9f, 0x2e, 0x83, 0xe1, 0xe6, 0xed, 0x9d, 0x98, 0x91,
+ 0x99, 0x25, 0xca, 0x03, 0x68, 0xf5, 0x98, 0xca, 0x6d, 0x29, 0x8e, 0x41, 0xcb, 0xcb, 0xcb, 0x2b,
+ 0x2a, 0x2a, 0x22, 0x91, 0x2e, 0x43, 0x43, 0x43, 0x0d, 0xcd, 0xaa, 0x60, 0x54, 0x4f, 0x78, 0x1e,
+ 0x8f, 0x07, 0x05, 0x4b, 0xed, 0xd1, 0x39, 0xfd, 0xaa, 0xb6, 0xb6, 0x11, 0x9b, 0xcd, 0xb6, 0xb3,
+ 0xa3, 0xcf, 0xbe, 0x83, 0x41, 0xc1, 0xc1, 0x55, 0x55, 0x55, 0x6d, 0x6d, 0x6d, 0x4f, 0x86, 0x87,
+ 0x97, 0xb0, 0x96, 0x60, 0x4e, 0x7b, 0x6d, 0x92, 0xfc, 0x9a, 0x9c, 0x92, 0x35, 0xc9, 0xdf, 0xe7,
+ 0xc2, 0xf8, 0xb9, 0x52, 0xec, 0x8b, 0x4f, 0x19, 0x1b, 0x1b, 0x1d, 0x78, 0x38, 0xd0, 0x2d, 0x69,
+ 0xb4, 0x58, 0x5b, 0x5b, 0x0b, 0x82, 0x05, 0x62, 0x21, 0x12, 0xce, 0x9e, 0x3d, 0xd7, 0xdf, 0x0f,
+ 0xd7, 0xad, 0x2f, 0x2d, 0x3d, 0x7d, 0xde, 0xe1, 0xd2, 0xd1, 0xd5, 0xb5, 0x77, 0x75, 0x5d, 0x93,
+ 0x98, 0x14, 0x97, 0x92, 0xea, 0x11, 0x10, 0xc0, 0x78, 0x79, 0xfe, 0x7a, 0x5e, 0x73, 0x72, 0x72,
+ 0xda, 0xbe, 0x7d, 0x47, 0x72, 0x72, 0x8a, 0x97, 0x97, 0x17, 0x64, 0x98, 0x86, 0x66, 0x95, 0x35,
+ 0x52, 0x45, 0x00, 0x47, 0xc0, 0xdd, 0xdd, 0x1d, 0xb3, 0xd5, 0x96, 0x2d, 0x5b, 0x3c, 0x3c, 0x3c,
+ 0x66, 0xc6, 0x50, 0x4b, 0xcb, 0xc8, 0xcc, 0xcc, 0xd5, 0xd7, 0xd7, 0xc1, 0xd3, 0x83, 0x36, 0x7b,
+ 0xef, 0xcb, 0x3f, 0xfd, 0xe9, 0x9d, 0x1b, 0x37, 0xfe, 0x3e, 0xa4, 0x6c, 0x30, 0x4a, 0x0e, 0x5c,
+ 0x9f, 0x4f, 0x93, 0xaa, 0xd8, 0xf1, 0x9f, 0x82, 0xef, 0x26, 0x7b, 0xe0, 0x2f, 0x93, 0xe2, 0x5f,
+ 0xf0, 0x93, 0x82, 0xf1, 0xb3, 0x29, 0xd9, 0x26, 0xf2, 0x4a, 0xfe, 0xb7, 0x49, 0xc9, 0x32, 0xde,
+ 0x7b, 0xf7, 0x7a, 0x21, 0xc2, 0xcf, 0x9e, 0x3b, 0x07, 0x5f, 0x0c, 0xa0, 0x3d, 0x5c, 0x55, 0x7d,
+ 0xfd, 0xfa, 0x75, 0xd0, 0x6c, 0x45, 0x45, 0xc5, 0xcb, 0x06, 0x0d, 0x4f, 0xb1, 0xa5, 0xbd, 0x3d,
+ 0x4f, 0x20, 0xe0, 0xf2, 0x23, 0x6c, 0x9d, 0x9d, 0xe9, 0xca, 0x04, 0x10, 0x56, 0xae, 0x5c, 0x99,
+ 0x92, 0x92, 0xb2, 0x69, 0xd3, 0xa6, 0xf0, 0xf0, 0x70, 0x92, 0x50, 0xd0, 0x04, 0x0d, 0x94, 0x32,
+ 0x52, 0xa6, 0x65, 0x61, 0x61, 0xb9, 0x7a, 0xf5, 0xea, 0xfc, 0xfc, 0x7c, 0xb8, 0xc9, 0xb2, 0x3e,
+ 0xd7, 0x4a, 0x43, 0x43, 0xc0, 0x95, 0xcb, 0xe7, 0xdb, 0xb8, 0xb9, 0xca, 0xea, 0x58, 0x8c, 0xf6,
+ 0xd1, 0x9a, 0x9a, 0x47, 0x8f, 0x1e, 0x2f, 0xad, 0x93, 0x45, 0xf1, 0x2a, 0x81, 0x2b, 0x64, 0x67,
+ 0x5f, 0x7f, 0x7f, 0x47, 0x67, 0xd7, 0xed, 0x0e, 0x08, 0xcf, 0xae, 0x9e, 0xbb, 0xf7, 0x1e, 0x3c,
+ 0x1c, 0x10, 0x47, 0x21, 0x26, 0x26, 0x9f, 0x4e, 0x4c, 0x63, 0x78, 0x82, 0xe2, 0x5f, 0x15, 0x71,
+ 0x2b, 0x4e, 0x61, 0x3c, 0x7c, 0xf0, 0xa0, 0xb5, 0xb5, 0x0d, 0xfe, 0x63, 0x55, 0x55, 0x35, 0x14,
+ 0xc2, 0xe9, 0xda, 0xda, 0xee, 0xae, 0x2e, 0xc8, 0xdd, 0x8c, 0x8c, 0x8c, 0x05, 0x86, 0x8e, 0x65,
+ 0x61, 0xe1, 0x19, 0x10, 0xe0, 0xe4, 0xe5, 0x65, 0x6c, 0x61, 0xa1, 0xa5, 0xcc, 0xe4, 0x0e, 0xa0,
+ 0x96, 0x96, 0x96, 0xa5, 0xa7, 0xa7, 0x93, 0x84, 0x82, 0x66, 0x01, 0xa3, 0xe2, 0x46, 0x2d, 0xe3,
+ 0xc2, 0x54, 0x15, 0x1b, 0x1b, 0x5b, 0x52, 0xb2, 0x19, 0x6e, 0x2c, 0x45, 0xb0, 0xda, 0x3a, 0x3a,
+ 0x96, 0x4e, 0x4e, 0x80, 0xab, 0x3f, 0x2f, 0xd4, 0x48, 0xa6, 0x38, 0x16, 0x3e, 0xef, 0xfb, 0xef,
+ 0xbf, 0x0f, 0x08, 0x2d, 0x6d, 0x61, 0xe1, 0xb3, 0xe7, 0xd3, 0x04, 0x0b, 0x0c, 0x02, 0x8d, 0xdd,
+ 0x77, 0x7a, 0xbe, 0xfe, 0xfa, 0x6b, 0x70, 0x11, 0x24, 0x1f, 0x97, 0xcb, 0x85, 0x4b, 0x98, 0x99,
+ 0x99, 0xf9, 0xdb, 0xdf, 0xfe, 0xf3, 0xde, 0xbd, 0x5f, 0xd6, 0xd6, 0x9e, 0x69, 0x69, 0x6d, 0x1b,
+ 0x1a, 0x7a, 0x22, 0xe1, 0xde, 0xa9, 0x19, 0x06, 0x9e, 0xb5, 0x69, 0x87, 0x12, 0xff, 0x7a, 0x62,
+ 0x62, 0xe2, 0xd1, 0xa3, 0x47, 0xed, 0xed, 0xed, 0xf5, 0x97, 0x2f, 0x9f, 0x3a, 0x75, 0xea, 0xf4,
+ 0xe9, 0xd3, 0x37, 0x6e, 0xdc, 0xc0, 0x5f, 0xfe, 0xf6, 0xb7, 0xef, 0xe7, 0xe9, 0x8d, 0x2c, 0xe3,
+ 0x84, 0x1a, 0x9b, 0x9b, 0x9b, 0x3b, 0x3a, 0x1a, 0x59, 0x58, 0xd0, 0x94, 0x59, 0xdb, 0x08, 0x5e,
+ 0x8d, 0x8f, 0x8f, 0xc7, 0x57, 0x8b, 0x88, 0x88, 0xd0, 0xec, 0x27, 0xae, 0x94, 0x51, 0x59, 0x03,
+ 0x3c, 0xec, 0xd9, 0xd9, 0x42, 0x91, 0x28, 0x6f, 0x26, 0xaa, 0xa3, 0xa5, 0x65, 0xc0, 0x62, 0x71,
+ 0xb8, 0xdc, 0x90, 0xc8, 0x28, 0x27, 0x0e, 0x87, 0x2e, 0x73, 0x47, 0xe2, 0x13, 0x12, 0x80, 0x99,
+ 0xc5, 0x44, 0xfb, 0x5f, 0x86, 0x58, 0xa2, 0x07, 0x00, 0xbf, 0x87, 0x0f, 0x07, 0x76, 0xef, 0xde,
+ 0x6d, 0x65, 0x65, 0xc5, 0x98, 0xcf, 0x5c, 0x5d, 0xdd, 0x72, 0x72, 0x72, 0x76, 0xef, 0x7e, 0xbf,
+ 0xe6, 0xd8, 0xb1, 0xde, 0xbe, 0xbe, 0xa7, 0x00, 0xdc, 0xb4, 0x72, 0x90, 0x4a, 0x05, 0xe5, 0x51,
+ 0x0b, 0x5a, 0x87, 0x3b, 0xd6, 0xd1, 0xd1, 0xf1, 0x4b, 0x43, 0x43, 0x5d, 0x5d, 0x9d, 0xa4, 0x48,
+ 0xe6, 0x6e, 0x53, 0xd3, 0xad, 0x94, 0xd4, 0xd4, 0x59, 0x23, 0x46, 0xa3, 0xc1, 0x09, 0xd5, 0x33,
+ 0x31, 0x5e, 0xc9, 0x34, 0xd4, 0x96, 0x48, 0x50, 0x1d, 0x03, 0x03, 0x3c, 0xf3, 0xf0, 0x5d, 0xb5,
+ 0x94, 0x09, 0xd2, 0x42, 0x83, 0x81, 0x1f, 0x40, 0xb3, 0xde, 0xde, 0xde, 0x9a, 0xd2, 0x59, 0xc5,
+ 0x0d, 0x93, 0x11, 0xa9, 0x7b, 0x91, 0x04, 0xb5, 0x8a, 0xe3, 0xe3, 0x13, 0xa8, 0xb6, 0xbd, 0x34,
+ 0x1d, 0x1d, 0x1b, 0x17, 0x97, 0x20, 0x3e, 0x3f, 0x30, 0x2c, 0x9c, 0xc5, 0x66, 0x53, 0xe3, 0x69,
+ 0x6d, 0x63, 0xb3, 0x67, 0xcf, 0x1e, 0x92, 0x88, 0x5f, 0x62, 0xc4, 0x12, 0x82, 0x95, 0xc8, 0xd4,
+ 0x2b, 0x57, 0xaf, 0xc6, 0xc4, 0xc4, 0xcc, 0x0b, 0x57, 0xca, 0x8c, 0x8c, 0x8c, 0xfd, 0xfd, 0xfd,
+ 0x71, 0xd9, 0xdf, 0x7c, 0xfb, 0xed, 0x83, 0x07, 0x0f, 0xc5, 0x88, 0x9d, 0x10, 0x1f, 0x93, 0x52,
+ 0xa1, 0x4b, 0xca, 0x15, 0x15, 0xbf, 0x4c, 0xbc, 0xe1, 0xc9, 0xd0, 0x93, 0x3b, 0xdd, 0x77, 0x20,
+ 0x6b, 0x6f, 0xde, 0xbc, 0xd9, 0xd1, 0x71, 0xfb, 0xe1, 0xc3, 0x87, 0x7b, 0xfe, 0x7d, 0x8f, 0x6c,
+ 0x1f, 0x3c, 0xed, 0x95, 0x2b, 0xcd, 0x6c, 0x6d, 0x1d, 0x3c, 0x3c, 0x70, 0x58, 0x38, 0x3a, 0x88,
+ 0xdd, 0x2e, 0x1a, 0x0d, 0x70, 0xd5, 0x35, 0x34, 0x64, 0xae, 0x32, 0xd3, 0x56, 0x38, 0x93, 0x0b,
+ 0x5e, 0x85, 0x9a, 0xdd, 0xb8, 0x71, 0x23, 0xf4, 0x95, 0x26, 0x36, 0xab, 0xa0, 0x51, 0x95, 0xdb,
+ 0xce, 0xce, 0xce, 0xeb, 0xd6, 0xad, 0xdb, 0xbc, 0x79, 0xb3, 0xb7, 0x4c, 0x77, 0x4a, 0x03, 0x53,
+ 0x53, 0xef, 0xe0, 0xe0, 0x90, 0x28, 0x81, 0x13, 0xc7, 0x4b, 0x87, 0x5a, 0xb5, 0xa7, 0xa5, 0x95,
+ 0x94, 0x94, 0xd4, 0xd0, 0xd0, 0x30, 0xb1, 0x44, 0x5d, 0x31, 0xe7, 0x22, 0x56, 0xe2, 0x4f, 0x01,
+ 0x75, 0x70, 0xd8, 0x43, 0x42, 0x42, 0x16, 0x46, 0x2c, 0x31, 0x3d, 0x3d, 0x3d, 0x48, 0x1a, 0x08,
+ 0x86, 0x1f, 0x7f, 0xfc, 0xf1, 0xd1, 0xe3, 0x21, 0x02, 0x5a, 0x22, 0x12, 0x66, 0xc4, 0xad, 0x32,
+ 0xd7, 0x30, 0x0a, 0xf1, 0xdc, 0xdb, 0x0b, 0xb8, 0x76, 0x75, 0x76, 0x0e, 0x3c, 0x1c, 0x80, 0xb8,
+ 0xe5, 0xf3, 0xf9, 0xd4, 0xd7, 0x67, 0x18, 0x1b, 0xdb, 0x7b, 0x7a, 0x40, 0xbe, 0x72, 0x02, 0x02,
+ 0x3c, 0x02, 0xfc, 0x6d, 0x5c, 0x5d, 0x75, 0x25, 0x64, 0x6b, 0x6a, 0x6d, 0x6d, 0xef, 0xe1, 0x61,
+ 0x66, 0x6b, 0xa3, 0xf8, 0xf8, 0x63, 0xb4, 0x31, 0xe6, 0xc0, 0x2d, 0xf8, 0x56, 0x43, 0xb3, 0x8a,
+ 0x18, 0xc6, 0x87, 0x2c, 0x8d, 0xf1, 0xf5, 0xf5, 0xc5, 0x24, 0x5b, 0x54, 0x54, 0x34, 0xb3, 0x9e,
+ 0x94, 0x4e, 0xb7, 0x75, 0x71, 0x09, 0x8e, 0x88, 0x08, 0x0c, 0x0d, 0x33, 0x35, 0x67, 0x53, 0xb2,
+ 0x0d, 0xd8, 0xf8, 0xef, 0x6f, 0xbe, 0x79, 0xf2, 0x64, 0x78, 0xc9, 0xe1, 0x2a, 0x45, 0xec, 0x33,
+ 0x82, 0xd8, 0x86, 0x86, 0x5f, 0xa1, 0xf4, 0x14, 0x41, 0x2c, 0x85, 0x5b, 0x30, 0x95, 0x48, 0x24,
+ 0xba, 0x78, 0xf1, 0x22, 0x71, 0xcd, 0x88, 0x48, 0x90, 0x11, 0xb6, 0x4a, 0x5c, 0xc6, 0xf8, 0xf8,
+ 0x38, 0x49, 0xef, 0x0e, 0x0e, 0x0c, 0xf6, 0xf5, 0xf5, 0x96, 0x95, 0x96, 0x12, 0x2c, 0x41, 0x12,
+ 0x18, 0xb2, 0xd9, 0xae, 0xbe, 0x3e, 0x9c, 0xc0, 0x40, 0x72, 0xb8, 0xfb, 0xfb, 0x99, 0xda, 0x58,
+ 0x83, 0x63, 0xcd, 0x6d, 0x6c, 0x7c, 0x82, 0x83, 0xbd, 0x82, 0x57, 0xd3, 0x15, 0x5e, 0x93, 0x0b,
+ 0x88, 0x0a, 0x85, 0x42, 0x0c, 0x3b, 0x7c, 0x07, 0xe8, 0x1f, 0x4d, 0xa5, 0x81, 0x5c, 0xa3, 0x0a,
+ 0x09, 0x30, 0x31, 0xc1, 0x0b, 0x88, 0x8c, 0x8c, 0x9c, 0x7e, 0x01, 0x0a, 0xd6, 0xd4, 0xd4, 0x8b,
+ 0x10, 0xac, 0xa7, 0x27, 0x35, 0xd3, 0x81, 0x90, 0x33, 0x32, 0x33, 0xbb, 0xba, 0xba, 0xd4, 0x94,
+ 0x84, 0xa5, 0x10, 0x0b, 0x7a, 0x7c, 0xfc, 0x78, 0x68, 0xd7, 0xae, 0x5d, 0xb8, 0x3c, 0xc5, 0x41,
+ 0x4b, 0x0c, 0x3a, 0xfc, 0xed, 0xb7, 0xff, 0xa5, 0xa5, 0xa5, 0x75, 0x5c, 0xdc, 0x0e, 0x69, 0x6a,
+ 0xb6, 0x3b, 0xa6, 0x44, 0xcc, 0x76, 0x4a, 0x12, 0xa9, 0x18, 0x7e, 0xf2, 0x64, 0x74, 0x74, 0x74,
+ 0xef, 0xde, 0xbd, 0x40, 0xd4, 0x0a, 0x09, 0x62, 0x99, 0x16, 0x16, 0x40, 0x29, 0x85, 0x58, 0x90,
+ 0xad, 0x85, 0xa3, 0x23, 0xdc, 0x2e, 0x23, 0x16, 0x0b, 0xce, 0xe1, 0x9a, 0x84, 0x44, 0x67, 0x0e,
+ 0x47, 0x71, 0xaa, 0xe4, 0x70, 0x38, 0xa5, 0xa5, 0x65, 0x92, 0x36, 0x9e, 0xae, 0x9a, 0xed, 0x3f,
+ 0x16, 0x36, 0x92, 0xe7, 0x32, 0x31, 0x31, 0x71, 0x73, 0x73, 0x4b, 0x48, 0x48, 0x28, 0x2b, 0xdb,
+ 0x4a, 0xed, 0xd6, 0x8d, 0xf1, 0xb7, 0x72, 0x76, 0x9e, 0x26, 0x58, 0x99, 0xf2, 0x2d, 0xdc, 0xb5,
+ 0xca, 0xca, 0xc3, 0xea, 0x5b, 0xc6, 0x05, 0x44, 0x91, 0xd0, 0x16, 0x90, 0x06, 0xb4, 0x55, 0x56,
+ 0x56, 0x62, 0xde, 0x54, 0x16, 0xb1, 0x30, 0xcc, 0x14, 0x09, 0x89, 0x89, 0xc7, 0x4f, 0x9c, 0x78,
+ 0x3c, 0xf4, 0x64, 0x5a, 0x21, 0xc8, 0xba, 0x63, 0xca, 0x5c, 0x12, 0x09, 0xfa, 0x36, 0x37, 0x37,
+ 0x47, 0x45, 0x09, 0xc8, 0xa8, 0x19, 0xac, 0x5a, 0xe5, 0xe6, 0xe7, 0x4b, 0x21, 0xd6, 0xcd, 0xcf,
+ 0x0f, 0x7a, 0x80, 0xf8, 0x5c, 0x5e, 0x01, 0x01, 0xa9, 0xc2, 0x1c, 0x41, 0x5c, 0x9c, 0xbe, 0x02,
+ 0x25, 0x19, 0xc4, 0x40, 0xb3, 0xe0, 0x58, 0x4c, 0x70, 0x01, 0x01, 0x01, 0xe6, 0xe6, 0xe6, 0x9a,
+ 0x5d, 0x96, 0x16, 0x30, 0xd2, 0x3d, 0xc3, 0xc2, 0xc2, 0x22, 0x30, 0x30, 0x70, 0xfd, 0xfa, 0xdc,
+ 0x99, 0x0d, 0x5b, 0x25, 0x04, 0xeb, 0xe1, 0xef, 0x0f, 0x82, 0xf5, 0xf0, 0xf3, 0xa3, 0xcb, 0xb8,
+ 0x12, 0x79, 0x79, 0x79, 0x3d, 0x3d, 0x77, 0xd5, 0x57, 0xe5, 0x32, 0x9d, 0x3e, 0x90, 0xe6, 0x0e,
+ 0x1e, 0x3c, 0x1c, 0xd8, 0xb1, 0x63, 0x07, 0x98, 0x47, 0x35, 0xd0, 0xc2, 0x29, 0xfb, 0xec, 0xf3,
+ 0xcf, 0xef, 0xf5, 0xf6, 0x51, 0xb1, 0x2f, 0xe5, 0x05, 0xc2, 0xb4, 0x0d, 0x0d, 0x0d, 0x65, 0x65,
+ 0x65, 0x11, 0xf6, 0xd3, 0x35, 0x30, 0x70, 0xf0, 0x70, 0xe7, 0x04, 0x06, 0x00, 0xae, 0x18, 0x25,
+ 0x2b, 0x67, 0x27, 0x5d, 0x69, 0xce, 0x8b, 0x65, 0x6e, 0x9e, 0x96, 0x93, 0x93, 0x99, 0xbb, 0xc1,
+ 0x85, 0xc3, 0x51, 0xbc, 0x48, 0x06, 0x58, 0x2d, 0x2b, 0x2b, 0x8b, 0x8a, 0x8a, 0xd2, 0xec, 0x27,
+ 0xbe, 0xb0, 0x91, 0xad, 0xb8, 0x30, 0x4a, 0x18, 0x2b, 0x10, 0x2c, 0xe5, 0x73, 0x81, 0x60, 0x2d,
+ 0x1c, 0x1c, 0x02, 0x42, 0x43, 0x57, 0x47, 0x46, 0x5a, 0x3a, 0x38, 0x50, 0xe7, 0xeb, 0xe8, 0xea,
+ 0x56, 0x57, 0x1f, 0x59, 0x92, 0x5d, 0x33, 0x16, 0x30, 0x02, 0x28, 0x2a, 0xdb, 0x75, 0xf1, 0xd2,
+ 0x25, 0xdc, 0x50, 0x15, 0x10, 0x4b, 0x40, 0xeb, 0xe8, 0xe8, 0x08, 0x85, 0xd0, 0xdd, 0xdd, 0x4d,
+ 0xc2, 0x08, 0x93, 0x53, 0xaa, 0xf8, 0x62, 0xcf, 0x25, 0xd1, 0xda, 0x0f, 0x3f, 0xfc, 0x90, 0x6c,
+ 0x55, 0x46, 0xd3, 0xd6, 0x66, 0x9a, 0x99, 0xd9, 0xb8, 0xba, 0xd8, 0xba, 0xba, 0x82, 0x5d, 0xc5,
+ 0x3e, 0xa9, 0x4c, 0x7e, 0x30, 0x36, 0x29, 0x79, 0x43, 0x51, 0x51, 0x58, 0x74, 0x34, 0x63, 0x76,
+ 0x7e, 0x70, 0x01, 0xc3, 0x75, 0x6e, 0xdd, 0xba, 0x2d, 0x35, 0x35, 0x95, 0xc3, 0x11, 0x27, 0x6d,
+ 0x35, 0xfe, 0xd7, 0xbc, 0x46, 0x85, 0x61, 0xa1, 0xa3, 0x30, 0x56, 0x5b, 0xb6, 0x94, 0x4e, 0xc7,
+ 0xc9, 0xb5, 0xb4, 0x56, 0x1a, 0x1b, 0x3b, 0x79, 0x79, 0x05, 0x47, 0x44, 0xfa, 0xf3, 0x78, 0x74,
+ 0x99, 0xea, 0x02, 0x51, 0x41, 0x41, 0x6f, 0x6f, 0xaf, 0xba, 0x90, 0x2a, 0xb5, 0x67, 0xcf, 0x67,
+ 0xd1, 0xec, 0xe8, 0xd8, 0xf8, 0x57, 0x5f, 0x7d, 0x8d, 0x6b, 0x53, 0x0d, 0xb4, 0x0c, 0x71, 0x2e,
+ 0xcf, 0xe2, 0xf5, 0xd7, 0x5f, 0xbf, 0xd3, 0xd3, 0x23, 0x4e, 0x34, 0x4c, 0xa8, 0x28, 0x0f, 0x70,
+ 0x6e, 0x5d, 0x5d, 0x1d, 0xbc, 0xce, 0xe9, 0xd1, 0xa3, 0xd1, 0x30, 0xf5, 0xe0, 0xa0, 0xbd, 0x10,
+ 0x8f, 0x72, 0xf1, 0xf2, 0x12, 0x15, 0x17, 0xc7, 0xa7, 0xa5, 0xad, 0x92, 0xe8, 0x5e, 0x05, 0x2d,
+ 0x21, 0x21, 0x11, 0xda, 0x80, 0xc7, 0xe3, 0xc1, 0x79, 0xd4, 0xd7, 0xd7, 0xd7, 0x08, 0x83, 0x17,
+ 0x0d, 0x88, 0x25, 0xce, 0x75, 0x48, 0x48, 0x08, 0xc6, 0x2a, 0x2e, 0x2e, 0x8e, 0x4c, 0x46, 0x90,
+ 0xb6, 0x2c, 0x6b, 0x6b, 0x2f, 0x6e, 0x10, 0x24, 0x81, 0x8b, 0x4c, 0xa4, 0x0b, 0x27, 0x7f, 0xf7,
+ 0xdd, 0xff, 0x2c, 0xd5, 0x3e, 0x2f, 0x72, 0xe1, 0x21, 0xa6, 0x59, 0x71, 0x1e, 0x41, 0xac, 0x66,
+ 0x47, 0x46, 0x46, 0xcb, 0xb6, 0x6e, 0xc5, 0x05, 0xa8, 0x0c, 0x5a, 0x00, 0x3e, 0x3b, 0x3b, 0xfb,
+ 0xee, 0xdd, 0x7b, 0x54, 0xb4, 0x56, 0x05, 0x79, 0xf0, 0xe0, 0xc1, 0x03, 0x6f, 0x05, 0x36, 0xa6,
+ 0xc1, 0x4c, 0xb4, 0xbe, 0xa0, 0x30, 0x3d, 0x37, 0xd7, 0xc1, 0xd5, 0x55, 0x71, 0x61, 0x80, 0x1b,
+ 0xb1, 0x6d, 0xdb, 0xb6, 0xb8, 0xb8, 0x75, 0x94, 0xff, 0xa5, 0xda, 0x6d, 0xfd, 0x7f, 0x6c, 0xc0,
+ 0x27, 0xe9, 0x07, 0x0b, 0xac, 0xc2, 0x57, 0xb5, 0xb7, 0xb7, 0x27, 0x33, 0x91, 0x0e, 0x60, 0xec,
+ 0xe2, 0xe2, 0x0f, 0x49, 0x10, 0x15, 0x65, 0x20, 0x53, 0xfc, 0xb9, 0x3e, 0x37, 0x57, 0xbc, 0x0d,
+ 0x87, 0x1a, 0x71, 0x3a, 0x63, 0x54, 0x31, 0xcc, 0xa4, 0x84, 0x15, 0x01, 0xb1, 0x8e, 0xce, 0x4e,
+ 0x3e, 0x9f, 0xaf, 0x32, 0x62, 0x89, 0xa5, 0xa5, 0xa5, 0x35, 0x36, 0x35, 0x8d, 0x3f, 0x9d, 0x50,
+ 0x4d, 0xd3, 0x42, 0x0e, 0x09, 0xa2, 0xa3, 0xe5, 0xce, 0xd7, 0xd0, 0x5a, 0x69, 0xc2, 0x9c, 0x9c,
+ 0x82, 0x02, 0xaf, 0xc0, 0x00, 0x9a, 0xc2, 0x8a, 0xd4, 0xc0, 0xc0, 0x00, 0x3a, 0x19, 0xae, 0x04,
+ 0xf1, 0xbf, 0x18, 0x9a, 0x6a, 0xae, 0xd9, 0x46, 0xc2, 0xb0, 0x6c, 0x36, 0xdb, 0xcf, 0xcf, 0x4f,
+ 0x28, 0x14, 0x66, 0x67, 0x0b, 0xa7, 0x37, 0x93, 0xa5, 0xd1, 0xf4, 0x58, 0x2c, 0x07, 0x8e, 0x27,
+ 0x10, 0xeb, 0x1b, 0x12, 0x42, 0xcd, 0x4d, 0x10, 0x5a, 0x7f, 0x7e, 0xff, 0xcf, 0x83, 0x83, 0x83,
+ 0xea, 0x45, 0xaa, 0x8c, 0x49, 0x4b, 0x0d, 0xa7, 0x08, 0x68, 0x47, 0xc7, 0xc6, 0xf6, 0xed, 0xfb,
+ 0xc1, 0xc6, 0xc6, 0x66, 0x31, 0x88, 0x05, 0x2a, 0xd2, 0xd3, 0xd3, 0x2f, 0xd5, 0xd5, 0x8d, 0x8d,
+ 0x3f, 0x95, 0x56, 0x7f, 0x29, 0x01, 0x5a, 0x9c, 0xfd, 0xee, 0x7b, 0xef, 0xc9, 0x75, 0x8b, 0x30,
+ 0x68, 0xfc, 0x98, 0x98, 0xf5, 0x85, 0x85, 0xdc, 0xf0, 0x70, 0x86, 0xbe, 0xde, 0xc2, 0x27, 0x53,
+ 0x86, 0x8f, 0xe5, 0x72, 0x83, 0x36, 0x6f, 0x16, 0x77, 0x3e, 0xb7, 0xb3, 0xb3, 0xd7, 0x54, 0x73,
+ 0xcd, 0x31, 0x92, 0x99, 0xb5, 0xb3, 0xb3, 0xe3, 0xf3, 0x23, 0x36, 0x6d, 0x2a, 0xe1, 0xf1, 0x42,
+ 0xc9, 0x34, 0xa4, 0x45, 0xa7, 0x1b, 0x59, 0x58, 0x38, 0x7b, 0x7b, 0xfb, 0x04, 0x07, 0xc3, 0xf9,
+ 0xa2, 0x1e, 0x73, 0x38, 0xdd, 0x55, 0x55, 0x55, 0xaf, 0xb8, 0x37, 0x11, 0x89, 0x74, 0x91, 0xd8,
+ 0x2c, 0x10, 0xd6, 0xd9, 0xd5, 0xb5, 0x71, 0xe3, 0xc6, 0x45, 0xd2, 0x2c, 0x3c, 0xf1, 0x94, 0x94,
+ 0x94, 0xda, 0xda, 0x33, 0xe2, 0x4d, 0x16, 0x94, 0x94, 0x07, 0x38, 0xe5, 0xe2, 0xc5, 0x8b, 0x0c,
+ 0x79, 0xe5, 0x2e, 0x18, 0x34, 0x47, 0x0f, 0x0f, 0x08, 0x03, 0x5e, 0x54, 0x94, 0xbe, 0x32, 0xc5,
+ 0xde, 0xb8, 0x1d, 0xf8, 0x82, 0x49, 0x49, 0x49, 0xee, 0xee, 0x1e, 0x20, 0x10, 0x4d, 0xc4, 0x80,
+ 0x32, 0xaa, 0x1a, 0xd6, 0xd3, 0xd3, 0x33, 0x39, 0x39, 0xb9, 0xa0, 0xa0, 0x10, 0x0e, 0x35, 0x79,
+ 0x89, 0xc6, 0x60, 0xb0, 0x6c, 0x6c, 0x1c, 0x39, 0x1c, 0x57, 0x5f, 0xdf, 0x95, 0x32, 0x55, 0xca,
+ 0xb9, 0xb9, 0x1b, 0x20, 0x09, 0x5e, 0x71, 0xff, 0x37, 0x31, 0x62, 0x65, 0x52, 0x60, 0xc0, 0xd8,
+ 0xb7, 0xdf, 0x7e, 0x8b, 0xdb, 0xba, 0x78, 0xd0, 0xc6, 0xc6, 0xc6, 0x9e, 0xae, 0xad, 0x1d, 0x9b,
+ 0xd6, 0x07, 0x4a, 0x80, 0xf6, 0x7e, 0x7f, 0xbf, 0x6c, 0xa1, 0xfb, 0xcb, 0xcc, 0x94, 0xcd, 0xce,
+ 0x16, 0x89, 0x78, 0xd1, 0x02, 0x03, 0x85, 0xa3, 0xb2, 0x2b, 0x24, 0xe5, 0x70, 0x78, 0x9a, 0x36,
+ 0x6c, 0x10, 0x05, 0x06, 0x06, 0x62, 0xfa, 0xd3, 0x44, 0x0c, 0x28, 0x93, 0x86, 0x61, 0x49, 0x35,
+ 0x6c, 0x41, 0x7c, 0x7c, 0x3c, 0x75, 0x17, 0xb4, 0xf5, 0xf4, 0x4c, 0xe0, 0x03, 0xb8, 0xb8, 0x98,
+ 0xdb, 0xdb, 0x53, 0x25, 0xca, 0x10, 0x66, 0x6f, 0xec, 0xdc, 0xd9, 0xd7, 0xd7, 0xa7, 0x8e, 0x30,
+ 0x2c, 0x99, 0xfb, 0x17, 0x78, 0x75, 0x4a, 0x1a, 0xe9, 0x02, 0xcd, 0x5e, 0xbf, 0x7e, 0x23, 0x31,
+ 0x31, 0x71, 0x91, 0x88, 0x65, 0x48, 0xe4, 0x01, 0xfc, 0xcd, 0xf3, 0xe7, 0x2f, 0x4c, 0x47, 0x0f,
+ 0x14, 0x06, 0xed, 0xc8, 0xc8, 0x88, 0x22, 0x88, 0x35, 0x32, 0x36, 0x4e, 0xca, 0xcc, 0x5c, 0x1d,
+ 0x15, 0x69, 0xa8, 0xcc, 0x2a, 0x30, 0xdc, 0x97, 0x90, 0x10, 0x1e, 0xa6, 0xbc, 0x88, 0x88, 0x08,
+ 0x5b, 0x5b, 0x5b, 0x4d, 0xc4, 0x80, 0x18, 0xb5, 0x03, 0xb2, 0x8b, 0x8b, 0x0b, 0xb0, 0x5a, 0x58,
+ 0x58, 0x38, 0xb3, 0xbf, 0xbc, 0x96, 0x96, 0x38, 0x65, 0xcb, 0x66, 0xb3, 0xac, 0xad, 0x64, 0x63,
+ 0x89, 0x4e, 0x4e, 0x4e, 0x7f, 0xfd, 0xeb, 0x57, 0xc3, 0xc3, 0x6a, 0x29, 0x24, 0x90, 0xf4, 0x28,
+ 0x78, 0xe9, 0xa6, 0x09, 0xe2, 0xe2, 0xc3, 0x29, 0x29, 0xcd, 0x4a, 0x22, 0x5d, 0x7f, 0x7c, 0xeb,
+ 0x2d, 0x5c, 0xfc, 0xe2, 0x41, 0x8b, 0x67, 0x16, 0xdf, 0xab, 0xbe, 0xbe, 0x5e, 0x29, 0xa6, 0x9d,
+ 0x98, 0x98, 0x30, 0x59, 0xb0, 0xa1, 0x13, 0x31, 0x43, 0x26, 0x53, 0xb0, 0x6e, 0x5d, 0x60, 0x68,
+ 0xa8, 0xa1, 0x32, 0x1c, 0xbb, 0x42, 0xb2, 0x23, 0x18, 0xee, 0x08, 0x84, 0x01, 0x7e, 0xc1, 0xd7,
+ 0xd4, 0x08, 0x83, 0x15, 0xd2, 0xf5, 0x5c, 0x24, 0xcf, 0x25, 0x12, 0x89, 0x32, 0x33, 0x33, 0xf5,
+ 0x65, 0xc0, 0x09, 0x7f, 0x8c, 0xce, 0x64, 0x02, 0xd0, 0xb2, 0x75, 0x9e, 0x51, 0x02, 0x41, 0x5d,
+ 0x7d, 0xfd, 0xa4, 0x1a, 0xb6, 0x36, 0x00, 0x4a, 0xfa, 0xfb, 0xfb, 0x7a, 0xee, 0x74, 0x2f, 0x70,
+ 0xce, 0x33, 0x69, 0x93, 0x43, 0x42, 0xb3, 0xfb, 0xf7, 0x1f, 0x70, 0x77, 0x77, 0x5f, 0x3c, 0x62,
+ 0x89, 0x41, 0x9f, 0x9f, 0x38, 0x79, 0x72, 0x64, 0x64, 0x54, 0x41, 0x47, 0x0c, 0x67, 0xa4, 0xce,
+ 0xae, 0x95, 0x9d, 0xd7, 0xf4, 0x0c, 0x0c, 0x82, 0x22, 0x22, 0xbc, 0xb8, 0x41, 0x06, 0x4a, 0xf6,
+ 0xf6, 0x84, 0x54, 0x23, 0x11, 0x03, 0x5f, 0x5f, 0x3f, 0x53, 0x53, 0x4d, 0x2a, 0x61, 0xa6, 0x90,
+ 0xc0, 0xd9, 0xd9, 0x39, 0x26, 0x66, 0x6d, 0x49, 0xc9, 0xe6, 0x80, 0x80, 0x80, 0x99, 0x97, 0xb5,
+ 0xb5, 0xc5, 0x07, 0xc4, 0x00, 0x0e, 0xe9, 0x40, 0xe1, 0x2d, 0xe9, 0x19, 0x19, 0xb7, 0x6f, 0xdf,
+ 0x56, 0x87, 0x24, 0x18, 0x1b, 0x1b, 0x6b, 0x69, 0x69, 0x81, 0x42, 0x5e, 0xa0, 0x80, 0x55, 0x1a,
+ 0x34, 0x98, 0x8e, 0xcd, 0x36, 0x37, 0xb7, 0x08, 0x04, 0x82, 0xa5, 0x42, 0x2c, 0x1e, 0xde, 0xb0,
+ 0xb0, 0xb0, 0xea, 0xea, 0xea, 0xe1, 0xe1, 0x11, 0x45, 0x40, 0x8b, 0x3f, 0xff, 0xeb, 0x07, 0x1f,
+ 0xc8, 0x1d, 0x67, 0x7c, 0x2e, 0x27, 0x90, 0xeb, 0xe2, 0xe3, 0xa3, 0xc7, 0x7c, 0x61, 0xf1, 0xc2,
+ 0x82, 0x06, 0x3e, 0x81, 0xc6, 0x06, 0xcd, 0xf2, 0x78, 0x3c, 0x4b, 0x4b, 0x4b, 0x4d, 0x8d, 0x01,
+ 0x69, 0x5a, 0x68, 0x65, 0x65, 0x05, 0x82, 0xcd, 0xc9, 0xc1, 0xa3, 0x9c, 0x2b, 0x4b, 0xb0, 0xba,
+ 0x4c, 0xa6, 0x21, 0x8b, 0xa5, 0xa3, 0xaf, 0x27, 0xbb, 0x5e, 0xc9, 0xc0, 0xc0, 0xf0, 0xcd, 0x37,
+ 0xdf, 0x1c, 0x18, 0x18, 0x58, 0x72, 0xb8, 0x3e, 0x97, 0xec, 0xb0, 0x59, 0x5f, 0x57, 0x77, 0xe5,
+ 0xca, 0x15, 0xf9, 0x88, 0x95, 0xc6, 0x66, 0x47, 0x47, 0xc7, 0x8a, 0x8a, 0x8a, 0x54, 0x28, 0xe8,
+ 0x7a, 0x99, 0x61, 0x04, 0xa0, 0x1b, 0xab, 0xaa, 0xab, 0xc5, 0x4c, 0xab, 0x80, 0x3c, 0x38, 0x78,
+ 0xf0, 0xa0, 0xdc, 0x71, 0xd6, 0x61, 0x30, 0xec, 0x3d, 0xdc, 0xad, 0x5d, 0x5d, 0x74, 0x15, 0x8e,
+ 0x6e, 0x51, 0xc6, 0xe5, 0x72, 0x8b, 0x8b, 0x8b, 0xd7, 0xac, 0x59, 0xa3, 0x69, 0x81, 0x48, 0xd2,
+ 0xb2, 0x2c, 0x16, 0x0b, 0xb3, 0x6a, 0x5c, 0x5c, 0xdc, 0xb6, 0x6d, 0xaf, 0xe3, 0x17, 0xd9, 0x97,
+ 0x59, 0xd6, 0xd6, 0x0e, 0x9e, 0x9e, 0x16, 0x0e, 0x0e, 0xba, 0x32, 0x30, 0x76, 0x74, 0x74, 0xfc,
+ 0xdf, 0x7d, 0xfb, 0xd4, 0x14, 0xd7, 0xea, 0xef, 0xef, 0x3f, 0x75, 0xea, 0xa7, 0x33, 0x67, 0xcf,
+ 0x2e, 0x7c, 0xda, 0x4c, 0xd1, 0xac, 0x84, 0x66, 0xdf, 0xdb, 0xbd, 0x9b, 0xac, 0x98, 0x5e, 0x42,
+ 0xd0, 0x86, 0x86, 0x86, 0x9e, 0x38, 0x71, 0x42, 0x11, 0x4d, 0x7b, 0xfe, 0xfc, 0x79, 0xb9, 0x43,
+ 0x4d, 0xa3, 0xd3, 0xe1, 0xc0, 0x62, 0x3c, 0xe9, 0xca, 0xef, 0x6a, 0x07, 0x9f, 0x0b, 0x8f, 0x24,
+ 0xa4, 0x2c, 0x1c, 0x0d, 0x22, 0x65, 0x97, 0xad, 0x30, 0xa0, 0x4a, 0x61, 0xe1, 0x90, 0xe6, 0x4b,
+ 0x6c, 0xd6, 0xf3, 0xab, 0xad, 0x6d, 0xeb, 0xe6, 0xe6, 0xcf, 0xe3, 0x89, 0xe3, 0x5a, 0x32, 0x51,
+ 0x44, 0x3f, 0x3f, 0x3f, 0x70, 0x20, 0x6e, 0xe2, 0x92, 0xc3, 0x15, 0x70, 0xe8, 0xee, 0xea, 0x3e,
+ 0x7a, 0xb4, 0xe6, 0xcc, 0x99, 0x33, 0x72, 0xce, 0x9c, 0x59, 0xfc, 0x25, 0x56, 0xb3, 0x15, 0x15,
+ 0x15, 0xf8, 0x16, 0x4b, 0x88, 0x58, 0x86, 0x44, 0x1e, 0xe0, 0x9b, 0x5e, 0xba, 0x74, 0x49, 0x6e,
+ 0xf4, 0xe0, 0x97, 0x5f, 0x7e, 0x91, 0x3f, 0xd6, 0x50, 0x5f, 0x86, 0x86, 0xba, 0x26, 0x26, 0x4a,
+ 0x2d, 0xfb, 0x22, 0x06, 0x56, 0xc1, 0xad, 0xc9, 0xce, 0x16, 0x7a, 0x79, 0x79, 0x99, 0x9a, 0x9a,
+ 0x2e, 0xdb, 0x72, 0x59, 0x6a, 0xad, 0x81, 0xb7, 0xb7, 0x77, 0x4a, 0x4a, 0xca, 0xf6, 0xed, 0x3b,
+ 0x6c, 0x6c, 0x66, 0x2d, 0xee, 0x80, 0x3f, 0x06, 0xac, 0x46, 0x27, 0x24, 0xf8, 0x05, 0x07, 0x53,
+ 0x0b, 0x64, 0x24, 0x9d, 0xcd, 0x04, 0x3d, 0x3d, 0x3d, 0xea, 0x10, 0xb1, 0xf0, 0xbb, 0x9b, 0x9a,
+ 0x6e, 0x55, 0x56, 0x56, 0x5d, 0xb8, 0x70, 0x41, 0x0e, 0x62, 0xa5, 0x52, 0x76, 0x52, 0xbc, 0x71,
+ 0xed, 0x64, 0x4b, 0x6b, 0x9b, 0x9b, 0x9b, 0xdb, 0xd2, 0x22, 0x96, 0x98, 0x83, 0x83, 0xc3, 0xd9,
+ 0x73, 0xe7, 0x16, 0x4e, 0x2e, 0xdc, 0xb8, 0xf1, 0x77, 0xf9, 0xa3, 0x2d, 0x09, 0x20, 0xae, 0x00,
+ 0x5c, 0x55, 0x02, 0x5b, 0x4a, 0x4a, 0x6a, 0x5e, 0x5e, 0x3e, 0x94, 0xdb, 0x72, 0x4e, 0xd7, 0x82,
+ 0x4e, 0x99, 0x4c, 0x26, 0xee, 0x88, 0x64, 0x5b, 0xae, 0x4d, 0xeb, 0xd6, 0xc5, 0xeb, 0xce, 0x5e,
+ 0x40, 0xc7, 0x30, 0x36, 0xf6, 0x0e, 0x0e, 0x4e, 0x13, 0xe6, 0x04, 0x85, 0x87, 0x53, 0xd9, 0x70,
+ 0x30, 0xcf, 0xae, 0x5d, 0xbb, 0x86, 0xd5, 0xb3, 0x40, 0x06, 0x6e, 0x17, 0xf8, 0xea, 0x50, 0x79,
+ 0x05, 0xa4, 0xac, 0x3c, 0xc4, 0xce, 0x2a, 0x33, 0x18, 0x19, 0x1d, 0x5d, 0xbd, 0x7a, 0xb5, 0x3a,
+ 0x10, 0x0b, 0x4f, 0x07, 0xae, 0x68, 0x4d, 0x4d, 0xcd, 0xf0, 0xcb, 0xa3, 0x07, 0x8d, 0x8d, 0x4d,
+ 0x72, 0x47, 0x1b, 0xb2, 0x4a, 0x5c, 0x85, 0xa8, 0x40, 0xe4, 0x76, 0x5e, 0xe3, 0xf3, 0xf9, 0x45,
+ 0x45, 0xc5, 0x70, 0xbe, 0x96, 0xed, 0x3a, 0x1a, 0xa2, 0x60, 0xd9, 0x6c, 0xb6, 0x8f, 0x8f, 0x4f,
+ 0x7a, 0x7a, 0x46, 0x61, 0x61, 0x91, 0xb5, 0xf5, 0xdc, 0xd5, 0x73, 0x06, 0xab, 0x56, 0x71, 0xc3,
+ 0xf9, 0xc2, 0xfc, 0x82, 0x10, 0x7e, 0x04, 0xe5, 0x79, 0x99, 0x98, 0x98, 0xfc, 0xf0, 0xc3, 0x8f,
+ 0x6a, 0x2a, 0x88, 0x1d, 0x19, 0x19, 0xa9, 0xab, 0xab, 0x3b, 0x78, 0xa8, 0xfc, 0xea, 0xb5, 0x6b,
+ 0x72, 0x4f, 0x7e, 0x46, 0x35, 0x31, 0x90, 0x14, 0xc6, 0x88, 0x44, 0x22, 0x75, 0x20, 0x96, 0x21,
+ 0x91, 0x07, 0xe1, 0xe1, 0xe1, 0x47, 0x8e, 0x1c, 0x91, 0x84, 0xbc, 0xe6, 0x61, 0xda, 0xa6, 0xa6,
+ 0xa6, 0x85, 0x49, 0x0f, 0xaf, 0x9a, 0xdb, 0xd9, 0xb9, 0xf9, 0xfa, 0x1a, 0x99, 0x99, 0xa9, 0xc6,
+ 0xb1, 0x9e, 0x9e, 0x9e, 0x25, 0x25, 0xd3, 0x79, 0x84, 0xe5, 0xe9, 0x7c, 0x11, 0x05, 0x0b, 0x82,
+ 0x8d, 0x8c, 0x8c, 0x84, 0xaa, 0x0f, 0x0b, 0x0b, 0xd7, 0x7d, 0x61, 0x85, 0x32, 0xcb, 0xd2, 0x92,
+ 0x27, 0x10, 0xac, 0x2f, 0x28, 0x0c, 0x89, 0x88, 0xa4, 0xd4, 0x17, 0x54, 0xc4, 0xf9, 0x0b, 0x17,
+ 0xd4, 0xb4, 0x8b, 0xf7, 0xd0, 0xd0, 0xd0, 0xb9, 0xf3, 0xe7, 0x0f, 0x1c, 0x2a, 0xbf, 0x7e, 0xfd,
+ 0x86, 0x22, 0x88, 0x7d, 0x26, 0x6d, 0xbb, 0x81, 0x63, 0xd7, 0xae, 0xdf, 0xab, 0x09, 0xb1, 0x0c,
+ 0x49, 0x46, 0x2c, 0x4a, 0x20, 0x38, 0x7e, 0xfc, 0xc4, 0xbc, 0xf2, 0xe0, 0x56, 0x73, 0xf3, 0xc2,
+ 0xde, 0x10, 0x24, 0x81, 0x57, 0x70, 0x70, 0x70, 0x44, 0x84, 0x52, 0xf5, 0xb1, 0xb2, 0x06, 0x31,
+ 0x50, 0x5a, 0x5a, 0x1a, 0x13, 0x13, 0x03, 0xb7, 0x77, 0x19, 0xf6, 0x91, 0xa3, 0x2a, 0xb7, 0xbd,
+ 0xbd, 0x41, 0xb0, 0xe9, 0x42, 0x61, 0x8e, 0xd5, 0x8b, 0x23, 0x49, 0xa3, 0xad, 0xb2, 0xb5, 0x0d,
+ 0x97, 0x54, 0x1c, 0x01, 0xb1, 0x54, 0x0f, 0x6a, 0x0c, 0xdd, 0xcd, 0x9b, 0x37, 0xd5, 0x21, 0x62,
+ 0x61, 0x83, 0x83, 0x83, 0xb5, 0x67, 0xce, 0x80, 0x63, 0x6f, 0x35, 0xdd, 0x92, 0x8f, 0x58, 0x69,
+ 0x2a, 0x81, 0x20, 0xf6, 0xe3, 0x8f, 0x3f, 0x56, 0x1f, 0x62, 0x09, 0x68, 0xf1, 0x74, 0xe3, 0x69,
+ 0x7d, 0x4a, 0x3a, 0x77, 0xc8, 0x80, 0xb6, 0xb9, 0xa5, 0x45, 0x5f, 0x5f, 0x7f, 0x01, 0xd0, 0xd2,
+ 0xb4, 0xb5, 0xa3, 0x13, 0x13, 0xe1, 0x11, 0xb0, 0xad, 0x55, 0x44, 0x2c, 0x2e, 0x60, 0xdb, 0xb6,
+ 0xd7, 0xe3, 0xe3, 0xe3, 0xa9, 0x70, 0x81, 0x6a, 0x9f, 0xf3, 0x0f, 0x6a, 0xd4, 0xbe, 0x06, 0x50,
+ 0x47, 0xf9, 0xf9, 0x05, 0x61, 0x61, 0x61, 0xf3, 0xe8, 0x22, 0x3a, 0x9d, 0x6d, 0x6f, 0xc7, 0x5f,
+ 0xbb, 0x16, 0x88, 0x0d, 0x8d, 0x8a, 0xa2, 0x56, 0xce, 0xda, 0xda, 0xd9, 0x75, 0xab, 0x6d, 0xd9,
+ 0xec, 0xfd, 0xfb, 0xf7, 0x4f, 0xfe, 0xf4, 0xd3, 0xc1, 0xf2, 0x8a, 0xb6, 0xb6, 0x76, 0x45, 0xce,
+ 0xa7, 0xf2, 0x08, 0x00, 0xd0, 0x81, 0x03, 0x07, 0xd5, 0x8a, 0x58, 0x86, 0x44, 0x1e, 0x04, 0x05,
+ 0x05, 0xdd, 0x6c, 0x6c, 0x7c, 0x2a, 0x53, 0x04, 0x0e, 0xd8, 0xb6, 0xb6, 0xb6, 0x5a, 0x58, 0x5a,
+ 0x2e, 0x00, 0x5a, 0x6d, 0x3a, 0x3d, 0xb7, 0xa0, 0x30, 0x21, 0x35, 0xd5, 0x64, 0x11, 0xbb, 0x2c,
+ 0x6d, 0xd9, 0x52, 0x9a, 0x9a, 0x9a, 0xea, 0xe1, 0xe1, 0x69, 0x62, 0xc2, 0x5a, 0x56, 0xd5, 0xdd,
+ 0x54, 0x92, 0xcb, 0xdd, 0xdd, 0x1d, 0x1e, 0x28, 0x08, 0x16, 0x64, 0x3b, 0xcf, 0x69, 0x62, 0xc4,
+ 0xda, 0x87, 0x46, 0xaf, 0xc9, 0xc9, 0x2f, 0x00, 0x6e, 0x19, 0x86, 0xd3, 0x55, 0x5b, 0x80, 0x77,
+ 0x7f, 0x7f, 0xbf, 0x3a, 0xe0, 0x0a, 0xeb, 0xed, 0xed, 0x3d, 0x76, 0xfc, 0xc4, 0xc1, 0xf2, 0xf2,
+ 0xee, 0xee, 0x85, 0xb2, 0xb4, 0x73, 0x10, 0x4b, 0xaa, 0x62, 0x2e, 0x5f, 0xbe, 0xac, 0x6e, 0xc4,
+ 0x12, 0xe3, 0x72, 0xb9, 0xbf, 0x34, 0x34, 0xc8, 0xae, 0x22, 0x6f, 0xbf, 0x7d, 0xdb, 0xc7, 0xd7,
+ 0x17, 0x7a, 0x09, 0x6e, 0xda, 0xbc, 0xf3, 0xb5, 0x3e, 0x93, 0x59, 0xb6, 0xe3, 0x37, 0x6b, 0x13,
+ 0x12, 0x54, 0x08, 0xc6, 0x52, 0x56, 0x5c, 0xbc, 0x31, 0x2b, 0x2b, 0xcb, 0xdb, 0xdb, 0x9b, 0x04,
+ 0xb8, 0x54, 0xfe, 0x9c, 0x7f, 0x38, 0x03, 0x62, 0x31, 0xb0, 0x98, 0xdc, 0xe1, 0x02, 0xe7, 0xe6,
+ 0xe6, 0x46, 0x47, 0x47, 0xcf, 0x7f, 0x1e, 0x8d, 0x66, 0x6a, 0x6d, 0xb5, 0x3a, 0x32, 0x2a, 0x3b,
+ 0x2f, 0x2f, 0x26, 0x31, 0xd1, 0x58, 0x8a, 0xea, 0x8c, 0xac, 0x2c, 0x35, 0x65, 0xbb, 0xc4, 0xc1,
+ 0xd8, 0x3b, 0x77, 0x8e, 0x1c, 0xad, 0x39, 0x54, 0x5e, 0xde, 0xd3, 0x73, 0x47, 0x59, 0xc4, 0xde,
+ 0xbb, 0x77, 0xef, 0xd5, 0x20, 0x16, 0x4c, 0x1b, 0x1b, 0x1b, 0x7b, 0xf1, 0xd2, 0xa5, 0x71, 0x71,
+ 0x11, 0xb8, 0x98, 0x69, 0x3b, 0x3a, 0x3b, 0x13, 0x12, 0x13, 0xc9, 0x26, 0xb3, 0x8c, 0xf9, 0x76,
+ 0x38, 0xf2, 0xe1, 0x72, 0xb7, 0xbf, 0xf1, 0x06, 0x97, 0xc7, 0x5b, 0xcc, 0x8d, 0x83, 0x77, 0x2c,
+ 0x14, 0x0a, 0x7d, 0x7c, 0x7c, 0x97, 0xdb, 0x42, 0x45, 0x52, 0xb9, 0x0d, 0x49, 0x10, 0x1a, 0x1a,
+ 0x9a, 0x97, 0x97, 0xe7, 0x20, 0xb3, 0x30, 0x76, 0x8e, 0x19, 0xae, 0x32, 0xf3, 0xe3, 0xf1, 0xd2,
+ 0x72, 0x72, 0x12, 0x33, 0x32, 0x2d, 0xa4, 0xa1, 0xda, 0xd7, 0x4a, 0x4b, 0xd5, 0x87, 0xd8, 0x8e,
+ 0x8e, 0x8e, 0xaa, 0xea, 0xea, 0x43, 0xe5, 0x15, 0x77, 0xef, 0xde, 0x55, 0x14, 0xb1, 0xd2, 0xca,
+ 0xc3, 0xb1, 0xf1, 0x71, 0x4c, 0x1c, 0xaf, 0x06, 0xb4, 0x4c, 0x26, 0x13, 0x13, 0xf4, 0x85, 0x0b,
+ 0x17, 0x25, 0xa0, 0x9d, 0xc2, 0x83, 0xf6, 0xda, 0x96, 0x2d, 0x92, 0x4d, 0x66, 0x6d, 0xc9, 0x26,
+ 0xb3, 0x73, 0x46, 0x32, 0x5b, 0x24, 0xda, 0x5c, 0x56, 0x66, 0x65, 0xff, 0xd2, 0xa1, 0x56, 0xc4,
+ 0x44, 0xa2, 0x3c, 0x4c, 0x88, 0xcb, 0x10, 0xb1, 0x12, 0x11, 0x6b, 0x68, 0x6f, 0xef, 0x20, 0x10,
+ 0x08, 0x48, 0x44, 0xe8, 0x65, 0x67, 0xea, 0x18, 0x18, 0xb8, 0xf9, 0xfb, 0xc7, 0xa7, 0xa5, 0x67,
+ 0xe6, 0x6e, 0x70, 0x76, 0x73, 0x23, 0x7f, 0xdc, 0xb9, 0xf3, 0x9f, 0xd4, 0xb4, 0xf5, 0x3c, 0x44,
+ 0x61, 0x7b, 0x7b, 0x7b, 0xe5, 0xe1, 0xaa, 0xf2, 0x8a, 0x0a, 0x05, 0xd7, 0xe7, 0x4e, 0x2f, 0x49,
+ 0x90, 0xae, 0x0a, 0x77, 0x71, 0x75, 0x7d, 0x35, 0x88, 0x65, 0x88, 0xfb, 0xd1, 0x19, 0x65, 0x64,
+ 0x64, 0x5c, 0xb9, 0x7a, 0x15, 0x7e, 0xd8, 0xbd, 0xde, 0xde, 0x3f, 0xbe, 0xf5, 0x36, 0xdc, 0x22,
+ 0xd2, 0x29, 0x6b, 0xce, 0x94, 0x6d, 0xc4, 0x62, 0x6d, 0xd9, 0xb6, 0x2d, 0x2b, 0x37, 0x77, 0x31,
+ 0x92, 0x00, 0x06, 0x8f, 0x23, 0x3b, 0x3b, 0xdb, 0xc7, 0xc7, 0x67, 0x19, 0x22, 0xd6, 0xd0, 0x90,
+ 0xe9, 0xe8, 0xe8, 0xb4, 0x66, 0x4d, 0xcc, 0x9c, 0x5d, 0xd5, 0xe6, 0x18, 0xa4, 0xac, 0x8d, 0x9b,
+ 0x8b, 0x20, 0x3e, 0x5e, 0x98, 0x97, 0xef, 0x1b, 0x18, 0x48, 0xb6, 0xfe, 0x79, 0xe3, 0x8d, 0x9d,
+ 0xf0, 0x8f, 0xd4, 0x84, 0xd8, 0xd6, 0xd6, 0xb6, 0x8a, 0xca, 0xc3, 0xe5, 0x95, 0x87, 0xef, 0xf7,
+ 0x2b, 0xf4, 0x2f, 0xe6, 0x20, 0x16, 0x0a, 0xf3, 0x95, 0x21, 0x96, 0x80, 0x36, 0x2d, 0x2d, 0xad,
+ 0xb9, 0xa5, 0x05, 0xc2, 0x7e, 0xcf, 0x9e, 0x8f, 0x40, 0x80, 0x7e, 0x7e, 0xfe, 0xec, 0x17, 0x72,
+ 0x52, 0x61, 0x91, 0x91, 0xbf, 0xd9, 0xb9, 0x93, 0x1b, 0x16, 0xb6, 0xc8, 0x1b, 0x57, 0x5c, 0x5c,
+ 0x8c, 0x67, 0xc4, 0xcb, 0xcb, 0x8b, 0xc5, 0x5a, 0x5e, 0x3a, 0x96, 0xa4, 0xba, 0x08, 0x62, 0x73,
+ 0x72, 0x72, 0x16, 0x3e, 0x99, 0xc9, 0x5e, 0x15, 0xc4, 0xe7, 0x67, 0xe4, 0xe6, 0xc6, 0x25, 0x27,
+ 0xb3, 0x24, 0x7e, 0xee, 0xf6, 0x1d, 0x3b, 0xa0, 0x18, 0xd5, 0x11, 0x2b, 0x80, 0x22, 0xbc, 0x75,
+ 0xab, 0xb9, 0xbc, 0xa2, 0x12, 0x34, 0xab, 0x20, 0x8d, 0x93, 0x45, 0x34, 0x14, 0x62, 0x97, 0xb0,
+ 0xe6, 0x50, 0xd6, 0x20, 0x5c, 0x01, 0x4e, 0xf8, 0x3b, 0x10, 0xff, 0xb6, 0xb6, 0x76, 0x98, 0xfd,
+ 0x41, 0xa7, 0x19, 0x99, 0x99, 0x38, 0xb2, 0xb2, 0xb2, 0xdf, 0x79, 0xe7, 0x9d, 0xde, 0xbe, 0xbe,
+ 0xff, 0xfa, 0xe4, 0x93, 0x0d, 0x22, 0x11, 0x97, 0x1b, 0x64, 0x69, 0x69, 0x89, 0xf3, 0x31, 0xc8,
+ 0x04, 0xb4, 0x74, 0x1d, 0x9d, 0xec, 0xdc, 0xdc, 0xd7, 0xb6, 0x6e, 0xd3, 0x7b, 0xb1, 0x43, 0xb2,
+ 0x32, 0x86, 0x4f, 0x2b, 0x29, 0xd9, 0x9c, 0x94, 0x94, 0x0c, 0x1a, 0x5f, 0x6e, 0x0b, 0xbe, 0xa8,
+ 0xae, 0x2f, 0xf0, 0xb9, 0x0a, 0x0b, 0x0b, 0x19, 0x0b, 0x4e, 0x55, 0x34, 0x5d, 0x5d, 0x47, 0x4f,
+ 0xcf, 0xb8, 0xd4, 0x54, 0x61, 0x7e, 0xbe, 0x8b, 0xbb, 0x07, 0x34, 0x70, 0xd9, 0xd6, 0xad, 0x77,
+ 0xd5, 0x53, 0x54, 0x00, 0xd0, 0x35, 0x36, 0x36, 0x42, 0xc4, 0x56, 0x1e, 0xae, 0x1e, 0x18, 0x50,
+ 0x68, 0x89, 0xee, 0x34, 0x62, 0xa7, 0xd3, 0x5e, 0xe2, 0xca, 0xea, 0x25, 0x04, 0x2a, 0xe9, 0xa0,
+ 0xeb, 0xef, 0xef, 0x9f, 0x99, 0x99, 0xf9, 0xee, 0x7b, 0xef, 0x95, 0x97, 0x57, 0xe0, 0x81, 0x1a,
+ 0x1e, 0x1e, 0x91, 0x69, 0xa4, 0x4c, 0x3a, 0x81, 0x4f, 0xf5, 0xf6, 0xf5, 0x7f, 0xf0, 0xc1, 0x87,
+ 0xe0, 0x58, 0x90, 0x3c, 0x1c, 0x04, 0xc0, 0x1b, 0xbe, 0x2d, 0x68, 0x10, 0xb8, 0x72, 0xe1, 0x70,
+ 0x36, 0x95, 0x96, 0x86, 0x91, 0xf6, 0x5c, 0x8b, 0x30, 0xdc, 0xb2, 0xd2, 0xd2, 0x52, 0x78, 0x7c,
+ 0xce, 0xce, 0xce, 0x20, 0x9c, 0x65, 0x95, 0x41, 0x90, 0x78, 0x5e, 0xe2, 0x2d, 0xba, 0x22, 0x23,
+ 0x23, 0x31, 0xd1, 0xc0, 0x59, 0x58, 0xe8, 0x6c, 0x2d, 0x2d, 0xe6, 0x2a, 0x33, 0xd0, 0x6c, 0x66,
+ 0x6e, 0x6e, 0x7c, 0x5a, 0x9a, 0xa1, 0xb1, 0x71, 0x41, 0x61, 0xe1, 0x9d, 0xee, 0x3b, 0x6a, 0x2a,
+ 0x83, 0xb9, 0x79, 0x93, 0x20, 0xb6, 0x4a, 0x41, 0xe7, 0x6e, 0x76, 0xa2, 0x76, 0x6a, 0xa9, 0x12,
+ 0xb5, 0x80, 0x1c, 0x80, 0x8a, 0x6f, 0xfa, 0xe9, 0xa7, 0x9f, 0x35, 0xfc, 0xfa, 0x2b, 0x89, 0x09,
+ 0x90, 0x96, 0x47, 0x4f, 0xa5, 0xc7, 0xc4, 0xc4, 0x4c, 0x23, 0xe5, 0xae, 0xee, 0x9e, 0xdf, 0xfd,
+ 0x6e, 0x57, 0x52, 0x52, 0x12, 0x10, 0x0b, 0x44, 0x59, 0x59, 0x59, 0xb3, 0xd9, 0x6c, 0x73, 0x4b,
+ 0x4b, 0x3b, 0x47, 0xa7, 0x88, 0x98, 0x98, 0x9c, 0xbc, 0x3c, 0x4b, 0x3b, 0xbb, 0x15, 0x92, 0x3c,
+ 0xc2, 0x4a, 0x08, 0x32, 0x53, 0x53, 0x26, 0x3c, 0x44, 0x3d, 0x3d, 0xa5, 0x84, 0x28, 0x3e, 0x56,
+ 0xd2, 0x6d, 0x3e, 0x72, 0x19, 0x96, 0xc8, 0x52, 0x8d, 0x5f, 0x78, 0x3c, 0x1e, 0x69, 0x52, 0xba,
+ 0xf0, 0xf9, 0xda, 0x3a, 0x3a, 0x56, 0x4e, 0x4e, 0x51, 0xeb, 0xd6, 0x65, 0xe7, 0xe5, 0xf9, 0x70,
+ 0xb9, 0x59, 0xd9, 0xd9, 0x6a, 0xca, 0x20, 0x48, 0x11, 0x5b, 0x09, 0xc8, 0x3e, 0x78, 0xf0, 0x40,
+ 0x41, 0xc4, 0x3e, 0x93, 0x41, 0x6c, 0x59, 0x59, 0xd9, 0xe2, 0xe1, 0x1a, 0x14, 0x14, 0xf4, 0xfb,
+ 0x3f, 0xfc, 0xa1, 0xa6, 0xa6, 0xa6, 0xaf, 0xbf, 0xff, 0xa9, 0xb4, 0x4f, 0xf2, 0xc4, 0xcc, 0x06,
+ 0x37, 0x53, 0xff, 0x47, 0xde, 0x75, 0x40, 0x45, 0x91, 0x6d, 0xdb, 0xf5, 0x27, 0x3c, 0xc3, 0x8c,
+ 0x3e, 0x05, 0x1c, 0x92, 0x80, 0x0a, 0x92, 0x04, 0x0c, 0x04, 0x9d, 0x51, 0x0c, 0x28, 0x20, 0x06,
+ 0x90, 0x31, 0x83, 0x0a, 0x88, 0x01, 0x45, 0x31, 0x47, 0x40, 0x11, 0x45, 0x47, 0x40, 0x51, 0x4c,
+ 0x38, 0x32, 0x98, 0xc5, 0x38, 0x0a, 0x88, 0x24, 0x45, 0xcc, 0x80, 0x12, 0xa5, 0x69, 0xb2, 0xb4,
+ 0x48, 0x14, 0x90, 0x54, 0xd5, 0x01, 0x9d, 0xf5, 0x77, 0x55, 0x75, 0x37, 0x0d, 0x8d, 0x0c, 0x86,
+ 0x79, 0x8f, 0xbf, 0xfe, 0x5d, 0x77, 0xf5, 0xc2, 0xae, 0xea, 0x6b, 0xd5, 0xb9, 0xfb, 0xee, 0xb3,
+ 0xcf, 0x8d, 0xef, 0xc5, 0xf9, 0x83, 0xf0, 0x0f, 0x70, 0x2f, 0xc2, 0xa2, 0x09, 0x66, 0x66, 0x30,
+ 0x29, 0x40, 0x3b, 0x6a, 0xf4, 0x98, 0x59, 0x73, 0xe7, 0x2e, 0x74, 0x72, 0x5a, 0xee, 0xba, 0x6a,
+ 0xc5, 0x6a, 0x37, 0x70, 0xec, 0x10, 0x43, 0x23, 0x10, 0xc5, 0x8f, 0x7d, 0xfa, 0x18, 0x98, 0x98,
+ 0x8c, 0x9b, 0x3c, 0x79, 0x9c, 0x85, 0x85, 0x89, 0xa9, 0xa9, 0xde, 0xb0, 0xe1, 0x83, 0x34, 0x35,
+ 0xa1, 0x36, 0xa4, 0x77, 0x3d, 0x92, 0x4e, 0x74, 0xc7, 0x8e, 0xbd, 0x91, 0x91, 0xf1, 0xff, 0xc3,
+ 0x65, 0x08, 0x4c, 0x7f, 0xac, 0xbc, 0xbc, 0x3c, 0x6c, 0xbb, 0x70, 0xe1, 0x22, 0xc9, 0x35, 0x4a,
+ 0xea, 0x4a, 0xdd, 0x4f, 0xef, 0x95, 0x3d, 0xe7, 0xd7, 0xf7, 0xbc, 0x7f, 0x9f, 0x73, 0x7e, 0x7d,
+ 0x82, 0x77, 0xc9, 0xfd, 0xd0, 0xe3, 0x1b, 0xfc, 0xe0, 0x5f, 0x3d, 0x7b, 0x0e, 0xd4, 0xd1, 0x31,
+ 0x9f, 0x3a, 0xcd, 0x7a, 0xf6, 0xec, 0x5f, 0xc6, 0x8c, 0x29, 0x29, 0x29, 0xf9, 0xea, 0x70, 0x65,
+ 0x10, 0x9b, 0xc3, 0xce, 0x05, 0xc7, 0x46, 0x74, 0x3e, 0xf2, 0x62, 0x0e, 0x8f, 0x13, 0x21, 0x76,
+ 0xc3, 0x86, 0x0d, 0x5f, 0x82, 0x55, 0x10, 0xe3, 0x8a, 0x15, 0x2b, 0x9e, 0x3e, 0x7d, 0x56, 0x53,
+ 0xfb, 0xae, 0x85, 0x45, 0x25, 0xf1, 0xd9, 0xe6, 0xec, 0x30, 0xd1, 0x02, 0xc9, 0x94, 0x94, 0x94,
+ 0x89, 0x13, 0x27, 0x01, 0xb1, 0xe6, 0x16, 0x16, 0x0b, 0x1c, 0x1c, 0xbd, 0x7c, 0xf6, 0x06, 0x9d,
+ 0x0a, 0x0e, 0x08, 0x3c, 0xb2, 0xd5, 0xd3, 0xd3, 0x69, 0xf9, 0x72, 0xeb, 0x59, 0xb3, 0x06, 0x0f,
+ 0xd1, 0x83, 0x48, 0xe8, 0xd9, 0xab, 0xd7, 0x90, 0x11, 0x86, 0x93, 0x6d, 0x6d, 0x67, 0xce, 0x9f,
+ 0x3f, 0x7b, 0xc1, 0x82, 0xb9, 0x0b, 0x16, 0xda, 0xce, 0x9b, 0x37, 0x71, 0xca, 0x14, 0xa3, 0x9f,
+ 0x7f, 0xe9, 0x3f, 0x68, 0x50, 0x07, 0xf3, 0x66, 0xa9, 0x63, 0x28, 0xe9, 0xc1, 0xf4, 0xff, 0x5b,
+ 0x1d, 0x05, 0xff, 0xf3, 0x29, 0xa9, 0xe3, 0x72, 0x50, 0x3b, 0xcc, 0x08, 0xc2, 0x82, 0x05, 0x0b,
+ 0x1d, 0x1c, 0x1c, 0x7b, 0xd1, 0xb3, 0xb5, 0x0f, 0xbb, 0xcb, 0xa4, 0x87, 0xff, 0xd4, 0x94, 0xa1,
+ 0x40, 0xbc, 0x94, 0xa7, 0x72, 0xa6, 0x7c, 0x63, 0xba, 0xc2, 0xd3, 0x2b, 0xfd, 0xd6, 0xce, 0x95,
+ 0xa3, 0x76, 0x4d, 0xff, 0xf1, 0x47, 0x75, 0x5d, 0xdd, 0xb1, 0xe6, 0xe6, 0xc6, 0x63, 0xc6, 0x14,
+ 0x17, 0x17, 0xff, 0x53, 0x88, 0xcd, 0xc9, 0x81, 0x28, 0x08, 0xbf, 0x1d, 0x59, 0x55, 0x59, 0xd5,
+ 0x29, 0xc4, 0xb6, 0x9a, 0x0c, 0xf3, 0x61, 0xe7, 0xce, 0x9d, 0x9f, 0x0d, 0x57, 0xc4, 0x53, 0x57,
+ 0xaf, 0x5e, 0xab, 0xa8, 0xa8, 0x14, 0x88, 0x8e, 0x58, 0x6a, 0x96, 0x40, 0xe9, 0x7b, 0x31, 0x4a,
+ 0xa5, 0x4e, 0x69, 0x04, 0xaa, 0x63, 0x63, 0xe3, 0x10, 0xf4, 0x4d, 0x9f, 0x6e, 0xed, 0xba, 0xda,
+ 0xed, 0xc4, 0xef, 0xa7, 0xae, 0xdf, 0xba, 0x75, 0x2a, 0x24, 0x64, 0xc7, 0x4e, 0xaf, 0x65, 0xcb,
+ 0x97, 0x4f, 0x9d, 0x36, 0x7d, 0x84, 0x91, 0x91, 0x32, 0x3d, 0xe1, 0x0a, 0xa0, 0xed, 0xd6, 0xbd,
+ 0xfb, 0x8f, 0xbd, 0x7b, 0xff, 0x5b, 0x4e, 0x4e, 0x49, 0x43, 0x63, 0xd8, 0xc8, 0x91, 0x16, 0x54,
+ 0x80, 0xb0, 0x60, 0xbe, 0x83, 0xc3, 0x92, 0x95, 0x2b, 0xcd, 0xac, 0xa6, 0x28, 0x7c, 0x44, 0xa1,
+ 0xc9, 0xc9, 0xc9, 0x41, 0xf0, 0x30, 0xcb, 0x69, 0xbb, 0xf2, 0x06, 0xc8, 0x0c, 0xf6, 0xa0, 0x58,
+ 0x20, 0xe0, 0xd1, 0xac, 0x3a, 0x6f, 0x7c, 0xdc, 0xcc, 0xc8, 0x7e, 0xb4, 0x4d, 0xe9, 0x57, 0x63,
+ 0x56, 0xce, 0xc2, 0xb9, 0xd0, 0xab, 0x87, 0x1c, 0x37, 0x6e, 0x58, 0xbb, 0x78, 0x96, 0x41, 0x5c,
+ 0x70, 0xbf, 0x86, 0x74, 0x79, 0x21, 0x56, 0x5b, 0xe7, 0xda, 0xe7, 0x8a, 0x27, 0x3c, 0xe5, 0x7a,
+ 0xfd, 0xf0, 0x0d, 0x75, 0x38, 0x85, 0xb2, 0xf2, 0x20, 0x6d, 0xed, 0x94, 0x94, 0xd4, 0x7f, 0xe2,
+ 0xbc, 0x03, 0x28, 0xc2, 0x82, 0x82, 0x82, 0xdb, 0xb7, 0x23, 0xc3, 0x22, 0x6e, 0x77, 0x7e, 0xbf,
+ 0x44, 0x06, 0xb1, 0xcc, 0x01, 0x5e, 0xde, 0xde, 0xde, 0x9f, 0x81, 0x55, 0xb0, 0x96, 0xd3, 0xe2,
+ 0xc5, 0xd9, 0x6c, 0x36, 0x9f, 0x1e, 0x79, 0x15, 0x1f, 0x97, 0x20, 0xdc, 0xc7, 0x5b, 0x92, 0x51,
+ 0xdb, 0x3b, 0x57, 0xb4, 0xbe, 0xa1, 0xe1, 0x60, 0xc0, 0x21, 0x6b, 0x6b, 0xeb, 0x55, 0x6e, 0x6e,
+ 0xa0, 0xd6, 0xa8, 0x98, 0xb8, 0xa8, 0x98, 0x58, 0xf8, 0x89, 0x0b, 0x17, 0x2f, 0xf9, 0xfa, 0xfa,
+ 0xad, 0x74, 0x75, 0x9d, 0x3a, 0x75, 0x1a, 0x54, 0xb1, 0x82, 0xa2, 0x22, 0xa2, 0x27, 0xd4, 0x0b,
+ 0xe5, 0xd0, 0xe9, 0x73, 0x94, 0xa8, 0x39, 0xde, 0xdf, 0x7e, 0xdb, 0xa3, 0x77, 0xaf, 0x61, 0x26,
+ 0x26, 0x6b, 0x36, 0x6c, 0x38, 0xf9, 0x7b, 0xf0, 0xee, 0xbd, 0x7b, 0x87, 0x19, 0x1b, 0x7f, 0xd7,
+ 0xad, 0xed, 0x24, 0x3a, 0x08, 0x15, 0x70, 0x0b, 0xe2, 0x0e, 0x84, 0x75, 0x88, 0x07, 0xbb, 0xa6,
+ 0x88, 0x65, 0xb0, 0xda, 0x8d, 0x9e, 0x32, 0x84, 0x66, 0x85, 0x56, 0x06, 0x56, 0x94, 0xa7, 0x92,
+ 0xc2, 0xc7, 0x12, 0x2e, 0xe1, 0x32, 0xee, 0x82, 0x77, 0x93, 0x81, 0xbc, 0xef, 0xd5, 0x0b, 0xc8,
+ 0x6c, 0x33, 0x37, 0x83, 0xd9, 0xfb, 0x85, 0x9e, 0xc8, 0x3d, 0x00, 0x16, 0x58, 0xe5, 0xba, 0xfc,
+ 0x6a, 0xd0, 0xe2, 0x57, 0x77, 0xb5, 0xdb, 0xc5, 0xaa, 0x38, 0x37, 0xa4, 0x29, 0x1d, 0x71, 0x97,
+ 0xe9, 0xd7, 0xf7, 0x5b, 0xfc, 0xbe, 0x4f, 0x9f, 0x3e, 0x67, 0xce, 0x9c, 0x29, 0x2f, 0x2f, 0xff,
+ 0xea, 0xbb, 0xc1, 0xa0, 0x40, 0x0e, 0x87, 0x13, 0x15, 0x1d, 0x0d, 0x61, 0x50, 0xda, 0xe1, 0xea,
+ 0x6f, 0x09, 0xb8, 0x7e, 0x29, 0x62, 0x95, 0x94, 0x95, 0x3d, 0x3c, 0x3c, 0xab, 0xab, 0x6b, 0x5a,
+ 0xe2, 0x29, 0xba, 0xa8, 0xf7, 0x92, 0xbc, 0x4a, 0xbb, 0x7e, 0x49, 0x25, 0x20, 0x3e, 0x66, 0x94,
+ 0xc7, 0x17, 0x64, 0x64, 0x66, 0x2e, 0x72, 0x70, 0x5c, 0xed, 0xe6, 0x16, 0x10, 0x18, 0x18, 0x71,
+ 0x27, 0x2a, 0x29, 0xf9, 0x79, 0x68, 0xe8, 0x65, 0x7f, 0x7f, 0xff, 0x67, 0x89, 0x49, 0x90, 0x37,
+ 0x87, 0x0f, 0x07, 0xba, 0xb9, 0xad, 0x01, 0x68, 0xf5, 0xf5, 0xf5, 0x5b, 0x81, 0xb6, 0x75, 0x52,
+ 0x53, 0x57, 0x77, 0x5a, 0xb6, 0x3c, 0x38, 0x24, 0x64, 0xe3, 0xd6, 0x6d, 0xaa, 0x83, 0x07, 0x4b,
+ 0x2a, 0x5b, 0x3c, 0xe4, 0xd4, 0xa9, 0x53, 0xed, 0xec, 0xec, 0xc0, 0x30, 0xa8, 0xd9, 0x6e, 0x5d,
+ 0x72, 0x01, 0x02, 0x03, 0x57, 0xa8, 0xcd, 0x3e, 0x7d, 0xfb, 0x2a, 0x29, 0x29, 0x6b, 0x68, 0x0c,
+ 0xc6, 0xfb, 0x0e, 0x1f, 0x31, 0xc2, 0x10, 0x61, 0x92, 0x91, 0xf1, 0xc7, 0x12, 0x2e, 0xe1, 0x32,
+ 0xda, 0x23, 0x5a, 0xb4, 0x8e, 0x8e, 0x8e, 0xda, 0x80, 0x01, 0x78, 0x41, 0xc6, 0x44, 0x2d, 0x87,
+ 0xc7, 0xa1, 0x51, 0xf7, 0xe8, 0x01, 0x54, 0x1b, 0x18, 0x18, 0xd8, 0xd8, 0xcc, 0x08, 0xdc, 0xbd,
+ 0xb8, 0x34, 0x41, 0xab, 0x15, 0x3e, 0xb3, 0x90, 0x15, 0x5a, 0xb2, 0x18, 0xb4, 0xe9, 0x8a, 0x87,
+ 0xb6, 0xf5, 0x95, 0xf9, 0xf7, 0x37, 0x28, 0x6d, 0xfc, 0xf8, 0xf1, 0xa7, 0x4e, 0x9d, 0x42, 0x60,
+ 0xf2, 0x75, 0xe3, 0x2f, 0x94, 0x56, 0x5e, 0x5e, 0x11, 0x77, 0xf7, 0x6e, 0x58, 0x58, 0x78, 0x71,
+ 0xf1, 0xab, 0xce, 0xff, 0xea, 0xb3, 0x11, 0xab, 0xa8, 0xa8, 0xb8, 0xdf, 0xd7, 0x17, 0x24, 0xd9,
+ 0xdc, 0x46, 0xb5, 0x7e, 0x68, 0xc9, 0x1f, 0x3e, 0xb4, 0x84, 0x5a, 0x02, 0x6e, 0x1d, 0x9f, 0xe4,
+ 0x08, 0xc8, 0x57, 0x02, 0xb2, 0x48, 0x40, 0x16, 0x08, 0x88, 0xdc, 0xa6, 0xda, 0x8c, 0xb4, 0xe4,
+ 0xeb, 0xe7, 0xfe, 0xd8, 0x77, 0xf8, 0xc8, 0xd1, 0xeb, 0x37, 0x6f, 0x01, 0xae, 0xe9, 0xe9, 0x19,
+ 0x56, 0x56, 0x53, 0x54, 0x55, 0x55, 0x03, 0x8f, 0x1c, 0x81, 0xbe, 0xbd, 0x73, 0x27, 0x0a, 0xa0,
+ 0x5d, 0xb5, 0x6a, 0xb5, 0xa5, 0xe5, 0xe4, 0x21, 0x43, 0x86, 0x80, 0x58, 0x98, 0x61, 0x5c, 0x69,
+ 0xd4, 0x19, 0x9b, 0x9a, 0xae, 0x5e, 0xb7, 0xde, 0x65, 0xb5, 0xdb, 0x50, 0x13, 0x93, 0xee, 0xad,
+ 0x37, 0x33, 0x71, 0x74, 0x14, 0xce, 0x81, 0x61, 0x06, 0xd4, 0xba, 0x20, 0x62, 0x99, 0x13, 0x36,
+ 0xf1, 0x78, 0x40, 0x1d, 0x5a, 0x16, 0x54, 0x3d, 0x1e, 0x18, 0xad, 0x6c, 0x21, 0x62, 0x7b, 0x07,
+ 0x24, 0xc7, 0x76, 0x33, 0x2e, 0xe1, 0x32, 0xdc, 0xc7, 0x9c, 0x39, 0x73, 0xa6, 0x4d, 0x9b, 0x36,
+ 0x7a, 0xf4, 0x68, 0x6d, 0x6d, 0x6d, 0x98, 0x08, 0x2c, 0xcd, 0x98, 0x88, 0x51, 0xb0, 0x28, 0x16,
+ 0x72, 0x68, 0xc2, 0x04, 0xb3, 0xe5, 0xcb, 0x5d, 0x58, 0xb7, 0x4d, 0xa0, 0x57, 0x25, 0xe0, 0xaa,
+ 0x48, 0x64, 0x2b, 0x11, 0xd9, 0xfd, 0x89, 0x6c, 0x15, 0xfa, 0x53, 0x99, 0x60, 0x29, 0xb6, 0x80,
+ 0x36, 0x55, 0xe9, 0x98, 0xbb, 0xdc, 0xf7, 0xdf, 0x51, 0xad, 0x49, 0x4b, 0x4b, 0xeb, 0xc0, 0x81,
+ 0x83, 0x5f, 0x7d, 0x28, 0xa1, 0xba, 0xba, 0x3a, 0x21, 0xe1, 0x01, 0x10, 0x9b, 0x9f, 0x97, 0xff,
+ 0x4f, 0x23, 0x16, 0x6e, 0x6b, 0xf7, 0x9e, 0x3d, 0x0d, 0x8d, 0x8d, 0x02, 0x89, 0xd3, 0xbe, 0xde,
+ 0x4b, 0xe0, 0x93, 0x29, 0x53, 0xd4, 0xaf, 0xc5, 0x17, 0xf0, 0x6a, 0x79, 0x8d, 0x85, 0xbc, 0xfa,
+ 0x14, 0x7e, 0x43, 0x32, 0xbf, 0x21, 0x91, 0x57, 0xff, 0x88, 0xf7, 0xee, 0x2e, 0xaf, 0xe6, 0x0e,
+ 0xb7, 0x26, 0xbc, 0xbe, 0x2c, 0x32, 0xe5, 0x79, 0x5c, 0xd2, 0xf3, 0x17, 0xf9, 0x05, 0x85, 0xfb,
+ 0xf6, 0xfd, 0x26, 0x27, 0xd7, 0x0f, 0x6c, 0xa3, 0xab, 0xab, 0x1b, 0x14, 0x14, 0x94, 0x96, 0x96,
+ 0x1e, 0x19, 0x79, 0x27, 0x20, 0xe0, 0xd0, 0xb2, 0x65, 0xcb, 0xcd, 0xcd, 0xcd, 0xf1, 0x25, 0x7c,
+ 0x65, 0xbb, 0x9e, 0x5d, 0x55, 0x53, 0xd3, 0xca, 0x66, 0x86, 0xa5, 0xb5, 0xb5, 0xae, 0xa1, 0x61,
+ 0xf7, 0x1f, 0x84, 0x88, 0x05, 0x3e, 0x27, 0x4e, 0x9c, 0xb8, 0x71, 0xe3, 0x46, 0xa8, 0x0e, 0xd4,
+ 0x26, 0x1c, 0x5c, 0x17, 0x44, 0xac, 0xd8, 0x71, 0xab, 0xa8, 0xa8, 0x82, 0x36, 0xc1, 0x84, 0x2b,
+ 0x57, 0xba, 0x7a, 0x79, 0x79, 0xc1, 0xd1, 0x1c, 0x42, 0x73, 0x45, 0xd3, 0xfd, 0x48, 0xc2, 0x15,
+ 0x5c, 0x3e, 0x18, 0x10, 0xb0, 0x77, 0xef, 0xbe, 0x2d, 0x5b, 0xb6, 0x02, 0xde, 0x80, 0x25, 0xc8,
+ 0x16, 0x4c, 0xcb, 0x8c, 0xc2, 0x88, 0x8a, 0x55, 0x31, 0x31, 0x31, 0x99, 0x3f, 0xdf, 0x2e, 0xfc,
+ 0xa8, 0x79, 0x4b, 0x9c, 0x45, 0x51, 0xab, 0x12, 0x05, 0x54, 0xb6, 0x1a, 0xc1, 0x1e, 0x48, 0xb0,
+ 0x07, 0x11, 0x6c, 0x75, 0x2a, 0x67, 0xab, 0x4a, 0x32, 0x6d, 0x7d, 0x8a, 0xe2, 0xde, 0x95, 0xc2,
+ 0x83, 0x3c, 0x40, 0x50, 0xdb, 0xdd, 0xdd, 0x21, 0x0f, 0xbe, 0x22, 0x68, 0xeb, 0xeb, 0xeb, 0x13,
+ 0x13, 0x13, 0xa1, 0x0a, 0xb2, 0x59, 0xd9, 0xff, 0x28, 0x62, 0xd1, 0x6c, 0xb7, 0x6d, 0xdf, 0x5e,
+ 0x5e, 0x51, 0x21, 0x90, 0xa6, 0x56, 0x49, 0xa0, 0xd2, 0x8b, 0xc8, 0xaa, 0xaa, 0xaa, 0x1e, 0x24,
+ 0xdc, 0x3b, 0xfd, 0xc7, 0x31, 0xbf, 0xfd, 0x5e, 0x3b, 0x3d, 0x37, 0x79, 0x7a, 0x6c, 0xf0, 0xdd,
+ 0xbf, 0xf3, 0x74, 0x48, 0x60, 0x7c, 0xdc, 0xb5, 0x37, 0x9c, 0xe7, 0xbc, 0xa6, 0x7c, 0x3e, 0x91,
+ 0x47, 0x36, 0x14, 0x55, 0xbf, 0x2d, 0xbb, 0x79, 0x2b, 0x6c, 0xf8, 0xf0, 0xe1, 0x80, 0x6b, 0x37,
+ 0x7a, 0xa4, 0x0c, 0xb1, 0xed, 0xf9, 0xf3, 0xe7, 0x21, 0x1b, 0xc2, 0x23, 0x22, 0x7e, 0xdb, 0xbf,
+ 0xdf, 0xd9, 0x79, 0x89, 0x99, 0x99, 0x19, 0x1a, 0x7b, 0xbb, 0xf3, 0x12, 0x11, 0x23, 0x50, 0x47,
+ 0x30, 0xff, 0xf2, 0x8b, 0x92, 0xba, 0xba, 0xf8, 0x98, 0x09, 0x18, 0x79, 0xdd, 0xba, 0xf5, 0x3b,
+ 0x76, 0xec, 0xa0, 0x39, 0xb6, 0x8b, 0x76, 0x14, 0x88, 0xf7, 0x71, 0xd5, 0xd3, 0xd3, 0x83, 0xfe,
+ 0x59, 0xb3, 0x66, 0xed, 0x91, 0xa3, 0x47, 0xc3, 0xc2, 0xc3, 0x1f, 0x3c, 0x7c, 0xf8, 0xf4, 0xd9,
+ 0xb3, 0xc4, 0xc4, 0xa4, 0x0e, 0x32, 0x2e, 0x3f, 0x7e, 0xf2, 0x24, 0x36, 0x2e, 0xee, 0xe2, 0xc5,
+ 0x4b, 0x7b, 0x7c, 0x7c, 0xc0, 0xba, 0xa6, 0xa6, 0x63, 0x07, 0x0d, 0x1a, 0xf4, 0x6f, 0x7a, 0x52,
+ 0x13, 0xad, 0x07, 0x7e, 0x82, 0xc0, 0x40, 0x54, 0xbb, 0x6b, 0x9d, 0x33, 0x27, 0x5e, 0xab, 0x05,
+ 0xae, 0x2c, 0x06, 0xae, 0x00, 0xaa, 0x26, 0xc1, 0xd6, 0x21, 0xd8, 0xba, 0xa2, 0xac, 0x49, 0x83,
+ 0x56, 0x49, 0x0c, 0xda, 0xc2, 0x38, 0x85, 0x51, 0xba, 0xc2, 0x95, 0xe0, 0x70, 0x70, 0xb6, 0xb6,
+ 0xbf, 0xd6, 0xd6, 0xd6, 0x7e, 0x2d, 0xd0, 0x92, 0x04, 0x99, 0x95, 0x95, 0x15, 0x15, 0x15, 0x9d,
+ 0x99, 0x99, 0xf9, 0xcf, 0x21, 0x16, 0x68, 0x81, 0xb3, 0x2a, 0x2a, 0x7a, 0x45, 0x8d, 0x5e, 0xb5,
+ 0x16, 0xae, 0xc2, 0x01, 0xdf, 0x66, 0xe1, 0x60, 0x41, 0x52, 0x52, 0xf2, 0xfa, 0xf5, 0xeb, 0xf5,
+ 0xf5, 0xf4, 0xd4, 0xd4, 0xd4, 0x10, 0x28, 0xc8, 0xc9, 0xca, 0xf6, 0xa5, 0x52, 0x1f, 0x20, 0x07,
+ 0xff, 0x54, 0x55, 0x55, 0xd1, 0xd2, 0xd4, 0x98, 0x34, 0x71, 0x82, 0xef, 0xfe, 0x3d, 0xe9, 0x69,
+ 0xc9, 0xc9, 0x49, 0xcf, 0x2c, 0x2d, 0x2d, 0x25, 0x37, 0xfa, 0xa0, 0x40, 0x3b, 0x7c, 0xf8, 0xed,
+ 0xc8, 0xc8, 0xcc, 0x97, 0x59, 0xd7, 0xae, 0xdf, 0xd8, 0xe3, 0xb3, 0x97, 0xae, 0x11, 0x53, 0x75,
+ 0x75, 0x0d, 0x04, 0x1a, 0x6d, 0x40, 0xfb, 0xe3, 0x4f, 0xfd, 0x20, 0xfe, 0x54, 0x34, 0x35, 0x7b,
+ 0xf4, 0xed, 0x7b, 0x70, 0x8b, 0x5c, 0x7a, 0x78, 0xbf, 0xf4, 0xdb, 0x72, 0xac, 0x68, 0xc5, 0xd7,
+ 0x8f, 0xb5, 0x43, 0x4f, 0xd9, 0x2f, 0x5a, 0xb4, 0x10, 0x3c, 0x03, 0x00, 0x77, 0xc1, 0xc8, 0x4b,
+ 0x3c, 0x8a, 0x6a, 0x3a, 0x76, 0xec, 0x92, 0xa5, 0x4b, 0x0f, 0x1d, 0x3a, 0x1c, 0x1b, 0x1b, 0x77,
+ 0xe0, 0xc0, 0x81, 0x81, 0x9d, 0x4e, 0x50, 0x4d, 0x0f, 0x1f, 0x3e, 0xba, 0x7e, 0xe3, 0x86, 0x97,
+ 0xd7, 0xae, 0x79, 0xf3, 0xe6, 0x31, 0xb3, 0xe0, 0x60, 0x22, 0xb4, 0x02, 0x78, 0x16, 0x0b, 0x0b,
+ 0x8b, 0x35, 0x2b, 0x97, 0x3e, 0x3b, 0x3b, 0xa6, 0x21, 0x45, 0xe4, 0xf1, 0x29, 0xb8, 0xaa, 0xd2,
+ 0x70, 0xd5, 0x26, 0xd8, 0x43, 0xa4, 0xb2, 0x26, 0xc1, 0x52, 0x91, 0x64, 0xda, 0xf8, 0xf3, 0xb2,
+ 0xfd, 0x64, 0x5a, 0x8c, 0xc6, 0x6c, 0x5f, 0xf0, 0x55, 0xd6, 0x2a, 0x02, 0x40, 0xaf, 0x39, 0xaf,
+ 0x13, 0x9f, 0x3d, 0xeb, 0xcc, 0x3a, 0x2f, 0x69, 0xc4, 0xee, 0xdb, 0xb7, 0xef, 0x6f, 0xe1, 0x0a,
+ 0x14, 0xc1, 0xcf, 0x3e, 0x7f, 0xfe, 0xa2, 0x4d, 0x17, 0x96, 0x50, 0x06, 0xd0, 0x58, 0x6d, 0x6a,
+ 0x22, 0x9e, 0x3c, 0x7d, 0x66, 0x6f, 0x6f, 0xcf, 0xcc, 0x77, 0xed, 0x4c, 0x42, 0xb1, 0x1f, 0x3b,
+ 0x97, 0x01, 0x36, 0x47, 0x1b, 0x04, 0xd3, 0xde, 0xb8, 0x71, 0x63, 0xcf, 0x1e, 0x1f, 0xa8, 0xba,
+ 0x71, 0xe3, 0xc6, 0x0d, 0x1e, 0xac, 0x09, 0xa6, 0x65, 0x96, 0x2d, 0x30, 0x81, 0xd8, 0x77, 0x3f,
+ 0xfc, 0x00, 0xd0, 0x7e, 0xdf, 0xab, 0xd7, 0xe4, 0x51, 0x7d, 0x5e, 0xde, 0x52, 0x20, 0x58, 0xca,
+ 0x44, 0xf6, 0x00, 0xc6, 0xcd, 0x35, 0x65, 0x2a, 0x05, 0xf9, 0x4e, 0x9d, 0x62, 0x65, 0x49, 0xf7,
+ 0x6e, 0x75, 0x2d, 0x61, 0xc0, 0x2c, 0x10, 0x80, 0xa1, 0x98, 0xb3, 0x33, 0xb6, 0x6e, 0xdb, 0x76,
+ 0x29, 0x34, 0x34, 0x3d, 0x23, 0xf3, 0x93, 0xc6, 0x1f, 0x81, 0xcf, 0xcb, 0x57, 0xae, 0x80, 0x8f,
+ 0x83, 0x83, 0xff, 0x80, 0x4f, 0x41, 0xa4, 0x69, 0x60, 0x30, 0x14, 0x4c, 0x0b, 0x7f, 0x84, 0xa0,
+ 0xc9, 0xd9, 0x71, 0xd1, 0x79, 0x2f, 0xdb, 0xd2, 0x38, 0x4d, 0xe2, 0x25, 0x98, 0x53, 0x81, 0xd6,
+ 0xae, 0x6a, 0xb4, 0x06, 0x68, 0x03, 0x57, 0x3d, 0x51, 0xc6, 0xdf, 0x1a, 0x34, 0x68, 0x81, 0x70,
+ 0x2a, 0xc3, 0x80, 0xd7, 0x03, 0xfb, 0x0d, 0x54, 0xee, 0xc6, 0xf4, 0x9e, 0x21, 0x81, 0xb7, 0xef,
+ 0x44, 0x45, 0x35, 0x36, 0x35, 0x7d, 0x21, 0xd5, 0x22, 0x02, 0xaf, 0xa9, 0xa9, 0x61, 0xb3, 0xd9,
+ 0x85, 0x85, 0x85, 0x9f, 0x84, 0x58, 0x66, 0x09, 0x0b, 0xb4, 0xd3, 0xdf, 0x1a, 0x07, 0x76, 0x80,
+ 0x49, 0x45, 0x9d, 0xae, 0x6d, 0xc5, 0x00, 0xbe, 0x7c, 0x57, 0x57, 0x17, 0x12, 0x12, 0xf2, 0xd9,
+ 0x67, 0xd9, 0xb4, 0x9b, 0x46, 0x18, 0x1a, 0xde, 0xbb, 0x77, 0x2f, 0x25, 0x35, 0x2d, 0xf4, 0xf2,
+ 0xe5, 0x5d, 0xde, 0xde, 0x0e, 0x8e, 0x8e, 0xe3, 0xc7, 0x4f, 0x40, 0x75, 0xc8, 0xcb, 0xcb, 0xb7,
+ 0xf4, 0x1e, 0x20, 0x7f, 0xfb, 0xad, 0xa2, 0xec, 0xf7, 0xe7, 0xf6, 0xc9, 0x35, 0xa1, 0x6a, 0x28,
+ 0x02, 0xd1, 0xa5, 0x8d, 0xaf, 0x4b, 0xb0, 0x06, 0x54, 0x3f, 0x51, 0x5b, 0xea, 0x68, 0xd3, 0x05,
+ 0x8f, 0xf7, 0x12, 0x75, 0xef, 0xcb, 0x23, 0xe4, 0xb7, 0xb7, 0x5f, 0xb0, 0xdf, 0xd7, 0x2f, 0x3a,
+ 0x26, 0x26, 0xbf, 0xa0, 0x00, 0x6f, 0xf7, 0x49, 0x26, 0x82, 0xec, 0xc9, 0xc8, 0xc8, 0x04, 0x8a,
+ 0xfc, 0x0f, 0x1c, 0x58, 0xba, 0x6c, 0x99, 0x95, 0x95, 0xd5, 0x98, 0x31, 0x63, 0x26, 0x4d, 0x9a,
+ 0x84, 0x08, 0x2d, 0xc0, 0xc3, 0x25, 0xfd, 0xc2, 0x84, 0xfa, 0x94, 0xc1, 0x44, 0xd6, 0x40, 0x98,
+ 0x82, 0x56, 0xad, 0x1a, 0xb4, 0x12, 0x90, 0xc4, 0xaa, 0x3e, 0xc1, 0x1e, 0x4a, 0xe4, 0x0c, 0x23,
+ 0x72, 0x46, 0x10, 0xb9, 0x46, 0x44, 0xee, 0x70, 0x22, 0x47, 0x87, 0xc8, 0x1e, 0x44, 0xb0, 0x06,
+ 0x32, 0xb9, 0x31, 0x5d, 0x3d, 0x70, 0xbb, 0x4a, 0x7f, 0x85, 0x5e, 0xdd, 0x7b, 0xf4, 0x80, 0xb2,
+ 0x02, 0x51, 0x18, 0x0c, 0x1d, 0x7a, 0xe6, 0xcc, 0x19, 0xe0, 0xed, 0x0b, 0x15, 0x02, 0x49, 0x92,
+ 0xe5, 0x65, 0xe5, 0x15, 0x9d, 0x9d, 0xd1, 0x2d, 0x46, 0x2c, 0x95, 0xb7, 0x6f, 0xdf, 0xde, 0xb1,
+ 0x59, 0x00, 0x0f, 0x57, 0x57, 0x57, 0x61, 0xe7, 0x40, 0xeb, 0x6e, 0x01, 0x46, 0x0c, 0xf0, 0xf8,
+ 0x7c, 0x04, 0x0b, 0x5f, 0xbe, 0x85, 0x72, 0x9b, 0x04, 0x06, 0x86, 0x6b, 0x8b, 0x8a, 0x8e, 0x4e,
+ 0x4c, 0x4a, 0xba, 0x74, 0x29, 0x14, 0x82, 0x6d, 0xf1, 0xe2, 0xc5, 0xa0, 0x7a, 0x84, 0xff, 0x70,
+ 0xf4, 0x08, 0x2e, 0x18, 0xda, 0xfc, 0xd7, 0x77, 0xdf, 0xb8, 0xd8, 0xc8, 0xbc, 0x7d, 0xac, 0x42,
+ 0xbb, 0x3c, 0x9d, 0x56, 0x6e, 0xee, 0xa5, 0xf2, 0xa6, 0x75, 0x0b, 0x51, 0x89, 0x5d, 0x6d, 0x5e,
+ 0x01, 0xd3, 0xbd, 0x8f, 0xa7, 0x1a, 0x3b, 0x76, 0xec, 0x8a, 0x15, 0x2b, 0x83, 0x4e, 0x9e, 0x84,
+ 0x7b, 0x7a, 0xfc, 0xf8, 0xf1, 0xa7, 0x1e, 0xb8, 0x86, 0xa0, 0xf2, 0xfc, 0x85, 0x0b, 0x08, 0x54,
+ 0xaf, 0x5c, 0xbd, 0xe6, 0xe3, 0xb3, 0xd7, 0xd5, 0x75, 0x95, 0xa3, 0x93, 0x13, 0x3e, 0xfd, 0xbc,
+ 0xb7, 0x25, 0x1c, 0xb7, 0xab, 0x4c, 0x30, 0x25, 0xb2, 0x0d, 0x09, 0x36, 0x70, 0x68, 0x40, 0xe5,
+ 0x5c, 0x80, 0x93, 0xfe, 0x9b, 0x21, 0x55, 0xea, 0xcb, 0x11, 0x64, 0xae, 0x09, 0x91, 0x37, 0x9a,
+ 0xc8, 0x1b, 0x47, 0xe6, 0x4f, 0xa4, 0xf3, 0x58, 0x32, 0x6f, 0x24, 0x99, 0x63, 0x28, 0xca, 0x23,
+ 0x38, 0x0f, 0x0d, 0x6d, 0x2d, 0x07, 0x29, 0x28, 0x28, 0x32, 0x7d, 0xbf, 0x68, 0xf8, 0x70, 0x7f,
+ 0x3e, 0x3e, 0x3e, 0xd5, 0x00, 0xad, 0x70, 0xfc, 0x54, 0x88, 0x28, 0xd1, 0xa7, 0x38, 0xb5, 0x73,
+ 0xaa, 0xe6, 0x5f, 0x62, 0xf8, 0xbd, 0x7f, 0xdf, 0x48, 0xa7, 0x96, 0x9b, 0xff, 0x12, 0x8e, 0xc6,
+ 0x4a, 0x14, 0xd8, 0x92, 0x3e, 0x48, 0x20, 0x16, 0x9a, 0xb3, 0x63, 0xb3, 0xc0, 0x73, 0x65, 0xb1,
+ 0x58, 0x2d, 0xd3, 0x03, 0xe8, 0x5e, 0x56, 0xd1, 0xcf, 0x29, 0x91, 0x70, 0xe5, 0xca, 0x95, 0xaf,
+ 0x0e, 0x57, 0x26, 0xc1, 0x44, 0x36, 0x36, 0x36, 0xe0, 0x1f, 0x68, 0xe3, 0xab, 0xd7, 0xae, 0xfd,
+ 0xf6, 0xdb, 0xfe, 0xa5, 0x4b, 0x97, 0x59, 0x5a, 0x4e, 0xd6, 0x37, 0x30, 0x50, 0x52, 0x52, 0x62,
+ 0xce, 0x98, 0xd3, 0x56, 0xe9, 0x71, 0xef, 0x98, 0x4a, 0xd3, 0x4b, 0xe8, 0x01, 0x0d, 0x11, 0xc1,
+ 0x0e, 0x11, 0xd1, 0x6c, 0xff, 0xf0, 0x20, 0x33, 0xc0, 0x5e, 0x5d, 0x5d, 0x1d, 0x60, 0xe8, 0x3a,
+ 0xb3, 0x0d, 0x99, 0x70, 0x1e, 0x4f, 0x35, 0x79, 0xf2, 0xe4, 0xcd, 0x9b, 0x37, 0x5f, 0xbc, 0x14,
+ 0x0a, 0xaa, 0x3c, 0x76, 0xec, 0xd8, 0x67, 0x9c, 0x5d, 0x05, 0x19, 0x9c, 0x97, 0x9f, 0xff, 0xf4,
+ 0xe9, 0xb3, 0xcb, 0x97, 0xaf, 0x20, 0x76, 0x83, 0x12, 0xfe, 0xfd, 0xf8, 0xb1, 0xfb, 0x21, 0x9e,
+ 0x9c, 0x68, 0xc7, 0x86, 0xec, 0x59, 0x64, 0xe1, 0x0c, 0xb2, 0x60, 0x3a, 0x51, 0x68, 0x49, 0x16,
+ 0x4c, 0x22, 0xf3, 0xc7, 0x91, 0x79, 0xbf, 0x50, 0x74, 0x4a, 0x61, 0x15, 0xe8, 0x35, 0x24, 0xf3,
+ 0x46, 0x93, 0xf9, 0x93, 0xc8, 0x42, 0x6b, 0xe2, 0xd5, 0x5c, 0xb2, 0x78, 0x21, 0xb7, 0xd8, 0x81,
+ 0x2c, 0x5e, 0x44, 0x16, 0xcf, 0x23, 0x0b, 0x7f, 0x25, 0x0b, 0x6d, 0xe9, 0x8c, 0x9f, 0xcf, 0x48,
+ 0x8d, 0x9e, 0x62, 0x31, 0xd1, 0x58, 0x53, 0x53, 0x53, 0x59, 0x59, 0x59, 0x56, 0x56, 0xae, 0xaf,
+ 0x8c, 0x0c, 0xfe, 0x5e, 0xbb, 0x6e, 0x1d, 0x42, 0x7e, 0xe6, 0x4c, 0x37, 0x66, 0x6b, 0xac, 0x56,
+ 0xb9, 0xf5, 0x80, 0x91, 0x34, 0xfc, 0x98, 0x71, 0x4f, 0x08, 0x5a, 0xf1, 0x37, 0x1f, 0x5a, 0x5f,
+ 0x95, 0x2a, 0x53, 0xa4, 0x3f, 0xdf, 0x7f, 0x00, 0x7f, 0x76, 0x6c, 0x93, 0x83, 0x07, 0x03, 0x04,
+ 0xe2, 0x21, 0x2d, 0xe1, 0xa0, 0x80, 0x88, 0x60, 0xdf, 0xbf, 0x87, 0xa9, 0x8d, 0x3b, 0x77, 0xb0,
+ 0xf8, 0xe7, 0x25, 0x20, 0x6d, 0xee, 0xdc, 0xb9, 0x8f, 0x1e, 0x3d, 0x4e, 0x49, 0x4d, 0xbd, 0xf1,
+ 0xe7, 0x4d, 0x5f, 0x3f, 0x7f, 0x97, 0x15, 0x2b, 0x26, 0x4f, 0xb6, 0xd2, 0xd3, 0xd7, 0xa7, 0x06,
+ 0x80, 0x64, 0x7a, 0x1d, 0x71, 0x19, 0x50, 0x97, 0x24, 0x4d, 0xb0, 0x74, 0xce, 0x56, 0xe1, 0xc4,
+ 0x6a, 0x40, 0x28, 0xd2, 0x7d, 0x5c, 0x5d, 0x65, 0x2d, 0xad, 0x78, 0xa7, 0x41, 0x5d, 0x5d, 0xdd,
+ 0x5f, 0x67, 0xce, 0x84, 0xe0, 0x09, 0x0b, 0x0b, 0xcf, 0xcb, 0xcb, 0x87, 0x56, 0xff, 0x8c, 0x83,
+ 0xab, 0x64, 0x64, 0x65, 0xcf, 0x9e, 0x3d, 0x57, 0x58, 0x54, 0x94, 0x94, 0x9c, 0x7c, 0x2f, 0x3e,
+ 0x1e, 0xe1, 0x5b, 0x4a, 0x74, 0x28, 0x27, 0xe1, 0x40, 0x1d, 0x7b, 0x37, 0x59, 0xe2, 0xc1, 0x7d,
+ 0xb3, 0x8d, 0x5b, 0xb2, 0x89, 0x2c, 0x71, 0x25, 0x39, 0x8e, 0x64, 0xd1, 0x2c, 0xb2, 0xc0, 0x82,
+ 0xcc, 0xfd, 0x99, 0x06, 0x2d, 0x0d, 0xd7, 0x02, 0x2b, 0xf2, 0x95, 0x1d, 0xf9, 0xda, 0x95, 0xfb,
+ 0x66, 0x2b, 0xb7, 0x6c, 0x17, 0x59, 0xee, 0xc3, 0x2d, 0xdf, 0xcb, 0x2d, 0xdf, 0xcd, 0x2d, 0xf3,
+ 0xe2, 0x96, 0x7a, 0xd0, 0xd9, 0x9d, 0xba, 0xf4, 0x7a, 0x7d, 0x46, 0xcc, 0x8a, 0x49, 0xe6, 0xe6,
+ 0x23, 0x46, 0x8c, 0x00, 0x56, 0xd1, 0xd0, 0xe0, 0xe6, 0x20, 0x95, 0x77, 0xec, 0xd8, 0x59, 0x55,
+ 0xf9, 0x96, 0x39, 0xd9, 0x4d, 0x3a, 0xb7, 0x0c, 0xd3, 0xb7, 0x42, 0xa0, 0xf0, 0xfb, 0x36, 0x77,
+ 0x4a, 0xcc, 0x3c, 0xf9, 0xd0, 0xee, 0x3d, 0xe2, 0xed, 0xe5, 0xf1, 0xe9, 0xe4, 0xe4, 0xd4, 0x81,
+ 0x41, 0xf4, 0xf4, 0xf4, 0xca, 0xca, 0xca, 0xc4, 0x88, 0x15, 0x0f, 0x66, 0x31, 0x0a, 0xb6, 0xae,
+ 0xae, 0x1e, 0x9e, 0xfa, 0x4b, 0x4e, 0xb5, 0xeb, 0x4c, 0x02, 0x1d, 0xa1, 0x36, 0x53, 0xd3, 0xd2,
+ 0xd3, 0xd2, 0x33, 0x6e, 0x85, 0x85, 0x1f, 0x38, 0x70, 0xd0, 0xc5, 0x65, 0x85, 0xb9, 0x85, 0x85,
+ 0xde, 0x10, 0x5d, 0xb7, 0xe9, 0xba, 0xc5, 0xb7, 0xf4, 0x88, 0x2c, 0x15, 0x5a, 0xa4, 0xe9, 0xd2,
+ 0xa0, 0xd5, 0x6a, 0x81, 0x2e, 0x4b, 0xb5, 0xe2, 0xe1, 0x40, 0xd1, 0x5a, 0x5a, 0xd9, 0xae, 0x83,
+ 0xd8, 0x6e, 0xf4, 0x1c, 0x15, 0x43, 0x43, 0x23, 0x07, 0x07, 0xc7, 0x83, 0x01, 0x01, 0x77, 0xef,
+ 0xc5, 0x67, 0xb3, 0xd9, 0xc3, 0x87, 0x7f, 0xce, 0x62, 0x10, 0x59, 0x59, 0xd9, 0xb8, 0xb8, 0xbb,
+ 0xd5, 0x35, 0xb5, 0x6f, 0x4a, 0xcb, 0x5e, 0x15, 0x17, 0x97, 0xe4, 0xbd, 0xac, 0xca, 0x49, 0xa8,
+ 0x7f, 0x1d, 0xc3, 0xad, 0x8e, 0xe0, 0xd5, 0xdc, 0xe2, 0xd5, 0xdc, 0xe4, 0x55, 0x5f, 0xe1, 0x56,
+ 0x9d, 0x24, 0xcb, 0x77, 0x93, 0xaf, 0x57, 0x91, 0x45, 0x33, 0xc9, 0xfc, 0x09, 0x44, 0xee, 0x48,
+ 0x8a, 0x6c, 0x0b, 0x26, 0x93, 0xaf, 0x16, 0x90, 0x6f, 0x36, 0x73, 0x2b, 0x02, 0xb8, 0x6f, 0x2f,
+ 0x72, 0x6b, 0xc3, 0xb8, 0xb5, 0x91, 0xbc, 0xda, 0x28, 0x3a, 0xdf, 0xe6, 0xd5, 0x86, 0xd1, 0x19,
+ 0x25, 0x5c, 0xe7, 0xbd, 0x3d, 0xc7, 0xad, 0x38, 0xbc, 0x6d, 0xcb, 0x4a, 0xf8, 0x3b, 0x00, 0x75,
+ 0xdc, 0xf8, 0xf1, 0xd3, 0xa6, 0x4f, 0x77, 0x76, 0x76, 0xf6, 0xdc, 0xb1, 0x03, 0xde, 0xa1, 0xac,
+ 0xbc, 0x5c, 0xbc, 0xda, 0x54, 0xd4, 0x21, 0x2f, 0x44, 0x8b, 0xf4, 0xd0, 0x52, 0x73, 0xeb, 0x1e,
+ 0x7b, 0xc9, 0xfb, 0x25, 0x7e, 0xd5, 0x66, 0xe2, 0x9f, 0xb0, 0x63, 0x4a, 0x3c, 0xc0, 0x6a, 0x67,
+ 0x6f, 0xff, 0x31, 0x6b, 0x00, 0x8a, 0xc7, 0x8f, 0x9f, 0x20, 0xb9, 0x3c, 0xc9, 0x7d, 0x06, 0xc4,
+ 0x5b, 0xd3, 0xe3, 0xe7, 0xf0, 0xd4, 0xe2, 0xbd, 0xe6, 0x80, 0xab, 0x7e, 0xfd, 0xfa, 0x21, 0x80,
+ 0x45, 0x98, 0x86, 0x66, 0x88, 0x4f, 0x35, 0x35, 0x35, 0x08, 0x4e, 0x90, 0x24, 0xd3, 0xd7, 0xfa,
+ 0x25, 0x09, 0x25, 0x38, 0x39, 0x2d, 0x86, 0x38, 0xc9, 0xc8, 0x7c, 0x09, 0xd0, 0xfa, 0xfb, 0x1f,
+ 0x70, 0x73, 0x75, 0xf1, 0x77, 0x9b, 0x93, 0x77, 0xc9, 0xaa, 0x21, 0x73, 0x88, 0x28, 0x04, 0xd6,
+ 0xa0, 0x3b, 0xc6, 0x41, 0xb6, 0x08, 0x34, 0x06, 0x53, 0x00, 0xce, 0x56, 0x2d, 0x8d, 0x57, 0xef,
+ 0x6a, 0x2b, 0x13, 0x45, 0x1b, 0x5f, 0xf4, 0x37, 0x35, 0x1d, 0x0b, 0x07, 0xf7, 0xfb, 0xa9, 0xe0,
+ 0xc4, 0xa4, 0xe4, 0x88, 0x88, 0xdb, 0x30, 0x9a, 0xf4, 0x8b, 0x83, 0x8a, 0x55, 0xe8, 0x04, 0x4b,
+ 0xb6, 0xbb, 0xd9, 0xef, 0xc0, 0x81, 0x03, 0xab, 0xde, 0xbe, 0x6d, 0x6a, 0x22, 0x1a, 0xea, 0xeb,
+ 0x0b, 0x73, 0xd9, 0xf1, 0xd1, 0xe1, 0x71, 0x91, 0x57, 0xef, 0x45, 0x87, 0xc6, 0xc7, 0x5d, 0x8c,
+ 0x8f, 0xbb, 0x10, 0x1f, 0x7b, 0x2e, 0x3e, 0x26, 0xa4, 0xae, 0x22, 0x9a, 0xf7, 0xf6, 0x34, 0x59,
+ 0xea, 0x09, 0xa7, 0x4f, 0x14, 0x58, 0x92, 0x79, 0xa6, 0x64, 0xbe, 0x19, 0x59, 0x34, 0x9b, 0x2c,
+ 0x59, 0x0b, 0x28, 0x02, 0x99, 0x65, 0xc5, 0x71, 0xd4, 0x9d, 0xd4, 0x4f, 0x42, 0xe9, 0x7c, 0x49,
+ 0xf8, 0xf3, 0xb8, 0xf3, 0xf1, 0xb1, 0x67, 0x5f, 0xa6, 0x5c, 0x6b, 0xaa, 0x0a, 0x2b, 0xcf, 0x09,
+ 0xf4, 0xde, 0xe1, 0xb6, 0x60, 0xc1, 0xc2, 0x45, 0x0e, 0x0e, 0x90, 0x04, 0x7e, 0x7e, 0xfe, 0xa8,
+ 0xfd, 0xf8, 0xf8, 0xfb, 0xb1, 0x71, 0x71, 0x31, 0xb1, 0xb1, 0xf7, 0xef, 0x27, 0xdc, 0x4f, 0x78,
+ 0x80, 0x9c, 0x40, 0x67, 0xfc, 0x91, 0x96, 0x9e, 0xce, 0xec, 0xc9, 0x2a, 0x89, 0x52, 0x92, 0xe4,
+ 0xe2, 0x7b, 0xc9, 0xdb, 0x90, 0x9f, 0x25, 0x26, 0x56, 0x54, 0x54, 0x8a, 0x87, 0x50, 0xeb, 0xea,
+ 0x1b, 0xf0, 0xcd, 0x7d, 0xd1, 0x55, 0x26, 0xc3, 0xc3, 0x22, 0xba, 0x17, 0x08, 0x9a, 0x81, 0x3a,
+ 0x5b, 0x5b, 0xdb, 0x8f, 0xe1, 0xe4, 0xe7, 0x9f, 0x7f, 0x66, 0xb3, 0xd9, 0xc2, 0xfe, 0x81, 0x0f,
+ 0xad, 0x10, 0x8b, 0x67, 0x40, 0x09, 0x3b, 0x77, 0x7a, 0x99, 0x98, 0x98, 0x98, 0x99, 0x99, 0x01,
+ 0x15, 0xab, 0x56, 0xad, 0xf6, 0xf5, 0xf3, 0x43, 0x20, 0x80, 0xe7, 0x87, 0x7b, 0x8a, 0x89, 0x89,
+ 0xbd, 0x79, 0xf3, 0x66, 0x50, 0x50, 0x10, 0x1a, 0x23, 0xac, 0xfd, 0x85, 0x88, 0xed, 0x46, 0x07,
+ 0x62, 0x6b, 0xd7, 0xae, 0xcd, 0xce, 0x66, 0xa7, 0xa6, 0xa5, 0xdd, 0x0e, 0xfb, 0xf3, 0x6e, 0xe8,
+ 0xd1, 0xbc, 0x30, 0xf7, 0xea, 0xc4, 0xd9, 0x44, 0x8e, 0x31, 0x99, 0xab, 0x27, 0xea, 0x99, 0x51,
+ 0xa2, 0xb2, 0xb0, 0xe3, 0x51, 0x83, 0xc8, 0xee, 0x5f, 0x12, 0x37, 0x78, 0xf6, 0xec, 0x39, 0x06,
+ 0x06, 0x06, 0x10, 0x60, 0x5d, 0x04, 0xb1, 0x10, 0xb1, 0xbd, 0x7b, 0xf7, 0x46, 0x8b, 0x86, 0x20,
+ 0xdf, 0xbc, 0x65, 0x0b, 0x82, 0x4a, 0x34, 0x43, 0x98, 0x4e, 0x5e, 0x5e, 0x5e, 0xfa, 0xad, 0xe1,
+ 0x5c, 0x42, 0x42, 0x4e, 0x23, 0x43, 0xee, 0xb6, 0x1b, 0x2c, 0x80, 0xf7, 0xf8, 0x02, 0x01, 0x97,
+ 0xc7, 0xe3, 0x91, 0xe4, 0xc9, 0xa0, 0x13, 0xc6, 0x46, 0x46, 0x3a, 0xda, 0xda, 0x3a, 0xda, 0x5a,
+ 0x3a, 0x3a, 0x74, 0xd6, 0xd6, 0xd2, 0xd7, 0xd7, 0xad, 0x7c, 0x93, 0xc8, 0xab, 0xbd, 0xc9, 0x2d,
+ 0xff, 0x8d, 0xe4, 0x2c, 0x25, 0x0a, 0xa6, 0x12, 0x80, 0x6b, 0xc1, 0x54, 0x92, 0xb3, 0x98, 0x5b,
+ 0xb6, 0x9b, 0x5b, 0x7d, 0x99, 0xdf, 0xf8, 0xe2, 0x64, 0x90, 0x7f, 0xcb, 0x4f, 0x24, 0xb3, 0x36,
+ 0x95, 0x77, 0x78, 0x6e, 0xac, 0x2e, 0x4b, 0x20, 0xab, 0x42, 0x5f, 0x3c, 0x38, 0xe8, 0xe1, 0xb1,
+ 0xdd, 0x6b, 0xd7, 0xae, 0xa3, 0xc7, 0x8e, 0x85, 0x47, 0x44, 0xa0, 0x22, 0xc2, 0xc2, 0xc3, 0x67,
+ 0xce, 0x9c, 0x89, 0x48, 0x07, 0xba, 0x4b, 0xa7, 0x75, 0x02, 0x2a, 0x8a, 0x39, 0x9c, 0x96, 0x49,
+ 0x7d, 0x34, 0x1a, 0x4b, 0xde, 0x94, 0x5a, 0xdb, 0xd8, 0xb4, 0xb9, 0x73, 0xda, 0xb4, 0x69, 0x4f,
+ 0x9e, 0x3c, 0x65, 0xee, 0xe4, 0xf1, 0xf8, 0x91, 0x77, 0xa2, 0x8c, 0xf0, 0x16, 0x12, 0x49, 0x5f,
+ 0x5f, 0x7f, 0xd3, 0xa6, 0x4d, 0x65, 0xe5, 0x15, 0x7c, 0x1a, 0xb1, 0x10, 0xff, 0xed, 0x22, 0xa4,
+ 0x67, 0xcf, 0x9e, 0xde, 0xde, 0xde, 0xef, 0xea, 0xea, 0xc5, 0x27, 0xd4, 0x8b, 0x13, 0x83, 0xd8,
+ 0x9a, 0x9a, 0xda, 0x87, 0x8f, 0x1e, 0x27, 0x3c, 0x78, 0x90, 0x93, 0x93, 0xdb, 0xd0, 0xd0, 0x28,
+ 0x90, 0x58, 0x6b, 0xc0, 0x64, 0x40, 0x1a, 0xb2, 0x6a, 0xdd, 0xba, 0x75, 0xaa, 0xaa, 0xaa, 0x5f,
+ 0x8e, 0xd8, 0x6e, 0x74, 0x68, 0xec, 0xee, 0xee, 0xce, 0xce, 0x66, 0xbd, 0xc9, 0xcf, 0xa8, 0x78,
+ 0x19, 0xf9, 0x36, 0xfd, 0x48, 0x63, 0xde, 0x72, 0xca, 0xbb, 0xe5, 0x19, 0x53, 0x61, 0x57, 0x96,
+ 0x32, 0xd5, 0xf1, 0x28, 0x1c, 0xdc, 0x51, 0xa4, 0x06, 0x77, 0x58, 0x4a, 0x45, 0x91, 0x3a, 0x90,
+ 0xc1, 0x06, 0x06, 0x43, 0xe5, 0xe4, 0xba, 0x04, 0x62, 0xc5, 0x3d, 0xb1, 0xa8, 0xe1, 0x19, 0xb6,
+ 0xb6, 0xde, 0xde, 0xbb, 0x51, 0xe9, 0x30, 0xe0, 0x62, 0x67, 0xe7, 0x76, 0xc5, 0x15, 0x48, 0x8c,
+ 0x31, 0xe6, 0x1f, 0x7f, 0x84, 0xb4, 0x8b, 0x58, 0x5f, 0x5f, 0x3f, 0x30, 0x0f, 0x9f, 0xcf, 0x27,
+ 0x49, 0x72, 0xc9, 0x92, 0x25, 0xd2, 0x3c, 0x6c, 0x60, 0xa0, 0xc7, 0x6b, 0xca, 0xe5, 0xd5, 0x46,
+ 0x70, 0xcb, 0x7d, 0x49, 0xce, 0x32, 0x02, 0x71, 0x56, 0xbe, 0x05, 0x08, 0x96, 0x5b, 0xb2, 0x8e,
+ 0x5b, 0x79, 0x8c, 0x1a, 0x34, 0x6f, 0x2c, 0x9c, 0x68, 0xd6, 0xd1, 0x5a, 0x3f, 0xef, 0x5d, 0xdb,
+ 0xdf, 0x55, 0xbd, 0x80, 0x5a, 0xa8, 0xe6, 0x5c, 0x8c, 0x8e, 0x38, 0x75, 0xee, 0xdc, 0xf9, 0xe8,
+ 0xe8, 0x98, 0xac, 0x2c, 0x16, 0x9e, 0x1c, 0x22, 0xe1, 0x63, 0x9a, 0x10, 0x6e, 0xd1, 0xc3, 0xc3,
+ 0x83, 0x7e, 0xf8, 0x66, 0x21, 0x24, 0x04, 0xcd, 0xa0, 0x4a, 0x19, 0x19, 0x99, 0x36, 0x77, 0x4e,
+ 0x9a, 0x34, 0x29, 0xbf, 0xa0, 0x80, 0xe2, 0x4f, 0x41, 0x33, 0x40, 0x05, 0x00, 0xb7, 0xb9, 0x01,
+ 0xe2, 0xf9, 0xe6, 0xad, 0x5b, 0x3c, 0xbe, 0x80, 0x41, 0xec, 0xa8, 0x51, 0xa3, 0xda, 0xfd, 0x1f,
+ 0x35, 0xb5, 0xb4, 0xee, 0x44, 0x45, 0x09, 0xc4, 0xe7, 0x7c, 0x4b, 0xc6, 0x7a, 0x12, 0xc2, 0xa0,
+ 0x65, 0x51, 0x8c, 0xa0, 0x19, 0x65, 0x0a, 0x8b, 0x15, 0x34, 0xb3, 0x58, 0xac, 0xf5, 0xeb, 0xd7,
+ 0x0f, 0x1b, 0x36, 0x0c, 0x6a, 0x41, 0xba, 0x70, 0xe8, 0x87, 0xcf, 0xdb, 0x1e, 0x1c, 0xe1, 0xea,
+ 0x9e, 0xdd, 0xbb, 0xca, 0x39, 0xb9, 0x8d, 0xe5, 0xa9, 0x8d, 0x25, 0xd7, 0xb8, 0x25, 0x5e, 0x24,
+ 0x22, 0xdc, 0xbc, 0x89, 0x24, 0xdb, 0x80, 0x60, 0x0d, 0x6a, 0x01, 0x2d, 0x35, 0xc4, 0xa3, 0x00,
+ 0xdc, 0xe6, 0x47, 0xe8, 0xdb, 0xd9, 0xd9, 0x75, 0x9d, 0x2d, 0x64, 0x45, 0xfb, 0x0f, 0xf7, 0x1b,
+ 0x3a, 0x74, 0xd8, 0x7c, 0x3b, 0x3b, 0xc8, 0x9b, 0xbb, 0xf7, 0xee, 0x25, 0x27, 0x3f, 0xb7, 0xb0,
+ 0xb0, 0x90, 0x7e, 0x59, 0xb4, 0x50, 0x44, 0x0a, 0xa8, 0x02, 0x1e, 0x9f, 0xbf, 0x69, 0xf3, 0xe6,
+ 0x76, 0x2d, 0x49, 0xb1, 0x13, 0x10, 0x2b, 0x68, 0x2e, 0x2a, 0x7a, 0x65, 0x69, 0x69, 0x29, 0x7d,
+ 0xc3, 0xb2, 0x65, 0xce, 0x7c, 0x82, 0x0d, 0x41, 0xcb, 0x2d, 0xdb, 0x4b, 0x72, 0x96, 0x90, 0x85,
+ 0xd6, 0x14, 0xc1, 0x16, 0x3b, 0x72, 0x4b, 0xbd, 0xb8, 0x6f, 0x2f, 0xf1, 0x1b, 0x5e, 0xa4, 0xbe,
+ 0xb8, 0x8f, 0x18, 0xb6, 0x03, 0x9b, 0x07, 0x07, 0x1f, 0x23, 0xea, 0xf3, 0x78, 0xf5, 0x4f, 0x79,
+ 0xb5, 0xb1, 0x6f, 0x5f, 0xc7, 0xa5, 0xa7, 0x3c, 0x61, 0xe7, 0xe4, 0x42, 0xc6, 0x80, 0xfa, 0x3a,
+ 0x0e, 0x15, 0x35, 0x34, 0x34, 0xa8, 0x2d, 0xd7, 0xa8, 0xf9, 0x25, 0xcd, 0x0c, 0xd8, 0xe0, 0x2c,
+ 0xda, 0xdc, 0x03, 0x62, 0x44, 0x24, 0x45, 0x72, 0xb9, 0xcc, 0x0d, 0xf0, 0xd1, 0x6d, 0x8e, 0x40,
+ 0xc2, 0x5b, 0xaf, 0x5a, 0xb5, 0xaa, 0xbe, 0xbe, 0x41, 0x5c, 0x08, 0xd8, 0xbc, 0xdd, 0xff, 0x6e,
+ 0xfe, 0xfc, 0xf9, 0xc5, 0xc5, 0x1c, 0x31, 0xc1, 0xb6, 0x42, 0x6c, 0xcb, 0xae, 0x32, 0x42, 0x79,
+ 0x8c, 0x72, 0x50, 0x1a, 0x28, 0x9d, 0x47, 0x4d, 0x97, 0x6d, 0x4e, 0x4c, 0x4a, 0x1a, 0x3d, 0x7a,
+ 0xb4, 0xf4, 0xde, 0x1d, 0x68, 0x8f, 0xa6, 0xa6, 0xa6, 0x47, 0x8f, 0x1e, 0x7d, 0xf2, 0xe4, 0x09,
+ 0x64, 0x83, 0xc9, 0xa7, 0x77, 0x32, 0xa0, 0xe5, 0xaa, 0xa9, 0xa9, 0x1e, 0x0e, 0xf0, 0xab, 0xad,
+ 0xcc, 0xe3, 0xbe, 0x7b, 0xca, 0xad, 0x0a, 0x41, 0x38, 0x4c, 0x16, 0xcd, 0x23, 0xf3, 0xc6, 0x52,
+ 0x7d, 0x8c, 0xac, 0x01, 0xf4, 0xe0, 0x78, 0xcb, 0xc4, 0x8f, 0x37, 0x77, 0x07, 0x3b, 0x3a, 0x3a,
+ 0xa1, 0x55, 0x32, 0xb3, 0x64, 0xff, 0xeb, 0x83, 0x08, 0x54, 0x4f, 0x6c, 0xcf, 0x9e, 0x8a, 0xf4,
+ 0xf2, 0x2b, 0x67, 0xe7, 0x25, 0xc7, 0x4f, 0x9c, 0x00, 0xe4, 0xae, 0x5d, 0xbf, 0x31, 0x74, 0xe8,
+ 0x50, 0xe9, 0x97, 0x35, 0x37, 0x37, 0x67, 0x0c, 0x5b, 0xcc, 0x79, 0x3d, 0x73, 0xe6, 0x2c, 0xe9,
+ 0x1b, 0x20, 0x2d, 0x2a, 0xab, 0xde, 0x32, 0x55, 0x09, 0x31, 0x06, 0xf1, 0x23, 0x7d, 0xcf, 0xc5,
+ 0x0b, 0xc1, 0xfc, 0xc6, 0x54, 0x6e, 0xf5, 0x25, 0x6e, 0xe9, 0x4e, 0xaa, 0x75, 0x17, 0xda, 0x90,
+ 0x45, 0xbf, 0x72, 0x11, 0x85, 0x55, 0x1c, 0xe2, 0xd5, 0xde, 0xe1, 0x37, 0xe5, 0xed, 0xf2, 0xda,
+ 0xde, 0x6e, 0x5b, 0x10, 0x57, 0xd9, 0xed, 0x88, 0x1b, 0x02, 0x6e, 0x19, 0xaf, 0x89, 0xc5, 0x6b,
+ 0x4c, 0xe3, 0x35, 0x66, 0x95, 0x97, 0xe6, 0x9f, 0x3d, 0x7b, 0x16, 0xff, 0xf5, 0xdf, 0x56, 0x16,
+ 0x0c, 0x3e, 0x6f, 0xde, 0xbc, 0xda, 0x77, 0xef, 0xc4, 0x60, 0x43, 0x5d, 0xb4, 0xb9, 0x07, 0x4c,
+ 0x72, 0xe8, 0xd0, 0x21, 0x86, 0xf4, 0xe0, 0xf7, 0xd1, 0x0a, 0xda, 0xdc, 0x80, 0xa8, 0xb9, 0xa8,
+ 0xa8, 0x88, 0xb1, 0x03, 0x53, 0x48, 0x1b, 0xf9, 0x84, 0x87, 0x87, 0xec, 0x44, 0x6b, 0x8d, 0x8a,
+ 0x8a, 0x16, 0x08, 0x19, 0xf6, 0xaf, 0x0f, 0xad, 0x3b, 0xd7, 0xc4, 0x1d, 0x5c, 0x62, 0xd0, 0xf2,
+ 0x19, 0x82, 0xe5, 0xf1, 0x09, 0x92, 0xbc, 0x15, 0x16, 0x86, 0x70, 0xac, 0x4d, 0xb4, 0x85, 0x17,
+ 0x1f, 0x39, 0xd2, 0x24, 0x34, 0x34, 0xb4, 0xaa, 0xaa, 0x8a, 0x20, 0x09, 0x81, 0x40, 0x50, 0x57,
+ 0x57, 0xf7, 0xb7, 0x5d, 0xc1, 0xed, 0x26, 0x94, 0x0c, 0xf8, 0xfd, 0x7e, 0x32, 0xb0, 0xae, 0x9a,
+ 0xc5, 0xab, 0xbb, 0xcb, 0xad, 0x0c, 0x22, 0xdf, 0x6c, 0x22, 0x8b, 0xe6, 0x10, 0x79, 0xa6, 0x14,
+ 0x68, 0xb3, 0x07, 0x12, 0xac, 0xfe, 0xf4, 0x38, 0x23, 0x85, 0xdb, 0x9a, 0x64, 0x15, 0x37, 0x37,
+ 0x37, 0xf8, 0x1d, 0xb4, 0x77, 0xb4, 0xa0, 0xff, 0xba, 0x30, 0x10, 0x6d, 0x7c, 0x31, 0x00, 0x11,
+ 0xb7, 0xdb, 0x9a, 0x35, 0x67, 0xcf, 0x9d, 0x4f, 0x4d, 0x4b, 0xf7, 0xf7, 0xf7, 0x6f, 0x97, 0xe5,
+ 0xf6, 0xec, 0xd9, 0xc3, 0xd4, 0x14, 0x42, 0x0f, 0xa3, 0xf6, 0xf6, 0xa6, 0xb6, 0xb7, 0xb7, 0xaf,
+ 0x13, 0x92, 0x8f, 0xe0, 0xc8, 0x91, 0x23, 0x8c, 0x1f, 0x91, 0x4c, 0xf0, 0x65, 0xac, 0x97, 0x4f,
+ 0x78, 0xf5, 0x8f, 0x79, 0x55, 0xa7, 0xb8, 0x6f, 0x36, 0x53, 0x7d, 0x59, 0x85, 0x36, 0x04, 0x3e,
+ 0x4b, 0xb6, 0xa2, 0xb1, 0xe3, 0xfb, 0xca, 0x32, 0xd6, 0x58, 0xd3, 0xd1, 0x1d, 0x84, 0xc6, 0x88,
+ 0xec, 0x12, 0x12, 0xee, 0xf2, 0x79, 0x35, 0x7c, 0xa2, 0x94, 0x4f, 0xbe, 0x6e, 0x6a, 0x28, 0x09,
+ 0x0e, 0x3e, 0x8e, 0x98, 0xba, 0x93, 0x95, 0x85, 0x37, 0xbd, 0x70, 0xf1, 0x22, 0xe3, 0x05, 0x00,
+ 0x0f, 0xe9, 0x03, 0xb9, 0x50, 0x2f, 0x08, 0xc1, 0xf0, 0x9a, 0x04, 0x41, 0x42, 0x45, 0xb4, 0x69,
+ 0x3b, 0xe0, 0xdb, 0xb3, 0x67, 0xcf, 0x89, 0xe1, 0xca, 0x14, 0xc2, 0x10, 0x3b, 0x3e, 0x01, 0x54,
+ 0x93, 0x91, 0x23, 0x3d, 0x3d, 0x3d, 0xd3, 0xd2, 0x33, 0x60, 0x01, 0x46, 0x30, 0xb7, 0x11, 0x04,
+ 0x12, 0xdd, 0xc5, 0x12, 0xf3, 0x0a, 0xde, 0x0b, 0x09, 0x96, 0x20, 0xb9, 0xe1, 0xe1, 0x11, 0x3a,
+ 0x52, 0xa4, 0x0d, 0x01, 0xe0, 0xe2, 0xb2, 0xbc, 0xb2, 0xb2, 0x82, 0xcf, 0xe7, 0xd2, 0x99, 0xd2,
+ 0x0e, 0x88, 0x70, 0x6d, 0x66, 0xcc, 0xe8, 0xe4, 0x8b, 0x4b, 0x27, 0x3c, 0xed, 0xe9, 0x90, 0x13,
+ 0x4d, 0x75, 0x59, 0xfc, 0x77, 0x31, 0xdc, 0xca, 0xe3, 0x64, 0xe9, 0x36, 0x92, 0xe3, 0x40, 0x14,
+ 0x4c, 0xa1, 0x46, 0x70, 0x72, 0x47, 0x10, 0x39, 0xba, 0xd4, 0x88, 0x2d, 0x4b, 0xb9, 0x21, 0x5d,
+ 0x39, 0x70, 0xbf, 0x0b, 0x5a, 0x3a, 0xc4, 0x3c, 0x70, 0xfe, 0xb1, 0x79, 0xb6, 0xff, 0xb1, 0xc4,
+ 0x88, 0x58, 0x2d, 0x2d, 0xea, 0x58, 0x58, 0x77, 0x77, 0x8f, 0x1b, 0x7f, 0xfe, 0x09, 0x6b, 0xaf,
+ 0x5e, 0xed, 0x26, 0xed, 0x5e, 0xa1, 0x48, 0x21, 0x18, 0x98, 0xca, 0x3a, 0x73, 0xf6, 0x6c, 0xbb,
+ 0xd1, 0xeb, 0xe1, 0xc3, 0x81, 0xb0, 0x39, 0x6e, 0x40, 0xc8, 0x80, 0xb0, 0x54, 0x1a, 0x78, 0x13,
+ 0x26, 0x8c, 0x7f, 0x5d, 0x9c, 0x4a, 0xb5, 0xeb, 0x8a, 0x40, 0xb2, 0x64, 0x0d, 0x59, 0x34, 0x97,
+ 0x1a, 0x17, 0xe0, 0x38, 0x71, 0xcb, 0x7c, 0xb8, 0xd5, 0xd7, 0xf8, 0x4d, 0x19, 0xb7, 0x6e, 0x5e,
+ 0x54, 0x57, 0xef, 0x88, 0x2d, 0x8d, 0x8d, 0x8d, 0x9f, 0x3f, 0x4f, 0xe2, 0xf3, 0x1b, 0x79, 0xdc,
+ 0x77, 0x7c, 0x5e, 0x2d, 0x8b, 0x95, 0x66, 0x65, 0xd5, 0x7e, 0xe0, 0xd3, 0x6e, 0x52, 0x52, 0x52,
+ 0x82, 0x1f, 0xa1, 0x63, 0xfc, 0xe6, 0x82, 0xc2, 0x42, 0xe9, 0x27, 0x44, 0xf9, 0x95, 0x95, 0x55,
+ 0x78, 0xcd, 0x47, 0x8f, 0x1e, 0xeb, 0xe9, 0xe9, 0xb5, 0xb9, 0x6a, 0x6d, 0x6d, 0x83, 0x26, 0x29,
+ 0x10, 0x88, 0x75, 0x45, 0x73, 0xd5, 0xff, 0x12, 0x77, 0xa5, 0x41, 0x51, 0x5c, 0xed, 0xfa, 0x67,
+ 0xee, 0xad, 0xa4, 0xea, 0xab, 0xfa, 0x72, 0xab, 0x72, 0x73, 0x5d, 0xbe, 0xba, 0x31, 0x1a, 0xaf,
+ 0x89, 0x0b, 0x5a, 0x51, 0xf3, 0x89, 0x1a, 0x35, 0x5e, 0x83, 0x71, 0x41, 0xa2, 0x46, 0x13, 0x8d,
+ 0x6b, 0xdc, 0x89, 0x1b, 0x0a, 0xa2, 0xc1, 0x2d, 0x8a, 0xb8, 0xc6, 0x25, 0xc6, 0x0d, 0x41, 0x11,
+ 0x05, 0x5c, 0x40, 0x04, 0x11, 0x86, 0x5d, 0x51, 0x01, 0x05, 0x91, 0x7d, 0x9b, 0x61, 0x99, 0x7d,
+ 0x5f, 0xfb, 0x74, 0x0f, 0x5a, 0x75, 0x9f, 0xd3, 0xad, 0xed, 0xd0, 0x33, 0xf1, 0xc3, 0x84, 0xd4,
+ 0x3d, 0x35, 0x65, 0x8d, 0x43, 0x4f, 0x4f, 0xf7, 0x39, 0xcf, 0x79, 0xdf, 0xe7, 0x79, 0xdf, 0xf7,
+ 0x9c, 0xd6, 0x1b, 0xde, 0xe2, 0x67, 0xe2, 0xe4, 0xc9, 0x93, 0x8f, 0x1e, 0x3b, 0xd6, 0xd4, 0x2c,
+ 0xe7, 0x17, 0xc1, 0xbc, 0x2a, 0x26, 0xf4, 0x34, 0xb0, 0x9e, 0xa1, 0x5e, 0x49, 0xf0, 0x8d, 0x9e,
+ 0x90, 0x73, 0x57, 0x55, 0x57, 0x4f, 0x99, 0x32, 0x55, 0xd2, 0xf9, 0xd0, 0x0b, 0xa1, 0xa1, 0xa1,
+ 0x26, 0x93, 0x1e, 0xe2, 0x80, 0xe3, 0x5c, 0xfc, 0x0b, 0x9d, 0xcc, 0x95, 0x95, 0x95, 0xfd, 0xc9,
+ 0xe7, 0x86, 0xe0, 0xcc, 0x37, 0x93, 0xe3, 0x19, 0x5b, 0x15, 0x6b, 0xc9, 0x22, 0xfa, 0xb3, 0x8c,
+ 0x2a, 0xc2, 0xd5, 0xba, 0xd4, 0xd5, 0x34, 0x85, 0x1a, 0xdb, 0xfa, 0x61, 0xae, 0xba, 0x81, 0x34,
+ 0xe4, 0x55, 0xdd, 0xb3, 0xfd, 0xde, 0x87, 0x91, 0xdb, 0xbe, 0x01, 0x42, 0xd0, 0x21, 0x70, 0x28,
+ 0x42, 0x1d, 0xd7, 0xff, 0x0b, 0x68, 0xc5, 0xf5, 0xad, 0xe0, 0xd5, 0x98, 0x44, 0xfb, 0xa2, 0xa2,
+ 0x64, 0xb2, 0x6c, 0xa8, 0xd7, 0xe9, 0xd3, 0x7d, 0xcc, 0x5c, 0x98, 0x23, 0x0c, 0x31, 0x46, 0x03,
+ 0x14, 0x6e, 0xfb, 0xf6, 0xed, 0xde, 0x90, 0x86, 0x84, 0x81, 0x2e, 0xc3, 0x78, 0xa1, 0xf3, 0x6b,
+ 0xeb, 0xea, 0xa0, 0xc1, 0xbd, 0x4f, 0xb2, 0x7e, 0x7d, 0xb0, 0x51, 0xf7, 0x94, 0x35, 0xa7, 0x11,
+ 0xed, 0x01, 0xa6, 0x6d, 0x15, 0x45, 0xac, 0x7c, 0x36, 0x4d, 0x19, 0x68, 0x8f, 0xb1, 0x96, 0x3b,
+ 0x2e, 0x5b, 0xed, 0xa6, 0x90, 0x1f, 0xc5, 0xd4, 0x30, 0xec, 0x3c, 0x94, 0x14, 0x18, 0xb5, 0xa7,
+ 0x38, 0x0a, 0x08, 0x08, 0xa8, 0xae, 0xa9, 0xe6, 0xed, 0x0c, 0x06, 0x8e, 0xb9, 0x73, 0xe7, 0xf6,
+ 0xa0, 0x41, 0x9d, 0x1c, 0x37, 0xbe, 0x1e, 0x14, 0x14, 0xb4, 0x89, 0x6f, 0xf3, 0xe6, 0xcd, 0x43,
+ 0xf7, 0x7a, 0xfe, 0x15, 0x3e, 0x3d, 0x3b, 0x27, 0x57, 0xe4, 0xa8, 0x92, 0xcb, 0xc3, 0x4d, 0xcd,
+ 0x9f, 0x3f, 0x9f, 0xd6, 0xa6, 0x1a, 0x0c, 0xab, 0x56, 0xad, 0x92, 0x30, 0x58, 0x10, 0x0f, 0x99,
+ 0x4c, 0x26, 0x18, 0x4f, 0x51, 0xc1, 0xd5, 0x37, 0x34, 0x60, 0xdc, 0x77, 0xee, 0xdc, 0x59, 0x5d,
+ 0x53, 0x4b, 0xf8, 0x67, 0xcf, 0xbf, 0xaa, 0x7d, 0x15, 0xf2, 0x11, 0x9d, 0x13, 0x16, 0x2f, 0x69,
+ 0x80, 0xe4, 0x45, 0xbf, 0xe5, 0x70, 0x3a, 0xbd, 0x1d, 0x53, 0x9f, 0x3e, 0x7d, 0xf6, 0xed, 0xdb,
+ 0xc7, 0x5b, 0x57, 0xc0, 0xd5, 0xc9, 0xbf, 0xe8, 0x8d, 0x13, 0xc2, 0xac, 0x5c, 0xb9, 0xd2, 0x27,
+ 0x0e, 0xdf, 0xa8, 0xf9, 0xf9, 0x0d, 0xbe, 0x9d, 0x96, 0xc8, 0x81, 0x62, 0x51, 0xd0, 0x9e, 0x63,
+ 0xd4, 0xa0, 0x6a, 0x8b, 0xa0, 0x2c, 0x5c, 0x0d, 0xfe, 0xae, 0xba, 0x61, 0x7c, 0xa5, 0x47, 0x3f,
+ 0xe7, 0xd3, 0x1e, 0x15, 0x37, 0xfd, 0xb6, 0xac, 0x9d, 0x0d, 0x5a, 0x28, 0x56, 0x3e, 0xd3, 0x05,
+ 0x8f, 0x3c, 0xc1, 0x90, 0xb4, 0xbf, 0xb4, 0xc4, 0x4b, 0x88, 0xc4, 0xa2, 0xc3, 0xfd, 0xfd, 0xfd,
+ 0x7f, 0xf8, 0x61, 0xd9, 0x6f, 0xa7, 0x4e, 0x3d, 0x78, 0xf0, 0x10, 0x8a, 0x7b, 0xc8, 0x10, 0x3f,
+ 0xef, 0x5b, 0x9b, 0xfd, 0xcd, 0x37, 0x1a, 0x2d, 0x8d, 0xe7, 0x34, 0xcb, 0x15, 0x80, 0xb7, 0xf7,
+ 0x01, 0x50, 0x01, 0xd5, 0x35, 0x35, 0x82, 0xf1, 0x01, 0x74, 0xbd, 0x19, 0x20, 0x6e, 0x33, 0x36,
+ 0xe6, 0xb4, 0xcb, 0x5a, 0xc5, 0x9a, 0xae, 0x12, 0xcd, 0xcf, 0x4c, 0xeb, 0x32, 0x46, 0x31, 0x87,
+ 0x51, 0x2c, 0x60, 0x94, 0x61, 0xc4, 0x10, 0x03, 0x25, 0x55, 0x53, 0x75, 0x77, 0xd2, 0xa4, 0x2f,
+ 0xc4, 0xe3, 0x03, 0x02, 0x26, 0xe3, 0x7a, 0xd2, 0xd3, 0x6f, 0x7f, 0xe8, 0xb1, 0x15, 0x1b, 0x10,
+ 0xd5, 0xd2, 0xda, 0x02, 0x0b, 0xc3, 0xbf, 0xdc, 0x67, 0xcf, 0x9e, 0x95, 0x48, 0xe6, 0x01, 0x03,
+ 0x06, 0xa4, 0xa7, 0xa7, 0x83, 0xe3, 0x99, 0xcc, 0x96, 0x4b, 0x97, 0x2e, 0x49, 0x66, 0x16, 0xee,
+ 0xb4, 0x5d, 0xa9, 0x12, 0x10, 0xeb, 0x3d, 0xe2, 0xe8, 0x8d, 0x5f, 0x7f, 0xfd, 0x15, 0x50, 0xbc,
+ 0x71, 0x23, 0x59, 0x52, 0x05, 0x04, 0xe4, 0x87, 0x87, 0x6f, 0x35, 0x99, 0xcc, 0x22, 0x26, 0x05,
+ 0xd0, 0x56, 0x55, 0x55, 0x45, 0x9f, 0x3f, 0x6f, 0x30, 0x9a, 0x84, 0xd8, 0xac, 0x58, 0x9d, 0xf5,
+ 0x22, 0x00, 0xeb, 0x03, 0xae, 0xf4, 0x99, 0xb6, 0x75, 0xf5, 0xf5, 0xf7, 0xef, 0x3f, 0xc8, 0x92,
+ 0xc9, 0xd0, 0xdb, 0x19, 0x19, 0x19, 0x78, 0x83, 0x57, 0xd2, 0xd5, 0xab, 0xd3, 0xa6, 0x4d, 0xf3,
+ 0xfc, 0x51, 0x78, 0xe1, 0xbd, 0x7b, 0xf7, 0xea, 0x0d, 0x7a, 0x1a, 0x42, 0x78, 0x61, 0x60, 0x29,
+ 0x62, 0xdd, 0x6e, 0xf6, 0xea, 0xd5, 0x24, 0x9f, 0xe1, 0xc7, 0x37, 0x6d, 0xb8, 0xaf, 0xcf, 0xc7,
+ 0x8e, 0x2e, 0xc8, 0xbb, 0xc5, 0x39, 0x6b, 0x58, 0xb3, 0x8c, 0x82, 0x56, 0x19, 0x0e, 0x21, 0x0c,
+ 0x7a, 0xc0, 0x80, 0x1e, 0xd4, 0xf9, 0xf1, 0xcc, 0xb6, 0x8f, 0xe5, 0xf1, 0x3f, 0x6e, 0x45, 0x4f,
+ 0xfe, 0x61, 0xf1, 0xa2, 0x71, 0xe3, 0xc6, 0xc1, 0x76, 0xc1, 0x98, 0x80, 0x5f, 0x41, 0xfb, 0x4c,
+ 0x98, 0x30, 0x61, 0xe2, 0xcb, 0x06, 0xae, 0x8b, 0xbf, 0x42, 0x01, 0xc1, 0xc2, 0xfc, 0x45, 0x02,
+ 0x8d, 0x46, 0x62, 0xff, 0xf6, 0xb7, 0x0f, 0xfb, 0xf6, 0x85, 0x4c, 0xd8, 0x18, 0x12, 0x12, 0x7f,
+ 0xf9, 0x72, 0xc5, 0xd3, 0xca, 0xe8, 0xe8, 0xf3, 0xde, 0x01, 0x1f, 0xb4, 0x7d, 0xfb, 0xa2, 0x84,
+ 0x98, 0x61, 0x71, 0x71, 0x89, 0xcf, 0xa2, 0xb8, 0xa5, 0x4b, 0x97, 0xaa, 0x54, 0x6a, 0x41, 0x41,
+ 0xc4, 0xc5, 0xc5, 0x79, 0x57, 0xd1, 0xe0, 0x1e, 0xf3, 0x72, 0x6e, 0x71, 0xf6, 0x72, 0x62, 0x88,
+ 0xa3, 0xe9, 0x83, 0xd6, 0xa5, 0x34, 0xc9, 0xd5, 0xba, 0x8a, 0x68, 0x22, 0x89, 0x39, 0x99, 0x75,
+ 0x56, 0x25, 0x5c, 0x89, 0xfe, 0xe0, 0x83, 0xff, 0x16, 0x0e, 0x06, 0x57, 0xd9, 0xba, 0x6d, 0x1b,
+ 0x40, 0x79, 0xfb, 0xf6, 0x6d, 0x70, 0x57, 0xf1, 0x24, 0x1b, 0x36, 0x6c, 0x04, 0x3c, 0x84, 0x79,
+ 0x61, 0xb6, 0x58, 0xb7, 0x6c, 0xd9, 0x22, 0xf1, 0xec, 0x53, 0xa6, 0x4c, 0xa9, 0xaa, 0xa6, 0x13,
+ 0xc7, 0xe1, 0x74, 0x49, 0xaa, 0xaa, 0x30, 0x3a, 0xf3, 0xe6, 0xcd, 0x67, 0x79, 0x2b, 0xe9, 0x74,
+ 0xb9, 0xbc, 0x1f, 0x13, 0x03, 0xa3, 0xfa, 0xf8, 0xf1, 0x63, 0x45, 0x4b, 0xcb, 0xf7, 0xdf, 0x7f,
+ 0x2f, 0x31, 0xce, 0x63, 0xc6, 0x8e, 0x2d, 0x29, 0x2d, 0x15, 0xa0, 0xde, 0xe1, 0x11, 0x92, 0x72,
+ 0x3a, 0x5d, 0xf8, 0x21, 0x91, 0x24, 0x88, 0xf1, 0xde, 0x17, 0xd9, 0x5e, 0x8f, 0x58, 0x96, 0x10,
+ 0xce, 0x02, 0x59, 0xc5, 0x4c, 0x81, 0xa9, 0xef, 0xdb, 0xb7, 0x1f, 0x8c, 0x36, 0xfa, 0x04, 0x77,
+ 0xf7, 0x01, 0xdf, 0xc0, 0xc6, 0x3d, 0x83, 0x03, 0x60, 0x8c, 0xb8, 0x0c, 0xad, 0x4e, 0x47, 0xdd,
+ 0x16, 0x88, 0x2b, 0x75, 0x2b, 0x00, 0x2d, 0xe3, 0x76, 0x93, 0xdc, 0xdc, 0x9c, 0xa1, 0x43, 0x87,
+ 0xfe, 0xf9, 0x44, 0x98, 0xf8, 0x43, 0x5f, 0x7d, 0xf5, 0xe5, 0xa3, 0x92, 0x3c, 0xce, 0x59, 0x4b,
+ 0xcc, 0x59, 0xac, 0xee, 0x24, 0x51, 0x86, 0x31, 0x8a, 0xf9, 0x34, 0x4e, 0x4b, 0x73, 0xe8, 0x7e,
+ 0x7c, 0x81, 0xc1, 0x07, 0x86, 0xd2, 0x3e, 0xe7, 0x8f, 0x7f, 0xb7, 0x70, 0xe1, 0x42, 0xc0, 0x72,
+ 0xcc, 0x98, 0x31, 0xcb, 0x97, 0x2f, 0x8f, 0x8e, 0x8e, 0x86, 0x71, 0xb8, 0xe3, 0xd1, 0x52, 0x53,
+ 0x53, 0xa1, 0x5b, 0xc1, 0x1f, 0x70, 0x23, 0xdd, 0x0e, 0x5a, 0xf1, 0xb9, 0x5a, 0x03, 0x07, 0x0e,
+ 0x9a, 0x39, 0x73, 0xe6, 0xae, 0x5d, 0xbb, 0xd2, 0xd2, 0xd2, 0x2a, 0x2b, 0xab, 0x80, 0x01, 0x9f,
+ 0xf7, 0x85, 0x49, 0xb4, 0x78, 0x09, 0xda, 0x52, 0x5c, 0x8f, 0x44, 0x8f, 0xe0, 0x96, 0xa7, 0x4e,
+ 0x9d, 0x5a, 0x56, 0x5e, 0xce, 0x53, 0x02, 0xb7, 0xd1, 0x68, 0x0a, 0x0d, 0x0d, 0xf3, 0x3e, 0x43,
+ 0x40, 0xc0, 0xa4, 0xea, 0xca, 0xbb, 0xac, 0xbd, 0x88, 0x17, 0xa7, 0xa1, 0x4c, 0xeb, 0x12, 0xa6,
+ 0x65, 0x09, 0x69, 0xdf, 0x8c, 0xff, 0xb2, 0xd6, 0x02, 0x93, 0xbe, 0x66, 0xe3, 0xc6, 0xb5, 0xe2,
+ 0x28, 0xc0, 0xae, 0xa6, 0xa5, 0xa5, 0x03, 0x18, 0x87, 0x0e, 0x1d, 0x12, 0x1d, 0x25, 0xfe, 0x0a,
+ 0x17, 0x29, 0x84, 0x9e, 0xf0, 0xaa, 0xaf, 0x6f, 0x98, 0xde, 0x99, 0x7b, 0xe0, 0x00, 0xf0, 0x67,
+ 0xb0, 0x68, 0x8a, 0x67, 0xb3, 0x45, 0xb2, 0x87, 0x1b, 0x66, 0xe2, 0x91, 0x97, 0x71, 0x80, 0x87,
+ 0xc5, 0x25, 0x9e, 0x13, 0x41, 0x68, 0x70, 0xc1, 0x0e, 0x87, 0x33, 0x26, 0x26, 0x46, 0x32, 0x67,
+ 0xa9, 0xb2, 0x3e, 0x73, 0x06, 0x60, 0xf3, 0xdc, 0xa1, 0x45, 0x70, 0xe5, 0x22, 0xa7, 0xe5, 0x3a,
+ 0xdb, 0x58, 0xcf, 0x9c, 0xc1, 0xab, 0x42, 0x82, 0x8e, 0x67, 0x18, 0xe2, 0xae, 0x84, 0x35, 0x84,
+ 0x8b, 0xc9, 0xe1, 0x09, 0x0c, 0xdf, 0xab, 0x1c, 0x0f, 0x5a, 0xd6, 0x66, 0xb3, 0x5e, 0xbd, 0x7a,
+ 0x15, 0x76, 0xac, 0xbb, 0xe0, 0x2a, 0x34, 0x78, 0xa2, 0xa0, 0xa0, 0xc0, 0xca, 0xa7, 0xf7, 0x59,
+ 0x67, 0x2d, 0x6b, 0x4e, 0x27, 0xda, 0x5f, 0x31, 0x2e, 0x8c, 0xe2, 0x3b, 0x1a, 0x2a, 0xaf, 0x1f,
+ 0x49, 0xeb, 0x3f, 0x79, 0x4b, 0x6b, 0xaf, 0xe8, 0x75, 0xe1, 0xe4, 0xa2, 0x4d, 0x21, 0x1b, 0x0f,
+ 0x1c, 0x38, 0x50, 0x58, 0x58, 0x68, 0x30, 0x18, 0x6c, 0x36, 0x9b, 0x46, 0xa3, 0x69, 0x6b, 0x6b,
+ 0x53, 0xa9, 0x54, 0xf0, 0x6b, 0x2e, 0x97, 0x0b, 0xef, 0x13, 0x13, 0x13, 0xc1, 0xe5, 0x60, 0xb2,
+ 0xba, 0x97, 0x1e, 0x08, 0xdb, 0x0a, 0x51, 0x79, 0x3b, 0x7c, 0xf8, 0x82, 0x85, 0xb4, 0x9c, 0x20,
+ 0x2f, 0x3f, 0xbf, 0xb4, 0xb4, 0xd4, 0x27, 0x89, 0x7d, 0x4d, 0xc3, 0x85, 0x81, 0x24, 0x54, 0x54,
+ 0x54, 0x60, 0xc4, 0x04, 0x67, 0x0d, 0xba, 0x0b, 0x19, 0xe2, 0x7d, 0xe4, 0xba, 0x75, 0x6b, 0x74,
+ 0xea, 0x27, 0x94, 0x2f, 0x69, 0x8e, 0x30, 0xed, 0xeb, 0x28, 0x62, 0x5b, 0x57, 0x31, 0xea, 0xdd,
+ 0x2c, 0xcd, 0x73, 0x95, 0x3f, 0x2e, 0xc9, 0x1b, 0x33, 0x66, 0xb4, 0x70, 0x24, 0x86, 0x03, 0xee,
+ 0x5b, 0xa3, 0x01, 0x79, 0x73, 0xaf, 0x58, 0xb1, 0x42, 0x4c, 0x0a, 0x00, 0x48, 0x67, 0xce, 0x9c,
+ 0x15, 0x41, 0x72, 0xaf, 0xa8, 0x48, 0x22, 0xab, 0x81, 0xed, 0xe3, 0xc7, 0x4f, 0x08, 0xc1, 0x7f,
+ 0xb9, 0x42, 0x21, 0x29, 0xe6, 0x87, 0xec, 0x02, 0x4b, 0x17, 0x40, 0x75, 0xea, 0xf4, 0x69, 0xef,
+ 0x50, 0x06, 0x28, 0x07, 0x88, 0x0d, 0x0c, 0x88, 0xe7, 0x87, 0xf8, 0xf5, 0xf9, 0xf3, 0xbf, 0x57,
+ 0x2a, 0x55, 0x9d, 0xd6, 0x12, 0x8a, 0x88, 0xed, 0x78, 0x85, 0x58, 0x40, 0x0a, 0xaa, 0x0d, 0x96,
+ 0xff, 0x95, 0xe6, 0xea, 0x14, 0x7a, 0xa5, 0x39, 0xac, 0xae, 0xd7, 0xbd, 0x00, 0x96, 0xe8, 0x81,
+ 0x97, 0x37, 0x4b, 0x21, 0xab, 0x68, 0x51, 0x44, 0xee, 0x8b, 0xec, 0x7a, 0x60, 0xe4, 0x8d, 0x1a,
+ 0xfa, 0xfc, 0xbb, 0xef, 0xe6, 0x36, 0xd4, 0x3d, 0xe6, 0x1c, 0x15, 0xac, 0xf9, 0x26, 0xd1, 0x1d,
+ 0x25, 0xca, 0x8d, 0xa0, 0x6d, 0xae, 0xc6, 0x2f, 0x98, 0xfa, 0x11, 0x3c, 0x68, 0xf9, 0x8a, 0xd9,
+ 0x3a, 0xbf, 0x7c, 0x59, 0x74, 0x65, 0x65, 0x25, 0xb0, 0xaa, 0x54, 0x2a, 0x01, 0xce, 0xad, 0x5b,
+ 0xb7, 0xae, 0x5e, 0xbd, 0x1a, 0xaa, 0x21, 0x36, 0x36, 0xb6, 0xa9, 0xa9, 0x89, 0x10, 0x82, 0xcf,
+ 0xa3, 0xa2, 0xa2, 0xe0, 0x47, 0xba, 0xb7, 0x72, 0x06, 0x46, 0x1b, 0xb4, 0xad, 0x77, 0xef, 0xde,
+ 0xf0, 0x77, 0x50, 0x19, 0x40, 0x42, 0x71, 0x49, 0x69, 0x41, 0x41, 0xe1, 0x1b, 0x55, 0x71, 0xa3,
+ 0xf3, 0x97, 0x2c, 0x59, 0x5c, 0x53, 0x5b, 0xed, 0x76, 0xb3, 0x62, 0xd4, 0x05, 0xb0, 0x87, 0xb3,
+ 0x93, 0x1c, 0x09, 0x37, 0x71, 0xe2, 0xf8, 0x41, 0xe2, 0x00, 0x59, 0x4a, 0x25, 0xea, 0x48, 0xa6,
+ 0x7d, 0x0d, 0x65, 0x05, 0x6d, 0xeb, 0x69, 0xdd, 0x0b, 0x26, 0xb5, 0xbd, 0xee, 0x72, 0x7c, 0x0c,
+ 0x0c, 0xbe, 0x70, 0xf0, 0xdb, 0xef, 0xbc, 0xb3, 0x26, 0x38, 0x18, 0x78, 0xd0, 0xe9, 0x0d, 0x53,
+ 0xa7, 0xbe, 0xa2, 0x76, 0xb0, 0x8a, 0xf4, 0xd1, 0xb4, 0xfc, 0x20, 0x12, 0x96, 0x4d, 0x4c, 0x4c,
+ 0x92, 0x58, 0x7b, 0x61, 0x55, 0x02, 0xcb, 0xcf, 0x9c, 0x1b, 0xc9, 0xc9, 0x92, 0x6b, 0xf8, 0xa8,
+ 0x7f, 0x7f, 0x81, 0x70, 0xe2, 0x00, 0xb8, 0x66, 0xef, 0xa8, 0x2f, 0x48, 0xec, 0x9e, 0x3d, 0x7b,
+ 0x24, 0xd4, 0xf7, 0x7f, 0x06, 0x0c, 0xb8, 0x93, 0x99, 0xf9, 0xaa, 0x5c, 0xf0, 0x59, 0xa7, 0xda,
+ 0x2d, 0x21, 0x78, 0x62, 0xb1, 0x58, 0x4b, 0x4b, 0x1f, 0x5d, 0xbc, 0x18, 0xb7, 0x7e, 0xfd, 0x86,
+ 0xf2, 0x27, 0x4f, 0x7c, 0xd6, 0xbd, 0xe0, 0xc3, 0xcc, 0x4c, 0xdf, 0x31, 0x6a, 0x9f, 0x0d, 0xc2,
+ 0xbc, 0xa9, 0xa9, 0x99, 0x32, 0x0d, 0xca, 0x61, 0x98, 0xec, 0xec, 0xec, 0x45, 0x8b, 0x16, 0xf9,
+ 0x24, 0x6c, 0x5d, 0x69, 0x3d, 0x7b, 0xf6, 0x9c, 0x30, 0x61, 0x7c, 0x60, 0xe0, 0x74, 0x00, 0xe9,
+ 0xf7, 0xec, 0x33, 0x88, 0xd0, 0x8a, 0x15, 0x3f, 0x68, 0xd5, 0xd5, 0xac, 0xe3, 0x11, 0x31, 0x5d,
+ 0x23, 0x9a, 0x43, 0x4c, 0xdb, 0x5a, 0x46, 0x3e, 0xcb, 0x45, 0xab, 0x95, 0x86, 0xf3, 0x95, 0xf6,
+ 0xc3, 0x48, 0xcb, 0x1c, 0xb7, 0x25, 0x99, 0x71, 0xd9, 0xd5, 0x6a, 0x35, 0xdc, 0x1f, 0x5c, 0x33,
+ 0x6c, 0x7e, 0x41, 0x41, 0xc1, 0xdd, 0xbb, 0x77, 0x4f, 0x9d, 0x3a, 0x05, 0x05, 0xda, 0xdc, 0xdc,
+ 0xcc, 0x30, 0x50, 0xc4, 0x77, 0x40, 0xcf, 0xde, 0xf9, 0x73, 0x7b, 0x81, 0x4a, 0x1a, 0x64, 0x17,
+ 0x68, 0x1b, 0x9c, 0x2f, 0x48, 0x6c, 0x48, 0xc8, 0xa6, 0x4b, 0xf1, 0xf1, 0x15, 0x4f, 0x9f, 0x26,
+ 0x25, 0x25, 0x75, 0xbd, 0xf2, 0x0d, 0x47, 0x82, 0xcc, 0x28, 0x14, 0x72, 0x1e, 0xae, 0x2e, 0x51,
+ 0xc3, 0x26, 0x5d, 0x4d, 0x92, 0x90, 0xc0, 0xb7, 0x68, 0x55, 0x73, 0xff, 0x5b, 0xa9, 0x57, 0x38,
+ 0x67, 0x39, 0x2c, 0x2a, 0xa3, 0xda, 0x4e, 0xad, 0x6b, 0xeb, 0x0a, 0xa2, 0x0c, 0x27, 0xfa, 0x33,
+ 0xc4, 0x56, 0xa0, 0x53, 0x57, 0x07, 0x07, 0xaf, 0x12, 0x0f, 0xc6, 0xb8, 0x40, 0xfb, 0x00, 0x0c,
+ 0x8f, 0x1f, 0x97, 0x8d, 0x1a, 0x35, 0x4a, 0xfc, 0x1c, 0xfc, 0x59, 0x26, 0xcb, 0x16, 0x10, 0x6b,
+ 0xb1, 0xda, 0x22, 0x22, 0xa4, 0xdb, 0x07, 0x41, 0x08, 0x34, 0x34, 0xd4, 0x03, 0xcc, 0x0c, 0x61,
+ 0xbd, 0xb7, 0xc3, 0x0a, 0x0c, 0x0c, 0xe4, 0x8d, 0x95, 0x5b, 0xad, 0xd6, 0xe0, 0xae, 0x25, 0x03,
+ 0x07, 0x00, 0x27, 0x24, 0x24, 0x48, 0x5c, 0x36, 0x3e, 0x04, 0x4d, 0x02, 0xe9, 0x15, 0x17, 0x67,
+ 0x89, 0xc5, 0x87, 0x02, 0x43, 0x78, 0xf8, 0xb0, 0xf8, 0xdc, 0xb9, 0x68, 0xcc, 0xaf, 0xcf, 0x3f,
+ 0xff, 0x1c, 0x7a, 0x04, 0x78, 0x68, 0x69, 0x6d, 0xeb, 0x78, 0x45, 0x65, 0x5f, 0x56, 0x6e, 0x77,
+ 0x3c, 0x33, 0x99, 0xcd, 0x9b, 0x37, 0x6f, 0x96, 0xc4, 0x1f, 0x5e, 0xd3, 0x20, 0xc9, 0xd7, 0xae,
+ 0x5d, 0x9b, 0x98, 0x94, 0x74, 0xe1, 0xc2, 0xc5, 0xb0, 0xb0, 0x2d, 0x7f, 0x78, 0x5f, 0x65, 0x38,
+ 0x1a, 0x10, 0xb9, 0x73, 0xe7, 0xce, 0x94, 0x97, 0x3f, 0x6a, 0x6e, 0x6e, 0xbc, 0x7e, 0xe3, 0x3a,
+ 0x5c, 0xf6, 0xef, 0x81, 0x16, 0xf7, 0x1b, 0x1e, 0x1e, 0x62, 0xd4, 0xd7, 0xb0, 0xf6, 0x87, 0xb4,
+ 0xca, 0x4e, 0xb3, 0x9f, 0x96, 0xd8, 0x35, 0xcf, 0x70, 0x09, 0x25, 0x76, 0x8d, 0x63, 0x39, 0x75,
+ 0xf8, 0x33, 0xa6, 0xf2, 0x59, 0x07, 0xb9, 0x79, 0xf3, 0x66, 0x44, 0x44, 0xc4, 0x93, 0x27, 0x4f,
+ 0x40, 0xc3, 0xa0, 0x70, 0xa1, 0x10, 0x81, 0x5b, 0xb0, 0x85, 0xcb, 0x97, 0x2f, 0x3b, 0x9d, 0x4e,
+ 0x7c, 0x0e, 0x06, 0x09, 0x51, 0xdc, 0x5d, 0xc4, 0x40, 0x28, 0x27, 0x00, 0x30, 0xa0, 0xac, 0x31,
+ 0x8e, 0x3f, 0x45, 0x6c, 0x07, 0x42, 0x20, 0x58, 0xb6, 0x6d, 0xdb, 0xd6, 0xf5, 0xae, 0x00, 0x1f,
+ 0x80, 0x2c, 0xa2, 0x64, 0xc0, 0x23, 0xf0, 0xe2, 0x70, 0xd8, 0x42, 0x43, 0x43, 0xbd, 0x0f, 0xfe,
+ 0xe2, 0x8b, 0xf1, 0x15, 0x65, 0xf9, 0xac, 0xed, 0x21, 0x31, 0xc4, 0x00, 0xa8, 0x14, 0xb1, 0x6d,
+ 0xc1, 0x44, 0xfd, 0x33, 0x31, 0x5e, 0x66, 0xed, 0x8f, 0x6a, 0xab, 0x8b, 0x3f, 0xf9, 0xe4, 0x63,
+ 0xf1, 0x60, 0x98, 0x68, 0x28, 0x0e, 0x20, 0x36, 0x25, 0xe5, 0xa6, 0xa7, 0xdf, 0x07, 0x2f, 0x85,
+ 0x29, 0x13, 0x10, 0xab, 0x52, 0x6b, 0x02, 0x3b, 0xc7, 0xcf, 0x31, 0x4d, 0x16, 0x2e, 0x5c, 0xe0,
+ 0x72, 0xd9, 0x59, 0xd6, 0x01, 0x9f, 0xf5, 0xdb, 0xa9, 0x53, 0x21, 0x2f, 0x1b, 0x0d, 0x75, 0x6d,
+ 0xde, 0x7c, 0x23, 0x39, 0xc5, 0x05, 0x28, 0xb3, 0x5c, 0x61, 0xe1, 0x5d, 0x3f, 0x3f, 0x69, 0x3c,
+ 0xe4, 0x83, 0x3e, 0x7d, 0x82, 0x82, 0x82, 0x24, 0x1f, 0x62, 0x8e, 0x40, 0x88, 0x89, 0xdc, 0x55,
+ 0xac, 0xeb, 0x16, 0x37, 0xdd, 0x9a, 0x33, 0x67, 0x6e, 0xaf, 0x5e, 0xbd, 0xc4, 0x19, 0x1a, 0x1c,
+ 0xfc, 0xa3, 0x55, 0x28, 0x7d, 0x79, 0x26, 0xad, 0xa4, 0x05, 0x87, 0x79, 0xd3, 0x47, 0x82, 0x62,
+ 0x80, 0x60, 0x52, 0x40, 0x03, 0x5e, 0x93, 0x04, 0x7c, 0x7d, 0x03, 0x66, 0xd6, 0xad, 0x0b, 0xae,
+ 0xaa, 0x7c, 0xe4, 0x72, 0xe8, 0x39, 0xd6, 0xc2, 0x71, 0x76, 0x86, 0xb1, 0x03, 0x54, 0xde, 0x4e,
+ 0x50, 0x6c, 0xef, 0xbf, 0xff, 0x9f, 0x91, 0x7b, 0xb6, 0x5b, 0x8d, 0x35, 0x9c, 0xad, 0x88, 0xa6,
+ 0x26, 0x35, 0x91, 0x4c, 0xdb, 0x0a, 0x17, 0x05, 0xed, 0x78, 0x46, 0x3e, 0x83, 0x33, 0x9c, 0x7e,
+ 0xee, 0x56, 0x83, 0x4e, 0x1f, 0x3f, 0x7e, 0xfc, 0xc2, 0x85, 0x0b, 0x0a, 0x85, 0x02, 0x96, 0x1f,
+ 0x76, 0x15, 0xf3, 0x3a, 0x25, 0x25, 0x25, 0x37, 0x37, 0x17, 0x4e, 0x0a, 0xfc, 0x56, 0x2e, 0x97,
+ 0x03, 0xcf, 0x98, 0xfe, 0xdd, 0xb5, 0xd0, 0x46, 0x7c, 0xda, 0xe6, 0x90, 0x21, 0x7e, 0xe8, 0xf3,
+ 0x7d, 0xfb, 0xa2, 0xe0, 0xf8, 0x6a, 0xeb, 0xea, 0x02, 0x02, 0x02, 0xba, 0xde, 0x1b, 0x02, 0xdb,
+ 0x34, 0x99, 0xe1, 0x67, 0x89, 0x88, 0x58, 0xb3, 0xd9, 0x08, 0x6b, 0xe3, 0x7d, 0xf0, 0xa2, 0x85,
+ 0xf3, 0xcc, 0x86, 0x1a, 0xd6, 0x9a, 0x47, 0xf4, 0xa7, 0x68, 0xb6, 0xab, 0x75, 0x35, 0xd3, 0x1e,
+ 0x02, 0x4a, 0x40, 0x4b, 0x62, 0x1c, 0xb5, 0x09, 0x97, 0x63, 0x3d, 0xcd, 0xf2, 0xec, 0xd9, 0xb3,
+ 0x85, 0x60, 0xd1, 0x89, 0x13, 0x27, 0x3c, 0xd9, 0x26, 0x18, 0x42, 0x63, 0x63, 0x93, 0x80, 0x58,
+ 0x78, 0x4c, 0x49, 0xb7, 0xe3, 0x76, 0xf6, 0xef, 0x8f, 0xc2, 0xa0, 0x70, 0xc4, 0xa0, 0x56, 0xb7,
+ 0x63, 0x02, 0x3e, 0x79, 0x52, 0x51, 0x0e, 0x27, 0x5d, 0xf1, 0x14, 0xef, 0x1b, 0x1a, 0x1a, 0x60,
+ 0x5a, 0x61, 0x99, 0x01, 0xda, 0x73, 0xe7, 0xce, 0x79, 0x97, 0xf1, 0xc0, 0x65, 0x48, 0x80, 0x81,
+ 0x1b, 0x8c, 0x8f, 0x8f, 0x17, 0xc5, 0x94, 0x67, 0x35, 0xb8, 0xb0, 0xb1, 0x21, 0x8c, 0x89, 0x67,
+ 0x96, 0x01, 0x5f, 0xc7, 0x14, 0xe3, 0x5e, 0x3e, 0x68, 0x5e, 0x4c, 0x69, 0xe1, 0xeb, 0x36, 0xbb,
+ 0x1d, 0x9d, 0xec, 0xb3, 0x3e, 0xf3, 0xaf, 0x6b, 0x30, 0x29, 0x27, 0x8e, 0x1f, 0x36, 0xea, 0x9a,
+ 0x38, 0x57, 0x1b, 0xe7, 0x6a, 0xe5, 0x18, 0x25, 0x7a, 0xc6, 0xcd, 0x39, 0x65, 0xb2, 0x2c, 0x58,
+ 0xaa, 0xdf, 0xfb, 0x96, 0x50, 0x78, 0x00, 0x0a, 0xe7, 0xb4, 0x35, 0xb2, 0x14, 0xb4, 0xf1, 0x44,
+ 0xbd, 0x9b, 0xd6, 0x2c, 0xc9, 0x83, 0x48, 0xcb, 0x77, 0x6e, 0x63, 0xec, 0x73, 0xb7, 0xce, 0x68,
+ 0x34, 0x1c, 0x3e, 0x7c, 0x18, 0x10, 0x05, 0x62, 0xc7, 0x8d, 0x1b, 0x37, 0x6b, 0xd6, 0xac, 0x79,
+ 0xf3, 0xe6, 0x01, 0xa8, 0x30, 0xad, 0xe1, 0xe1, 0xe1, 0xd0, 0x62, 0x78, 0x7f, 0xf6, 0xec, 0x59,
+ 0xf8, 0x85, 0xee, 0xa2, 0xb2, 0xfc, 0x13, 0xa1, 0xff, 0x0d, 0x4a, 0x64, 0xe4, 0xc8, 0x91, 0x8b,
+ 0x97, 0x2c, 0x39, 0x76, 0xfc, 0x38, 0x24, 0xc9, 0xd3, 0xca, 0xaa, 0x37, 0x2d, 0x07, 0x02, 0xe5,
+ 0x9b, 0x35, 0x6b, 0xa6, 0x56, 0xab, 0xe1, 0x41, 0xcb, 0x80, 0x1e, 0x34, 0xcb, 0x9b, 0xbd, 0x1d,
+ 0x1f, 0xc5, 0x52, 0xd4, 0x2e, 0xce, 0x55, 0xcf, 0xe7, 0x0e, 0x8e, 0x90, 0xf6, 0x10, 0xa6, 0x6d,
+ 0x1d, 0x51, 0x6d, 0x67, 0x69, 0x66, 0xb6, 0xd0, 0x69, 0x93, 0x07, 0x06, 0x76, 0x8a, 0x43, 0x26,
+ 0x24, 0x26, 0x0a, 0x11, 0xf5, 0x8d, 0x21, 0x21, 0x9e, 0xfe, 0x6b, 0xc1, 0x82, 0x05, 0x26, 0x93,
+ 0x59, 0x88, 0x23, 0xdd, 0x4a, 0x4b, 0x93, 0xfc, 0x0a, 0xc4, 0x75, 0x6e, 0x4e, 0x26, 0x06, 0x85,
+ 0x73, 0x35, 0xb3, 0xf6, 0xca, 0xd2, 0x92, 0x22, 0x59, 0x76, 0x4e, 0x66, 0x96, 0x0c, 0x8a, 0xfb,
+ 0x5e, 0xd1, 0xfd, 0xf2, 0x27, 0x15, 0xcd, 0x72, 0x85, 0xde, 0x60, 0x04, 0x68, 0x37, 0x6c, 0xdc,
+ 0xe8, 0xcd, 0x5b, 0xbc, 0x07, 0x8e, 0x4f, 0x3a, 0xdb, 0x5e, 0x45, 0xab, 0x24, 0x8b, 0xbc, 0x3a,
+ 0xe8, 0x76, 0xf4, 0x9e, 0xb1, 0xe2, 0xf1, 0xe3, 0xc7, 0xd7, 0xd4, 0xd4, 0xbe, 0x12, 0x68, 0x1e,
+ 0x06, 0x16, 0x13, 0xa7, 0x7b, 0xd7, 0xc9, 0xbe, 0xbe, 0x61, 0xf6, 0x0d, 0x1e, 0x3c, 0x28, 0x47,
+ 0x96, 0xea, 0x66, 0x14, 0x9c, 0xe3, 0x29, 0x6b, 0x2f, 0x65, 0xed, 0xe5, 0x9c, 0xb3, 0x9e, 0x65,
+ 0xd4, 0x84, 0xb1, 0xc4, 0xc5, 0x5d, 0x90, 0xf0, 0x61, 0x8c, 0x23, 0xa6, 0x1b, 0xbe, 0x25, 0xf6,
+ 0x36, 0x40, 0x7b, 0xf6, 0xcc, 0x09, 0x9b, 0x99, 0xaf, 0x38, 0x32, 0x5c, 0x82, 0x37, 0x04, 0x8b,
+ 0x63, 0x14, 0xf3, 0x39, 0xed, 0xde, 0x67, 0xa4, 0xd6, 0xe5, 0xb4, 0x9f, 0x3e, 0x7d, 0xfa, 0xe4,
+ 0xc9, 0x93, 0xb0, 0xae, 0x4b, 0x97, 0x2e, 0xd5, 0xe9, 0x74, 0x60, 0xb0, 0xe0, 0xae, 0xc0, 0x30,
+ 0x90, 0x6c, 0x36, 0x9b, 0xdb, 0xdb, 0xdb, 0x0f, 0x1e, 0x3c, 0x88, 0x79, 0xd1, 0x5d, 0x4b, 0xc3,
+ 0x84, 0x67, 0x15, 0x09, 0x7b, 0xbc, 0xaf, 0x5e, 0x13, 0x7c, 0x2e, 0xfa, 0x3c, 0xbc, 0xed, 0xb5,
+ 0xeb, 0xd7, 0xff, 0x40, 0xe7, 0x00, 0xe4, 0x61, 0x61, 0x61, 0x3a, 0x1d, 0x54, 0x2d, 0x0b, 0x92,
+ 0x08, 0x1e, 0xee, 0x7d, 0xcc, 0x47, 0xfd, 0xfa, 0xa5, 0xa6, 0x5c, 0x61, 0xd1, 0x75, 0xc6, 0x6b,
+ 0x94, 0x1a, 0x01, 0xb1, 0xed, 0x9b, 0x88, 0x26, 0x8a, 0x35, 0x26, 0x71, 0xf6, 0x32, 0x79, 0x53,
+ 0xc5, 0xbb, 0xef, 0xbe, 0xea, 0x40, 0x18, 0x55, 0x50, 0x41, 0x8c, 0xb2, 0xa2, 0xa5, 0x75, 0xee,
+ 0xb7, 0xdf, 0x8a, 0x9f, 0xe3, 0x82, 0xd7, 0xae, 0x5d, 0x27, 0xd6, 0xf8, 0x85, 0x87, 0x6f, 0x95,
+ 0xfc, 0xca, 0xb0, 0x61, 0xc3, 0x34, 0x9a, 0x16, 0x8e, 0x2f, 0x92, 0xe1, 0xac, 0x45, 0x9a, 0xe6,
+ 0xcc, 0x84, 0x84, 0xc4, 0xcb, 0x57, 0xae, 0x40, 0xac, 0xa5, 0xa5, 0xa5, 0x63, 0x4a, 0x56, 0xd7,
+ 0xd4, 0xaa, 0x35, 0x9a, 0x9a, 0xda, 0x3a, 0x9f, 0x65, 0x3c, 0x92, 0x86, 0x11, 0xcc, 0x92, 0xc9,
+ 0x84, 0xdd, 0x30, 0x04, 0x3e, 0xe0, 0xb5, 0x2c, 0xf1, 0x59, 0x41, 0x61, 0xa1, 0xa8, 0xdc, 0x31,
+ 0xe8, 0x34, 0xc5, 0xc0, 0xef, 0x01, 0x2b, 0x0a, 0x34, 0x81, 0xc1, 0x32, 0x0c, 0x39, 0x78, 0xf0,
+ 0x50, 0xd7, 0xe3, 0x51, 0x38, 0x12, 0xe0, 0xf9, 0x03, 0x4b, 0x96, 0x84, 0x06, 0x34, 0xce, 0x98,
+ 0x31, 0xbd, 0xa4, 0x38, 0x97, 0x38, 0xea, 0x38, 0xe0, 0xcd, 0x92, 0xc5, 0x5a, 0xb3, 0x60, 0x19,
+ 0xd0, 0xff, 0x1c, 0xa3, 0x52, 0x29, 0x29, 0xc6, 0xc4, 0x83, 0xd1, 0xdb, 0x9f, 0x7d, 0x36, 0x72,
+ 0xe6, 0xcc, 0xa0, 0xd5, 0xab, 0x56, 0xac, 0x58, 0xb1, 0x6c, 0xda, 0xb4, 0xa9, 0xe2, 0x1c, 0xec,
+ 0xd7, 0xaf, 0x5f, 0xc2, 0x95, 0x0b, 0x4e, 0x5b, 0x13, 0x6b, 0x2b, 0x20, 0x86, 0x58, 0x5a, 0x5c,
+ 0xd7, 0xba, 0x82, 0x55, 0x85, 0x76, 0xd8, 0x73, 0x9e, 0x77, 0xd8, 0xee, 0xde, 0x2d, 0x04, 0x13,
+ 0xc8, 0xcc, 0xcc, 0x8c, 0x8a, 0x8a, 0x82, 0xaf, 0xc1, 0x1b, 0x38, 0x44, 0xb0, 0x4a, 0xe0, 0x96,
+ 0x10, 0x02, 0x63, 0x0b, 0x6d, 0xfb, 0xde, 0x7b, 0xef, 0x75, 0x17, 0x8f, 0x15, 0x9e, 0xa3, 0xf1,
+ 0x61, 0xdf, 0xbe, 0x5f, 0x06, 0x04, 0x40, 0x0e, 0x60, 0x58, 0xab, 0x6b, 0x6a, 0x7c, 0xf2, 0x4f,
+ 0xdc, 0xfe, 0xe4, 0xc9, 0x93, 0x83, 0x83, 0x83, 0x21, 0x2e, 0x3c, 0x65, 0xbb, 0x67, 0xeb, 0xdf,
+ 0xbf, 0x7f, 0x72, 0x72, 0x32, 0x1f, 0x3f, 0x77, 0x43, 0x2c, 0x78, 0x1f, 0x30, 0x72, 0xe4, 0xf0,
+ 0x86, 0xba, 0x62, 0xd6, 0x56, 0x4c, 0x97, 0xc3, 0xa8, 0xf7, 0x12, 0xc0, 0x55, 0xf5, 0x13, 0xd1,
+ 0xfd, 0x4a, 0x2c, 0x19, 0x9c, 0xab, 0xe1, 0xe4, 0xc9, 0xa3, 0x9e, 0x07, 0x4f, 0x9f, 0x3e, 0xdd,
+ 0xc2, 0xd7, 0x34, 0x96, 0x3e, 0x7a, 0xe4, 0x19, 0x50, 0xc5, 0x95, 0xd0, 0x52, 0x9c, 0x97, 0x91,
+ 0x4f, 0x38, 0x23, 0xcf, 0x6f, 0x61, 0x7c, 0xe7, 0xce, 0x9d, 0xe3, 0xe6, 0x6c, 0x1c, 0xd3, 0xce,
+ 0x3a, 0x2a, 0x59, 0x6b, 0xa1, 0x53, 0x9f, 0x9e, 0x27, 0x4b, 0xb8, 0x18, 0x17, 0x77, 0x25, 0x21,
+ 0xe1, 0x66, 0x6a, 0x6a, 0x7e, 0x41, 0x21, 0xb8, 0x81, 0x46, 0xa3, 0xcd, 0xce, 0xc9, 0xe9, 0xca,
+ 0x4a, 0x40, 0x78, 0xf0, 0xbc, 0xfc, 0xfc, 0x17, 0x0f, 0x83, 0xed, 0x8c, 0x58, 0x71, 0x19, 0x2c,
+ 0x66, 0x04, 0xfc, 0x94, 0x70, 0x7c, 0xef, 0xde, 0xbd, 0x31, 0x5b, 0xc5, 0xa7, 0xc7, 0x7a, 0xee,
+ 0xa0, 0xa5, 0x54, 0xa9, 0xbc, 0x69, 0xb3, 0xcf, 0x86, 0x41, 0x19, 0x3e, 0x7c, 0xf8, 0xb2, 0x65,
+ 0xcb, 0xb6, 0x84, 0x87, 0xa3, 0x27, 0x47, 0x8f, 0x1e, 0xdd, 0x75, 0xa5, 0x26, 0x34, 0x20, 0x70,
+ 0xe5, 0xca, 0xe5, 0xd5, 0x95, 0xc5, 0xac, 0xab, 0x91, 0x6e, 0xd2, 0x65, 0x4e, 0x26, 0xa6, 0x04,
+ 0x62, 0xbe, 0xce, 0x5a, 0xb3, 0x81, 0x58, 0xc2, 0xa8, 0x33, 0x32, 0x6e, 0x09, 0x81, 0x68, 0xdc,
+ 0xe0, 0x67, 0x23, 0x47, 0x1c, 0x3c, 0xb0, 0xf7, 0x49, 0x59, 0x91, 0xd3, 0xa6, 0xa2, 0xbe, 0x89,
+ 0x35, 0xdb, 0x6c, 0xfa, 0x98, 0xf3, 0xe7, 0x44, 0xf9, 0xe9, 0xe7, 0x37, 0xe4, 0x76, 0xfa, 0x0d,
+ 0x37, 0x4e, 0x65, 0x91, 0x11, 0xfd, 0x69, 0xa2, 0xdc, 0x4a, 0xda, 0xd7, 0x72, 0xfa, 0x93, 0xcf,
+ 0x48, 0x9d, 0xc3, 0x6e, 0x02, 0x1f, 0x86, 0x69, 0x8d, 0x8e, 0x8e, 0xce, 0xcf, 0xcf, 0xbf, 0x76,
+ 0xed, 0x1a, 0xde, 0x83, 0x6e, 0xc1, 0xde, 0x9a, 0x4c, 0xa6, 0xc4, 0xc4, 0xc4, 0x2f, 0xbf, 0xfc,
+ 0x12, 0x17, 0xdf, 0x2d, 0x88, 0x15, 0x1f, 0xb8, 0x09, 0x61, 0x3b, 0x63, 0x46, 0xd0, 0x8e, 0x1d,
+ 0x3b, 0x52, 0x6e, 0xde, 0x6c, 0x96, 0xcb, 0xc7, 0xfa, 0xe2, 0x9f, 0x03, 0x3e, 0xfe, 0x18, 0xd3,
+ 0xc7, 0xe9, 0x62, 0xf0, 0x3a, 0x72, 0xe4, 0x17, 0x9f, 0xbd, 0x84, 0x59, 0x99, 0x94, 0x94, 0xc4,
+ 0x47, 0x26, 0xdd, 0x23, 0x46, 0x8c, 0x90, 0xfc, 0x15, 0xb6, 0x71, 0xd6, 0xac, 0x20, 0x97, 0x5d,
+ 0x8e, 0x69, 0x4e, 0x65, 0x97, 0x7a, 0x37, 0x5d, 0x9f, 0xa8, 0x8e, 0x24, 0x86, 0x8b, 0xa0, 0x49,
+ 0x2e, 0x47, 0xcb, 0xa4, 0x49, 0x13, 0x3d, 0x8f, 0xff, 0xe5, 0x97, 0xa3, 0x42, 0x39, 0x4d, 0x46,
+ 0xc6, 0x1d, 0x71, 0x0d, 0xd4, 0x5b, 0x7c, 0x7c, 0xe6, 0xcc, 0x99, 0x33, 0xee, 0x97, 0xd9, 0x2e,
+ 0x09, 0x81, 0x41, 0xff, 0x1f, 0x3d, 0xfa, 0x8b, 0x1b, 0x24, 0x96, 0x81, 0x8d, 0x6d, 0x80, 0x9a,
+ 0x63, 0x2d, 0x05, 0x86, 0xb6, 0x2c, 0x59, 0x66, 0x5a, 0xfa, 0xed, 0xdb, 0xb9, 0x79, 0x79, 0x25,
+ 0xfc, 0x8e, 0x6a, 0x06, 0xa3, 0x31, 0x2e, 0xee, 0xd2, 0xeb, 0xeb, 0x6f, 0xc5, 0x76, 0xe5, 0x4a,
+ 0x02, 0xcb, 0x71, 0x12, 0xc4, 0x3e, 0xf7, 0xd8, 0xeb, 0xf8, 0xf0, 0x91, 0x23, 0x62, 0x44, 0x6e,
+ 0xd2, 0xa4, 0x49, 0xa0, 0x55, 0x9d, 0xb6, 0x81, 0x7d, 0x59, 0xe5, 0x12, 0x17, 0x17, 0xd7, 0x15,
+ 0x83, 0x89, 0x29, 0x39, 0x77, 0xee, 0xb7, 0x19, 0x19, 0x19, 0xed, 0x4a, 0x15, 0x6e, 0xd0, 0x66,
+ 0x31, 0x17, 0x16, 0x16, 0x4c, 0xf7, 0x55, 0x9e, 0xf1, 0x7b, 0x0d, 0x70, 0x8d, 0x88, 0xd8, 0xda,
+ 0xdc, 0x54, 0xc5, 0x31, 0xad, 0xac, 0xbd, 0x84, 0xae, 0x95, 0x83, 0x6d, 0x34, 0xc4, 0xb0, 0xa6,
+ 0x24, 0x28, 0x08, 0xce, 0x59, 0x67, 0xd0, 0x2b, 0x02, 0x03, 0xe9, 0x09, 0x71, 0xd9, 0x4b, 0x97,
+ 0x2e, 0xca, 0xcf, 0xbb, 0xcd, 0x38, 0x5a, 0xc1, 0xd6, 0x38, 0x47, 0x25, 0xe7, 0xa8, 0x66, 0x5d,
+ 0x4d, 0xf0, 0x50, 0x46, 0x83, 0x72, 0xdd, 0xba, 0x1f, 0xc5, 0x73, 0x0e, 0x1f, 0xfe, 0x69, 0x69,
+ 0x71, 0x0e, 0xe7, 0xac, 0xe2, 0x19, 0xdd, 0x09, 0x8c, 0x1d, 0xab, 0xda, 0xda, 0x61, 0xbd, 0xf9,
+ 0x9c, 0x53, 0x39, 0x1c, 0x96, 0xc2, 0xc2, 0xc2, 0x4b, 0x97, 0x2e, 0xc5, 0xc6, 0xc6, 0xe2, 0xdf,
+ 0xec, 0x6c, 0x99, 0xc9, 0xa8, 0x73, 0x33, 0xfa, 0x87, 0x0f, 0x8b, 0x60, 0xe2, 0x60, 0xc7, 0xfe,
+ 0xfd, 0x0d, 0x1f, 0xbb, 0xf0, 0x1a, 0xc4, 0x42, 0x76, 0xe1, 0x9a, 0x85, 0xfd, 0x34, 0xf6, 0xef,
+ 0x3f, 0x20, 0xcb, 0xce, 0x7e, 0x52, 0x51, 0xd1, 0xa3, 0x47, 0x0f, 0xef, 0x4e, 0x18, 0x3d, 0x66,
+ 0x8c, 0x8a, 0x2e, 0x05, 0xa5, 0x96, 0x03, 0x07, 0xfb, 0xec, 0xa8, 0x51, 0xa3, 0xfc, 0xcb, 0xca,
+ 0xca, 0x61, 0xf7, 0x00, 0x09, 0xef, 0x9a, 0x2e, 0x4c, 0x8d, 0xdd, 0xbb, 0x23, 0xc0, 0x2d, 0x09,
+ 0xe6, 0xa9, 0xee, 0x34, 0xa3, 0xda, 0xc5, 0xa8, 0xb6, 0x13, 0xed, 0x31, 0x62, 0xba, 0x09, 0x8a,
+ 0x55, 0x5a, 0x9c, 0xd7, 0xbb, 0xf7, 0x2b, 0x11, 0x84, 0xaf, 0xdf, 0xbb, 0x77, 0x4f, 0x48, 0xf5,
+ 0x42, 0x8a, 0x7a, 0x4a, 0x21, 0xa0, 0x37, 0x39, 0x25, 0x45, 0x50, 0x64, 0x05, 0x05, 0x85, 0x92,
+ 0x5f, 0xc1, 0x74, 0x2e, 0x2e, 0x7e, 0x08, 0x59, 0xc1, 0x11, 0x13, 0x47, 0x34, 0x1c, 0xd3, 0xc2,
+ 0x39, 0x1b, 0x88, 0xad, 0x46, 0xd9, 0x06, 0x2e, 0x50, 0xd7, 0xd2, 0xd2, 0xaa, 0xd1, 0x6a, 0x2d,
+ 0x16, 0x2b, 0x68, 0x30, 0x0c, 0x75, 0x17, 0x1d, 0xee, 0x81, 0x03, 0x07, 0x5c, 0x0c, 0x23, 0x20,
+ 0xb0, 0xd3, 0xf2, 0x81, 0x17, 0x50, 0x7c, 0xbe, 0x71, 0x63, 0x88, 0x90, 0x8c, 0x86, 0x13, 0x0f,
+ 0x09, 0x09, 0x01, 0xf1, 0xf6, 0x7c, 0x66, 0x81, 0xb0, 0x7a, 0xd1, 0xe9, 0x72, 0x49, 0x52, 0x12,
+ 0x3e, 0x1b, 0xe0, 0xba, 0x76, 0xdd, 0xba, 0x47, 0x8f, 0x1f, 0xcb, 0xe5, 0x0a, 0x88, 0xca, 0x96,
+ 0x96, 0x16, 0xa7, 0xd5, 0xe8, 0x72, 0xd8, 0x22, 0x23, 0xf7, 0x76, 0x51, 0xaf, 0xe1, 0x4a, 0x7e,
+ 0xfb, 0xed, 0xa4, 0x56, 0xdb, 0xce, 0x11, 0x1d, 0xe7, 0xa8, 0x61, 0x2d, 0x39, 0x2c, 0x94, 0xbe,
+ 0xee, 0x34, 0xd1, 0x47, 0xc3, 0xd2, 0x72, 0xf6, 0x62, 0x37, 0x69, 0x3f, 0x7d, 0xea, 0x04, 0x3a,
+ 0x0a, 0x73, 0x7f, 0xe7, 0xce, 0xed, 0x0a, 0x79, 0x25, 0x71, 0xc2, 0xe3, 0x97, 0x52, 0xf3, 0x6b,
+ 0xce, 0xa0, 0x99, 0x1d, 0x50, 0x08, 0x67, 0x3d, 0x61, 0xf4, 0xd7, 0xae, 0x25, 0x8a, 0x3d, 0x0f,
+ 0x8a, 0x12, 0x10, 0xf0, 0xbf, 0x15, 0xe5, 0x05, 0x9c, 0xa3, 0x9c, 0x98, 0x52, 0x88, 0xe6, 0x17,
+ 0xa2, 0x0c, 0x67, 0xb5, 0xfb, 0x3a, 0x6c, 0x99, 0xcf, 0xb9, 0xf6, 0xe7, 0xcf, 0x1c, 0x8c, 0xd3,
+ 0x64, 0x32, 0x28, 0x1d, 0x76, 0xc3, 0xf3, 0x0e, 0xc7, 0x73, 0x4e, 0xed, 0xb6, 0xa4, 0x47, 0x9f,
+ 0x3d, 0x3a, 0x71, 0xe2, 0x44, 0xfc, 0x0a, 0xfa, 0xb9, 0x5b, 0x72, 0xb5, 0x02, 0x89, 0xfd, 0xaf,
+ 0x1e, 0x3d, 0x46, 0xf9, 0xfb, 0x2f, 0x5b, 0xb6, 0xfc, 0xe4, 0x6f, 0xb4, 0x00, 0x06, 0xc4, 0xc0,
+ 0x3b, 0x3a, 0x8d, 0xbe, 0x5a, 0xbc, 0x78, 0x09, 0xc7, 0x27, 0xe2, 0xc1, 0xd0, 0xbc, 0x8b, 0x5b,
+ 0x84, 0x3b, 0x82, 0x54, 0x14, 0x14, 0x0a, 0x4e, 0xe2, 0xbd, 0x67, 0x14, 0x0c, 0x5a, 0x46, 0xc6,
+ 0x0d, 0xce, 0x59, 0x49, 0x73, 0x07, 0xba, 0xe3, 0x44, 0xb5, 0x93, 0x51, 0xef, 0xa1, 0xdd, 0x68,
+ 0xcd, 0xe5, 0x5c, 0xf2, 0xdd, 0xbb, 0x7e, 0xf2, 0x4c, 0xa6, 0x07, 0x4c, 0x9e, 0x0c, 0xd8, 0x0b,
+ 0xe1, 0x56, 0x78, 0x19, 0xcf, 0xf3, 0x0c, 0x1e, 0x3c, 0xf8, 0xfe, 0xfd, 0x07, 0x02, 0x25, 0xd8,
+ 0xeb, 0xb5, 0xd5, 0x15, 0x9c, 0xb2, 0xd3, 0xe5, 0x14, 0x6a, 0xba, 0x22, 0x23, 0x77, 0x7f, 0xfa,
+ 0xe9, 0xd0, 0x21, 0x43, 0x06, 0x0e, 0x19, 0xf2, 0xc9, 0xe0, 0xc1, 0x9f, 0x0c, 0x1a, 0x34, 0x30,
+ 0x2c, 0x6c, 0x8b, 0x46, 0xab, 0x83, 0xbd, 0x6c, 0x69, 0x6d, 0x85, 0xaa, 0xf5, 0x46, 0x8b, 0xb0,
+ 0xef, 0x9f, 0xe4, 0x73, 0xf8, 0x65, 0x0a, 0x42, 0x0f, 0xdd, 0xe5, 0x99, 0x11, 0x80, 0xf9, 0xc5,
+ 0x8d, 0x0b, 0xdf, 0x82, 0xe8, 0x83, 0x1f, 0x14, 0x1f, 0xb7, 0xe1, 0xb1, 0xb8, 0xe0, 0x79, 0x72,
+ 0x72, 0xca, 0xbb, 0xef, 0xfe, 0xc7, 0xef, 0x03, 0x8d, 0x36, 0xf4, 0xc0, 0xb1, 0x63, 0xc7, 0xeb,
+ 0xeb, 0x1b, 0x20, 0x0f, 0xc1, 0xb7, 0xf3, 0xf2, 0xf2, 0xcb, 0x1e, 0x95, 0x58, 0x35, 0x0a, 0xc6,
+ 0x6e, 0xde, 0x1f, 0x15, 0xf9, 0x2f, 0x11, 0x8b, 0x6b, 0x00, 0x3c, 0x2e, 0x5d, 0x8a, 0x77, 0x38,
+ 0x1d, 0xb4, 0x0e, 0x93, 0x51, 0xd3, 0xbc, 0x95, 0x25, 0x83, 0x35, 0x5c, 0xa0, 0x88, 0x35, 0x5c,
+ 0x24, 0x96, 0x3b, 0xac, 0xb3, 0xa6, 0xb1, 0xa1, 0xfc, 0xa3, 0x8f, 0xfa, 0x61, 0xe2, 0xc7, 0xc4,
+ 0x44, 0x5b, 0x2d, 0x6a, 0xd6, 0xd5, 0xf2, 0xd2, 0x0e, 0xe3, 0xb0, 0x33, 0x44, 0x1f, 0xcb, 0x9a,
+ 0x52, 0xe1, 0x9b, 0xdc, 0x44, 0x93, 0x97, 0x9b, 0xe5, 0x99, 0x59, 0x7b, 0xe7, 0xed, 0xb7, 0xbf,
+ 0x0e, 0x9a, 0x5e, 0x5f, 0xfb, 0x80, 0xcf, 0x2c, 0x5c, 0x67, 0xb5, 0x07, 0x18, 0x65, 0x28, 0xab,
+ 0xd9, 0xed, 0x36, 0xc5, 0xb9, 0xad, 0xb7, 0xdc, 0xd6, 0x34, 0xfe, 0xdf, 0x54, 0xb7, 0x25, 0xc5,
+ 0x6d, 0x8c, 0x66, 0xdb, 0x97, 0xef, 0xde, 0xb1, 0x06, 0x7c, 0x06, 0x97, 0xd4, 0x2d, 0xfb, 0xcb,
+ 0x89, 0xbb, 0x6e, 0x82, 0xab, 0x80, 0x69, 0x84, 0x6c, 0xda, 0x14, 0x1f, 0x7f, 0x19, 0xee, 0x0c,
+ 0xf2, 0xd9, 0x3b, 0xe8, 0x87, 0x71, 0x3c, 0x73, 0xf6, 0xac, 0x60, 0xd6, 0x72, 0xf3, 0xf2, 0x7b,
+ 0xf7, 0xf6, 0x91, 0x1f, 0xc4, 0x70, 0xef, 0xd8, 0xb9, 0x53, 0xc8, 0x57, 0xae, 0x59, 0xb3, 0xc6,
+ 0xbb, 0x7b, 0xfb, 0xf6, 0xfd, 0x50, 0xaf, 0x6b, 0xe0, 0xec, 0xa5, 0xc4, 0x98, 0x48, 0xb4, 0x87,
+ 0xa9, 0x8d, 0xd5, 0x1e, 0x22, 0xc6, 0x04, 0x74, 0x97, 0x46, 0x55, 0x3d, 0x7e, 0xdc, 0x58, 0x4f,
+ 0xa8, 0x6c, 0xda, 0xbc, 0xb9, 0xb1, 0xb1, 0x49, 0xa5, 0xd6, 0xc0, 0xe6, 0xcf, 0x9a, 0x3d, 0xdb,
+ 0xf3, 0x3c, 0x9f, 0xfd, 0xf3, 0x9f, 0xa0, 0x2e, 0x7c, 0xc6, 0x8a, 0x0b, 0xf0, 0xca, 0x02, 0xcf,
+ 0x99, 0x33, 0xd7, 0xcd, 0xe7, 0xdf, 0xd5, 0x6a, 0x95, 0x64, 0x71, 0x2b, 0xce, 0x0f, 0x6b, 0x69,
+ 0xb3, 0x3b, 0x80, 0xf6, 0xc7, 0x8f, 0xcb, 0x24, 0x9a, 0x1d, 0x7f, 0x5d, 0xbc, 0x78, 0x71, 0xf8,
+ 0xd6, 0xad, 0xc2, 0x4e, 0xd4, 0x9e, 0x2d, 0x70, 0xc6, 0x0c, 0xcc, 0x44, 0x2f, 0xc4, 0xbe, 0x48,
+ 0x1f, 0x28, 0x95, 0xca, 0x09, 0x13, 0x26, 0x08, 0x67, 0x80, 0x49, 0x69, 0x6d, 0x6b, 0xeb, 0x5c,
+ 0x75, 0x40, 0x8f, 0xb1, 0xd9, 0xec, 0x81, 0x81, 0x81, 0xaf, 0x31, 0xe9, 0xf8, 0x13, 0x04, 0xf5,
+ 0xf5, 0xeb, 0xd7, 0x61, 0x5a, 0x8b, 0xee, 0x3f, 0xb8, 0x76, 0xed, 0x7a, 0x74, 0xf4, 0x79, 0x08,
+ 0xe1, 0xdc, 0xdb, 0xa9, 0x46, 0x79, 0x85, 0x4d, 0xdf, 0x16, 0xb1, 0xed, 0x5f, 0x6f, 0x91, 0x34,
+ 0x62, 0xc4, 0xc8, 0xac, 0x2c, 0x19, 0x21, 0xfc, 0x2a, 0x31, 0xca, 0x8b, 0xb4, 0x9c, 0x83, 0x2f,
+ 0x79, 0x35, 0x5c, 0x26, 0xfa, 0x18, 0xd6, 0x98, 0x48, 0x59, 0xbd, 0xb5, 0x21, 0x38, 0x78, 0x25,
+ 0xac, 0xfd, 0xfd, 0xfb, 0x45, 0x6e, 0xb7, 0x8b, 0x25, 0x7a, 0xd6, 0x59, 0xc7, 0x5a, 0xf3, 0x89,
+ 0x21, 0x8e, 0x68, 0x0f, 0xd2, 0xad, 0x21, 0xb4, 0x87, 0x69, 0x20, 0xcb, 0x7a, 0xd7, 0xcd, 0xb4,
+ 0x17, 0xe4, 0xcb, 0x24, 0x2b, 0xa9, 0x31, 0xac, 0xf3, 0xe6, 0xcd, 0xa9, 0xaf, 0xb9, 0x4f, 0xec,
+ 0xa5, 0xac, 0x29, 0x91, 0xd1, 0x44, 0x32, 0xed, 0xeb, 0x49, 0xdb, 0x72, 0xd2, 0xba, 0x80, 0x28,
+ 0x66, 0x13, 0xc5, 0x0c, 0x22, 0x9f, 0x46, 0x9a, 0xa7, 0xd2, 0x8d, 0x53, 0xea, 0x06, 0x46, 0x84,
+ 0x2f, 0x1c, 0x3d, 0x7a, 0x4c, 0xaf, 0x5e, 0xbd, 0xbb, 0x65, 0xe3, 0x23, 0x81, 0x12, 0xfc, 0xfd,
+ 0xef, 0xef, 0x82, 0xc4, 0xce, 0x9c, 0x39, 0x6b, 0xd7, 0xee, 0x9f, 0x53, 0x6f, 0xa5, 0xd5, 0xd6,
+ 0xd6, 0xf9, 0xcc, 0x83, 0x60, 0x9a, 0x08, 0xee, 0x1e, 0x2f, 0xd0, 0x4b, 0xef, 0x31, 0x7d, 0x8b,
+ 0x86, 0x41, 0xfe, 0x01, 0x33, 0x22, 0x2c, 0xfc, 0xfc, 0x7c, 0xdc, 0x38, 0xef, 0x93, 0x4c, 0x9f,
+ 0x36, 0x05, 0xfe, 0x08, 0x2a, 0xe0, 0x45, 0xe7, 0xc0, 0xc0, 0xea, 0x4e, 0xb2, 0xe6, 0x5b, 0x9c,
+ 0xb3, 0x3a, 0x25, 0x39, 0xbe, 0x9f, 0x07, 0x53, 0xc5, 0x77, 0x31, 0x37, 0xe7, 0xcf, 0xa7, 0x5b,
+ 0x2c, 0x7f, 0xfd, 0xf5, 0xd7, 0x92, 0x09, 0xf2, 0xc5, 0xc4, 0x89, 0x36, 0xbb, 0x1d, 0xf3, 0xa2,
+ 0xad, 0x5d, 0xe9, 0x9d, 0x4a, 0xa6, 0xe5, 0x04, 0x3c, 0x91, 0x2e, 0xba, 0x5f, 0x24, 0x59, 0x2a,
+ 0x88, 0xcb, 0xa6, 0x61, 0x52, 0x9a, 0x99, 0x73, 0xa7, 0xa7, 0xdf, 0x96, 0x14, 0x95, 0xc1, 0xbe,
+ 0xfd, 0xfc, 0xf3, 0x1e, 0xc8, 0x07, 0xef, 0x08, 0x2d, 0x44, 0x90, 0xd9, 0x6c, 0x91, 0xa4, 0x5c,
+ 0x45, 0x56, 0x50, 0x52, 0x5a, 0xfa, 0xe9, 0xa7, 0x54, 0xc1, 0xe1, 0x84, 0x50, 0xaf, 0x42, 0xe1,
+ 0x96, 0xb8, 0xb3, 0x81, 0xd0, 0x69, 0x10, 0x08, 0x3e, 0x17, 0xd1, 0x0b, 0x0d, 0x60, 0xf3, 0xf7,
+ 0x1f, 0x7d, 0xeb, 0x56, 0x5a, 0x4b, 0x6b, 0xdb, 0xc3, 0xe2, 0x92, 0xc4, 0xc4, 0xa4, 0x43, 0x87,
+ 0x0e, 0xff, 0x14, 0xb1, 0x7d, 0xfb, 0x8e, 0x1d, 0x99, 0x49, 0xb1, 0xba, 0xda, 0x07, 0xda, 0x96,
+ 0xda, 0x0d, 0x1e, 0x94, 0xd2, 0xbb, 0xe1, 0xa7, 0xbf, 0xfa, 0xea, 0x2b, 0x08, 0x1f, 0xa0, 0x95,
+ 0xa7, 0x52, 0x44, 0xa3, 0x69, 0x6f, 0x6a, 0xac, 0xb0, 0x1a, 0xab, 0x58, 0xeb, 0x5d, 0x62, 0xba,
+ 0xca, 0x1a, 0x2e, 0xb1, 0xa6, 0x1b, 0x9c, 0xed, 0xfe, 0xd3, 0xf2, 0x9c, 0xb0, 0xd0, 0x90, 0xaa,
+ 0xaa, 0xa7, 0x7c, 0x82, 0xd2, 0x01, 0xe6, 0xc0, 0x23, 0x36, 0x8f, 0x1a, 0x58, 0xcd, 0x7e, 0x46,
+ 0xb5, 0x13, 0xff, 0xb2, 0x86, 0x38, 0xd6, 0x5a, 0x40, 0x9c, 0xad, 0xc9, 0x37, 0x12, 0xbd, 0xe3,
+ 0x9c, 0x30, 0x68, 0xab, 0x57, 0x2d, 0x6b, 0x6f, 0x29, 0x83, 0xfa, 0x60, 0xf5, 0x17, 0x19, 0x1a,
+ 0xa4, 0x5d, 0xc9, 0xc8, 0xbf, 0x76, 0x35, 0x4e, 0x70, 0xd1, 0xc2, 0x03, 0x3f, 0xba, 0xb1, 0x0f,
+ 0xdd, 0xf8, 0xa8, 0x77, 0xf8, 0xe6, 0x6f, 0xfd, 0xfd, 0xfd, 0x7b, 0xf6, 0xec, 0x9e, 0xad, 0xba,
+ 0x5e, 0x3e, 0x41, 0xe3, 0x7d, 0xe8, 0x65, 0x78, 0xfc, 0xa3, 0x47, 0x8f, 0xe5, 0xe5, 0x83, 0x15,
+ 0x16, 0xfa, 0xcc, 0x77, 0x0f, 0x1d, 0x3a, 0xd4, 0xe1, 0x70, 0xba, 0x69, 0x12, 0x9f, 0x5b, 0xbc,
+ 0x64, 0x89, 0x4f, 0xf7, 0xf4, 0xc9, 0xc0, 0x81, 0xb4, 0xd2, 0xbb, 0xe3, 0x59, 0x49, 0x49, 0x89,
+ 0x77, 0xd1, 0x3e, 0xda, 0xfe, 0xa8, 0x3d, 0x1c, 0x23, 0x07, 0x07, 0xa0, 0x9d, 0xa3, 0x3d, 0x42,
+ 0xe7, 0x32, 0xfc, 0x94, 0x35, 0xdf, 0x69, 0x6b, 0x08, 0x0b, 0xdd, 0xd0, 0xc5, 0xad, 0xbd, 0xe8,
+ 0x12, 0xad, 0xff, 0x6b, 0xef, 0x3b, 0xc0, 0xa2, 0xba, 0xd6, 0x76, 0xef, 0xf3, 0xdf, 0xfb, 0x9f,
+ 0xfc, 0xf7, 0x9c, 0x93, 0xe4, 0xc4, 0xc4, 0x24, 0xf6, 0xae, 0x51, 0xda, 0x0c, 0x88, 0x80, 0x18,
+ 0xb1, 0xc6, 0xde, 0x42, 0x11, 0x1b, 0x22, 0x22, 0x28, 0x4d, 0x69, 0x02, 0xa2, 0xc4, 0x8a, 0x20,
+ 0x60, 0x17, 0x1b, 0x52, 0x14, 0x05, 0x11, 0x91, 0x5e, 0xa5, 0xf7, 0xde, 0x19, 0x7a, 0xef, 0x33,
+ 0xc0, 0x30, 0xc3, 0x34, 0x92, 0xe7, 0x3e, 0xf7, 0xdd, 0x7b, 0xcb, 0x88, 0x33, 0x68, 0x6c, 0x49,
+ 0x4e, 0x9e, 0x93, 0xef, 0x59, 0x31, 0xcc, 0xec, 0x32, 0x7b, 0xaf, 0xf5, 0xae, 0xf7, 0x7b, 0xbf,
+ 0x55, 0x77, 0xec, 0x20, 0x91, 0x40, 0xb4, 0xc4, 0x4a, 0x8c, 0xbd, 0x47, 0xd1, 0xe7, 0xe6, 0xe5,
+ 0x51, 0x41, 0x99, 0xff, 0xc3, 0x87, 0x12, 0x63, 0x45, 0x00, 0xbc, 0x9c, 0x9c, 0x1c, 0x1c, 0xe2,
+ 0x70, 0x87, 0x5c, 0x5d, 0x5d, 0x25, 0xee, 0x8c, 0xb0, 0x11, 0x50, 0x81, 0x42, 0x1e, 0x1d, 0xe5,
+ 0x51, 0x06, 0x61, 0x8f, 0x48, 0xed, 0x15, 0xc4, 0xbe, 0x5c, 0x84, 0xf3, 0x97, 0xf0, 0xf0, 0x08,
+ 0x04, 0x17, 0x9f, 0x90, 0x23, 0xf9, 0xe3, 0xe2, 0xe3, 0x47, 0xd6, 0x87, 0xff, 0x45, 0x0c, 0x57,
+ 0xe8, 0xa8, 0x31, 0x47, 0x2f, 0x50, 0x06, 0x3d, 0xb9, 0x7e, 0xfd, 0xfa, 0xe7, 0xcf, 0x13, 0x7b,
+ 0x7a, 0x7b, 0x6b, 0xeb, 0xea, 0x63, 0xe3, 0xe2, 0x3d, 0x3d, 0x6f, 0xda, 0xd9, 0xdb, 0x1b, 0x1b,
+ 0x1f, 0x34, 0x35, 0x33, 0x4b, 0x7c, 0xe8, 0xd9, 0x5d, 0x91, 0xda, 0x5c, 0x5d, 0x78, 0xc0, 0xf0,
+ 0xb5, 0x0b, 0xce, 0xe0, 0x0e, 0xa8, 0xdb, 0xe4, 0x18, 0xc8, 0x61, 0xf2, 0xdd, 0x87, 0x23, 0x22,
+ 0x22, 0x0e, 0x1d, 0x3a, 0xa8, 0xa3, 0xa3, 0x15, 0xfc, 0xe4, 0x1e, 0x87, 0x95, 0x45, 0xc8, 0x4e,
+ 0x48, 0x59, 0xf8, 0xf1, 0xc1, 0xf4, 0xa6, 0xba, 0xcc, 0xee, 0xae, 0x46, 0xb2, 0x27, 0x9d, 0xec,
+ 0x52, 0x17, 0xf6, 0x11, 0x52, 0x9f, 0x93, 0x47, 0xb4, 0x37, 0x42, 0xaa, 0x75, 0x5d, 0x20, 0x06,
+ 0xd5, 0x23, 0x40, 0x1b, 0xcc, 0xe9, 0x63, 0xd6, 0xd9, 0xda, 0x8e, 0xb1, 0xdf, 0x13, 0xf8, 0x64,
+ 0xc5, 0x8a, 0xe5, 0x15, 0xe5, 0xf9, 0x08, 0x10, 0x20, 0x92, 0x11, 0xd3, 0xf1, 0x3b, 0x4f, 0xf3,
+ 0x5b, 0x8c, 0xf9, 0x0d, 0x5b, 0x79, 0xb5, 0x1a, 0xc4, 0xca, 0x7e, 0x04, 0x62, 0xe7, 0x0d, 0x55,
+ 0x4c, 0xb2, 0x32, 0xdf, 0xb6, 0x70, 0xe1, 0x42, 0x84, 0x24, 0x1f, 0x45, 0xc7, 0x8e, 0xde, 0x6d,
+ 0xf3, 0xc8, 0x11, 0x4b, 0x5f, 0x5f, 0xbf, 0xfc, 0x82, 0x02, 0xaf, 0x7b, 0xf7, 0xc6, 0xec, 0xb6,
+ 0x33, 0x32, 0x32, 0xa2, 0x06, 0xd4, 0xb5, 0xb6, 0xb6, 0x51, 0x1e, 0x50, 0xfa, 0x2d, 0x36, 0x6e,
+ 0xdc, 0x08, 0x7f, 0x04, 0x20, 0x79, 0x7b, 0x7b, 0x8f, 0x39, 0x89, 0x23, 0x33, 0x23, 0x51, 0xc4,
+ 0xab, 0x17, 0x0e, 0x24, 0x0b, 0x99, 0x54, 0x20, 0xe0, 0x45, 0xc4, 0x5c, 0x9c, 0xa2, 0xaa, 0x8a,
+ 0xac, 0xf5, 0xeb, 0xdf, 0x76, 0xc2, 0x0b, 0x4a, 0xc7, 0xda, 0xda, 0x9a, 0x7a, 0x18, 0x50, 0xa2,
+ 0x84, 0xe4, 0x86, 0xbf, 0x68, 0xef, 0x20, 0xc6, 0x69, 0xf3, 0x78, 0xfc, 0x33, 0x67, 0xce, 0x48,
+ 0x0c, 0x8d, 0x40, 0x00, 0xde, 0xd8, 0xd4, 0x8c, 0xa3, 0x4c, 0x56, 0xdf, 0xf6, 0xed, 0xdb, 0x25,
+ 0xee, 0x0c, 0x42, 0x2e, 0x2e, 0x2e, 0x49, 0x4b, 0x4f, 0x97, 0x93, 0xaa, 0xb3, 0xa8, 0x26, 0x0d,
+ 0xe4, 0x24, 0x44, 0xf1, 0x74, 0xad, 0x11, 0x49, 0x40, 0x84, 0x54, 0xb7, 0xef, 0xdc, 0xa1, 0x62,
+ 0x55, 0x75, 0x75, 0xf5, 0x7e, 0x6a, 0x2b, 0xae, 0x57, 0xb7, 0x38, 0x4c, 0x4a, 0x4e, 0x46, 0x6c,
+ 0x3b, 0xe6, 0xeb, 0xe0, 0x09, 0xb5, 0xb4, 0xb4, 0x72, 0x73, 0xf3, 0x38, 0x1c, 0x6e, 0x2f, 0x93,
+ 0x49, 0xcc, 0x05, 0x8e, 0x8c, 0x82, 0x17, 0x83, 0x72, 0x86, 0x7f, 0x81, 0x4a, 0xc9, 0x0c, 0xbc,
+ 0xda, 0x5d, 0x9e, 0x58, 0x53, 0x9a, 0xb5, 0x43, 0x57, 0x67, 0xcc, 0x3b, 0xe0, 0xd9, 0x8e, 0x58,
+ 0x5a, 0xd6, 0xd6, 0xd6, 0x91, 0xdc, 0xfe, 0x33, 0x8f, 0x2f, 0xf0, 0xf1, 0xf5, 0x05, 0x63, 0x50,
+ 0x3e, 0xce, 0xc1, 0xfe, 0x08, 0xab, 0x33, 0x03, 0xf9, 0x4c, 0x70, 0x2c, 0x2b, 0x50, 0x40, 0xcc,
+ 0xa9, 0xaf, 0x22, 0x22, 0x32, 0x21, 0xa4, 0x3e, 0x4c, 0xd0, 0xd8, 0x50, 0xf3, 0xe8, 0xa1, 0x57,
+ 0x69, 0x61, 0x34, 0xbf, 0xff, 0xb9, 0x80, 0xe9, 0x4f, 0x14, 0x0a, 0x21, 0x77, 0x63, 0x84, 0xdc,
+ 0xf2, 0x86, 0xfa, 0x52, 0x05, 0x05, 0xc9, 0xac, 0x00, 0x59, 0x11, 0xcb, 0x24, 0xc6, 0x44, 0x73,
+ 0x38, 0x2c, 0x91, 0x80, 0x54, 0x1d, 0x6c, 0x5c, 0xe8, 0x33, 0x02, 0xda, 0xcd, 0xbc, 0xda, 0xa5,
+ 0xc4, 0x44, 0x1b, 0xc6, 0xdc, 0x8c, 0xa7, 0xea, 0x3b, 0xb7, 0x6f, 0x80, 0xd4, 0xf9, 0x28, 0x6b,
+ 0xc8, 0x88, 0xdb, 0xb5, 0xe0, 0x55, 0x37, 0x6c, 0xdc, 0x78, 0xc2, 0xc9, 0xe9, 0x69, 0x48, 0x08,
+ 0x42, 0x69, 0x3b, 0x3b, 0xbb, 0x31, 0x57, 0xd9, 0xf5, 0xbb, 0x7f, 0xff, 0xe7, 0x91, 0xcc, 0x1f,
+ 0x73, 0x76, 0x2d, 0xf2, 0x4d, 0x2c, 0x62, 0xad, 0x6d, 0x6c, 0xa4, 0x1b, 0x0f, 0x51, 0xd1, 0x58,
+ 0xcc, 0x36, 0xa2, 0x13, 0x8a, 0x98, 0xac, 0x1d, 0x0e, 0x29, 0x0b, 0x27, 0x25, 0x24, 0xc4, 0x52,
+ 0xfd, 0x93, 0xa0, 0xfb, 0x33, 0xa5, 0x46, 0xa8, 0xbe, 0xce, 0x00, 0x51, 0x6a, 0xbd, 0x35, 0x3e,
+ 0x5f, 0x00, 0xb2, 0x95, 0x50, 0x86, 0x10, 0x12, 0x2c, 0xb2, 0x2f, 0x0c, 0x82, 0x41, 0x5f, 0x5f,
+ 0x7f, 0xf4, 0x21, 0x72, 0x99, 0x82, 0x13, 0xf0, 0x14, 0x38, 0x0a, 0x54, 0xcf, 0x7e, 0x75, 0x67,
+ 0x79, 0x1c, 0xdd, 0xb2, 0x65, 0x0b, 0xc4, 0x46, 0x45, 0x65, 0xd5, 0x98, 0x8d, 0xb4, 0xf0, 0x3e,
+ 0xa3, 0x46, 0x68, 0xff, 0xbf, 0xd1, 0x23, 0x5b, 0xe0, 0xbb, 0x29, 0xfe, 0x44, 0x84, 0x48, 0x61,
+ 0x78, 0x34, 0xc1, 0x72, 0xb8, 0x5c, 0x7c, 0xff, 0xba, 0xd6, 0xd4, 0xdd, 0xbb, 0xf7, 0x20, 0xc0,
+ 0x14, 0x08, 0x85, 0x43, 0x3c, 0x3e, 0x9e, 0xbc, 0xbe, 0xa1, 0x31, 0xe1, 0x79, 0xa2, 0xe7, 0xcd,
+ 0x9b, 0x08, 0x2b, 0xf6, 0xed, 0xdb, 0x77, 0xc8, 0xd8, 0xa8, 0x20, 0xf8, 0x5a, 0x4f, 0x45, 0x62,
+ 0x45, 0x61, 0xda, 0xb6, 0xad, 0x63, 0xb4, 0x6e, 0xc1, 0x31, 0x1d, 0x3f, 0x71, 0xa2, 0xb3, 0xb3,
+ 0x8b, 0x82, 0x2b, 0x7b, 0x90, 0xe3, 0xe6, 0xe6, 0x2e, 0x96, 0x1f, 0x08, 0x75, 0x7d, 0x7d, 0xae,
+ 0xf1, 0xd8, 0x79, 0x44, 0x56, 0x43, 0xc7, 0x42, 0x8c, 0xf5, 0x47, 0x0b, 0xb9, 0x25, 0x22, 0x7e,
+ 0xc7, 0xb0, 0x08, 0xa1, 0x24, 0x37, 0x34, 0x34, 0x74, 0xcd, 0x9a, 0x35, 0x60, 0xad, 0x6b, 0x57,
+ 0x5c, 0xf8, 0xec, 0x7c, 0xe1, 0x40, 0x34, 0xc1, 0xc3, 0xfd, 0x11, 0x28, 0x23, 0x11, 0xbf, 0x29,
+ 0x28, 0xc8, 0x5f, 0xc2, 0x99, 0xa2, 0x7e, 0xfd, 0xf8, 0xe3, 0x8f, 0x05, 0x85, 0x05, 0xe4, 0x1c,
+ 0x5e, 0xc1, 0xb0, 0x68, 0x90, 0x3f, 0xd4, 0x81, 0x2a, 0x20, 0x64, 0x27, 0x92, 0xa0, 0x3d, 0x45,
+ 0xce, 0xe2, 0xdf, 0xc4, 0xab, 0x55, 0x1d, 0x28, 0x9a, 0x7f, 0xe1, 0xc4, 0xfa, 0x65, 0xcb, 0x34,
+ 0x10, 0x08, 0x53, 0x0b, 0x27, 0x7e, 0x20, 0xc1, 0x8a, 0x47, 0x71, 0x43, 0x03, 0xe8, 0xe8, 0x6c,
+ 0xbf, 0x70, 0xc1, 0x2d, 0x2e, 0x2e, 0xbe, 0xac, 0xac, 0x0c, 0xf5, 0x5d, 0x5a, 0x7f, 0xe2, 0x9b,
+ 0xd2, 0xd2, 0xb2, 0xbe, 0xbe, 0x7e, 0xa4, 0xcb, 0x57, 0xae, 0x88, 0x9b, 0xca, 0x47, 0x1b, 0x9e,
+ 0x2a, 0x31, 0x31, 0x69, 0x98, 0x5c, 0x5c, 0x65, 0xeb, 0x58, 0x8b, 0xf9, 0x00, 0x0f, 0x43, 0x43,
+ 0x2c, 0x11, 0xbf, 0x5d, 0x88, 0x5a, 0x39, 0x98, 0x25, 0x60, 0xa7, 0x12, 0xd0, 0x1d, 0x62, 0xf4,
+ 0x31, 0x1b, 0xec, 0xec, 0x6c, 0xde, 0xbe, 0x1b, 0xe8, 0xeb, 0xaf, 0xbf, 0x26, 0xda, 0xe7, 0x7f,
+ 0xfe, 0xa5, 0xba, 0xba, 0x06, 0x5a, 0x57, 0xe2, 0xe8, 0xd5, 0x6b, 0xd7, 0x50, 0xf4, 0xc0, 0x64,
+ 0x5e, 0x7e, 0xc1, 0xe2, 0x51, 0x63, 0xbd, 0x3e, 0x21, 0x3d, 0x3b, 0xc8, 0x87, 0x6a, 0x61, 0x00,
+ 0x91, 0x4a, 0xfc, 0x22, 0xb9, 0x46, 0x0a, 0xb1, 0xec, 0x46, 0x77, 0x4f, 0xcf, 0x98, 0x6d, 0x50,
+ 0x7e, 0x7e, 0xf7, 0x29, 0xda, 0x1c, 0x99, 0x54, 0xf0, 0x22, 0xec, 0x62, 0xb1, 0xfa, 0xa8, 0x9e,
+ 0x23, 0xd4, 0xd9, 0x4a, 0x72, 0xa5, 0x4d, 0xf1, 0x52, 0x33, 0x14, 0x62, 0x8b, 0x4b, 0x4a, 0x56,
+ 0xac, 0x58, 0x21, 0x7d, 0x43, 0x80, 0x0d, 0xf1, 0x29, 0x55, 0xbf, 0x20, 0x3d, 0xb9, 0x43, 0x3c,
+ 0x68, 0x2a, 0xd4, 0x0b, 0x9c, 0x1f, 0x14, 0xf4, 0xc4, 0xd9, 0xf9, 0x3c, 0x1c, 0xdf, 0x99, 0x63,
+ 0x36, 0x65, 0xe1, 0xb7, 0x7a, 0xab, 0x92, 0x8a, 0x73, 0x13, 0xd7, 0xbf, 0x3a, 0xef, 0x12, 0x55,
+ 0x75, 0xea, 0xb4, 0x69, 0xd7, 0xaf, 0xdf, 0x20, 0xe7, 0xef, 0x10, 0x4a, 0xa0, 0xbd, 0xbd, 0xc3,
+ 0xd6, 0xf6, 0xe8, 0x37, 0xdf, 0x7c, 0x23, 0xde, 0x07, 0x41, 0x57, 0x57, 0xab, 0xb1, 0x2e, 0x97,
+ 0x1c, 0x12, 0xf0, 0x98, 0x68, 0x93, 0x01, 0x62, 0x07, 0x08, 0xc4, 0x0e, 0xf3, 0xbb, 0x7a, 0xba,
+ 0xdb, 0xec, 0xed, 0xed, 0x71, 0x32, 0x4e, 0xc3, 0x93, 0xc7, 0x44, 0x05, 0x0b, 0xb9, 0x0c, 0xc1,
+ 0x60, 0x86, 0x70, 0x20, 0x89, 0x98, 0xe0, 0x3c, 0x54, 0x39, 0x2c, 0xe8, 0xd1, 0xd4, 0x7c, 0x65,
+ 0x38, 0x10, 0xb2, 0xc8, 0xc4, 0xc4, 0xa4, 0xb3, 0xab, 0x9b, 0xec, 0x6d, 0x1c, 0x16, 0x08, 0x05,
+ 0x95, 0x95, 0xe5, 0x9a, 0x9a, 0xdb, 0x7c, 0xee, 0xdd, 0xe0, 0x0f, 0x32, 0x88, 0xd8, 0x8d, 0xe5,
+ 0xc7, 0xef, 0x3c, 0xc9, 0x6f, 0xde, 0xd7, 0x5f, 0xbe, 0xe6, 0xc1, 0x75, 0x44, 0xbd, 0x9b, 0xe5,
+ 0xe4, 0xe4, 0x28, 0x19, 0xfc, 0xe1, 0x92, 0x80, 0x9a, 0x8a, 0x48, 0x89, 0x58, 0x7d, 0xfd, 0x7d,
+ 0x37, 0x6e, 0x78, 0xa6, 0x67, 0x64, 0xc4, 0xc6, 0xc6, 0x2d, 0x5e, 0xbc, 0x58, 0x3a, 0x6f, 0xf1,
+ 0x52, 0xb2, 0x10, 0xa9, 0x72, 0xf2, 0x48, 0x28, 0xf7, 0x31, 0xd1, 0x05, 0x0a, 0xa5, 0xfa, 0xa7,
+ 0x20, 0x85, 0xc7, 0x1c, 0x98, 0x74, 0xe1, 0xc2, 0x05, 0x81, 0x80, 0x4b, 0xaa, 0xa6, 0x0e, 0x11,
+ 0xaf, 0x49, 0x08, 0x79, 0xc0, 0x6b, 0x44, 0x7c, 0x50, 0x5c, 0x9c, 0xf3, 0x36, 0xad, 0x94, 0x62,
+ 0x9b, 0x38, 0x71, 0x52, 0x4e, 0x4e, 0x2e, 0x35, 0x9a, 0x8b, 0x52, 0x8f, 0x62, 0x43, 0x05, 0x84,
+ 0x0b, 0xa0, 0xc6, 0x91, 0x86, 0x87, 0x87, 0x4b, 0xf4, 0x0e, 0x40, 0xc4, 0xa6, 0xa5, 0x67, 0x50,
+ 0x88, 0x95, 0x5e, 0xfe, 0x1d, 0xef, 0x15, 0x42, 0x86, 0x8d, 0x54, 0xfb, 0x83, 0xf4, 0x3b, 0x9e,
+ 0x3a, 0x7d, 0xfa, 0xe5, 0xc8, 0xd8, 0x91, 0x39, 0xb0, 0xf8, 0x58, 0x51, 0x59, 0x49, 0x8d, 0x1a,
+ 0x42, 0xd6, 0xfd, 0x32, 0xb2, 0xb4, 0x8b, 0x18, 0xb1, 0xb8, 0x5b, 0x40, 0x60, 0xa0, 0x74, 0xdf,
+ 0xfd, 0xdc, 0xb9, 0x73, 0x2f, 0x5d, 0xbe, 0x3c, 0x30, 0xc0, 0xa6, 0x46, 0xd5, 0x42, 0xa5, 0x3c,
+ 0x7d, 0xfa, 0x54, 0x45, 0x45, 0x05, 0xe5, 0x5b, 0x58, 0x58, 0x08, 0xdc, 0xde, 0xf3, 0xf6, 0x3e,
+ 0x73, 0xf6, 0xac, 0xef, 0x15, 0xe7, 0x9a, 0x78, 0x1f, 0x26, 0x23, 0xb9, 0x34, 0x3f, 0x69, 0xd3,
+ 0xc6, 0x97, 0xad, 0x22, 0x60, 0x6c, 0x64, 0xda, 0xd3, 0xa7, 0x21, 0x43, 0xe4, 0x56, 0xe0, 0xa0,
+ 0x68, 0xc4, 0xc5, 0xfb, 0x0c, 0x0c, 0x46, 0xb7, 0x9d, 0xca, 0xc8, 0x2c, 0x08, 0x0b, 0x0d, 0x18,
+ 0xe6, 0xd5, 0x12, 0x81, 0x03, 0x3c, 0x1a, 0xd3, 0x8f, 0x6c, 0x2b, 0x48, 0x12, 0xf1, 0xaa, 0x9b,
+ 0x1b, 0x2b, 0x76, 0xec, 0x78, 0x39, 0x41, 0x4f, 0x45, 0x65, 0x51, 0x6d, 0x4d, 0xb1, 0x90, 0x47,
+ 0xf6, 0xb6, 0x0c, 0xe6, 0x09, 0xb9, 0xa5, 0x22, 0x7e, 0x4b, 0x53, 0x13, 0x43, 0xec, 0x17, 0x70,
+ 0xb7, 0x19, 0x33, 0x66, 0x9c, 0x73, 0x76, 0xa6, 0x66, 0x5c, 0x8a, 0xc8, 0x49, 0xa9, 0x50, 0xec,
+ 0xd4, 0x28, 0x1a, 0x59, 0x59, 0x99, 0xa0, 0x40, 0x5f, 0x6e, 0x7f, 0x25, 0x82, 0x35, 0x7e, 0x8f,
+ 0x57, 0x7b, 0xc5, 0xc9, 0x10, 0xbf, 0xa3, 0x86, 0x86, 0x07, 0x34, 0x34, 0x34, 0xa0, 0x30, 0x3f,
+ 0xd6, 0x24, 0x71, 0x6a, 0x14, 0x37, 0x39, 0x15, 0xf1, 0x7b, 0x04, 0x05, 0xde, 0xde, 0x3e, 0xf9,
+ 0x05, 0x85, 0xc8, 0xa5, 0x37, 0xc4, 0xb3, 0x6f, 0xb6, 0x75, 0xeb, 0xd6, 0x53, 0xf4, 0xe2, 0xeb,
+ 0xeb, 0x3b, 0x66, 0x07, 0x84, 0xa5, 0x25, 0xa4, 0xb2, 0xb7, 0xaf, 0x8f, 0x97, 0xaf, 0xcf, 0x9d,
+ 0xfb, 0x7e, 0xb7, 0x1b, 0x1b, 0xca, 0x45, 0x82, 0x3e, 0x3e, 0x7f, 0x20, 0x28, 0x28, 0x60, 0xf4,
+ 0x58, 0x02, 0x94, 0x26, 0x9e, 0x61, 0xe5, 0xca, 0x55, 0x64, 0x5a, 0xa9, 0xfe, 0x2a, 0x4f, 0x7e,
+ 0x42, 0xb6, 0x48, 0xb4, 0xb5, 0xb5, 0x03, 0x93, 0x70, 0x7f, 0xe2, 0x6e, 0x26, 0xf1, 0xa1, 0x33,
+ 0x67, 0xce, 0xfa, 0xf9, 0xf9, 0x79, 0xfb, 0xf8, 0x40, 0x78, 0x4b, 0x5c, 0x08, 0x92, 0x87, 0x08,
+ 0xa7, 0x10, 0x2b, 0xbd, 0x1e, 0x11, 0xd4, 0x51, 0x43, 0x43, 0x23, 0xd5, 0x7c, 0x07, 0x01, 0x29,
+ 0x1d, 0x5a, 0x82, 0x48, 0xa9, 0x17, 0xfc, 0xe5, 0xd5, 0x7e, 0x01, 0xd4, 0x11, 0xaa, 0xe3, 0xf5,
+ 0xbc, 0x8b, 0xcb, 0xcf, 0x2f, 0xe7, 0xcf, 0xbe, 0x20, 0x58, 0x48, 0x53, 0x0b, 0x8b, 0x57, 0x7a,
+ 0xab, 0x71, 0x67, 0xd4, 0x9d, 0x87, 0x0f, 0x1f, 0xa1, 0xd0, 0x89, 0x45, 0x75, 0x84, 0xa2, 0xca,
+ 0xaa, 0x2a, 0xe8, 0x0a, 0x71, 0xce, 0x7b, 0x7a, 0x7a, 0x96, 0x95, 0x57, 0xa0, 0x3e, 0x5e, 0xbf,
+ 0xe1, 0x19, 0xe7, 0xef, 0xd9, 0x98, 0xec, 0xcf, 0xac, 0x4e, 0x6c, 0xad, 0xc9, 0x33, 0x33, 0x31,
+ 0xc6, 0xb5, 0xe0, 0xc3, 0xf9, 0xf3, 0xe7, 0x83, 0x9c, 0xa9, 0xc1, 0x96, 0xc3, 0xa4, 0x62, 0x47,
+ 0xf5, 0x5c, 0xb5, 0x6a, 0xd5, 0xe8, 0x5a, 0x36, 0x6e, 0xdc, 0x17, 0x27, 0x4e, 0x1c, 0x1b, 0x64,
+ 0xb7, 0x88, 0xb8, 0xe5, 0xc2, 0x81, 0xe7, 0x82, 0xbe, 0x10, 0x41, 0x5f, 0xb0, 0x70, 0x20, 0x56,
+ 0xc8, 0x29, 0xaa, 0x2c, 0x4b, 0xd3, 0xd3, 0xdb, 0x29, 0x7e, 0x41, 0x5c, 0x75, 0xcc, 0xc1, 0x0e,
+ 0x9e, 0x8e, 0x58, 0x51, 0x8a, 0x53, 0x4c, 0x24, 0x5e, 0xad, 0x48, 0xd8, 0xe3, 0xee, 0xee, 0x42,
+ 0x9d, 0x00, 0xc8, 0x2d, 0x5e, 0xac, 0xfe, 0x28, 0x20, 0x60, 0x68, 0x88, 0x47, 0x85, 0x0f, 0x3d,
+ 0x3d, 0xbd, 0x77, 0xef, 0x7a, 0xe1, 0x31, 0xc4, 0xbf, 0xa8, 0xb2, 0x48, 0x39, 0x3a, 0xf2, 0x09,
+ 0xb7, 0xbf, 0xaa, 0xbb, 0x2d, 0x25, 0x36, 0x9a, 0x58, 0x2f, 0x71, 0xdf, 0x3e, 0x03, 0x94, 0x1d,
+ 0xb5, 0xa0, 0xf7, 0x47, 0x41, 0x2c, 0x35, 0x9c, 0x60, 0xe6, 0xcc, 0x99, 0x00, 0x86, 0xa5, 0x95,
+ 0x55, 0x40, 0x40, 0x20, 0x82, 0x0e, 0xe4, 0xdb, 0xbb, 0x76, 0x5e, 0x53, 0x86, 0x0a, 0xf8, 0xf0,
+ 0xd1, 0x23, 0xe4, 0x3f, 0x54, 0xa2, 0x93, 0x93, 0xd3, 0xaf, 0x8e, 0x86, 0x82, 0xae, 0x88, 0x8b,
+ 0x8b, 0x11, 0x89, 0xf8, 0x4c, 0x66, 0x8f, 0xb9, 0xb9, 0xf9, 0xe8, 0x43, 0x00, 0xa1, 0xe3, 0xf1,
+ 0xe3, 0x15, 0x15, 0x95, 0xe5, 0xe5, 0x15, 0xe5, 0x15, 0x95, 0xf0, 0x8f, 0x12, 0xd7, 0xa2, 0x5e,
+ 0xf3, 0x05, 0x82, 0xfe, 0x01, 0x36, 0x2a, 0xda, 0xdb, 0x6b, 0x09, 0xbc, 0xac, 0xc5, 0xe1, 0xc3,
+ 0x7c, 0x04, 0x86, 0x64, 0x97, 0x84, 0x74, 0xfb, 0x15, 0xe4, 0x9c, 0x90, 0x6c, 0x17, 0xc2, 0x5b,
+ 0xd8, 0x8e, 0x35, 0xdc, 0x1a, 0xe1, 0xc6, 0x88, 0xc7, 0x7f, 0xb9, 0xcb, 0x06, 0x3e, 0x06, 0x06,
+ 0x06, 0xc2, 0xbf, 0xe0, 0xb1, 0xb3, 0xb3, 0x73, 0x5e, 0xce, 0xf8, 0x1e, 0x91, 0x04, 0x55, 0x0c,
+ 0xc6, 0xe8, 0xb6, 0x17, 0xe4, 0x0c, 0xaa, 0x61, 0x74, 0x74, 0x0c, 0x55, 0xfa, 0x60, 0xc8, 0xa0,
+ 0x27, 0x4f, 0x50, 0x95, 0x46, 0xc7, 0x0e, 0x08, 0x09, 0x9b, 0x9b, 0x5b, 0x52, 0x52, 0xd3, 0x1e,
+ 0xf8, 0xfb, 0xe7, 0x84, 0xf9, 0x35, 0xa7, 0x05, 0x30, 0xab, 0xe2, 0x06, 0x3b, 0x4b, 0xd3, 0x53,
+ 0xa2, 0x4f, 0x9d, 0x3c, 0x71, 0xf6, 0xec, 0xe9, 0xb0, 0xf0, 0x30, 0x32, 0xbe, 0xfb, 0x99, 0xd4,
+ 0x30, 0xbd, 0xd7, 0xaf, 0x5f, 0x97, 0x5e, 0x88, 0x63, 0xdd, 0xba, 0xb5, 0x8d, 0x8d, 0x0c, 0x72,
+ 0x64, 0x45, 0x09, 0xfc, 0x35, 0x81, 0x55, 0x76, 0xa2, 0x88, 0x53, 0x50, 0x52, 0x98, 0xb0, 0x67,
+ 0xb7, 0xee, 0x17, 0xa3, 0x7a, 0x6a, 0xa6, 0x4e, 0x9d, 0x12, 0x1e, 0x16, 0x24, 0xe0, 0xb5, 0x12,
+ 0x63, 0x30, 0xc0, 0xb1, 0x20, 0x58, 0x5e, 0x63, 0x1f, 0xab, 0x05, 0x12, 0xf4, 0x13, 0x32, 0x6a,
+ 0xd0, 0xd1, 0xd1, 0x49, 0x49, 0x49, 0xa5, 0xb4, 0x16, 0x52, 0x4b, 0x6b, 0xdb, 0xa9, 0x53, 0xa7,
+ 0x25, 0x86, 0xbb, 0xa3, 0x20, 0x96, 0x2f, 0x5f, 0x96, 0x9e, 0x96, 0x84, 0xc0, 0x36, 0x31, 0x29,
+ 0xf9, 0x86, 0xa7, 0xa7, 0xa9, 0xa9, 0xd9, 0xea, 0xd5, 0xab, 0xe7, 0xcc, 0x99, 0x43, 0xf5, 0x0a,
+ 0x7d, 0xb8, 0x2a, 0x20, 0xc2, 0x2e, 0x62, 0x3d, 0x8d, 0x79, 0x1b, 0x36, 0x6c, 0x38, 0x76, 0xcc,
+ 0x11, 0x35, 0x1a, 0x19, 0x2e, 0x11, 0xaa, 0xbc, 0xa5, 0x21, 0x3c, 0xbf, 0x77, 0xcf, 0x6b, 0x80,
+ 0x0d, 0x3d, 0x36, 0xdc, 0xd8, 0xd4, 0xb4, 0x73, 0xd4, 0x20, 0xab, 0xd7, 0x19, 0xf4, 0x67, 0x71,
+ 0x71, 0x31, 0xd0, 0x51, 0x57, 0x5f, 0x2f, 0x91, 0xdb, 0x78, 0xc7, 0x8c, 0xcc, 0x4c, 0x4a, 0x98,
+ 0xe1, 0x5f, 0xe0, 0x41, 0xe2, 0x5a, 0x72, 0x01, 0x25, 0x62, 0x39, 0x8b, 0x03, 0x07, 0x0e, 0xbc,
+ 0x65, 0x1f, 0x2b, 0xb1, 0x1d, 0x9b, 0xcc, 0x82, 0xc8, 0xa8, 0x48, 0xea, 0x9e, 0x99, 0x99, 0x59,
+ 0xd2, 0x80, 0x74, 0x72, 0xfa, 0x49, 0xbc, 0xc0, 0x0b, 0x28, 0xe2, 0x8b, 0x2f, 0x24, 0x7b, 0xfd,
+ 0xa0, 0x40, 0x46, 0x35, 0xb4, 0xbe, 0xf0, 0xfb, 0xe0, 0x37, 0x0f, 0x0f, 0x0f, 0xe0, 0x70, 0xd5,
+ 0xea, 0xd5, 0xd4, 0xfc, 0xaf, 0x17, 0x53, 0x14, 0x45, 0x90, 0x79, 0x22, 0x94, 0x72, 0x40, 0x40,
+ 0xc0, 0x68, 0xba, 0x06, 0xb7, 0x83, 0x1b, 0x49, 0xdf, 0xfa, 0x33, 0x88, 0xd4, 0xda, 0xda, 0x5a,
+ 0xba, 0x3d, 0x19, 0x61, 0x3e, 0x94, 0x46, 0x61, 0x51, 0x71, 0x44, 0x78, 0x78, 0x69, 0xfc, 0xe3,
+ 0xd6, 0xcc, 0xc0, 0xde, 0x8a, 0xc8, 0xc1, 0xf6, 0x5c, 0xde, 0x40, 0x13, 0x87, 0xdd, 0xcd, 0xe7,
+ 0x73, 0xc9, 0x99, 0x40, 0x44, 0xcd, 0x2a, 0xaf, 0xa8, 0x00, 0xd9, 0x4a, 0x7b, 0x34, 0x48, 0x8b,
+ 0xb4, 0xb4, 0x14, 0x91, 0x68, 0x80, 0x18, 0x54, 0x80, 0xa8, 0x81, 0x93, 0x27, 0x1c, 0xcc, 0x11,
+ 0x72, 0xcb, 0xca, 0x8a, 0x93, 0x76, 0xe8, 0x6a, 0x49, 0x44, 0xd6, 0xdb, 0xb6, 0x6d, 0xa9, 0x61,
+ 0xe4, 0x93, 0x04, 0x9b, 0x43, 0x44, 0x16, 0x9c, 0x22, 0x11, 0xbf, 0x39, 0x3e, 0x2e, 0x02, 0x48,
+ 0xc6, 0x7d, 0x6c, 0x6d, 0x6d, 0x19, 0x8c, 0x6a, 0xaa, 0x8d, 0x97, 0x9a, 0xef, 0x6f, 0x6c, 0x6c,
+ 0x3c, 0xe6, 0x9a, 0x2a, 0x28, 0x0b, 0x14, 0x0d, 0x78, 0xa6, 0x88, 0xdc, 0x4a, 0x00, 0x61, 0x38,
+ 0x90, 0xa0, 0xaa, 0xaa, 0x0a, 0x72, 0xf8, 0xec, 0xf3, 0xcf, 0xff, 0xf6, 0xb7, 0xbf, 0x7d, 0x08,
+ 0x68, 0xc5, 0xc3, 0x09, 0xa0, 0x4b, 0x35, 0x35, 0x35, 0xe1, 0x49, 0xa1, 0x49, 0x62, 0x62, 0xe3,
+ 0xc6, 0x1c, 0x80, 0xfd, 0x66, 0x53, 0x54, 0xa4, 0x3f, 0x7d, 0x1a, 0xc4, 0x19, 0x64, 0x89, 0x84,
+ 0xc8, 0x49, 0x41, 0x4e, 0x4e, 0xb6, 0xf4, 0x00, 0x18, 0x69, 0x33, 0x30, 0x30, 0x40, 0x2c, 0x8f,
+ 0xc2, 0x05, 0xb7, 0x8f, 0x26, 0x64, 0xb2, 0xaa, 0x2e, 0xe7, 0x70, 0x39, 0xd4, 0xc4, 0x46, 0x14,
+ 0xcb, 0x4f, 0x52, 0xbb, 0xb7, 0x00, 0xa8, 0xf8, 0x1e, 0xb2, 0x3f, 0x26, 0x26, 0x66, 0xcc, 0xce,
+ 0x62, 0x69, 0x9b, 0x3d, 0x7b, 0x76, 0x5c, 0x5c, 0x2c, 0x87, 0xc3, 0x16, 0x89, 0x04, 0xc3, 0xc3,
+ 0xa2, 0x8b, 0x17, 0x2f, 0x4a, 0x3b, 0xfd, 0x98, 0xd8, 0x58, 0xf1, 0xf0, 0xc5, 0x07, 0x0f, 0x1e,
+ 0x48, 0x77, 0x91, 0xa0, 0x98, 0x98, 0x2c, 0xd6, 0xf0, 0xab, 0x6d, 0xad, 0x08, 0x43, 0x0e, 0x1e,
+ 0x24, 0xd6, 0x3a, 0x80, 0xca, 0x05, 0xed, 0x83, 0xc3, 0x41, 0xe0, 0x88, 0xdc, 0x6b, 0x6b, 0xeb,
+ 0xaa, 0x6b, 0x6a, 0xdb, 0x3b, 0x3a, 0x47, 0x0f, 0xc0, 0xd8, 0xb4, 0x79, 0x73, 0x75, 0x4d, 0x0d,
+ 0xb5, 0x4c, 0xe2, 0xdd, 0xbb, 0x77, 0x55, 0xd5, 0xd4, 0xc6, 0x6c, 0x82, 0x86, 0x03, 0x82, 0x66,
+ 0xa8, 0xa9, 0xad, 0xcd, 0x48, 0x4b, 0xae, 0xc9, 0x08, 0x6f, 0xcf, 0x7d, 0xca, 0xac, 0x8c, 0x18,
+ 0x6c, 0xcd, 0xe4, 0xf5, 0xd7, 0x0a, 0x79, 0xbd, 0x22, 0xd1, 0x10, 0x5e, 0x81, 0xcf, 0x17, 0xc4,
+ 0xc7, 0x27, 0x00, 0x21, 0xd2, 0x2b, 0xc8, 0x7d, 0x42, 0xd4, 0x3e, 0x27, 0x84, 0x0c, 0x42, 0x61,
+ 0xbf, 0x90, 0xdf, 0x41, 0xc4, 0x0b, 0x43, 0xd5, 0x22, 0x5e, 0x7d, 0x6b, 0x53, 0x09, 0xe0, 0xfa,
+ 0xf9, 0xab, 0x55, 0x15, 0x97, 0xbb, 0xba, 0x9e, 0xe1, 0x71, 0x1a, 0x88, 0x71, 0xb3, 0x03, 0x09,
+ 0x44, 0x1a, 0xcc, 0x19, 0xe6, 0x37, 0x3a, 0x39, 0xd9, 0x43, 0x62, 0xf9, 0xf8, 0xf8, 0x40, 0xd5,
+ 0x88, 0x67, 0x07, 0x43, 0x53, 0x41, 0xb1, 0x8f, 0xf9, 0x8b, 0x94, 0xa1, 0x28, 0x41, 0xc8, 0x8c,
+ 0xea, 0x6a, 0xc4, 0x44, 0xf7, 0xee, 0x79, 0xdb, 0xd9, 0xdb, 0x6b, 0x6a, 0x6a, 0xd1, 0x15, 0x15,
+ 0x27, 0x4f, 0x9e, 0x0c, 0x8a, 0xf8, 0x90, 0x06, 0x2e, 0x6a, 0x14, 0x37, 0xe2, 0x44, 0x45, 0x45,
+ 0xa5, 0x9d, 0xe4, 0x32, 0x86, 0x90, 0xfa, 0xfe, 0x0f, 0x1f, 0xbe, 0xd3, 0x4a, 0x38, 0x28, 0xf4,
+ 0x95, 0x2b, 0x97, 0x67, 0x66, 0x24, 0x09, 0xf9, 0x3d, 0x22, 0x7e, 0x17, 0xd1, 0xd9, 0x27, 0x64,
+ 0x07, 0x07, 0x3f, 0xfe, 0xd5, 0x2d, 0xa8, 0xf0, 0x5e, 0xae, 0x17, 0x5c, 0xe1, 0xd9, 0x41, 0x78,
+ 0x12, 0xeb, 0x48, 0xe0, 0x9e, 0x2e, 0x2e, 0x2e, 0x23, 0x73, 0x1b, 0x05, 0xa0, 0x34, 0x2d, 0x2d,
+ 0xc9, 0xf1, 0xab, 0xce, 0xce, 0xce, 0xd4, 0x6c, 0x32, 0xa1, 0x90, 0xe7, 0xe9, 0x79, 0x7d, 0xe2,
+ 0xc4, 0x37, 0xad, 0x00, 0x4c, 0x68, 0x30, 0x35, 0xd5, 0xb2, 0xb2, 0x42, 0xa1, 0x60, 0x40, 0x28,
+ 0x1c, 0x10, 0x09, 0x39, 0x90, 0x22, 0x08, 0x81, 0x25, 0xe4, 0x04, 0x90, 0xc3, 0xea, 0xeb, 0xe3,
+ 0x70, 0x87, 0x06, 0xf1, 0x1f, 0x8f, 0x9f, 0x90, 0x90, 0x20, 0x4d, 0x23, 0xc0, 0x70, 0x51, 0x51,
+ 0x11, 0x50, 0xcd, 0xe7, 0x0b, 0xe1, 0xd3, 0x89, 0xc4, 0xe3, 0x23, 0xae, 0x87, 0x5a, 0xc3, 0xa1,
+ 0xb0, 0xf0, 0x70, 0x00, 0x35, 0x2b, 0x27, 0x37, 0x32, 0x32, 0x2a, 0x22, 0x22, 0x32, 0x29, 0x39,
+ 0xa5, 0xa2, 0xb2, 0xaa, 0xba, 0xba, 0x46, 0xdc, 0x61, 0xb4, 0x71, 0xd3, 0xa6, 0x9a, 0xda, 0x3a,
+ 0xdc, 0x1f, 0x1e, 0x04, 0x6f, 0x4d, 0x6d, 0x35, 0x32, 0xe6, 0x33, 0xe3, 0xd0, 0xc1, 0x43, 0x87,
+ 0x5a, 0x5a, 0x5b, 0x19, 0xe5, 0xc5, 0xad, 0x25, 0x29, 0xdd, 0x65, 0x31, 0x7d, 0xb5, 0x09, 0x9c,
+ 0x8e, 0x5c, 0xfe, 0x40, 0xbd, 0x90, 0xcf, 0x04, 0x14, 0x5b, 0x5a, 0x9a, 0x8f, 0x1e, 0x3d, 0x4a,
+ 0xed, 0x52, 0x24, 0x71, 0x2d, 0x88, 0x0e, 0x21, 0x7a, 0x5b, 0x7b, 0xdb, 0xf0, 0x30, 0x5f, 0x24,
+ 0x1c, 0x14, 0x0a, 0x98, 0x88, 0x6d, 0x87, 0x05, 0xdd, 0xac, 0xde, 0xa6, 0xbd, 0x7b, 0x77, 0x4b,
+ 0xbb, 0x24, 0x3a, 0x9d, 0xf6, 0x3c, 0x21, 0x94, 0x58, 0x52, 0x63, 0x20, 0x51, 0xd0, 0xf7, 0x54,
+ 0x40, 0xb4, 0x37, 0x26, 0x0a, 0x87, 0x18, 0x8c, 0xca, 0xbc, 0xd6, 0xd6, 0x46, 0xa1, 0x50, 0x48,
+ 0xf6, 0x77, 0x13, 0x6d, 0xbc, 0xb9, 0x79, 0xf9, 0x08, 0xa8, 0x7f, 0x55, 0x86, 0x01, 0x99, 0xa0,
+ 0xa3, 0x92, 0x92, 0x52, 0x20, 0xca, 0xeb, 0xde, 0x3d, 0x80, 0x76, 0xcb, 0xd6, 0xad, 0x8a, 0x24,
+ 0x68, 0x3f, 0xfd, 0xec, 0xb3, 0xf7, 0x5e, 0x25, 0x86, 0x42, 0x2c, 0x42, 0xe9, 0x85, 0x0b, 0x17,
+ 0xee, 0xde, 0xbd, 0xe7, 0xd2, 0xa5, 0xcb, 0xc9, 0x29, 0xa9, 0x08, 0x9f, 0xdf, 0x5e, 0x16, 0x02,
+ 0x5a, 0x5a, 0x9a, 0xdb, 0x2a, 0xca, 0xb3, 0x89, 0x91, 0xed, 0xc4, 0xd2, 0x82, 0xe5, 0xa2, 0xa1,
+ 0x9a, 0x81, 0xfe, 0xc6, 0xb3, 0x67, 0x7e, 0x7d, 0x43, 0x2b, 0xc4, 0x8f, 0x41, 0x41, 0x81, 0x40,
+ 0x5d, 0x4b, 0x4b, 0x8b, 0x04, 0xc9, 0x00, 0xed, 0x25, 0xc5, 0xf9, 0xc8, 0x6a, 0x62, 0x22, 0x12,
+ 0x32, 0x5c, 0xc8, 0x95, 0x93, 0x93, 0xec, 0x3b, 0x0b, 0x08, 0x78, 0x30, 0x2c, 0x64, 0x0b, 0x05,
+ 0x2c, 0x91, 0x80, 0xc5, 0xe5, 0x30, 0xcd, 0xcd, 0x4c, 0x5e, 0xa7, 0x0d, 0x10, 0xd0, 0xe9, 0x68,
+ 0x6b, 0x56, 0x56, 0xe4, 0x13, 0x93, 0x44, 0x88, 0xd6, 0x89, 0x16, 0x91, 0xa0, 0xbb, 0xad, 0xb5,
+ 0x4e, 0x62, 0xb1, 0x23, 0x18, 0x9c, 0xcb, 0x00, 0x9b, 0x0d, 0x4d, 0xd8, 0xd5, 0xd5, 0xdd, 0xcb,
+ 0x64, 0x15, 0x8e, 0xb5, 0x8c, 0x15, 0x14, 0x1d, 0xc2, 0x79, 0x90, 0x6a, 0x5d, 0x7d, 0x03, 0xd0,
+ 0x58, 0x59, 0xc5, 0x80, 0xda, 0x04, 0x38, 0x01, 0x57, 0x5c, 0x9e, 0x96, 0x9e, 0x01, 0xd5, 0x1d,
+ 0x9f, 0xf0, 0x1c, 0xfa, 0x0a, 0xa0, 0x85, 0xf0, 0x68, 0x68, 0x6c, 0xbc, 0x7e, 0xfd, 0x86, 0xf8,
+ 0x72, 0x08, 0x80, 0xd4, 0xd4, 0xb4, 0xb3, 0x67, 0xcf, 0xbe, 0x0d, 0x2d, 0xa8, 0xa9, 0xa9, 0xe5,
+ 0xe4, 0xe4, 0x76, 0xb5, 0x36, 0x31, 0x1b, 0x4a, 0xfb, 0x1a, 0x72, 0xd9, 0xad, 0xf9, 0x43, 0x4c,
+ 0x86, 0x80, 0xd3, 0xd1, 0xd5, 0xd1, 0x14, 0x11, 0x11, 0xa6, 0xae, 0x3e, 0x46, 0x7b, 0x0e, 0x65,
+ 0x0a, 0x0a, 0x0a, 0x29, 0xa9, 0xa9, 0x42, 0xb2, 0x6b, 0x80, 0x98, 0xbb, 0x44, 0xd4, 0xd0, 0x41,
+ 0x16, 0xb3, 0xd3, 0xd1, 0x71, 0xec, 0xa5, 0x27, 0x36, 0x6d, 0xda, 0xd0, 0xdc, 0x88, 0x68, 0xab,
+ 0x48, 0xd0, 0x1f, 0x41, 0x2c, 0xd1, 0xcf, 0xf4, 0x17, 0xf4, 0x47, 0x0a, 0xb9, 0x85, 0x44, 0x8e,
+ 0xa1, 0x14, 0x44, 0x42, 0x90, 0x2b, 0x7b, 0x70, 0x30, 0x34, 0x34, 0x54, 0xbc, 0x79, 0xe8, 0xaf,
+ 0x1a, 0x32, 0xc4, 0xc6, 0xc6, 0x06, 0x79, 0x88, 0x27, 0x41, 0x80, 0x76, 0xc4, 0xd2, 0x12, 0xce,
+ 0x45, 0x81, 0x46, 0x9b, 0x30, 0x61, 0x22, 0x15, 0x85, 0xbd, 0x37, 0x62, 0x51, 0x49, 0xe9, 0x74,
+ 0xc5, 0xed, 0xba, 0xba, 0xa0, 0xb5, 0x67, 0xa1, 0xa1, 0x86, 0x86, 0x07, 0x40, 0x08, 0x5f, 0x7e,
+ 0xf5, 0xeb, 0x06, 0xfe, 0xd9, 0xbd, 0x7b, 0x7b, 0x73, 0x63, 0xe1, 0x30, 0xb7, 0x52, 0xc8, 0x4e,
+ 0x23, 0xb7, 0x27, 0x88, 0xc6, 0x1f, 0xed, 0xcd, 0x99, 0xfb, 0xf4, 0x77, 0x7d, 0xf5, 0x95, 0xf8,
+ 0x1e, 0x5f, 0x7e, 0x26, 0x69, 0xc4, 0x74, 0x0c, 0x75, 0x75, 0xb5, 0xec, 0xac, 0xe4, 0x61, 0xd1,
+ 0xc0, 0x8d, 0x1b, 0x57, 0x25, 0x5e, 0x56, 0x59, 0x59, 0x49, 0xc0, 0xeb, 0x16, 0x22, 0x5e, 0xe0,
+ 0xb5, 0x08, 0x05, 0xed, 0xed, 0x6d, 0x35, 0xd2, 0xeb, 0xf3, 0x64, 0x65, 0xc4, 0x91, 0x03, 0x08,
+ 0x6b, 0x88, 0xc4, 0x6f, 0x6a, 0x6b, 0x29, 0xff, 0x7e, 0xc9, 0x18, 0x25, 0x88, 0xfa, 0x68, 0x66,
+ 0x66, 0x5c, 0x5d, 0x99, 0x25, 0x1a, 0xaa, 0x26, 0x85, 0x5c, 0x86, 0x70, 0x30, 0x57, 0x34, 0xc4,
+ 0x88, 0x8a, 0x0c, 0x98, 0x31, 0x43, 0xb2, 0x53, 0xcf, 0xc1, 0xce, 0xb6, 0xa3, 0xad, 0xb5, 0xaa,
+ 0x8a, 0x81, 0x88, 0xaf, 0xb6, 0xae, 0x1e, 0xbe, 0x5b, 0x7a, 0x29, 0x6c, 0x54, 0x2e, 0x37, 0x37,
+ 0x37, 0x60, 0x35, 0x27, 0x37, 0x0f, 0x09, 0xf8, 0x04, 0x62, 0xaf, 0x5c, 0x21, 0x5e, 0x01, 0x31,
+ 0x20, 0xf4, 0x5b, 0x7e, 0x01, 0xb1, 0xd1, 0x76, 0x58, 0x58, 0x38, 0xb1, 0x47, 0x49, 0x51, 0x31,
+ 0xe5, 0x43, 0xc5, 0x97, 0x23, 0xd3, 0xe0, 0x67, 0xdf, 0x52, 0x78, 0x43, 0x9a, 0x42, 0x1e, 0x33,
+ 0xbb, 0x3b, 0x39, 0xcc, 0x76, 0x6e, 0x6f, 0x13, 0xaf, 0xaf, 0x69, 0x90, 0xd5, 0x92, 0x97, 0x9d,
+ 0x76, 0xf4, 0xa8, 0xcd, 0x1b, 0xf6, 0x4e, 0xc2, 0x4f, 0x5c, 0xba, 0x74, 0x89, 0xcd, 0x1e, 0x14,
+ 0x2f, 0xc4, 0x31, 0x3c, 0x2c, 0x60, 0x32, 0xbb, 0x3d, 0x3c, 0x24, 0x1b, 0x55, 0xc4, 0xb6, 0x6b,
+ 0x97, 0x2e, 0x87, 0xdd, 0x08, 0x49, 0x20, 0xe8, 0x0f, 0x17, 0xf6, 0xfa, 0x12, 0x63, 0x68, 0xfb,
+ 0x42, 0x09, 0xd1, 0xcb, 0x6b, 0x86, 0xa8, 0x10, 0x0d, 0x0b, 0x21, 0x84, 0xee, 0x7a, 0x79, 0x21,
+ 0x78, 0x7c, 0xa7, 0x75, 0x3c, 0xf0, 0xa6, 0x20, 0x40, 0x30, 0x6d, 0x52, 0x72, 0xf2, 0xd5, 0x6b,
+ 0xd7, 0x4c, 0xcd, 0xcc, 0xd6, 0xac, 0x59, 0xbb, 0x60, 0x81, 0x0c, 0x20, 0x47, 0xed, 0x50, 0xfc,
+ 0xae, 0x4c, 0x4b, 0xe9, 0x58, 0xc0, 0x73, 0x81, 0x8c, 0xcc, 0xa6, 0x4d, 0x9b, 0x40, 0xdd, 0x3e,
+ 0x3e, 0xbe, 0x17, 0x2f, 0x5d, 0x82, 0x68, 0x3c, 0x03, 0x51, 0x3b, 0x86, 0x9d, 0x3b, 0x77, 0xce,
+ 0xf9, 0xfc, 0x79, 0x97, 0x0b, 0x6e, 0x6e, 0x37, 0xae, 0x5d, 0xf0, 0xf3, 0x76, 0x6b, 0xaa, 0x4b,
+ 0x21, 0x66, 0x61, 0xf4, 0x85, 0x09, 0x7b, 0xbd, 0x89, 0xc1, 0xbd, 0x3d, 0x37, 0x50, 0x43, 0xfb,
+ 0xda, 0xc3, 0xc3, 0x83, 0x2f, 0x7b, 0xdd, 0x3a, 0xe3, 0x75, 0xdb, 0xd9, 0xeb, 0xf6, 0xf9, 0xbb,
+ 0xb7, 0x9c, 0x6f, 0x5c, 0x3d, 0x29, 0x91, 0xae, 0x5d, 0x76, 0x7a, 0x12, 0x70, 0xbd, 0xa7, 0xa3,
+ 0x40, 0xc4, 0xab, 0x89, 0x8b, 0xf6, 0xf3, 0x70, 0x73, 0xa0, 0xd2, 0x45, 0x22, 0xd9, 0x87, 0x85,
+ 0xdc, 0x14, 0x0e, 0x95, 0x12, 0x9a, 0x6a, 0x30, 0x57, 0xc8, 0x2d, 0xea, 0x6a, 0xcb, 0xbe, 0x7e,
+ 0xc5, 0xc9, 0xc3, 0xcd, 0xf1, 0x22, 0x99, 0x3c, 0xdc, 0x8e, 0x79, 0x5c, 0xb0, 0xeb, 0x69, 0x4b,
+ 0x27, 0x9a, 0xc4, 0xd9, 0x89, 0x02, 0xf6, 0x73, 0xe1, 0x60, 0x9a, 0x88, 0x5b, 0x9c, 0x91, 0x1c,
+ 0x48, 0xde, 0xc4, 0x51, 0x9c, 0x70, 0xb2, 0xaf, 0xb7, 0x5b, 0x23, 0x1e, 0x92, 0x9b, 0x47, 0xf4,
+ 0xe3, 0xb0, 0x02, 0x05, 0xcc, 0x07, 0x42, 0x56, 0x90, 0x70, 0x20, 0xae, 0x24, 0x2f, 0xd0, 0xf3,
+ 0xea, 0x09, 0x0f, 0x57, 0x07, 0x77, 0x97, 0x63, 0xee, 0xe7, 0x1d, 0xdd, 0xce, 0x39, 0xba, 0x9e,
+ 0x39, 0x96, 0x9d, 0x18, 0x5e, 0x5f, 0x96, 0x17, 0x1b, 0x17, 0x1f, 0x15, 0x1d, 0xf3, 0x3c, 0x31,
+ 0x09, 0x1e, 0xf0, 0x84, 0x93, 0x13, 0x31, 0xe7, 0x96, 0x30, 0xbb, 0x17, 0xff, 0xb3, 0xb3, 0x87,
+ 0x70, 0x02, 0xf5, 0x65, 0x66, 0x65, 0x01, 0x9c, 0x70, 0xf1, 0x4d, 0x4d, 0x4d, 0x88, 0x55, 0xc1,
+ 0xbd, 0x40, 0x57, 0x6d, 0x5d, 0x5d, 0x46, 0x66, 0x16, 0x28, 0x17, 0x09, 0x0e, 0x0b, 0x0c, 0x9c,
+ 0x9e, 0x91, 0xf9, 0xde, 0x2b, 0xc0, 0xa3, 0x58, 0xe1, 0x82, 0x5d, 0x5d, 0xce, 0x87, 0x85, 0x3c,
+ 0x8d, 0x8d, 0x0a, 0xbf, 0xef, 0x7b, 0xd7, 0xde, 0xce, 0x66, 0x99, 0x86, 0xc6, 0x1b, 0x34, 0x24,
+ 0xa8, 0x60, 0xe7, 0xae, 0x5d, 0x54, 0x03, 0x1d, 0xb5, 0x10, 0x07, 0xb5, 0xae, 0xec, 0x8d, 0x1b,
+ 0x37, 0xa4, 0x57, 0xbc, 0x11, 0x9b, 0xae, 0xae, 0x76, 0x3f, 0xab, 0x41, 0xc4, 0x2d, 0x11, 0x0e,
+ 0xc4, 0x10, 0xe3, 0xb5, 0x58, 0xfe, 0x44, 0x87, 0x17, 0x27, 0x17, 0x88, 0x85, 0x9b, 0x63, 0xb1,
+ 0x7a, 0x9d, 0xcf, 0x3b, 0xcf, 0x91, 0x5a, 0xa7, 0xf4, 0x6d, 0x6c, 0xee, 0xdc, 0xb9, 0xb7, 0x6e,
+ 0xdd, 0xaa, 0xac, 0xac, 0x8c, 0x88, 0x8c, 0x74, 0x73, 0x73, 0x37, 0x34, 0x34, 0x44, 0x84, 0x32,
+ 0x67, 0xce, 0xdc, 0x71, 0xa4, 0x4c, 0x7a, 0x8f, 0x51, 0x31, 0xd4, 0x96, 0x07, 0xd3, 0x67, 0xcc,
+ 0x58, 0xb2, 0x64, 0x89, 0x9e, 0x9e, 0xde, 0xa9, 0x53, 0xa7, 0x6f, 0xdf, 0xb9, 0x13, 0x10, 0x18,
+ 0xf8, 0xf4, 0x69, 0x48, 0x48, 0xc8, 0x33, 0x29, 0x0b, 0x25, 0xd6, 0x31, 0x8b, 0x8d, 0x45, 0x59,
+ 0x94, 0x15, 0x67, 0xb1, 0xbb, 0x62, 0x89, 0x7d, 0x5e, 0x7a, 0xee, 0x0a, 0xbb, 0x5c, 0x88, 0x49,
+ 0x04, 0xad, 0x47, 0xf8, 0x6d, 0x56, 0x82, 0x76, 0x27, 0x02, 0xba, 0xcc, 0x47, 0xc4, 0x2e, 0x30,
+ 0xfd, 0x51, 0xc0, 0xc9, 0xeb, 0x53, 0x14, 0xb9, 0x65, 0x4c, 0x04, 0xf1, 0xc7, 0x40, 0xcc, 0xcb,
+ 0x2f, 0x07, 0x22, 0x05, 0xfd, 0xcf, 0x04, 0xac, 0x00, 0x21, 0xf2, 0x0d, 0xa9, 0x2f, 0x48, 0x88,
+ 0x8a, 0x8f, 0x13, 0x80, 0x4c, 0x22, 0x25, 0x10, 0xa3, 0xe6, 0x70, 0x1a, 0xeb, 0x09, 0x41, 0x05,
+ 0xbd, 0xb7, 0x89, 0xa9, 0xb8, 0xbd, 0xf7, 0x88, 0xc1, 0x8a, 0x7d, 0xb8, 0x55, 0xdc, 0xc8, 0x69,
+ 0x89, 0x64, 0x4a, 0x20, 0x2e, 0xec, 0x0f, 0x11, 0xb2, 0x7c, 0x05, 0xdd, 0x1e, 0xc4, 0x40, 0xdc,
+ 0x8e, 0x13, 0xc4, 0x04, 0xf3, 0xee, 0xab, 0x24, 0x74, 0x43, 0xf9, 0xcc, 0x98, 0xa1, 0xae, 0x78,
+ 0x4e, 0xeb, 0xf3, 0x81, 0xc6, 0xe7, 0x4c, 0x46, 0x7c, 0x67, 0x51, 0x54, 0x51, 0x6c, 0xe0, 0xe5,
+ 0xcb, 0x57, 0x2e, 0x5e, 0xba, 0x7c, 0xed, 0xfa, 0xf5, 0x7b, 0xde, 0xde, 0xc8, 0x8a, 0x60, 0x22,
+ 0x2f, 0x5e, 0xbc, 0x7f, 0x08, 0x91, 0x42, 0xe1, 0x89, 0xc2, 0xc3, 0x23, 0xe0, 0xfa, 0x01, 0x69,
+ 0x60, 0x03, 0x54, 0x8c, 0x72, 0x41, 0x68, 0xff, 0x24, 0x38, 0x18, 0x10, 0x4d, 0x4c, 0x4a, 0xc6,
+ 0x51, 0xd0, 0x6c, 0x56, 0x76, 0x4e, 0x63, 0x53, 0x33, 0x6a, 0xf9, 0xdb, 0xef, 0x2a, 0x2b, 0x6d,
+ 0x54, 0xa0, 0x41, 0x6c, 0xb5, 0x20, 0x2b, 0x0b, 0xa7, 0xf0, 0xab, 0xad, 0x8e, 0xf3, 0xe6, 0xcd,
+ 0x43, 0x19, 0x51, 0xc1, 0x23, 0xd5, 0x4e, 0x0b, 0xb8, 0x22, 0xbe, 0xc3, 0xf7, 0x6f, 0xa0, 0xc7,
+ 0xa5, 0x4b, 0xbf, 0x2f, 0x2c, 0x48, 0x23, 0x06, 0x7b, 0x70, 0xb2, 0xc8, 0xb2, 0x88, 0x12, 0x0e,
+ 0xa6, 0x0a, 0x87, 0x2a, 0xa0, 0x7e, 0x07, 0xd9, 0x2c, 0x0b, 0x0b, 0x8b, 0x31, 0xfb, 0x37, 0xdf,
+ 0xd2, 0xbe, 0xfb, 0xee, 0xbb, 0x00, 0x62, 0x8b, 0xd8, 0xd2, 0xa0, 0x27, 0x4f, 0x4e, 0x9f, 0x39,
+ 0xb3, 0x67, 0xcf, 0x1e, 0x75, 0xf5, 0x25, 0x33, 0x66, 0xce, 0x7c, 0xbf, 0xf6, 0x2e, 0x6a, 0x2c,
+ 0x37, 0x58, 0x1a, 0x79, 0x02, 0xf0, 0xeb, 0xee, 0xd8, 0x01, 0xd7, 0x66, 0x65, 0x65, 0x0d, 0x2a,
+ 0x01, 0xe5, 0xda, 0x3b, 0x38, 0x8c, 0x4e, 0x0e, 0xc7, 0x8e, 0x1d, 0x3f, 0x71, 0xe2, 0xcc, 0xd9,
+ 0x73, 0x97, 0x2f, 0x5f, 0xbd, 0xff, 0xe0, 0x41, 0x5d, 0xfe, 0x15, 0x7e, 0xeb, 0x09, 0x02, 0xa8,
+ 0xcd, 0x06, 0x82, 0x46, 0x6d, 0x62, 0x35, 0xf8, 0x86, 0xad, 0xe4, 0x52, 0x6f, 0xa6, 0x82, 0x36,
+ 0x7b, 0x7e, 0xfb, 0x49, 0x41, 0xc7, 0x59, 0x02, 0x1e, 0x9d, 0xe7, 0xde, 0x3a, 0x51, 0xe7, 0x9f,
+ 0xe2, 0x03, 0xf6, 0xed, 0xf6, 0x82, 0x76, 0x3b, 0x41, 0x87, 0x83, 0xa0, 0xf3, 0xb8, 0xa0, 0xeb,
+ 0x14, 0xbf, 0xfb, 0x3c, 0xbf, 0xdb, 0x8d, 0x18, 0xe5, 0xd5, 0x7d, 0x91, 0xdf, 0xed, 0x2e, 0x40,
+ 0x1d, 0xe9, 0x3c, 0xcd, 0x6f, 0x77, 0x20, 0xa7, 0x34, 0x5a, 0xf3, 0x89, 0x33, 0x7f, 0xe2, 0x77,
+ 0x9e, 0xe7, 0x77, 0xb9, 0x93, 0xe7, 0x5c, 0x7a, 0x91, 0xba, 0xdc, 0xf9, 0x5d, 0xce, 0x82, 0x0e,
+ 0x27, 0x01, 0xce, 0x69, 0x39, 0xc0, 0x6f, 0xda, 0x25, 0x20, 0xd7, 0x4e, 0x14, 0xb4, 0x98, 0xf0,
+ 0xdb, 0x8e, 0xf2, 0xda, 0x4e, 0x72, 0x1a, 0x5d, 0x06, 0x18, 0xee, 0xcc, 0x92, 0x8b, 0x5d, 0xb9,
+ 0x97, 0x5a, 0x93, 0x2e, 0xd6, 0x45, 0xb8, 0xa5, 0x78, 0x9d, 0x34, 0xdc, 0x6f, 0x68, 0x60, 0xb0,
+ 0xff, 0x80, 0x91, 0x91, 0x99, 0x99, 0x99, 0x95, 0x95, 0x15, 0x28, 0x96, 0xca, 0x0a, 0x22, 0x03,
+ 0x1c, 0x1d, 0xe1, 0x80, 0x5c, 0x5d, 0x2f, 0xdc, 0xbe, 0x73, 0x17, 0x30, 0xce, 0xce, 0xce, 0x81,
+ 0x24, 0x40, 0x45, 0x06, 0x19, 0xc2, 0xf5, 0x67, 0xe7, 0xe4, 0x14, 0x97, 0x94, 0xc6, 0xc5, 0x27,
+ 0x10, 0x78, 0x26, 0x25, 0x41, 0x5d, 0x5d, 0xfd, 0xda, 0xb5, 0x6b, 0x3f, 0xee, 0x8a, 0x58, 0x6f,
+ 0x30, 0x3c, 0x06, 0x7c, 0x25, 0x04, 0xa7, 0x18, 0xae, 0x5c, 0xee, 0xd0, 0xcd, 0x9b, 0x37, 0x41,
+ 0xf2, 0x6f, 0x7e, 0x06, 0xa8, 0x85, 0xcb, 0x97, 0xdc, 0xf9, 0x43, 0x9d, 0xc4, 0x96, 0xf7, 0x9c,
+ 0x22, 0xb2, 0x3d, 0xb6, 0x4a, 0xc4, 0xef, 0x68, 0x6f, 0xab, 0xd7, 0xdf, 0xab, 0xf7, 0xae, 0x1b,
+ 0x65, 0x4a, 0xdb, 0xac, 0x59, 0xb3, 0xd2, 0xd3, 0xd3, 0x73, 0x73, 0xf3, 0xee, 0x3f, 0xf0, 0x3f,
+ 0x7e, 0xfc, 0x04, 0x24, 0xa8, 0x8a, 0x8a, 0x0a, 0xd1, 0xde, 0x45, 0x46, 0x61, 0xef, 0x04, 0x5a,
+ 0x6a, 0x24, 0x0c, 0x5c, 0x09, 0x40, 0x8b, 0xdb, 0x42, 0x57, 0x2f, 0x56, 0x57, 0xd7, 0x58, 0xb6,
+ 0x6c, 0xc5, 0x8a, 0x95, 0x23, 0xfd, 0x4d, 0x2f, 0xd3, 0xaa, 0x55, 0xab, 0xa1, 0x43, 0x36, 0x6f,
+ 0xde, 0xb2, 0x6b, 0xd7, 0x6e, 0x0b, 0x8b, 0xc3, 0x2e, 0xe7, 0x5d, 0x8a, 0xc2, 0x4c, 0xfb, 0x8b,
+ 0x36, 0x71, 0xca, 0x96, 0x71, 0xcb, 0xd4, 0x38, 0x65, 0xca, 0x9c, 0x32, 0x15, 0x4e, 0xb9, 0x06,
+ 0xb7, 0x62, 0x1d, 0xb7, 0x72, 0x1b, 0xa7, 0x4a, 0x67, 0xb0, 0x6a, 0xc7, 0x60, 0xe5, 0xce, 0xc1,
+ 0x2a, 0x32, 0x31, 0x76, 0x72, 0xab, 0x77, 0x10, 0xa9, 0x46, 0x97, 0x5b, 0xab, 0x3b, 0x54, 0xbb,
+ 0x1d, 0x89, 0x57, 0xa7, 0xc3, 0xab, 0xd7, 0xe1, 0x37, 0x68, 0x8f, 0x4a, 0x5a, 0xfc, 0x06, 0x4d,
+ 0x72, 0x27, 0xc4, 0x8d, 0xc4, 0xea, 0xd0, 0xf5, 0xeb, 0xf9, 0x0d, 0x1b, 0xf9, 0x8d, 0xdb, 0xf8,
+ 0x4d, 0xda, 0xc4, 0x42, 0x9d, 0xcd, 0xbb, 0xf8, 0xcd, 0x7b, 0xc8, 0x6d, 0x13, 0x77, 0xf3, 0xf0,
+ 0xb1, 0x91, 0xdc, 0x72, 0x11, 0xa9, 0x51, 0x93, 0xf8, 0x48, 0x1c, 0xd2, 0xe7, 0x37, 0xef, 0x27,
+ 0xd3, 0x3e, 0x9c, 0x26, 0x68, 0xde, 0xc9, 0x6f, 0xda, 0xce, 0x6b, 0xdc, 0xc2, 0x27, 0x76, 0x5c,
+ 0xd2, 0xe0, 0xd7, 0xa8, 0xf1, 0xab, 0x55, 0xf8, 0x35, 0x4b, 0xf8, 0xb5, 0xab, 0x86, 0x6a, 0x37,
+ 0x0e, 0x32, 0xb4, 0xfb, 0x4b, 0x76, 0x33, 0xb3, 0xf5, 0x3b, 0x92, 0xf6, 0x37, 0x47, 0x1a, 0x56,
+ 0x07, 0x1a, 0x16, 0xdf, 0xd9, 0x1f, 0x7e, 0x72, 0xe7, 0xd2, 0x25, 0x6a, 0xca, 0x8b, 0x16, 0xa9,
+ 0xa8, 0xaa, 0xaa, 0x2f, 0x59, 0x42, 0x66, 0xc5, 0x0a, 0xea, 0xdd, 0x57, 0xaf, 0xfe, 0x61, 0xfd,
+ 0xfa, 0x0d, 0xda, 0xda, 0x3a, 0x87, 0x4c, 0x4c, 0xce, 0x39, 0x3b, 0x3f, 0x7c, 0xf8, 0x28, 0x2b,
+ 0x3b, 0xbb, 0xad, 0xbd, 0x63, 0xdf, 0x3e, 0x03, 0x84, 0x12, 0xe6, 0xe6, 0xe6, 0x60, 0x54, 0xb0,
+ 0x6e, 0x6c, 0x6c, 0x5c, 0x54, 0x54, 0x34, 0xc2, 0x2b, 0x46, 0x75, 0x35, 0x58, 0xe5, 0x5d, 0x77,
+ 0xf2, 0xfd, 0x10, 0x03, 0x00, 0x6c, 0x5f, 0x8c, 0xcb, 0x25, 0x26, 0x19, 0xf5, 0xf4, 0xf4, 0x22,
+ 0xf6, 0xf9, 0xd5, 0x7e, 0x1c, 0xca, 0xf0, 0x9c, 0xc1, 0x4f, 0x02, 0xd8, 0xec, 0xce, 0x61, 0x41,
+ 0xb7, 0x80, 0xd7, 0xc9, 0xec, 0x69, 0x8a, 0x8a, 0x0c, 0x5d, 0xbc, 0x58, 0xed, 0xbd, 0x27, 0xf0,
+ 0x4a, 0x18, 0x34, 0xf0, 0xf3, 0xe7, 0x89, 0xf0, 0x3b, 0x0f, 0x08, 0xd0, 0x1e, 0xd7, 0xd1, 0xd1,
+ 0x51, 0x52, 0x52, 0x9a, 0x3c, 0x79, 0xca, 0xa7, 0x9f, 0xbe, 0x33, 0x68, 0x71, 0x32, 0xd4, 0x2c,
+ 0xde, 0xeb, 0x5f, 0xff, 0xfa, 0xe2, 0x9b, 0x6f, 0xbf, 0xc5, 0x4d, 0xa6, 0x4d, 0x9b, 0x3e, 0xb2,
+ 0xe1, 0xfc, 0x4c, 0x89, 0x34, 0x7b, 0xf6, 0x6c, 0xb0, 0x31, 0x7e, 0x0b, 0x80, 0xde, 0xb9, 0x73,
+ 0x97, 0xbd, 0x8d, 0x75, 0xac, 0x87, 0x56, 0x85, 0xdf, 0xf2, 0xa6, 0x27, 0x2a, 0xad, 0xa1, 0xca,
+ 0xed, 0x11, 0x0b, 0x3b, 0xa2, 0x54, 0x3b, 0x63, 0x97, 0x74, 0xc6, 0x6b, 0x74, 0x25, 0xae, 0xe8,
+ 0x4a, 0x5a, 0xd9, 0x9d, 0xbc, 0xb2, 0x27, 0x65, 0x65, 0x4f, 0xea, 0xca, 0xde, 0xb4, 0x95, 0xcc,
+ 0x8c, 0x15, 0xac, 0xac, 0x15, 0x7d, 0xd9, 0xcb, 0xfb, 0x73, 0x97, 0xf5, 0xe7, 0x2d, 0x1b, 0xc8,
+ 0x5f, 0x3a, 0x50, 0xf8, 0x3d, 0xbb, 0x78, 0x09, 0xa7, 0x54, 0x9d, 0x5b, 0xbe, 0x98, 0x5b, 0xa1,
+ 0x36, 0x54, 0xa9, 0xc2, 0x63, 0x2c, 0xe2, 0x31, 0x94, 0x79, 0x0c, 0x25, 0x72, 0xc9, 0x47, 0x05,
+ 0x1e, 0x83, 0x46, 0xfe, 0xa1, 0xc4, 0xaf, 0x5e, 0xc8, 0xaf, 0x51, 0xe6, 0xd7, 0xa8, 0xf2, 0x6b,
+ 0xd5, 0xf8, 0x75, 0x6a, 0x3c, 0xa4, 0x5a, 0xfc, 0xab, 0xc2, 0xab, 0x55, 0x46, 0xe2, 0xd7, 0xaa,
+ 0xf2, 0xea, 0xd4, 0x79, 0x75, 0x1a, 0xfc, 0xba, 0x65, 0xc4, 0x56, 0xa1, 0x75, 0x4b, 0xc9, 0xa4,
+ 0x8e, 0xef, 0x89, 0x6d, 0x6d, 0xab, 0x15, 0x79, 0x0c, 0x79, 0x3e, 0x31, 0xb4, 0x78, 0x1e, 0xaf,
+ 0x72, 0x2e, 0xaf, 0x6a, 0xfe, 0x50, 0xb9, 0x02, 0xa7, 0x44, 0x79, 0xa0, 0x60, 0x31, 0x33, 0x6b,
+ 0x59, 0x57, 0xe2, 0xea, 0x96, 0xb0, 0x1f, 0xea, 0x1e, 0xad, 0x2d, 0xbf, 0xbd, 0x3e, 0xd7, 0x75,
+ 0x5d, 0xa0, 0xd9, 0xf2, 0x79, 0x33, 0xa6, 0x4c, 0x80, 0x17, 0x9c, 0x34, 0x09, 0x24, 0x30, 0x92,
+ 0x15, 0xc4, 0x06, 0x70, 0x70, 0xfd, 0xf2, 0x0a, 0x0a, 0xcb, 0x96, 0x2d, 0xdb, 0xb3, 0x47, 0xef,
+ 0xe4, 0xc9, 0x53, 0x8f, 0x02, 0x02, 0xa0, 0x63, 0x1b, 0x1a, 0x1b, 0x71, 0x08, 0x67, 0x42, 0x28,
+ 0x42, 0x21, 0xa0, 0x44, 0xc0, 0xb1, 0x10, 0x0c, 0x79, 0xf9, 0x05, 0x0d, 0x8d, 0x4d, 0xa0, 0xe6,
+ 0x0f, 0x91, 0x04, 0xef, 0x6a, 0x28, 0xc4, 0x0d, 0x1b, 0x36, 0x24, 0xa7, 0xa4, 0xe4, 0xe4, 0xe4,
+ 0x84, 0x85, 0x47, 0x48, 0xef, 0xe9, 0xf0, 0x66, 0x83, 0xfb, 0xbe, 0x70, 0xc1, 0x25, 0x3e, 0x2e,
+ 0x3a, 0xe4, 0x69, 0x90, 0xa9, 0xc9, 0xa1, 0x29, 0x53, 0x3e, 0x68, 0xb9, 0x6f, 0x09, 0x43, 0xa5,
+ 0x5e, 0xb3, 0x76, 0x6d, 0xc2, 0xf3, 0x44, 0xe8, 0x7c, 0x6f, 0x1f, 0x1f, 0x44, 0x07, 0xa0, 0x3e,
+ 0x1a, 0x8d, 0x86, 0x7c, 0x16, 0xef, 0xe0, 0xfc, 0x4e, 0x4c, 0x0b, 0x0d, 0x0c, 0xdc, 0xa2, 0x42,
+ 0xe1, 0xce, 0xff, 0x24, 0xed, 0xd3, 0xd7, 0x18, 0x8a, 0x00, 0xca, 0x0a, 0xc5, 0xb4, 0x70, 0xe1,
+ 0xc2, 0xf5, 0xeb, 0xd7, 0x1f, 0x32, 0xdc, 0x77, 0xc3, 0x46, 0x27, 0xec, 0xd4, 0xfa, 0x0c, 0x67,
+ 0xb5, 0x02, 0x77, 0xa5, 0xb2, 0xab, 0x4a, 0x95, 0xb7, 0x94, 0x19, 0xf7, 0x16, 0xd5, 0xf8, 0xaa,
+ 0xd4, 0x3e, 0x50, 0xa9, 0xf3, 0x57, 0x69, 0x08, 0x50, 0x69, 0x7c, 0xbc, 0xa8, 0xe9, 0xc9, 0xa2,
+ 0x96, 0x10, 0xe5, 0xd6, 0x67, 0xca, 0x6d, 0xe1, 0xca, 0xed, 0x51, 0x0b, 0x3b, 0x62, 0x94, 0xba,
+ 0xe2, 0x14, 0xbb, 0x9f, 0xd3, 0x7b, 0x92, 0x69, 0xcc, 0x34, 0x79, 0x56, 0x86, 0x5c, 0x5f, 0xb6,
+ 0x6c, 0x7f, 0xce, 0x02, 0x76, 0xfe, 0xfc, 0xc1, 0xc2, 0x79, 0x9c, 0xe2, 0x39, 0xdc, 0xd2, 0x59,
+ 0x43, 0xe5, 0x33, 0x78, 0x15, 0x33, 0xf8, 0x95, 0x54, 0x9a, 0xf9, 0x22, 0x55, 0x21, 0xcd, 0x42,
+ 0x22, 0x37, 0xf9, 0x9d, 0x45, 0xee, 0xa5, 0x3e, 0x8b, 0x57, 0x3d, 0x9b, 0x57, 0x3d, 0x97, 0x5f,
+ 0x3d, 0x8f, 0x5f, 0xfd, 0x1d, 0xf1, 0x2f, 0x63, 0x2e, 0x99, 0x66, 0x13, 0x27, 0x57, 0x52, 0x1b,
+ 0x85, 0x4f, 0xe7, 0x55, 0x4e, 0xe5, 0x55, 0x4c, 0x1e, 0x2a, 0x9f, 0xc2, 0x29, 0x99, 0xce, 0x2e,
+ 0x98, 0xd3, 0x9f, 0x3d, 0x9f, 0x95, 0x2a, 0xd7, 0x95, 0x40, 0xc7, 0xf3, 0x34, 0x04, 0x2e, 0x62,
+ 0xdc, 0x53, 0x29, 0xbe, 0xac, 0x96, 0x71, 0x72, 0xb1, 0x9f, 0x81, 0xe2, 0x37, 0x5f, 0x7c, 0xfa,
+ 0x7f, 0x49, 0xfb, 0xfb, 0xdf, 0xff, 0x41, 0xe5, 0x03, 0xb8, 0x4b, 0xfc, 0xd6, 0x10, 0xfc, 0x7b,
+ 0xf5, 0xf5, 0x11, 0x7e, 0x86, 0x86, 0x86, 0x41, 0xb5, 0x3e, 0xf0, 0xf7, 0x27, 0x17, 0xaf, 0x50,
+ 0x48, 0x4a, 0x4a, 0xaa, 0xad, 0xab, 0xcf, 0xce, 0xc9, 0x4d, 0x4a, 0x4e, 0x41, 0xb4, 0x55, 0x59,
+ 0x55, 0x55, 0x58, 0x54, 0x04, 0x1f, 0xfd, 0x11, 0x0b, 0xfd, 0x6d, 0x0c, 0x0f, 0x03, 0x56, 0xc1,
+ 0xf3, 0x8c, 0x1f, 0x3f, 0xfe, 0x3d, 0xd4, 0x08, 0xd5, 0x76, 0xf4, 0x86, 0xc8, 0xee, 0x43, 0x0c,
+ 0xb7, 0xdd, 0xb5, 0x6b, 0x57, 0x4a, 0x6a, 0x2a, 0xd2, 0xcd, 0x5b, 0xb7, 0xcc, 0x2d, 0x2c, 0xe0,
+ 0xb3, 0xc0, 0xbd, 0x13, 0x26, 0x4c, 0x78, 0xbf, 0x71, 0x32, 0x38, 0x1f, 0x7c, 0xfb, 0xbf, 0x49,
+ 0xfb, 0x3f, 0xaf, 0x37, 0x54, 0x07, 0x94, 0x26, 0xb4, 0x0d, 0x78, 0x08, 0x7c, 0xbb, 0x74, 0xa9,
+ 0x86, 0xb6, 0x96, 0xd6, 0x91, 0x03, 0x7a, 0xae, 0x47, 0x76, 0xf9, 0x38, 0x6c, 0x8f, 0x3a, 0xb6,
+ 0x2a, 0xc5, 0x61, 0x61, 0xba, 0x93, 0x52, 0xf6, 0x19, 0xa5, 0x3c, 0x17, 0xa5, 0x42, 0x77, 0xc5,
+ 0x92, 0xcb, 0x8a, 0x65, 0x57, 0xe9, 0xe5, 0x37, 0xe8, 0x95, 0xb7, 0x69, 0x55, 0x77, 0xe9, 0xd5,
+ 0xde, 0xb4, 0x1a, 0x3f, 0x5a, 0x9d, 0xbf, 0x42, 0xc3, 0x23, 0xf9, 0xa6, 0xc7, 0xf2, 0xcd, 0x4f,
+ 0xe5, 0x5b, 0x43, 0xe5, 0xda, 0xc2, 0x65, 0x3b, 0xa2, 0x65, 0xba, 0xe2, 0xe6, 0x77, 0x3f, 0xff,
+ 0xae, 0x37, 0x79, 0x2e, 0x2b, 0x7d, 0x76, 0x7f, 0xe6, 0x4c, 0x76, 0xee, 0xf4, 0xc1, 0xc2, 0xa9,
+ 0x9c, 0x92, 0x29, 0x43, 0xa5, 0x93, 0x86, 0xca, 0x27, 0xf2, 0x5e, 0x49, 0x13, 0xc8, 0xbd, 0xfc,
+ 0x26, 0x8c, 0x24, 0x72, 0x5f, 0xbf, 0x8a, 0x49, 0xa3, 0x12, 0xf9, 0x8d, 0xf8, 0x64, 0x72, 0x9f,
+ 0x94, 0xa1, 0xb2, 0x09, 0x9c, 0xe2, 0x49, 0x03, 0xb9, 0xd3, 0xfa, 0x32, 0x66, 0xf6, 0x26, 0xcd,
+ 0xe9, 0x8a, 0x9d, 0xdf, 0x1a, 0x26, 0xd7, 0xf8, 0x58, 0xa1, 0xd6, 0x57, 0xa1, 0xdc, 0x93, 0x5e,
+ 0xe0, 0xaa, 0x98, 0xea, 0xa8, 0xe4, 0xb5, 0x5b, 0xf6, 0x9f, 0xff, 0x43, 0x38, 0x29, 0x2a, 0x2b,
+ 0xa8, 0xf7, 0xfd, 0x84, 0x6c, 0xcf, 0x87, 0x03, 0x5a, 0xb0, 0x60, 0x01, 0xf4, 0xea, 0x11, 0x4b,
+ 0xcb, 0xdb, 0xb7, 0xef, 0xa4, 0xa4, 0xa6, 0x01, 0xa2, 0xdb, 0xb6, 0x6d, 0x03, 0xb3, 0xfd, 0xb0,
+ 0x66, 0x4d, 0x53, 0x53, 0x73, 0x75, 0x4d, 0x2d, 0xa8, 0x15, 0x1c, 0x52, 0x50, 0x58, 0x04, 0x85,
+ 0xf0, 0xf8, 0xf1, 0xe3, 0xdf, 0x53, 0x12, 0xfc, 0x29, 0x0c, 0x82, 0xd9, 0xc4, 0xc4, 0x04, 0xf5,
+ 0x3a, 0x2e, 0x3e, 0xfe, 0xd2, 0xa5, 0xcb, 0xd0, 0x57, 0xd0, 0xf9, 0x32, 0xa3, 0x36, 0x53, 0x78,
+ 0x27, 0xc4, 0x4a, 0xa0, 0xf7, 0x0d, 0x86, 0xd2, 0x44, 0x39, 0x82, 0x8d, 0xbf, 0xfc, 0xf2, 0x4b,
+ 0xb8, 0x4c, 0x70, 0x3b, 0xa2, 0x36, 0x94, 0x9d, 0xa1, 0xbe, 0x9e, 0xbd, 0xa9, 0x81, 0xab, 0xed,
+ 0x81, 0xbb, 0x8e, 0xfa, 0xc1, 0x76, 0x1b, 0xa3, 0xad, 0xd4, 0x12, 0xac, 0xe8, 0xc9, 0xf6, 0xf4,
+ 0xf4, 0x13, 0xf4, 0xac, 0x53, 0xb4, 0x9c, 0x73, 0xb4, 0x7c, 0x17, 0x5a, 0x91, 0xbb, 0x42, 0xc9,
+ 0x25, 0x85, 0xb2, 0xab, 0x0a, 0xe5, 0x37, 0xe4, 0x2b, 0x6f, 0xc9, 0x31, 0xee, 0xca, 0xd5, 0xf8,
+ 0xc8, 0xd5, 0xf9, 0xc9, 0x36, 0xf8, 0xcb, 0x36, 0x06, 0xca, 0x36, 0x07, 0xcb, 0xb4, 0x86, 0x2e,
+ 0x68, 0x8b, 0x9c, 0xdf, 0x19, 0x3b, 0xaf, 0x27, 0x71, 0x0e, 0x2b, 0x75, 0x66, 0x7f, 0xe6, 0xf4,
+ 0x81, 0xdc, 0xa9, 0x83, 0x85, 0x93, 0xb9, 0x25, 0x93, 0x86, 0xca, 0xbe, 0x7d, 0xb9, 0xb1, 0xd4,
+ 0x6b, 0xd3, 0xb7, 0xaf, 0xa6, 0x17, 0xdf, 0x0f, 0x95, 0x7e, 0xcb, 0x29, 0x02, 0x5c, 0xa7, 0xb2,
+ 0xd2, 0xa7, 0xf7, 0x24, 0xce, 0xea, 0x8c, 0xfe, 0xae, 0xed, 0x99, 0x4c, 0x63, 0xa0, 0x5c, 0xad,
+ 0x9f, 0x6c, 0xd5, 0x1d, 0xb9, 0x92, 0xcb, 0x0a, 0xb9, 0xe7, 0x68, 0x49, 0x76, 0xf4, 0x5b, 0xdb,
+ 0xe7, 0xff, 0xd7, 0xa8, 0x9a, 0x4e, 0x4d, 0xdb, 0x44, 0x0d, 0xc5, 0x9b, 0x82, 0xbb, 0xbe, 0xff,
+ 0xfe, 0xfb, 0x7d, 0x06, 0x06, 0x17, 0xdc, 0xdc, 0x11, 0x8f, 0x57, 0x54, 0x56, 0x45, 0x44, 0x46,
+ 0xce, 0x99, 0x33, 0x07, 0x0c, 0x7c, 0xe4, 0x88, 0x65, 0x57, 0x77, 0x37, 0x10, 0x5b, 0x54, 0x5c,
+ 0x02, 0xb8, 0x32, 0xaa, 0x6b, 0x80, 0x58, 0xa7, 0x9f, 0x7e, 0xfa, 0xad, 0x37, 0x44, 0xfe, 0x33,
+ 0x1a, 0x38, 0xdc, 0xf1, 0xf8, 0x71, 0x72, 0x3b, 0xcb, 0x08, 0x77, 0x77, 0x0f, 0x23, 0x23, 0x63,
+ 0xc4, 0x08, 0x10, 0x24, 0x54, 0x5b, 0xf1, 0x6f, 0xb7, 0x3b, 0x98, 0x58, 0x48, 0xa0, 0xbc, 0x50,
+ 0x41, 0xa6, 0x4f, 0x9f, 0x2e, 0x23, 0x23, 0x83, 0x00, 0x10, 0xf1, 0x89, 0xa6, 0xa6, 0xe6, 0xbe,
+ 0xbd, 0x7a, 0x16, 0x87, 0x0e, 0x38, 0x58, 0x99, 0xb9, 0x38, 0x98, 0x7b, 0xd9, 0xeb, 0x05, 0x5b,
+ 0xad, 0x89, 0x30, 0x57, 0x8d, 0x39, 0xa2, 0x94, 0x60, 0xa3, 0x94, 0x64, 0xa7, 0x98, 0xee, 0x48,
+ 0xcf, 0xfa, 0x89, 0x96, 0x7b, 0x86, 0x96, 0xef, 0xac, 0x50, 0x70, 0x41, 0xa1, 0xc8, 0x43, 0xa1,
+ 0xf4, 0x8a, 0x7c, 0xc5, 0x75, 0xf9, 0xca, 0x9b, 0x72, 0x0c, 0x2f, 0xd9, 0x5a, 0x1f, 0xd9, 0xba,
+ 0x07, 0x2f, 0xd0, 0xdb, 0x16, 0x36, 0x1f, 0xd0, 0xea, 0x4e, 0x98, 0xcd, 0x24, 0xa1, 0xcb, 0xce,
+ 0x9b, 0xca, 0x29, 0x9c, 0x34, 0x54, 0x32, 0x81, 0x57, 0xf6, 0xab, 0xb8, 0x7d, 0x99, 0x80, 0x73,
+ 0x6e, 0xc9, 0x04, 0x02, 0xae, 0x39, 0xd3, 0xfa, 0xd2, 0x66, 0xf4, 0x26, 0xcc, 0xe9, 0x88, 0xfa,
+ 0xae, 0xe5, 0xa9, 0x4c, 0xc3, 0x23, 0xfc, 0x96, 0x4c, 0xe5, 0x6d, 0x39, 0xfc, 0x7a, 0xa1, 0xab,
+ 0x42, 0xd6, 0x4f, 0xf4, 0x04, 0x2b, 0x9a, 0xf3, 0xc6, 0xd9, 0xa3, 0x5f, 0x93, 0xea, 0x64, 0x19,
+ 0x37, 0x6e, 0x1c, 0xa5, 0x07, 0x10, 0x72, 0x9e, 0x3e, 0x7d, 0x26, 0x28, 0xe8, 0x49, 0x7e, 0x7e,
+ 0x41, 0x53, 0x73, 0x8b, 0x91, 0xf1, 0x41, 0x6a, 0xb3, 0xe3, 0xfb, 0x0f, 0x1e, 0x00, 0xb1, 0x75,
+ 0xf5, 0xf5, 0x54, 0x2f, 0x58, 0x4b, 0x4b, 0x6b, 0x61, 0x61, 0xa1, 0xf4, 0x50, 0xc6, 0xbf, 0x8c,
+ 0x32, 0xe4, 0x27, 0x54, 0x41, 0x59, 0x59, 0x39, 0x94, 0x95, 0x8b, 0xeb, 0x05, 0x03, 0x83, 0xfd,
+ 0x88, 0x0e, 0x40, 0x08, 0x94, 0xe6, 0xff, 0x4d, 0x41, 0x8b, 0x9b, 0x83, 0x82, 0xa8, 0x55, 0xa1,
+ 0xf0, 0x18, 0x10, 0x24, 0xa0, 0x5c, 0xb8, 0x4e, 0x48, 0x5c, 0xd0, 0xd1, 0x0f, 0x3f, 0xfc, 0xb0,
+ 0x75, 0xeb, 0xd6, 0x1d, 0x3b, 0x76, 0x1a, 0x1a, 0x1e, 0x38, 0x6c, 0x61, 0x71, 0xd2, 0xc6, 0xe2,
+ 0xaa, 0xad, 0x81, 0xaf, 0xe5, 0xd6, 0xc7, 0xe6, 0xcb, 0x9e, 0x1d, 0x5e, 0x12, 0x65, 0xb5, 0x38,
+ 0xde, 0x46, 0x39, 0xe9, 0xa8, 0x62, 0x9a, 0x03, 0x2d, 0xc3, 0x89, 0x96, 0x7d, 0x8a, 0x60, 0xb9,
+ 0xfc, 0x0b, 0xb4, 0xa2, 0x8b, 0x0a, 0xa5, 0x57, 0xe5, 0x2b, 0x3d, 0x49, 0xf4, 0xfa, 0xca, 0xd6,
+ 0x3f, 0x94, 0x6d, 0x0a, 0x22, 0xa0, 0xdb, 0x11, 0x3d, 0xaf, 0x27, 0x61, 0x0e, 0x2b, 0x65, 0x66,
+ 0x1f, 0x58, 0x37, 0x67, 0xda, 0x60, 0xc1, 0x64, 0x6e, 0xd1, 0x24, 0x6e, 0xc9, 0x44, 0x6e, 0xe9,
+ 0x04, 0xf0, 0x27, 0x91, 0xca, 0x5e, 0x4d, 0x25, 0x13, 0x70, 0x88, 0x5b, 0x3c, 0x11, 0x58, 0x65,
+ 0xe7, 0x4d, 0xe9, 0xcb, 0x9e, 0x0e, 0xd8, 0xf7, 0xc4, 0xcf, 0x6d, 0x8f, 0x9c, 0xdf, 0xfc, 0x44,
+ 0x06, 0xb7, 0xad, 0xf1, 0x96, 0xad, 0xb8, 0x29, 0x07, 0xc2, 0x07, 0xf3, 0xc3, 0x05, 0x24, 0xdb,
+ 0xd1, 0x63, 0xcc, 0x68, 0xdb, 0xe4, 0xbf, 0x16, 0x63, 0x15, 0x4e, 0x04, 0x95, 0x11, 0x2c, 0xaa,
+ 0xac, 0xac, 0xbc, 0x69, 0xd3, 0x66, 0xe8, 0xae, 0xcb, 0x57, 0xae, 0x44, 0x46, 0x46, 0x95, 0x95,
+ 0x57, 0xb4, 0xb7, 0x77, 0xf8, 0xfb, 0x3f, 0xa4, 0x9c, 0xfe, 0xb4, 0x69, 0xd3, 0x18, 0x8c, 0x6a,
+ 0x16, 0xab, 0xaf, 0xb3, 0xab, 0xbb, 0xa3, 0xb3, 0xb3, 0xbb, 0xa7, 0xa7, 0xbf, 0x7f, 0x20, 0x2c,
+ 0x2c, 0x4c, 0x7a, 0xc5, 0xef, 0xbf, 0x4c, 0x6c, 0x60, 0xd4, 0xc0, 0xc7, 0x8f, 0x8b, 0x8b, 0x4b,
+ 0x42, 0x9e, 0x85, 0x3a, 0x3b, 0x9f, 0x47, 0x68, 0x00, 0x42, 0x00, 0x78, 0x00, 0x5a, 0xc0, 0xe9,
+ 0x63, 0xad, 0xd8, 0xf9, 0x06, 0xdc, 0x8a, 0x03, 0x37, 0x70, 0xce, 0xb8, 0x71, 0x5f, 0x7e, 0xf3,
+ 0xcd, 0xb7, 0x08, 0x9f, 0xc1, 0x4b, 0x40, 0x2f, 0x9d, 0x4e, 0x57, 0x53, 0x53, 0x5b, 0xb1, 0x62,
+ 0xe5, 0xc6, 0x8d, 0x9b, 0x74, 0x74, 0x74, 0xf6, 0xee, 0xdd, 0x6b, 0x6a, 0x62, 0xe2, 0x68, 0x69,
+ 0xea, 0x66, 0x6d, 0x70, 0xcb, 0x52, 0xc7, 0xf7, 0xf0, 0xc6, 0x40, 0xab, 0x35, 0xe1, 0xd6, 0xcb,
+ 0x62, 0xad, 0x55, 0x13, 0x6d, 0x14, 0x01, 0x9b, 0xb4, 0xe3, 0x40, 0x2f, 0x2d, 0xcf, 0x99, 0x56,
+ 0xe4, 0xa6, 0x50, 0x7a, 0x59, 0xbe, 0xc2, 0x53, 0x9e, 0x71, 0x57, 0x16, 0xbe, 0xbb, 0x21, 0x40,
+ 0xb6, 0x25, 0x58, 0xa6, 0x3d, 0x7c, 0x7e, 0x67, 0xcc, 0xbc, 0xee, 0x84, 0x39, 0xcc, 0x94, 0x99,
+ 0xac, 0xf4, 0x19, 0x7d, 0x59, 0x04, 0x7a, 0x07, 0xf2, 0xa6, 0x02, 0x93, 0x83, 0xf9, 0x53, 0xd8,
+ 0xa3, 0x53, 0xde, 0x14, 0xe2, 0xfb, 0xdc, 0x69, 0xfd, 0xd9, 0xd3, 0xfa, 0xd2, 0x67, 0x30, 0x53,
+ 0x66, 0x75, 0xc5, 0xcd, 0xc5, 0xe5, 0x4d, 0x80, 0xeb, 0x03, 0xd9, 0xea, 0x7b, 0xb2, 0xb8, 0x73,
+ 0x31, 0xe0, 0x7a, 0x9e, 0x06, 0x76, 0xc5, 0xef, 0xc6, 0x1d, 0xa6, 0xdd, 0xd6, 0x9d, 0x3f, 0xee,
+ 0xef, 0xff, 0x8d, 0x3a, 0x08, 0xa0, 0xca, 0xc9, 0xc9, 0x81, 0x24, 0x8d, 0x8c, 0x8c, 0x8e, 0x1f,
+ 0x3f, 0xee, 0xe6, 0xe6, 0x7e, 0xcf, 0xdb, 0x07, 0x5e, 0x2c, 0x3b, 0x27, 0xa7, 0xbe, 0xa1, 0xb1,
+ 0xbb, 0xbb, 0x27, 0x39, 0x39, 0x45, 0x3c, 0x3b, 0x5e, 0x5d, 0x5d, 0x9d, 0x3d, 0xc8, 0xe9, 0x65,
+ 0x32, 0x01, 0x57, 0xa4, 0x9e, 0x9e, 0x5e, 0x40, 0x57, 0x7a, 0xd9, 0xba, 0xbf, 0x4c, 0xc2, 0x64,
+ 0x65, 0x65, 0x83, 0x83, 0x83, 0xf3, 0x0b, 0x0a, 0x03, 0x03, 0x1f, 0xff, 0x74, 0xf2, 0xe4, 0x8e,
+ 0x1d, 0x3b, 0xe0, 0xa3, 0xe1, 0xac, 0xff, 0x45, 0x82, 0xf6, 0x77, 0xd8, 0x3c, 0x54, 0x4c, 0xb9,
+ 0x80, 0x2e, 0x7e, 0x11, 0x04, 0x85, 0xe8, 0x0c, 0xc4, 0x0b, 0xaa, 0x99, 0x34, 0x69, 0x12, 0xaa,
+ 0x0f, 0xb4, 0x0a, 0x62, 0xd8, 0x45, 0x8b, 0x16, 0x69, 0x68, 0x68, 0x40, 0x6f, 0xff, 0xf8, 0xe3,
+ 0x8f, 0xbb, 0x77, 0xef, 0x01, 0x24, 0x6c, 0xcc, 0x0f, 0x9d, 0xb5, 0x34, 0xbc, 0x6c, 0xb9, 0xeb,
+ 0x8e, 0xb5, 0xf6, 0x43, 0xdb, 0xad, 0xa1, 0xd6, 0x2b, 0xe3, 0x2c, 0x95, 0x13, 0x6d, 0xe8, 0x69,
+ 0xc7, 0x80, 0x25, 0x5a, 0xde, 0x39, 0x5a, 0xa1, 0x1b, 0x21, 0x1b, 0xa0, 0x19, 0xaa, 0xbd, 0xe4,
+ 0xea, 0xee, 0xcb, 0x36, 0x06, 0xc8, 0x34, 0x53, 0xd0, 0x8d, 0x9e, 0xd7, 0x1d, 0x3f, 0xa7, 0x27,
+ 0x71, 0x76, 0x6f, 0xf2, 0x2c, 0x02, 0xc0, 0xa9, 0x33, 0x59, 0x69, 0x33, 0x88, 0x94, 0x8e, 0x7f,
+ 0xc9, 0x8f, 0x48, 0x29, 0x33, 0x99, 0x49, 0xb3, 0x7a, 0x9e, 0x23, 0xce, 0x9a, 0x07, 0xa2, 0x06,
+ 0x5d, 0x43, 0x72, 0x80, 0xbd, 0xa1, 0xa2, 0x8b, 0x2f, 0x2a, 0xa0, 0x5e, 0x64, 0x3a, 0xd1, 0x93,
+ 0x6c, 0xe9, 0xb1, 0xe6, 0xb4, 0xeb, 0xda, 0xdf, 0x2d, 0x99, 0x35, 0x0e, 0x39, 0x86, 0xca, 0xbe,
+ 0x7d, 0xbb, 0x2e, 0x02, 0x84, 0x43, 0x87, 0x0e, 0xe1, 0xf1, 0x0e, 0x1f, 0x3e, 0x02, 0x25, 0x70,
+ 0xf7, 0xae, 0x57, 0x4c, 0x6c, 0x1c, 0xd8, 0x15, 0x7e, 0xff, 0xe6, 0xcd, 0x9b, 0x10, 0x3f, 0xe2,
+ 0x91, 0x8a, 0x96, 0x96, 0x96, 0x03, 0x6c, 0x36, 0x50, 0xda, 0xd6, 0x06, 0xea, 0xed, 0xe8, 0xed,
+ 0x65, 0xd6, 0xd4, 0xd6, 0xbd, 0xcd, 0x60, 0xcb, 0xff, 0x70, 0x43, 0xa8, 0x85, 0xf0, 0x27, 0x2a,
+ 0x2a, 0x2a, 0x3b, 0x3b, 0xc7, 0xcf, 0xef, 0xbe, 0xc3, 0xb1, 0x63, 0x5a, 0x5a, 0xda, 0x2f, 0x40,
+ 0xfb, 0x91, 0x86, 0x7f, 0xbf, 0x25, 0x6e, 0xc5, 0xac, 0x4b, 0xa1, 0x97, 0x7a, 0x36, 0xaa, 0x59,
+ 0x0c, 0x92, 0x0f, 0xca, 0x61, 0xea, 0xd4, 0xa9, 0x70, 0xb5, 0x32, 0x32, 0xb2, 0x4a, 0x4a, 0x4a,
+ 0x20, 0xa8, 0x55, 0xab, 0x56, 0x6d, 0xde, 0xbc, 0x59, 0x57, 0x57, 0x77, 0xbf, 0xc1, 0x3e, 0x4b,
+ 0x13, 0xa3, 0x93, 0x87, 0xf7, 0x7b, 0x58, 0xeb, 0x7b, 0xdb, 0xed, 0x0c, 0xb1, 0x5e, 0x13, 0x7b,
+ 0x58, 0xf9, 0xb9, 0x35, 0x3d, 0x15, 0xd0, 0x3d, 0x49, 0x2f, 0x38, 0xaf, 0x50, 0xec, 0x21, 0x5f,
+ 0x76, 0x95, 0x88, 0xd7, 0xaa, 0xbd, 0xe5, 0xea, 0x09, 0xad, 0x2b, 0x43, 0x45, 0x6a, 0xed, 0x11,
+ 0xf3, 0xdb, 0xa3, 0xbe, 0x83, 0xe2, 0xed, 0x8a, 0x9d, 0x0b, 0x64, 0x8a, 0x13, 0xc2, 0x37, 0x10,
+ 0x32, 0x54, 0x6b, 0x5b, 0xf8, 0xfc, 0x96, 0x10, 0xc4, 0x59, 0x32, 0x08, 0xf1, 0x10, 0xeb, 0x95,
+ 0x5d, 0x97, 0x47, 0x00, 0x88, 0xba, 0x90, 0x71, 0x9c, 0x86, 0xaa, 0x11, 0x65, 0x4a, 0x73, 0xd7,
+ 0x92, 0xd1, 0x5d, 0xa1, 0xb4, 0x61, 0xdd, 0xda, 0x9d, 0x3b, 0x77, 0xea, 0xeb, 0xeb, 0x6b, 0x6b,
+ 0xeb, 0xac, 0x5f, 0xbf, 0x01, 0xd5, 0x0a, 0xaa, 0xc6, 0xd8, 0xf8, 0x20, 0xdc, 0x16, 0x5c, 0x58,
+ 0x5e, 0x5e, 0x7e, 0x46, 0x66, 0x26, 0xa4, 0xec, 0x94, 0x29, 0xaf, 0x8c, 0x13, 0x08, 0x0c, 0x0c,
+ 0xec, 0xeb, 0xef, 0xef, 0xe8, 0xec, 0x6a, 0x05, 0x64, 0x3b, 0x3a, 0x21, 0x0f, 0x22, 0x22, 0x22,
+ 0x3f, 0xfd, 0xf4, 0x7d, 0x26, 0x71, 0xfc, 0xa7, 0x19, 0x38, 0x4d, 0x53, 0x4b, 0x2b, 0x31, 0x31,
+ 0x29, 0x3d, 0x3d, 0xc3, 0xeb, 0xde, 0x3d, 0xdb, 0xa3, 0x47, 0xf1, 0x51, 0x79, 0xd1, 0x22, 0x20,
+ 0x04, 0x87, 0x7e, 0xd3, 0xad, 0xeb, 0xde, 0x06, 0xc0, 0xe2, 0x3d, 0xf5, 0xc4, 0xf4, 0x0b, 0xe7,
+ 0x3b, 0x79, 0xf2, 0x64, 0x31, 0xfd, 0xaa, 0xaa, 0xaa, 0xae, 0x58, 0xb1, 0x02, 0xbe, 0x18, 0xe8,
+ 0x3d, 0x68, 0xb8, 0xdf, 0xde, 0xdc, 0xc8, 0xd5, 0xf6, 0xa0, 0xb7, 0x83, 0x5e, 0xa8, 0xe5, 0xf2,
+ 0x38, 0x0b, 0x7a, 0xd2, 0x51, 0x7a, 0xfa, 0x71, 0x5a, 0xce, 0x19, 0x5a, 0x81, 0x0b, 0x0d, 0xf4,
+ 0x08, 0xd4, 0x21, 0xc6, 0xaf, 0xf1, 0x26, 0x58, 0xb7, 0xe1, 0x91, 0x4c, 0x43, 0x20, 0x21, 0x77,
+ 0x01, 0x60, 0xa9, 0x84, 0xef, 0x89, 0x38, 0xae, 0xfe, 0xa1, 0x0c, 0x54, 0x31, 0x2e, 0x01, 0xe6,
+ 0xa1, 0x37, 0x72, 0xcf, 0xd2, 0xd2, 0x8f, 0x23, 0xd4, 0xa2, 0x47, 0x99, 0x2d, 0x0c, 0xb0, 0xfd,
+ 0xf1, 0x94, 0xb5, 0xa9, 0xe1, 0x7e, 0x83, 0xdd, 0xbb, 0x77, 0x6f, 0xd8, 0xb0, 0x11, 0x0a, 0x5c,
+ 0x51, 0x51, 0x51, 0x5e, 0x5e, 0x01, 0x59, 0x87, 0x87, 0x01, 0xc7, 0x7a, 0xde, 0xbc, 0x09, 0x19,
+ 0x90, 0x97, 0x9f, 0xaf, 0xa5, 0xad, 0x2d, 0xb1, 0x3e, 0x06, 0xde, 0xa5, 0xae, 0xae, 0x9e, 0xc9,
+ 0xea, 0x03, 0x62, 0xc1, 0xb0, 0x5d, 0xdd, 0x3d, 0x03, 0xec, 0xc1, 0x43, 0x87, 0x4c, 0x5e, 0x53,
+ 0x44, 0x7f, 0x99, 0xa4, 0x81, 0x4e, 0xf7, 0xef, 0xdf, 0x8f, 0x48, 0x36, 0x39, 0x25, 0xf5, 0xf6,
+ 0xed, 0x3b, 0x36, 0x36, 0xb6, 0xdb, 0xb6, 0xfd, 0xa8, 0xa8, 0xa8, 0x04, 0x60, 0xfc, 0xe1, 0x3b,
+ 0xde, 0xfe, 0xaf, 0x11, 0xe5, 0x40, 0x89, 0x07, 0x00, 0x18, 0xe8, 0x05, 0xfd, 0xe2, 0xc1, 0xf0,
+ 0xd8, 0x5f, 0x7d, 0x35, 0x9e, 0x1a, 0x89, 0x37, 0x77, 0xee, 0x5c, 0xa0, 0x77, 0xf1, 0xe2, 0xc5,
+ 0x10, 0x8a, 0x9a, 0x9a, 0x9a, 0x06, 0xfa, 0xfa, 0x56, 0x16, 0xa6, 0x17, 0xec, 0x4d, 0xfd, 0xad,
+ 0xb7, 0x86, 0x99, 0xab, 0xc5, 0x5a, 0x2e, 0x4c, 0xb2, 0x53, 0xcc, 0x38, 0x41, 0x03, 0xe4, 0x0a,
+ 0x2f, 0x90, 0x0d, 0x65, 0xd7, 0xe4, 0x2a, 0x6e, 0xca, 0x33, 0xee, 0x80, 0x78, 0x89, 0x60, 0xaa,
+ 0xd6, 0x87, 0x10, 0xbd, 0xe0, 0xd2, 0x5a, 0x3f, 0x99, 0xda, 0xfb, 0xe4, 0x1f, 0x3e, 0x32, 0x35,
+ 0xde, 0x32, 0x55, 0x77, 0xe5, 0xca, 0x3d, 0xe5, 0x21, 0x8c, 0x0b, 0x5c, 0x09, 0xd8, 0xa7, 0x1d,
+ 0x23, 0xe0, 0x1a, 0x69, 0xb6, 0xc8, 0xc7, 0x76, 0x87, 0x83, 0xad, 0x95, 0x9e, 0x9e, 0x1e, 0x18,
+ 0x15, 0x8a, 0x05, 0xbf, 0x8e, 0x0a, 0x3e, 0x69, 0x12, 0xea, 0xd1, 0x4c, 0xc4, 0x8f, 0x20, 0x5b,
+ 0x48, 0x82, 0x90, 0x90, 0x67, 0xa5, 0xa5, 0x65, 0xb6, 0xb6, 0xb6, 0xd2, 0x2b, 0xf9, 0x00, 0xdb,
+ 0x88, 0xb3, 0xfa, 0x07, 0xd8, 0xbd, 0x4c, 0x56, 0x4f, 0x2f, 0xb3, 0xaf, 0xaf, 0x9f, 0xd5, 0xd7,
+ 0xf7, 0x21, 0xe3, 0x46, 0xfe, 0x03, 0x0d, 0x00, 0xb0, 0xb3, 0xb3, 0xaf, 0xac, 0x62, 0x24, 0x25,
+ 0x25, 0xdf, 0xba, 0x75, 0xdb, 0xca, 0xca, 0x9a, 0xea, 0x0e, 0xfb, 0xf6, 0xdb, 0x6f, 0x01, 0x8f,
+ 0x3f, 0x1c, 0xb4, 0xa3, 0x6d, 0x34, 0x80, 0xc5, 0xea, 0xf7, 0xb3, 0xcf, 0x3e, 0x43, 0x20, 0x89,
+ 0x42, 0x07, 0xf7, 0x52, 0x2d, 0x66, 0x2b, 0x57, 0xae, 0x44, 0xbd, 0x33, 0x30, 0x30, 0x38, 0x7a,
+ 0xc4, 0xec, 0x8a, 0xcd, 0x5e, 0xff, 0xc3, 0x6b, 0x9f, 0x1d, 0xd1, 0x88, 0xb7, 0x56, 0x46, 0xb8,
+ 0x94, 0xe1, 0x04, 0xf8, 0x21, 0x7a, 0x52, 0x28, 0x24, 0x9a, 0x79, 0xe5, 0xcb, 0xae, 0xc8, 0x97,
+ 0x5d, 0x93, 0x2f, 0xbf, 0x2e, 0x0f, 0x99, 0x8a, 0xc0, 0x8a, 0x4a, 0xf8, 0x08, 0x5e, 0x2d, 0xbd,
+ 0x44, 0x50, 0x6b, 0xbe, 0x33, 0x04, 0x06, 0x2d, 0xc5, 0x9e, 0x1e, 0x7f, 0x84, 0x16, 0x66, 0xa6,
+ 0x7a, 0xd3, 0x66, 0x8f, 0xa9, 0xa9, 0x09, 0xf2, 0x07, 0xbf, 0x02, 0xac, 0xa2, 0xca, 0xa0, 0xee,
+ 0x50, 0x02, 0x66, 0xfa, 0x74, 0x62, 0x3c, 0xdb, 0x01, 0x23, 0x23, 0xe4, 0x61, 0x66, 0x66, 0x56,
+ 0x78, 0x78, 0xf8, 0x98, 0x93, 0xd9, 0xf7, 0xed, 0xdb, 0xc7, 0xe1, 0x70, 0x07, 0x39, 0x5c, 0x62,
+ 0x79, 0x57, 0x36, 0x31, 0x77, 0x21, 0x68, 0xac, 0x35, 0xc9, 0xff, 0xb2, 0x37, 0x1b, 0xca, 0xdd,
+ 0xc3, 0xc3, 0x83, 0x51, 0x5d, 0x9d, 0x98, 0x94, 0xe4, 0xe9, 0xe9, 0x69, 0x41, 0x74, 0x87, 0xad,
+ 0x9f, 0x3f, 0x7f, 0x3e, 0x90, 0x40, 0x8d, 0xa4, 0xfd, 0xa3, 0xa1, 0x3a, 0x86, 0x49, 0xa0, 0x17,
+ 0x95, 0x0b, 0xd0, 0x05, 0xa7, 0x01, 0xba, 0x33, 0x67, 0xce, 0x44, 0xe4, 0xae, 0xa6, 0xb6, 0x78,
+ 0xcd, 0x9a, 0xb5, 0x88, 0x89, 0x0e, 0x19, 0x1b, 0x9f, 0xb4, 0x3c, 0x78, 0xeb, 0x88, 0x76, 0x80,
+ 0xe5, 0xfa, 0x48, 0xeb, 0xa5, 0x09, 0xd6, 0x4a, 0x80, 0x6e, 0x3a, 0xd9, 0xc2, 0x00, 0xe2, 0x45,
+ 0xec, 0x5f, 0xe0, 0xa2, 0x50, 0xe0, 0xaa, 0x00, 0x06, 0x16, 0xa7, 0x7c, 0x17, 0x22, 0x82, 0xcb,
+ 0x39, 0x4d, 0x4b, 0x3f, 0x41, 0xa8, 0x8b, 0x58, 0x0b, 0x7a, 0x88, 0xc5, 0xd2, 0xeb, 0x36, 0x7a,
+ 0x46, 0x07, 0x0c, 0xd7, 0xac, 0x59, 0x03, 0x4a, 0x9f, 0x32, 0x65, 0x0a, 0x50, 0x8a, 0x1f, 0xa5,
+ 0xa4, 0x0b, 0x70, 0x3b, 0x87, 0xdc, 0xea, 0xd4, 0xc6, 0xd6, 0x36, 0x28, 0xe8, 0x49, 0x41, 0x61,
+ 0x91, 0xa3, 0xe3, 0xf1, 0x31, 0xfb, 0x2e, 0x2f, 0x5e, 0xbc, 0x48, 0x2d, 0xfe, 0xcc, 0x25, 0x37,
+ 0xf7, 0xe4, 0x0e, 0x0d, 0x49, 0xaf, 0xed, 0xf9, 0x97, 0xbd, 0x8d, 0x81, 0x2e, 0xbc, 0xbc, 0xbc,
+ 0x10, 0xda, 0x46, 0x45, 0x47, 0xbb, 0x7b, 0x5c, 0x3c, 0x70, 0xc0, 0xe8, 0xfb, 0xa5, 0x4b, 0xc1,
+ 0x5a, 0xc8, 0xf6, 0x3f, 0x44, 0xd0, 0xbe, 0x93, 0x8d, 0x6e, 0x76, 0x20, 0x5b, 0xcc, 0x08, 0xd6,
+ 0x85, 0xb0, 0x01, 0x0d, 0xd2, 0xe9, 0xf4, 0xa5, 0x4b, 0x97, 0x6e, 0xda, 0xb4, 0x69, 0xaf, 0x9e,
+ 0x9e, 0xb5, 0xa9, 0xb1, 0xab, 0xe5, 0xbe, 0x3b, 0x36, 0xba, 0x41, 0xb6, 0x1b, 0xa2, 0x0f, 0xab,
+ 0x24, 0x58, 0x12, 0x51, 0x7f, 0x8a, 0x03, 0x3d, 0xcd, 0x91, 0x0e, 0xd9, 0x90, 0xe9, 0x44, 0xcb,
+ 0xfc, 0x89, 0x4e, 0xa5, 0x8c, 0x13, 0x74, 0xc8, 0x00, 0x00, 0x1b, 0xe7, 0x44, 0x9b, 0x29, 0x3e,
+ 0xb6, 0x58, 0xe5, 0x66, 0xa5, 0x7f, 0xc0, 0x40, 0x1f, 0xec, 0xbd, 0x60, 0xc1, 0x02, 0xe4, 0x15,
+ 0x15, 0x28, 0x51, 0xa3, 0xe2, 0xc9, 0x95, 0x1e, 0xc7, 0x81, 0xde, 0x11, 0x76, 0x9d, 0x3c, 0x79,
+ 0x2a, 0x3a, 0x26, 0x36, 0x2e, 0x2e, 0x7e, 0xcc, 0x45, 0xc6, 0x60, 0xd1, 0xd1, 0xd1, 0x00, 0x2a,
+ 0xa8, 0x15, 0x09, 0xb8, 0xad, 0xaa, 0x62, 0x48, 0x4f, 0xc1, 0xfe, 0xcb, 0xde, 0xc6, 0xe0, 0x61,
+ 0xc1, 0x4b, 0x0f, 0x1f, 0x3e, 0x2c, 0x2c, 0x2a, 0x86, 0x9f, 0x42, 0xce, 0x23, 0x0a, 0xa3, 0xd1,
+ 0xe9, 0xd0, 0x06, 0xff, 0xb6, 0x34, 0x2b, 0x6d, 0x62, 0xe8, 0x7e, 0x42, 0x3a, 0x0e, 0x54, 0x37,
+ 0x04, 0x6b, 0xd0, 0xba, 0x40, 0x05, 0x34, 0xe7, 0xaa, 0x55, 0xab, 0xb4, 0xb4, 0xb4, 0x0e, 0xec,
+ 0x37, 0x70, 0xb0, 0x30, 0x76, 0xb3, 0x36, 0xf4, 0xb1, 0xdf, 0xf5, 0xd4, 0x7a, 0x5d, 0xa4, 0xb9,
+ 0x4a, 0x8c, 0x19, 0xd1, 0xb8, 0x1a, 0x6f, 0x29, 0x4e, 0xd0, 0x00, 0xe0, 0x55, 0x5a, 0xb4, 0x29,
+ 0x3d, 0xd4, 0x6c, 0xb1, 0x97, 0x95, 0xf6, 0x09, 0x73, 0x83, 0xdd, 0x3b, 0x77, 0x2c, 0x5f, 0xbe,
+ 0x7c, 0xde, 0xbc, 0x79, 0x5f, 0x7f, 0xfd, 0xf5, 0x3f, 0xfe, 0xf1, 0x4f, 0xf1, 0x80, 0xb7, 0x91,
+ 0x79, 0x19, 0x5f, 0xc9, 0xc9, 0x13, 0x9b, 0xf3, 0x9e, 0x3b, 0xe7, 0x9c, 0xf0, 0xfc, 0xf9, 0xed,
+ 0x3b, 0x77, 0xc6, 0xec, 0x0e, 0x00, 0x2d, 0xe7, 0xe4, 0xe6, 0xf6, 0x0f, 0x0c, 0x40, 0xc4, 0x22,
+ 0xf8, 0x1a, 0x20, 0x86, 0xfa, 0x7b, 0xfe, 0xd5, 0x71, 0xf0, 0xde, 0x86, 0x22, 0x06, 0x1d, 0x3d,
+ 0x09, 0x0e, 0x4e, 0x4d, 0x4d, 0xbb, 0x79, 0xeb, 0x96, 0x91, 0x91, 0xd1, 0xf7, 0xdf, 0x2f, 0x9d,
+ 0x3e, 0x7d, 0xfa, 0x47, 0x59, 0xb0, 0xeb, 0x77, 0x36, 0xf1, 0x60, 0x06, 0x71, 0xff, 0x1a, 0xd4,
+ 0xc2, 0xac, 0x59, 0xb3, 0xe4, 0xe5, 0xe5, 0xd5, 0xd5, 0xd5, 0xd7, 0xad, 0x5b, 0xa7, 0xbb, 0x5d,
+ 0xf7, 0xe0, 0x81, 0xfd, 0x76, 0x16, 0x07, 0xcf, 0xda, 0x98, 0x5c, 0xb3, 0x3b, 0xe0, 0x6b, 0xb7,
+ 0xeb, 0xb1, 0xcd, 0xe6, 0x10, 0x8b, 0x15, 0xa1, 0x16, 0x1a, 0xa1, 0x16, 0xcb, 0x42, 0x8e, 0xac,
+ 0x0e, 0xb0, 0xd9, 0x7a, 0xcb, 0x4e, 0xdf, 0xe9, 0x88, 0x91, 0xf1, 0x7e, 0xfd, 0x2d, 0x5b, 0xb6,
+ 0xa8, 0xaa, 0xaa, 0xc1, 0xef, 0x83, 0xba, 0x25, 0xb4, 0xbd, 0x78, 0x26, 0x91, 0xac, 0xac, 0x2c,
+ 0xb9, 0x25, 0xc4, 0xa9, 0xe0, 0xa7, 0x21, 0xe6, 0xe6, 0xe6, 0xe3, 0xc7, 0x8f, 0x97, 0x9e, 0xe9,
+ 0x86, 0xe8, 0x20, 0x27, 0x37, 0xaf, 0xb1, 0xa9, 0xa9, 0xba, 0xa6, 0xb6, 0xa6, 0xb6, 0xae, 0xbe,
+ 0xbe, 0x01, 0x92, 0x00, 0x75, 0xea, 0x2d, 0x26, 0xc9, 0xbd, 0xd6, 0x50, 0x2b, 0x3f, 0xd6, 0x90,
+ 0xd4, 0x3f, 0xa3, 0xa1, 0x70, 0x21, 0xc6, 0x1e, 0x3f, 0x0e, 0xba, 0x7f, 0xff, 0x81, 0xc5, 0xe1,
+ 0xc3, 0x2b, 0x57, 0xae, 0x9a, 0x3d, 0x7b, 0x36, 0x25, 0x0c, 0xfe, 0x58, 0x04, 0xbe, 0xb7, 0x89,
+ 0x1b, 0xca, 0x00, 0x5d, 0x54, 0x3d, 0x4a, 0xe8, 0x02, 0xba, 0xa4, 0xd0, 0x55, 0x83, 0xef, 0x26,
+ 0x7a, 0xd6, 0xb4, 0x75, 0xf4, 0xf6, 0xec, 0x3e, 0x60, 0xb8, 0xdf, 0xe4, 0xa0, 0xb1, 0xb9, 0xe9,
+ 0x21, 0x73, 0x93, 0x43, 0x26, 0x07, 0x8d, 0x0c, 0x0d, 0xf6, 0xed, 0xd0, 0xd5, 0x85, 0x9e, 0x5f,
+ 0xbc, 0x78, 0x31, 0x94, 0x00, 0x34, 0x06, 0xf2, 0x81, 0xea, 0x10, 0x94, 0xd0, 0x48, 0xd4, 0x62,
+ 0x8f, 0x73, 0xe7, 0xcd, 0xfb, 0xe1, 0x87, 0x35, 0x87, 0x8f, 0x1c, 0xb9, 0x77, 0xcf, 0x3b, 0x2e,
+ 0x3e, 0x3e, 0x2b, 0x2b, 0x3b, 0xbf, 0xa0, 0xb0, 0xb0, 0xa8, 0x08, 0x3e, 0x8b, 0x48, 0x85, 0x45,
+ 0x05, 0x05, 0x85, 0x79, 0x79, 0xf9, 0x59, 0xd9, 0x39, 0xf1, 0x09, 0xcf, 0xa3, 0xa0, 0xbd, 0x62,
+ 0x62, 0x93, 0x93, 0x53, 0x10, 0xa3, 0xe1, 0x4b, 0x1c, 0x7d, 0x71, 0xda, 0xfb, 0xa4, 0x22, 0xc8,
+ 0x66, 0x89, 0x84, 0x2f, 0x8b, 0x8a, 0x8a, 0x8b, 0x8a, 0x4b, 0x88, 0xcd, 0xf3, 0xca, 0xca, 0xc9,
+ 0x7e, 0x0c, 0x08, 0x90, 0xea, 0xea, 0xea, 0x1a, 0xd4, 0x14, 0xd4, 0x95, 0xba, 0xfa, 0x06, 0xa4,
+ 0xfa, 0x86, 0x17, 0x89, 0xf8, 0x58, 0x57, 0x5f, 0x43, 0xae, 0x96, 0x80, 0xb3, 0xaa, 0x18, 0x8c,
+ 0x8a, 0xca, 0xca, 0xb2, 0xf2, 0x8a, 0xd2, 0xd2, 0xb2, 0xe2, 0x92, 0x52, 0xdc, 0xa7, 0xe8, 0x35,
+ 0x3f, 0xf4, 0x1e, 0x09, 0x5e, 0x26, 0x35, 0x2d, 0x8d, 0x1a, 0x43, 0xf8, 0xa1, 0x29, 0x25, 0x35,
+ 0x31, 0x31, 0x09, 0x1a, 0x2c, 0x3c, 0x22, 0xe2, 0x86, 0xa7, 0xe7, 0xc1, 0x43, 0x87, 0x96, 0x2d,
+ 0x5b, 0x8e, 0x28, 0xe6, 0xf3, 0xcf, 0x3f, 0xff, 0xd3, 0x71, 0xac, 0x84, 0x8d, 0x16, 0xba, 0x20,
+ 0x49, 0xbc, 0x11, 0xfc, 0x38, 0xa0, 0x0b, 0x0f, 0x02, 0x47, 0x0f, 0xe2, 0x5d, 0xb8, 0x70, 0x21,
+ 0x00, 0x8c, 0x60, 0x7f, 0xe9, 0x52, 0x0d, 0x38, 0x1a, 0xfc, 0xa1, 0xa2, 0xa2, 0x02, 0x4a, 0x84,
+ 0x12, 0x46, 0x90, 0x05, 0x2a, 0x43, 0x5d, 0xa6, 0xd6, 0x27, 0x91, 0x96, 0xf4, 0xd4, 0x82, 0xba,
+ 0x38, 0x0d, 0xc2, 0x43, 0x5b, 0x5b, 0xdb, 0xf6, 0xe8, 0x51, 0x77, 0x77, 0x8f, 0xdb, 0xb7, 0x6f,
+ 0x7b, 0xfb, 0xf8, 0xf8, 0xfa, 0xfa, 0x51, 0xe6, 0xeb, 0xeb, 0x8b, 0x4f, 0x77, 0xef, 0x7a, 0x5d,
+ 0xbf, 0x71, 0x03, 0x61, 0xc2, 0x79, 0x17, 0x57, 0xd7, 0x0b, 0x6e, 0x97, 0x2e, 0x5f, 0xf6, 0xf4,
+ 0xbc, 0x79, 0xd7, 0xcb, 0x0b, 0xe7, 0x8d, 0x9c, 0xf8, 0xf1, 0xec, 0x3e, 0x58, 0xe7, 0xc1, 0x03,
+ 0x7f, 0xff, 0x87, 0x8f, 0x1e, 0x05, 0x04, 0x06, 0x3e, 0x46, 0x40, 0x18, 0x1c, 0x1c, 0xf2, 0xec,
+ 0x59, 0x58, 0x58, 0x18, 0xca, 0x37, 0x22, 0x32, 0x32, 0x32, 0x8a, 0xa8, 0x37, 0x54, 0xc2, 0x47,
+ 0x7c, 0x19, 0x16, 0x1e, 0x8e, 0x13, 0x82, 0x9f, 0x3e, 0x85, 0x2c, 0xa4, 0x36, 0x32, 0xf3, 0x7f,
+ 0xf8, 0x10, 0x37, 0xc1, 0xad, 0x3e, 0xfa, 0xd3, 0x7d, 0x14, 0x43, 0xae, 0x79, 0x7b, 0x7b, 0x43,
+ 0x0f, 0x20, 0x33, 0xad, 0x6d, 0x6c, 0x7e, 0xd4, 0xd4, 0x54, 0x5a, 0xb8, 0x90, 0x6a, 0x98, 0xfd,
+ 0xb3, 0xe8, 0xd8, 0x37, 0x1b, 0xd5, 0x3d, 0x41, 0x75, 0xae, 0x7d, 0x32, 0xd2, 0xb3, 0x46, 0x36,
+ 0xed, 0x7e, 0x05, 0xd7, 0x3c, 0x71, 0x22, 0x31, 0x89, 0x60, 0x2a, 0x69, 0x93, 0x27, 0x4f, 0x01,
+ 0x9e, 0xc9, 0xb1, 0xca, 0x5f, 0x50, 0x23, 0x00, 0xdf, 0xd0, 0xca, 0x47, 0x8d, 0xd7, 0x42, 0x15,
+ 0x80, 0x3f, 0x02, 0xec, 0x37, 0x6f, 0xd9, 0xb2, 0x67, 0x8f, 0x9e, 0x91, 0x91, 0xb1, 0x89, 0x89,
+ 0xa9, 0xa9, 0xa9, 0x99, 0xa9, 0x19, 0x99, 0x4c, 0xcd, 0xf0, 0xd1, 0xc8, 0xd8, 0xd8, 0xc0, 0x60,
+ 0xff, 0x1e, 0x3d, 0xbd, 0x9d, 0xbb, 0x76, 0xed, 0xda, 0xbd, 0x5b, 0x6f, 0xef, 0xde, 0xfd, 0x86,
+ 0x86, 0x07, 0x0f, 0x1e, 0x7a, 0x79, 0xda, 0xc7, 0x4b, 0x66, 0x66, 0xc4, 0x06, 0x6a, 0xe6, 0x16,
+ 0xb0, 0xc3, 0x87, 0x41, 0xfd, 0x96, 0x96, 0xd6, 0xd6, 0x36, 0xb6, 0xb6, 0xc4, 0xdc, 0x5e, 0x7b,
+ 0x87, 0x63, 0xc7, 0x8e, 0x39, 0x3a, 0x3a, 0x1e, 0x3f, 0x7e, 0xfc, 0x04, 0x12, 0xfe, 0x8f, 0x4f,
+ 0xf8, 0x0e, 0x07, 0x50, 0xdd, 0x50, 0xf4, 0x96, 0x56, 0x56, 0x38, 0x1f, 0xd7, 0xe1, 0x62, 0xdc,
+ 0x02, 0xb7, 0xfa, 0xe8, 0x8f, 0xf7, 0x71, 0x12, 0x95, 0xab, 0x46, 0x46, 0x7b, 0xf6, 0xec, 0xd9,
+ 0xbc, 0x79, 0xb3, 0xaa, 0x9a, 0x1a, 0x8a, 0x00, 0x6e, 0xf4, 0xf7, 0x19, 0x66, 0xf0, 0x7b, 0x9a,
+ 0x44, 0xcf, 0x1a, 0xd5, 0xb4, 0x4b, 0x2d, 0x88, 0xfa, 0x0f, 0xd2, 0xf0, 0x07, 0x25, 0x0e, 0x71,
+ 0x14, 0xe7, 0x8c, 0x49, 0xad, 0xa3, 0xef, 0x06, 0x3c, 0xe3, 0xaa, 0xaf, 0xc6, 0x8f, 0x9f, 0x3e,
+ 0x7d, 0x06, 0xf4, 0x06, 0xc8, 0x56, 0x5d, 0x7d, 0x09, 0xa2, 0x00, 0x98, 0x86, 0x86, 0x06, 0xc5,
+ 0xdb, 0xf8, 0xa8, 0xbe, 0x64, 0x89, 0xaa, 0xaa, 0xaa, 0xb2, 0xb2, 0xb2, 0xa2, 0x12, 0x61, 0xca,
+ 0x8b, 0x16, 0x8d, 0x10, 0x3b, 0x75, 0xe2, 0x6f, 0x67, 0xcb, 0x60, 0xcb, 0x97, 0xaf, 0xa0, 0xa6,
+ 0xe3, 0xad, 0x26, 0xec, 0x07, 0x68, 0x18, 0xca, 0xf0, 0x07, 0x3e, 0xe0, 0x2b, 0x44, 0xa6, 0x38,
+ 0x8c, 0x93, 0x70, 0x2e, 0xce, 0xc7, 0x55, 0xbf, 0xe9, 0x33, 0x7d, 0xb8, 0xbd, 0xc8, 0x55, 0xf5,
+ 0x25, 0xc8, 0x70, 0x64, 0x3b, 0x32, 0xff, 0xab, 0xaf, 0xc6, 0x7f, 0xac, 0x45, 0x11, 0xff, 0x9d,
+ 0x4d, 0x0c, 0x60, 0xf1, 0x94, 0x0a, 0xea, 0x6f, 0xea, 0xfb, 0xb7, 0xbc, 0x83, 0x78, 0xaa, 0xc5,
+ 0xf8, 0xf1, 0x5f, 0x4f, 0x98, 0x30, 0x11, 0xbe, 0x09, 0x84, 0x3d, 0xc2, 0xd9, 0x53, 0xa9, 0xbf,
+ 0xf1, 0x25, 0x98, 0xfc, 0xdb, 0x09, 0x13, 0xbe, 0x21, 0x6d, 0x02, 0xce, 0x23, 0x89, 0x7d, 0xf4,
+ 0x99, 0xbf, 0xa9, 0x4d, 0x23, 0x6d, 0xfa, 0x88, 0x8d, 0xcc, 0xce, 0x9b, 0x41, 0x7d, 0x9c, 0x36,
+ 0x62, 0xbf, 0xc7, 0xa3, 0x7c, 0x0c, 0x13, 0xe7, 0x2a, 0x32, 0x12, 0xd9, 0x8e, 0xcc, 0x47, 0x11,
+ 0xfc, 0xfb, 0x37, 0xc6, 0xfe, 0x9b, 0x18, 0xa5, 0x37, 0xa8, 0x0e, 0x05, 0x8a, 0xae, 0xc7, 0x34,
+ 0x1c, 0xfa, 0x9f, 0x51, 0xf6, 0x86, 0x33, 0x7f, 0x07, 0x13, 0x3b, 0x94, 0x3f, 0xbb, 0x8d, 0x76,
+ 0x88, 0xa3, 0xe1, 0xfa, 0xff, 0x01, 0x00, 0x07, 0xdb, 0x50, 0xec, 0x6b, 0x02, 0x00
+};
+
+fastimage_t bfin_logo = {
+		DEF_BFIN_LOGO_DATA,
+		DEF_BFIN_LOGO_WIDTH,
+		DEF_BFIN_LOGO_HEIGHT,
+		DEF_BFIN_LOGO_BPP,
+		DEF_BFIN_LOGO_PIXEL_SIZE,
+		DEF_BFIN_LOGO_SIZE
+};
diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h
new file mode 100644
index 0000000..c5b0be9
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h
@@ -0,0 +1,1242 @@
+/*
+ * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
+ *
+ * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
+ *
+ * Where:	'screen'	is the pointer to the frame buffer
+ *		'width'	is the screen width
+ *		'x'		is the horizontal position
+ *		'y'		is the vertical position
+ */
+
+#define EASYLOGO_ENABLE_GZIP 19303
+
+static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
+
+#include <video_easylogo.h>
+
+#define	DEF_BFIN_LOGO_WIDTH		230
+#define	DEF_BFIN_LOGO_HEIGHT		230
+#define	DEF_BFIN_LOGO_PIXELS		52900
+#define	DEF_BFIN_LOGO_BPP		16
+#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
+#define	DEF_BFIN_LOGO_SIZE		105800
+
+unsigned char DEF_BFIN_LOGO_DATA[] = {
+ 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77,
+ 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6,
+ 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb,
+ 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38,
+ 0x20, 0x85, 0x23, 0x48, 0x45, 0x24, 0x77, 0x65, 0x09, 0x55, 0x59, 0x97, 0x53, 0x2d, 0x99, 0x53,
+ 0x39, 0x99, 0x3f, 0xd2, 0x42, 0x6e, 0x49, 0xcc, 0x4a, 0x41, 0x35, 0x52, 0x90, 0x1c, 0xa9, 0xd9,
+ 0x9a, 0xdb, 0x90, 0x18, 0xa9, 0xd6, 0xc5, 0x52, 0xb9, 0x3b, 0x77, 0xc5, 0xea, 0x9c, 0x86, 0xe6,
+ 0x72, 0xdf, 0x37, 0x5f, 0x0f, 0xe3, 0xdf, 0x36, 0xb6, 0x93, 0xb4, 0x61, 0x3e, 0x5f, 0x85, 0xc4,
+ 0x63, 0x67, 0xfc, 0xb5, 0x3f, 0xbc, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0x3d, 0x89, 0x44, 0x84,
+ 0x88, 0x1f, 0x32, 0xe8, 0x34, 0x43, 0xc4, 0x8f, 0x05, 0x98, 0x2f, 0x2d, 0xa1, 0x25, 0x3a, 0x88,
+ 0x7e, 0xb2, 0x9f, 0x74, 0xc6, 0x0c, 0x78, 0xdc, 0x81, 0xae, 0xc3, 0xb3, 0x22, 0xab, 0x3f, 0x64,
+ 0x60, 0x0e, 0x81, 0x41, 0x27, 0xb9, 0x40, 0x05, 0xa9, 0x12, 0x99, 0x5c, 0xd6, 0xa4, 0xea, 0x54,
+ 0x0f, 0x6e, 0x8e, 0x4e, 0x55, 0x93, 0x4a, 0x2e, 0x2b, 0x91, 0x05, 0x29, 0x27, 0xc7, 0x2a, 0xe6,
+ 0x54, 0xc4, 0x0f, 0x0b, 0x3c, 0x8b, 0x0b, 0x88, 0xc1, 0x26, 0xd5, 0xa0, 0x7a, 0x91, 0x0d, 0xb1,
+ 0x4a, 0x5d, 0x97, 0x7e, 0xc8, 0xb0, 0x64, 0x14, 0xc6, 0x94, 0x61, 0xc8, 0xd0, 0xac, 0x27, 0x74,
+ 0x8b, 0xec, 0xa0, 0xba, 0x49, 0x85, 0x39, 0xed, 0x10, 0xf9, 0xfc, 0xc1, 0x00, 0x4b, 0x23, 0x66,
+ 0xb1, 0x53, 0x35, 0xc9, 0x12, 0x88, 0xc1, 0x25, 0x63, 0xa9, 0xb9, 0xd5, 0xd2, 0x6a, 0x29, 0x35,
+ 0x4f, 0x19, 0xba, 0xf4, 0xc0, 0x1e, 0xcf, 0xec, 0x9a, 0xb1, 0xd5, 0xd2, 0x6d, 0x61, 0xcc, 0x4b,
+ 0xc6, 0x21, 0x83, 0x12, 0x71, 0xda, 0x89, 0x18, 0x5d, 0xa0, 0xfa, 0x49, 0x51, 0xe7, 0x3e, 0x69,
+ 0x60, 0x69, 0x74, 0x92, 0x41, 0xaa, 0x49, 0xb5, 0x88, 0xd8, 0x9a, 0x42, 0x5c, 0x95, 0x9a, 0x4b,
+ 0xcd, 0xcd, 0xfa, 0x41, 0xb5, 0x93, 0x4c, 0xf7, 0xbf, 0x3a, 0x08, 0xb9, 0x4c, 0xa9, 0x83, 0x57,
+ 0xae, 0x21, 0x59, 0x6d, 0xd6, 0x2f, 0xb2, 0x20, 0xa3, 0x58, 0x42, 0x1f, 0xe7, 0xec, 0x45, 0x08,
+ 0xa0, 0x25, 0xc0, 0x23, 0x48, 0x63, 0x88, 0xed, 0xd2, 0xaf, 0x19, 0xd7, 0x90, 0x0e, 0x25, 0x74,
+ 0x72, 0x19, 0x9d, 0xe3, 0xff, 0x5e, 0xa0, 0x16, 0x59, 0x90, 0xd4, 0x35, 0x63, 0x97, 0x3e, 0x84,
+ 0x24, 0x34, 0x18, 0x95, 0x4f, 0x11, 0x8f, 0x17, 0x58, 0xaf, 0x06, 0x29, 0xe0, 0x71, 0xc8, 0x00,
+ 0x12, 0xa6, 0xd4, 0x35, 0xa9, 0x3a, 0xb6, 0x2c, 0x57, 0x5a, 0x24, 0xa3, 0x84, 0x0e, 0x74, 0xf2,
+ 0x90, 0x21, 0x84, 0xe4, 0x73, 0x41, 0xe4, 0xf3, 0x31, 0x03, 0x4b, 0xa4, 0x5c, 0xb6, 0x88, 0xe4,
+ 0x91, 0x31, 0xaf, 0x1d, 0x0f, 0xb1, 0x25, 0x32, 0xba, 0x80, 0xbb, 0x05, 0xa9, 0x10, 0x8b, 0x75,
+ 0xf3, 0xa4, 0x1a, 0x6b, 0xdb, 0xfc, 0xef, 0x26, 0x62, 0x2b, 0x00, 0x26, 0x17, 0xd0, 0x0a, 0x49,
+ 0xa0, 0x35, 0xaf, 0xdb, 0xd2, 0xac, 0x5f, 0xa0, 0xe8, 0x22, 0xdc, 0x73, 0x81, 0x52, 0xea, 0xba,
+ 0x2d, 0x53, 0x86, 0x90, 0x16, 0xa4, 0x53, 0x64, 0xf3, 0x71, 0x00, 0x98, 0x0c, 0x52, 0x83, 0xea,
+ 0x66, 0x24, 0x91, 0xa5, 0xe6, 0x42, 0xe4, 0x31, 0xf9, 0xce, 0x25, 0x32, 0xb0, 0x88, 0xba, 0x38,
+ 0xe9, 0x14, 0x75, 0xed, 0xa3, 0x06, 0x66, 0x72, 0x52, 0x3d, 0x64, 0x60, 0xd0, 0x0a, 0x47, 0x17,
+ 0x7c, 0xaf, 0x44, 0xf9, 0xd3, 0x12, 0xa0, 0x6d, 0xa7, 0x8c, 0x21, 0x56, 0x8e, 0x74, 0xad, 0xc8,
+ 0xe6, 0xa3, 0x03, 0x2f, 0x93, 0x60, 0xed, 0x84, 0xd8, 0xc2, 0x76, 0x10, 0xb4, 0xe4, 0x1a, 0x75,
+ 0x42, 0x35, 0xa0, 0xde, 0x27, 0x3b, 0x4b, 0xd2, 0x71, 0xd7, 0x3b, 0x55, 0x60, 0xdb, 0x12, 0xc8,
+ 0x96, 0x02, 0x36, 0x0b, 0x9b, 0xb1, 0x88, 0x74, 0xd0, 0x22, 0x8b, 0xa7, 0x53, 0xd5, 0xa5, 0x2f,
+ 0x35, 0x2f, 0x16, 0xc8, 0xa4, 0x44, 0x72, 0x80, 0x38, 0xa8, 0x7a, 0x41, 0xf7, 0xbe, 0xe1, 0x90,
+ 0xde, 0xcb, 0x26, 0xf2, 0x19, 0xa4, 0xa6, 0xd0, 0x6f, 0x0b, 0xec, 0x6f, 0x44, 0x36, 0x1f, 0x0d,
+ 0x68, 0x49, 0x3f, 0x89, 0x77, 0xf9, 0x85, 0xca, 0x24, 0xa0, 0x83, 0x70, 0xa9, 0xaf, 0x1b, 0x5b,
+ 0x2c, 0x2d, 0x96, 0x6f, 0x8c, 0x87, 0xf4, 0xe7, 0xd4, 0xd7, 0xe2, 0x2c, 0x28, 0x27, 0x39, 0x65,
+ 0x04, 0xd9, 0x97, 0x73, 0xeb, 0x66, 0xa1, 0xef, 0x25, 0x22, 0x1e, 0xfc, 0x4a, 0xb9, 0x66, 0x1c,
+ 0x32, 0x14, 0xe3, 0xdb, 0x3d, 0x4b, 0xde, 0x65, 0x77, 0x9a, 0xc3, 0xf6, 0x5f, 0x0e, 0xfb, 0xec,
+ 0x8c, 0xf9, 0x7d, 0x83, 0x97, 0x0d, 0xc6, 0xb1, 0xb9, 0x40, 0x81, 0x07, 0x77, 0x11, 0x5d, 0x15,
+ 0x6d, 0xda, 0x62, 0x83, 0xd7, 0xaf, 0x8c, 0x39, 0xbd, 0x77, 0x6e, 0x2b, 0xf8, 0x84, 0x7c, 0x01,
+ 0xed, 0x41, 0x0e, 0x0f, 0x8f, 0x8c, 0x1e, 0x8e, 0x61, 0xf3, 0x40, 0xcc, 0x6f, 0x49, 0x90, 0x02,
+ 0x4f, 0xd2, 0xa4, 0x7a, 0x81, 0x12, 0x6d, 0xa0, 0x62, 0x02, 0xa4, 0xb2, 0x44, 0x46, 0xe8, 0x18,
+ 0x73, 0xa7, 0xaa, 0x38, 0x77, 0xbc, 0x46, 0xbd, 0xa9, 0x9f, 0xb6, 0x9e, 0x1c, 0xfe, 0x60, 0xf4,
+ 0xa5, 0x81, 0x69, 0x7b, 0x8b, 0xe5, 0xba, 0x51, 0xa9, 0x4b, 0xd4, 0xb4, 0x9d, 0x2a, 0xd8, 0xa1,
+ 0x74, 0x8a, 0x36, 0x50, 0x51, 0x01, 0x52, 0x39, 0xa8, 0x06, 0xdf, 0x39, 0x5d, 0xa4, 0x3b, 0xfe,
+ 0x85, 0xec, 0x7d, 0xc3, 0xb4, 0x95, 0x1c, 0x08, 0xdb, 0xcf, 0x5b, 0xab, 0xcd, 0xd7, 0x8d, 0x6f,
+ 0xea, 0xff, 0x12, 0x71, 0xf9, 0x75, 0x9c, 0x64, 0x6a, 0x09, 0xa5, 0x0e, 0x6c, 0x20, 0xd8, 0x6d,
+ 0x16, 0xeb, 0x7d, 0x45, 0x14, 0x5b, 0x2a, 0x69, 0xc9, 0x0e, 0xc4, 0x25, 0x58, 0x3e, 0x3b, 0xcd,
+ 0x9f, 0x22, 0x5b, 0xf6, 0x2e, 0x7b, 0x0e, 0xed, 0x4e, 0xae, 0x25, 0xad, 0x8d, 0x4e, 0x12, 0xf4,
+ 0xec, 0x20, 0xa7, 0x67, 0x8b, 0xf3, 0xce, 0xdb, 0x1d, 0x60, 0xc1, 0x36, 0xa9, 0x20, 0xae, 0xdc,
+ 0x5f, 0x94, 0xb5, 0x12, 0x73, 0x79, 0x48, 0x8f, 0xa4, 0xd1, 0xf0, 0x8c, 0xce, 0x85, 0x58, 0xfc,
+ 0x9a, 0x3a, 0x4b, 0x1e, 0x48, 0xb9, 0x2a, 0x0e, 0xaa, 0x5b, 0x2d, 0x4a, 0x9d, 0x5c, 0x94, 0xcc,
+ 0x22, 0x41, 0x4b, 0x2c, 0x80, 0x05, 0x7b, 0x3c, 0xc4, 0xd2, 0x45, 0xbb, 0xe7, 0xd7, 0x94, 0x97,
+ 0xbd, 0xcb, 0x9e, 0x50, 0x01, 0x8b, 0x99, 0xee, 0x4a, 0x4b, 0x20, 0xca, 0x39, 0x29, 0x4a, 0x66,
+ 0x91, 0x80, 0x35, 0xec, 0xda, 0xf1, 0x12, 0x59, 0xf1, 0xee, 0x79, 0x96, 0xdc, 0x21, 0xfb, 0x84,
+ 0x3c, 0x90, 0x03, 0x3f, 0x41, 0xaa, 0xdb, 0xa2, 0xd4, 0x8b, 0x92, 0x59, 0x0c, 0x60, 0x0d, 0xdb,
+ 0x65, 0xe8, 0x32, 0x14, 0x4b, 0xc3, 0xe2, 0xbb, 0xd2, 0x39, 0xbf, 0x72, 0xca, 0x20, 0x4a, 0x66,
+ 0x71, 0x40, 0x4b, 0xc0, 0x86, 0x5d, 0x32, 0x12, 0x3a, 0xfa, 0x09, 0xcd, 0x40, 0x2e, 0x63, 0xcc,
+ 0x4a, 0x64, 0xcd, 0x8a, 0x5e, 0x83, 0x42, 0x01, 0xab, 0xe5, 0x22, 0xbb, 0x86, 0x24, 0xe3, 0x49,
+ 0xcd, 0xa0, 0x83, 0x80, 0x0c, 0x3e, 0xd8, 0x67, 0xd2, 0x4f, 0x6a, 0x0a, 0x4f, 0x09, 0xb4, 0x44,
+ 0x90, 0x82, 0x3c, 0x0e, 0x79, 0x11, 0x57, 0xcb, 0xad, 0x81, 0x96, 0x4c, 0xaa, 0xc1, 0x9f, 0x1f,
+ 0x14, 0xb5, 0x6c, 0x41, 0xa0, 0xb9, 0xbc, 0xb9, 0x66, 0xfd, 0x94, 0x61, 0x81, 0x7a, 0x72, 0xb3,
+ 0x08, 0x52, 0x4b, 0x46, 0xd8, 0x99, 0x88, 0x5a, 0xb6, 0x10, 0x00, 0x97, 0xb0, 0xb7, 0x1c, 0x32,
+ 0x6c, 0x3d, 0x33, 0xab, 0x78, 0xe8, 0x20, 0x94, 0x7a, 0xf0, 0x19, 0x88, 0x5a, 0xb6, 0x10, 0x80,
+ 0x15, 0xdb, 0xa9, 0x9a, 0x32, 0x34, 0xeb, 0x9f, 0xec, 0x3c, 0x20, 0x42, 0xb3, 0xc8, 0x8a, 0xb6,
+ 0x6c, 0x21, 0xe0, 0xad, 0x58, 0xa5, 0xee, 0xc9, 0xce, 0xa3, 0x44, 0x06, 0x73, 0x00, 0x5b, 0xf6,
+ 0xc9, 0xce, 0xe3, 0xc7, 0x0c, 0x2d, 0xe1, 0xe4, 0xa2, 0x96, 0x21, 0x36, 0xf5, 0xf3, 0x07, 0x88,
+ 0x7f, 0x20, 0x72, 0xd9, 0xf1, 0x27, 0xc3, 0x49, 0x1e, 0x54, 0x4d, 0xb2, 0x93, 0xea, 0x60, 0x4e,
+ 0x79, 0x7c, 0x1d, 0x04, 0xe8, 0x79, 0xc8, 0xc1, 0xcd, 0xe5, 0xd5, 0x22, 0x52, 0x81, 0xdf, 0x91,
+ 0x2c, 0xa6, 0xe4, 0xf2, 0x00, 0xf1, 0x35, 0x75, 0x50, 0x75, 0x42, 0x75, 0x50, 0xf5, 0xc9, 0x96,
+ 0xfd, 0x08, 0x10, 0x8d, 0x6e, 0xb1, 0x84, 0xed, 0xd3, 0xf6, 0xeb, 0xc6, 0x1d, 0x39, 0xd8, 0xc8,
+ 0x4a, 0x64, 0x4b, 0x8b, 0x2b, 0x66, 0x21, 0x00, 0x2e, 0x43, 0x88, 0xcb, 0xc1, 0x34, 0xbb, 0xcb,
+ 0x6b, 0x94, 0x4b, 0x7d, 0x48, 0xff, 0xa9, 0xe1, 0x4d, 0xfd, 0x09, 0xd5, 0x56, 0xe5, 0x13, 0xec,
+ 0xaa, 0x17, 0x74, 0x61, 0xfb, 0xc9, 0xe1, 0x69, 0x7b, 0xf6, 0x08, 0x8c, 0xb8, 0x62, 0x16, 0x0a,
+ 0xd8, 0x5d, 0x86, 0xb4, 0x6b, 0xc6, 0xa6, 0xb4, 0xdf, 0xf5, 0x59, 0xf2, 0x9c, 0xfa, 0x53, 0x43,
+ 0xb7, 0xa5, 0xc5, 0x72, 0x97, 0xcd, 0xb6, 0x9a, 0x41, 0x9e, 0x49, 0xa7, 0xea, 0x19, 0x9d, 0x52,
+ 0x07, 0x27, 0x0e, 0xe0, 0xcc, 0x1e, 0xac, 0xc7, 0x3b, 0xcd, 0x90, 0x5b, 0x90, 0x4d, 0x36, 0x21,
+ 0x7b, 0x56, 0x5c, 0x31, 0x0b, 0x01, 0xf6, 0x14, 0xac, 0xa5, 0xf0, 0x14, 0x00, 0x2f, 0x70, 0xe2,
+ 0x0e, 0xbe, 0xdb, 0x6b, 0xd4, 0x21, 0x3d, 0xb0, 0xe9, 0x52, 0xd3, 0x19, 0xee, 0x34, 0xa8, 0xde,
+ 0x69, 0x7e, 0x69, 0xe0, 0xe4, 0xe8, 0xc8, 0xe8, 0x25, 0xf4, 0xe7, 0x83, 0xd1, 0xc3, 0xc3, 0x17,
+ 0xac, 0x8b, 0x2c, 0x9c, 0x67, 0x58, 0x33, 0x1e, 0x1e, 0xde, 0x69, 0xce, 0x2c, 0xd7, 0x1d, 0xc4,
+ 0xda, 0xf1, 0x2e, 0xd1, 0xc7, 0x5e, 0x00, 0x52, 0x73, 0x09, 0x59, 0xac, 0x4b, 0xc6, 0x0b, 0xd6,
+ 0x1b, 0xf6, 0x0b, 0x56, 0xc8, 0x65, 0x85, 0x6c, 0xb9, 0x10, 0xdb, 0x6d, 0xf9, 0x26, 0xed, 0xca,
+ 0xa7, 0x25, 0xa6, 0x0c, 0x87, 0x87, 0xd7, 0x1d, 0x1a, 0x77, 0x8f, 0x7b, 0x6c, 0x06, 0x46, 0x8f,
+ 0xbb, 0xcd, 0x5d, 0xe6, 0x1a, 0x19, 0x9d, 0x32, 0xc0, 0xe9, 0x4d, 0xc6, 0x1c, 0xb6, 0x9f, 0xc8,
+ 0xa2, 0x67, 0xa7, 0x8c, 0x53, 0x86, 0x4e, 0x95, 0xc8, 0x65, 0xbe, 0xe0, 0xb9, 0x8c, 0x8f, 0x77,
+ 0x0d, 0xaa, 0xc3, 0xf6, 0x75, 0x47, 0x1b, 0xe2, 0x05, 0x18, 0x59, 0x77, 0x74, 0x5b, 0x20, 0x5f,
+ 0x4e, 0xa9, 0xfb, 0xc6, 0x98, 0x5a, 0x32, 0xb5, 0xc4, 0x75, 0xe3, 0xba, 0x63, 0x6c, 0x26, 0xe2,
+ 0xa1, 0xbc, 0xac, 0xb7, 0xdd, 0x87, 0x47, 0x9d, 0x97, 0xf2, 0xce, 0x7a, 0xd6, 0x1d, 0x90, 0xd9,
+ 0xb7, 0x40, 0x41, 0x6e, 0x65, 0x66, 0xc9, 0xe4, 0xad, 0x1f, 0x71, 0xc5, 0xcc, 0x0f, 0xbc, 0x37,
+ 0x36, 0x18, 0xe3, 0xc1, 0x93, 0xcb, 0xc2, 0xf6, 0x36, 0xf7, 0xb2, 0xa7, 0xce, 0xcb, 0x73, 0xb2,
+ 0xec, 0x09, 0xdb, 0x9d, 0xe4, 0x35, 0xea, 0x0b, 0xf6, 0x84, 0x8a, 0x4e, 0x71, 0x97, 0x21, 0x43,
+ 0x99, 0x8b, 0xf2, 0x9e, 0xf6, 0xcd, 0xf9, 0x57, 0x02, 0x1b, 0x81, 0x8d, 0xbb, 0xe5, 0xa1, 0xef,
+ 0xd1, 0xdf, 0x2b, 0x68, 0x8c, 0xfb, 0x29, 0xef, 0x6e, 0x17, 0x58, 0xc9, 0x4e, 0xd2, 0xcb, 0x5e,
+ 0xcb, 0xe8, 0x27, 0x1c, 0xe4, 0xbc, 0xb2, 0xa2, 0xf5, 0x93, 0x2f, 0x78, 0x2e, 0x05, 0x6f, 0x2c,
+ 0xc8, 0xd8, 0xd8, 0x4c, 0xbb, 0x6f, 0x25, 0x50, 0x1e, 0x6a, 0x40, 0xc3, 0x14, 0x6e, 0x08, 0x7d,
+ 0x7f, 0x77, 0xdc, 0x4f, 0x0e, 0x68, 0x89, 0xd4, 0x79, 0x1e, 0x8b, 0x6c, 0x99, 0x6b, 0xdc, 0xdf,
+ 0x10, 0xea, 0x0d, 0x4f, 0x44, 0x26, 0x22, 0xf3, 0xdc, 0x98, 0xe0, 0x46, 0x6f, 0xd8, 0x14, 0x2e,
+ 0x0f, 0xd9, 0x7c, 0x23, 0xa3, 0x20, 0xf7, 0x07, 0xb2, 0xec, 0x54, 0x4b, 0x64, 0x8c, 0x39, 0x24,
+ 0x7a, 0xd8, 0xf3, 0x46, 0xb2, 0x5c, 0xca, 0x65, 0x6d, 0xee, 0x39, 0xbf, 0x29, 0x0c, 0xac, 0xac,
+ 0x3e, 0xe4, 0xc7, 0x7c, 0xa4, 0x3c, 0x74, 0xc1, 0x9a, 0xea, 0x5b, 0xee, 0x27, 0xc3, 0xf6, 0x8d,
+ 0xc0, 0x04, 0x7a, 0x6d, 0x2a, 0xc0, 0xff, 0x34, 0x85, 0xdb, 0x7d, 0x6b, 0xc6, 0xec, 0x0c, 0x39,
+ 0xc9, 0x56, 0x0b, 0x21, 0x5a, 0xb2, 0x79, 0x83, 0xe7, 0x92, 0x5f, 0x2f, 0x69, 0xa4, 0x2f, 0x57,
+ 0x10, 0x33, 0xa9, 0x78, 0xb1, 0xf9, 0x52, 0x79, 0x14, 0x94, 0x3a, 0x9b, 0x2f, 0x35, 0x8f, 0x02,
+ 0x7a, 0xc3, 0xcb, 0x9e, 0xec, 0x31, 0x35, 0x5a, 0xd2, 0x6d, 0x11, 0x77, 0x25, 0xf9, 0x23, 0x91,
+ 0xcb, 0x0e, 0xa2, 0xcc, 0x35, 0x1f, 0x65, 0x72, 0x23, 0x30, 0xe7, 0xef, 0x0d, 0xc7, 0x72, 0x32,
+ 0x9d, 0x24, 0x99, 0x1d, 0xc4, 0x0d, 0x7b, 0x3c, 0xf3, 0xe5, 0xa1, 0x88, 0x67, 0x76, 0x86, 0xf2,
+ 0x36, 0x84, 0x62, 0xaf, 0x9a, 0xc2, 0xd3, 0xd6, 0xec, 0xb3, 0xe9, 0xb6, 0x36, 0xeb, 0xc5, 0xc8,
+ 0x57, 0xbe, 0x48, 0xe4, 0xd2, 0x49, 0x8e, 0xfb, 0xb1, 0x24, 0x85, 0xed, 0x21, 0x76, 0x52, 0xdd,
+ 0xa5, 0x5f, 0x77, 0x08, 0x5c, 0xd9, 0x7c, 0x89, 0xd2, 0x25, 0x97, 0x2d, 0x7b, 0x62, 0x19, 0x3b,
+ 0x39, 0x0c, 0xa7, 0xf1, 0xa0, 0x8a, 0x93, 0x52, 0x27, 0xfc, 0x56, 0x80, 0xae, 0xb5, 0xf9, 0xe8,
+ 0xac, 0xb3, 0x11, 0xb9, 0x2c, 0x04, 0x89, 0xfb, 0xcb, 0x05, 0x0a, 0x24, 0x71, 0xf5, 0xe1, 0x05,
+ 0x2b, 0xaf, 0xe9, 0xfa, 0xc9, 0x1b, 0x76, 0x9e, 0x93, 0xf9, 0x48, 0x62, 0x26, 0xc9, 0xa4, 0x7a,
+ 0x23, 0xc0, 0xf3, 0x35, 0x1f, 0x39, 0x39, 0x8c, 0xf3, 0xbf, 0x76, 0xc8, 0x7c, 0xf6, 0x9d, 0xe6,
+ 0x26, 0xd5, 0x4d, 0x87, 0xa0, 0x7d, 0x27, 0x22, 0xe9, 0x7d, 0x4b, 0x3c, 0x44, 0x1d, 0x5b, 0x08,
+ 0x12, 0xb9, 0x0c, 0x52, 0xc0, 0xdb, 0xec, 0x0c, 0x3c, 0x3e, 0x4b, 0x4e, 0x5b, 0x47, 0x46, 0xbb,
+ 0x0c, 0x1d, 0x44, 0x9b, 0x9b, 0x97, 0x2e, 0x9e, 0x4b, 0x3e, 0xcf, 0x6e, 0x91, 0x15, 0xb4, 0x70,
+ 0xc4, 0xc3, 0x4b, 0xf7, 0x41, 0x55, 0x99, 0xab, 0xc7, 0xed, 0xb3, 0x97, 0xc8, 0xda, 0x7d, 0x82,
+ 0xd4, 0x8e, 0x8c, 0x66, 0x9e, 0x4b, 0xbf, 0x68, 0xfb, 0x14, 0x04, 0xcc, 0x65, 0xe9, 0xe6, 0xe9,
+ 0x03, 0xcc, 0x65, 0xd8, 0x0e, 0xeb, 0xa2, 0x93, 0x1c, 0x19, 0xed, 0x71, 0x6b, 0xdc, 0x83, 0xea,
+ 0x49, 0xf5, 0x6a, 0x0c, 0x97, 0x50, 0x19, 0xc4, 0xa5, 0xf6, 0xb2, 0x3b, 0x64, 0xe0, 0x0d, 0x9a,
+ 0xd8, 0x94, 0xd9, 0xb0, 0x9d, 0xbf, 0x6b, 0x07, 0xc1, 0x98, 0x8f, 0xb8, 0xdb, 0xdc, 0x21, 0x76,
+ 0xc9, 0x28, 0x70, 0xb9, 0xec, 0xc9, 0x3c, 0x97, 0x20, 0xc5, 0x58, 0xc4, 0x3d, 0x49, 0xfe, 0x48,
+ 0xc5, 0xe5, 0xea, 0xc3, 0x6e, 0x0b, 0x7e, 0xee, 0xba, 0x11, 0x7c, 0x3f, 0xad, 0x96, 0xfe, 0xe8,
+ 0x2a, 0x8a, 0xb9, 0x84, 0xe8, 0x07, 0x63, 0x86, 0xb3, 0x22, 0x50, 0x3b, 0x8d, 0xd7, 0xbf, 0xa6,
+ 0x70, 0x6c, 0x6e, 0xc2, 0x02, 0xe5, 0xb3, 0x6b, 0x5c, 0x9f, 0x1a, 0x16, 0x28, 0x41, 0x07, 0xb7,
+ 0xfb, 0x32, 0xcf, 0x45, 0x2e, 0x13, 0x33, 0xb8, 0x0a, 0x01, 0x17, 0x27, 0x61, 0x4b, 0xcd, 0x7c,
+ 0xcc, 0x2b, 0x48, 0xc1, 0x4e, 0xb1, 0xd5, 0x82, 0x1f, 0x39, 0x49, 0x9f, 0xbd, 0xc7, 0x7d, 0x69,
+ 0xd4, 0x49, 0x6a, 0x5c, 0xb1, 0x72, 0xb9, 0x43, 0x76, 0x97, 0xed, 0xd2, 0x5f, 0x37, 0x76, 0xe9,
+ 0x0f, 0xe9, 0x79, 0xb9, 0x2c, 0x0f, 0xc5, 0xc7, 0xb5, 0x4a, 0x64, 0xcd, 0x7a, 0xf0, 0xfc, 0x95,
+ 0xb9, 0x04, 0xcb, 0x29, 0xf3, 0x5c, 0x3a, 0xd5, 0x6b, 0x62, 0xce, 0x73, 0x01, 0xc0, 0xf1, 0xcb,
+ 0x52, 0x33, 0xbf, 0x0e, 0x2e, 0x50, 0x26, 0xb4, 0xfe, 0x75, 0x5b, 0xf8, 0xe7, 0x9b, 0xf5, 0x6d,
+ 0xee, 0x9b, 0x0e, 0xd0, 0xb6, 0xf1, 0xb6, 0x0f, 0xae, 0xe7, 0x74, 0x96, 0x5c, 0x64, 0xf9, 0xbd,
+ 0xc7, 0x46, 0x20, 0xf1, 0x0c, 0x03, 0xcd, 0xfd, 0x99, 0xb6, 0xe6, 0xca, 0xe5, 0xa0, 0x7a, 0x4d,
+ 0x8c, 0x46, 0x17, 0x00, 0x9c, 0x57, 0x00, 0xba, 0x0d, 0x3f, 0xc6, 0x7b, 0x12, 0xf0, 0xd7, 0xe1,
+ 0xc7, 0x4d, 0xaa, 0xc3, 0xc3, 0xe4, 0x40, 0x7f, 0x94, 0xcb, 0x58, 0xd9, 0xa3, 0xb9, 0x9f, 0x41,
+ 0x8a, 0xb7, 0x8b, 0xca, 0x43, 0xa9, 0xec, 0x54, 0x5a, 0xd2, 0x6a, 0xe1, 0xb9, 0xac, 0xf3, 0x66,
+ 0x9e, 0x0b, 0xe4, 0x1d, 0x89, 0x5c, 0xe6, 0x8f, 0xe8, 0x19, 0x2f, 0x63, 0x48, 0x8b, 0x1f, 0x77,
+ 0x10, 0x37, 0x1d, 0x0f, 0x1f, 0xf6, 0xb8, 0x05, 0x9f, 0x5e, 0xa7, 0xea, 0xa0, 0x4a, 0x4b, 0xac,
+ 0x3b, 0x56, 0x23, 0x7d, 0xab, 0x9f, 0x9f, 0xe9, 0xfe, 0xd9, 0xae, 0x7d, 0x17, 0xf7, 0xed, 0x61,
+ 0xea, 0x98, 0x76, 0x34, 0x66, 0xf6, 0x5d, 0xd8, 0xfb, 0xa7, 0xa3, 0xc7, 0x96, 0xff, 0x25, 0x0c,
+ 0x5c, 0xa6, 0xca, 0x7c, 0xa7, 0x25, 0x61, 0x3b, 0xcf, 0x65, 0x9b, 0x3b, 0xf3, 0x5c, 0xa0, 0x5a,
+ 0x8c, 0xa8, 0x63, 0xf3, 0x87, 0x70, 0x9a, 0x84, 0xbf, 0xd2, 0xa5, 0x5f, 0x45, 0xbc, 0xc4, 0xe7,
+ 0xe5, 0xd1, 0x92, 0xd7, 0x3e, 0x6e, 0x18, 0xab, 0x6f, 0x7c, 0xa0, 0x38, 0x26, 0xed, 0x8b, 0x1b,
+ 0x26, 0xe9, 0x03, 0xc5, 0xd1, 0x9a, 0xef, 0xbb, 0xff, 0x6f, 0xb6, 0x7c, 0x35, 0x55, 0x5e, 0x66,
+ 0x07, 0x31, 0x3b, 0xc3, 0x73, 0x49, 0x0e, 0x64, 0x9e, 0x0b, 0xb6, 0x7d, 0x44, 0x2e, 0xf3, 0x05,
+ 0x9f, 0x1f, 0x2b, 0x70, 0x17, 0xe2, 0x76, 0x8c, 0x23, 0xa3, 0xb1, 0xbb, 0xbc, 0xf7, 0x77, 0x7d,
+ 0x77, 0xe4, 0x8c, 0xa2, 0x11, 0x31, 0xd7, 0x27, 0x9d, 0x78, 0x16, 0x8f, 0x3e, 0xe9, 0x6d, 0x45,
+ 0xbd, 0xe2, 0xa8, 0xe2, 0x41, 0xc5, 0x04, 0xba, 0x7a, 0x47, 0xf1, 0x46, 0xdf, 0xff, 0xa4, 0xc8,
+ 0xcb, 0x14, 0xf6, 0x2c, 0xc2, 0xde, 0x34, 0x1d, 0x20, 0x62, 0x1d, 0xe2, 0x2a, 0x8b, 0x14, 0xeb,
+ 0xd3, 0x6d, 0x2f, 0xe0, 0x13, 0x7b, 0xb1, 0x5c, 0x36, 0xa9, 0x28, 0x2f, 0xec, 0x30, 0x96, 0x8c,
+ 0xf8, 0xb1, 0x56, 0xf2, 0x5f, 0xcf, 0xd5, 0x31, 0x67, 0x14, 0xb7, 0x18, 0x1b, 0x33, 0xc7, 0x54,
+ 0x54, 0xf2, 0x5c, 0x1e, 0x93, 0xde, 0x62, 0xde, 0xad, 0x7d, 0xb7, 0x96, 0x65, 0x10, 0x9b, 0xe8,
+ 0xb1, 0x49, 0x7a, 0x4f, 0x5e, 0xfd, 0x93, 0x78, 0x3a, 0x4b, 0x62, 0x3c, 0x7c, 0x13, 0x91, 0x6c,
+ 0xf2, 0xa6, 0x25, 0x5a, 0x2d, 0xe2, 0x79, 0xaf, 0xfc, 0x81, 0xec, 0x51, 0xee, 0x7c, 0xbb, 0xa0,
+ 0x1f, 0x79, 0xcb, 0x73, 0x23, 0x00, 0x76, 0xce, 0x3f, 0x12, 0xbf, 0xde, 0xfb, 0x1e, 0x73, 0x55,
+ 0x71, 0x46, 0xf1, 0x5a, 0xed, 0x6b, 0xb5, 0xb7, 0x98, 0x63, 0x9c, 0x5c, 0xce, 0x4b, 0xe7, 0xa5,
+ 0x13, 0xd2, 0x0a, 0xc4, 0xe6, 0x87, 0xb5, 0x1f, 0xd6, 0x1e, 0x55, 0x4c, 0x48, 0xb1, 0xa4, 0xae,
+ 0x54, 0x8c, 0x95, 0xff, 0xd3, 0xde, 0xe8, 0xd2, 0x2b, 0x59, 0x64, 0xc7, 0x66, 0x04, 0x1f, 0x5e,
+ 0x9b, 0x9b, 0xce, 0x3a, 0x9b, 0x56, 0x4b, 0x97, 0xbe, 0x49, 0xcc, 0x12, 0xc9, 0x13, 0xfc, 0x79,
+ 0x92, 0x2e, 0xbd, 0x20, 0x35, 0x4b, 0x46, 0xec, 0x97, 0xb3, 0xf9, 0x86, 0x75, 0xb5, 0xd5, 0x73,
+ 0x88, 0xc9, 0x3e, 0xc4, 0x9b, 0x8d, 0x39, 0xaa, 0xe8, 0xe3, 0x99, 0xac, 0x9c, 0x7f, 0x11, 0xfd,
+ 0x41, 0x7c, 0x36, 0x4a, 0xaf, 0x2a, 0x2a, 0xa4, 0x13, 0x9b, 0x9a, 0x77, 0x02, 0xe9, 0xe1, 0x2b,
+ 0x15, 0xff, 0x2e, 0xff, 0xbc, 0xfe, 0xa7, 0x17, 0xbf, 0x0f, 0xfc, 0x7e, 0xd3, 0xb7, 0x6e, 0x0a,
+ 0xa7, 0xcb, 0xda, 0x8c, 0xc5, 0x12, 0x97, 0xf1, 0x23, 0x5a, 0xb2, 0xf9, 0x21, 0xd5, 0xd9, 0x20,
+ 0x5a, 0x72, 0x72, 0x18, 0xe2, 0xcf, 0x1f, 0xcf, 0xd7, 0x35, 0xdc, 0x62, 0x6e, 0x2b, 0x84, 0x35,
+ 0x12, 0x0f, 0xc4, 0xe5, 0x8b, 0x51, 0x2e, 0x9f, 0x4d, 0x3b, 0x10, 0xcb, 0x47, 0x6b, 0xae, 0x74,
+ 0xff, 0xfd, 0x8d, 0x63, 0xab, 0xab, 0x11, 0x53, 0xb8, 0xd5, 0x92, 0x8b, 0x45, 0x03, 0x9e, 0x61,
+ 0xd1, 0x92, 0xcd, 0x17, 0x3c, 0x97, 0x53, 0x71, 0x27, 0xdc, 0x95, 0x3a, 0xd6, 0xdb, 0x30, 0x4d,
+ 0x69, 0xee, 0x23, 0x26, 0x8f, 0xc5, 0x4a, 0x5d, 0x76, 0x2e, 0xa5, 0xa0, 0x7f, 0xe7, 0xa3, 0xff,
+ 0x9e, 0x40, 0x56, 0xae, 0xbd, 0xb1, 0x77, 0xec, 0x37, 0x67, 0x82, 0x39, 0x9d, 0x08, 0x6c, 0x52,
+ 0x89, 0x59, 0x22, 0xf9, 0x03, 0x9f, 0xbf, 0x84, 0x3e, 0x15, 0xb1, 0xe7, 0x2f, 0xcd, 0x92, 0xcf,
+ 0x5e, 0xad, 0x6b, 0x78, 0xbe, 0x86, 0x63, 0x32, 0x99, 0xad, 0x4a, 0x8e, 0xcb, 0x64, 0x8e, 0xb9,
+ 0x75, 0x74, 0x73, 0x6c, 0xbe, 0xbe, 0x42, 0xfa, 0x9a, 0x7c, 0x6d, 0x97, 0x36, 0xfd, 0x24, 0x36,
+ 0xd1, 0x4f, 0x76, 0x8b, 0xd6, 0x4f, 0x01, 0xe0, 0xb9, 0x14, 0x24, 0xc7, 0x2c, 0x79, 0x71, 0x6f,
+ 0xa4, 0xfa, 0x3e, 0x73, 0x07, 0xb4, 0x6b, 0x12, 0x97, 0x88, 0x31, 0x9e, 0xcb, 0x54, 0x4c, 0x56,
+ 0x46, 0x87, 0x34, 0xf6, 0xf9, 0x63, 0xd2, 0xbd, 0x8a, 0xbf, 0xdd, 0x9b, 0x7d, 0x2e, 0x5a, 0x82,
+ 0x31, 0x8b, 0xd6, 0x4f, 0xfe, 0x80, 0x8a, 0x30, 0xcd, 0x7a, 0x21, 0xb3, 0xe0, 0xb8, 0xe4, 0xd7,
+ 0x3f, 0xa3, 0x98, 0x0d, 0xce, 0xe2, 0x49, 0x66, 0x32, 0x9d, 0x86, 0x9d, 0xe7, 0x2d, 0xa2, 0x17,
+ 0xf9, 0x67, 0xe3, 0x9f, 0xef, 0x93, 0xfe, 0x8e, 0xc9, 0x2e, 0x99, 0x50, 0x53, 0x64, 0x4a, 0xcc,
+ 0x91, 0xcd, 0x1b, 0xf1, 0xf5, 0x0a, 0x64, 0x92, 0xff, 0x7e, 0x8e, 0xd2, 0xdc, 0x62, 0xae, 0xd6,
+ 0x98, 0xd2, 0x58, 0x36, 0x9b, 0x36, 0x6c, 0x22, 0xc3, 0x02, 0x93, 0x71, 0x5c, 0x9a, 0xa4, 0xdc,
+ 0x9d, 0xa4, 0xb7, 0x15, 0x4b, 0xbb, 0xb2, 0xcf, 0x66, 0x91, 0x65, 0x44, 0xdf, 0x4f, 0xde, 0xc0,
+ 0x51, 0xaf, 0xa5, 0xe8, 0xe9, 0xa0, 0x01, 0xe2, 0x72, 0xf5, 0x38, 0x73, 0xb4, 0xa6, 0xa2, 0x32,
+ 0x95, 0x4c, 0x46, 0x39, 0xab, 0x8c, 0x5f, 0x2b, 0xe7, 0xf9, 0xab, 0x71, 0x4c, 0xe2, 0xf5, 0xd2,
+ 0x58, 0x51, 0x56, 0xdd, 0xb3, 0xaf, 0x0f, 0xfd, 0xeb, 0x81, 0xe2, 0xef, 0x72, 0xd0, 0xb2, 0x41,
+ 0xaa, 0x55, 0xcc, 0x13, 0xc9, 0x1b, 0x38, 0x52, 0xb2, 0x64, 0xc4, 0x11, 0x90, 0xae, 0x5d, 0xf7,
+ 0xaa, 0x91, 0x54, 0xa6, 0xb2, 0x79, 0xe2, 0xb9, 0x4c, 0xbe, 0x96, 0x24, 0x93, 0xb7, 0x2b, 0xfe,
+ 0x28, 0xff, 0x56, 0x65, 0xa8, 0xfa, 0x9d, 0x1c, 0xb4, 0xf5, 0x55, 0xc5, 0xbf, 0x3d, 0x97, 0x7d,
+ 0x36, 0x70, 0x8e, 0x48, 0x5c, 0x31, 0xf3, 0x05, 0xf4, 0x0e, 0x99, 0xe4, 0xa2, 0x4d, 0xf0, 0xe8,
+ 0xaf, 0xf7, 0xb2, 0xcc, 0xf3, 0x35, 0x0f, 0x92, 0xf6, 0x94, 0xf1, 0x96, 0x6a, 0x02, 0x93, 0x89,
+ 0x2b, 0x25, 0x77, 0xdd, 0x8e, 0x24, 0xf2, 0x5b, 0xd5, 0xcb, 0xd5, 0xf7, 0xe5, 0xd8, 0x9a, 0x3d,
+ 0x53, 0x73, 0x37, 0x07, 0x59, 0xeb, 0x20, 0xa0, 0xdf, 0x14, 0x54, 0xae, 0xa4, 0x1f, 0xf1, 0xe7,
+ 0x7e, 0x1a, 0x41, 0x4b, 0xf0, 0x29, 0x77, 0xec, 0xf9, 0xfe, 0x2b, 0xc4, 0x65, 0x7d, 0x26, 0x0d,
+ 0x1b, 0xbb, 0xdb, 0x48, 0xb4, 0x79, 0x84, 0x55, 0x52, 0x5a, 0xaf, 0x18, 0xa9, 0xfa, 0x56, 0xf5,
+ 0x9e, 0xfc, 0x4e, 0x05, 0x6f, 0xfb, 0xdc, 0xcf, 0xc1, 0xf6, 0x01, 0x4c, 0xaa, 0xc5, 0x3d, 0x66,
+ 0xbe, 0x80, 0xa8, 0x17, 0xae, 0x95, 0x04, 0x8f, 0x9a, 0x77, 0x51, 0x9c, 0x5c, 0xa6, 0xe1, 0xf2,
+ 0xd9, 0xf9, 0x64, 0x76, 0x2b, 0x13, 0x25, 0xb2, 0x4f, 0x5a, 0x56, 0xad, 0xae, 0xfa, 0xac, 0x6a,
+ 0x6f, 0x8c, 0x74, 0x37, 0x56, 0xb6, 0x33, 0x74, 0x4e, 0xf3, 0x81, 0xc8, 0x57, 0xb3, 0x5e, 0x2e,
+ 0x56, 0x2e, 0xc8, 0x03, 0x98, 0xcb, 0xb5, 0x68, 0x3d, 0xbc, 0xe3, 0x92, 0x0f, 0xab, 0xe7, 0x98,
+ 0x33, 0x69, 0xac, 0xd8, 0x04, 0x26, 0x05, 0xed, 0xba, 0x29, 0x91, 0x8d, 0x52, 0xa3, 0x42, 0x5d,
+ 0xb5, 0xbf, 0x2a, 0xb2, 0x2f, 0xf6, 0x95, 0x7d, 0xd2, 0x33, 0x8a, 0x7f, 0x4e, 0xb0, 0x7c, 0xfa,
+ 0xc9, 0x2e, 0xfd, 0x4e, 0x73, 0xf2, 0xc9, 0x79, 0xa8, 0x42, 0x21, 0xe6, 0x17, 0xe4, 0x07, 0xa1,
+ 0x2a, 0x0c, 0x68, 0x35, 0x99, 0xe4, 0xc5, 0xbd, 0xf7, 0x6a, 0x29, 0x0d, 0x92, 0xcd, 0x8a, 0xd4,
+ 0xb2, 0x99, 0xb4, 0x52, 0x56, 0xf2, 0x12, 0xd9, 0x28, 0xfd, 0x45, 0x85, 0xa6, 0x7a, 0x57, 0x95,
+ 0xa6, 0xfa, 0x0d, 0x45, 0x3c, 0x93, 0x77, 0x14, 0x36, 0xcd, 0x7f, 0x26, 0x70, 0x06, 0xb5, 0x46,
+ 0x7d, 0xf6, 0x69, 0xab, 0x52, 0x77, 0x2d, 0x61, 0x6d, 0x84, 0x9c, 0x15, 0x42, 0x27, 0x6a, 0xd9,
+ 0xad, 0x43, 0xa8, 0xd6, 0x84, 0xf7, 0x01, 0x5f, 0x10, 0xa7, 0x6a, 0xef, 0xd5, 0x5e, 0xae, 0xa5,
+ 0x18, 0x7b, 0x1a, 0x4d, 0x1b, 0x6f, 0x07, 0x61, 0x89, 0x3c, 0x26, 0xfd, 0x48, 0x3e, 0xbb, 0x6f,
+ 0xd7, 0x7e, 0x4d, 0xf5, 0xeb, 0xf2, 0xbe, 0x04, 0x2f, 0xc1, 0x03, 0xc5, 0x2d, 0xe6, 0xa7, 0x47,
+ 0xfe, 0x35, 0x21, 0x1b, 0x28, 0x48, 0xb5, 0x20, 0x2e, 0x81, 0x4d, 0x86, 0xeb, 0x54, 0x22, 0x30,
+ 0x57, 0x22, 0x83, 0x1e, 0x8b, 0xe2, 0x69, 0xf7, 0x7c, 0xc0, 0xd5, 0x8f, 0xd5, 0x37, 0xeb, 0xb1,
+ 0x77, 0x7d, 0x81, 0xfc, 0x9b, 0x57, 0xfd, 0xf5, 0x94, 0xe6, 0x72, 0xed, 0x87, 0xb5, 0xb7, 0xe4,
+ 0xb7, 0x2b, 0xb2, 0x49, 0xe6, 0xc4, 0xb3, 0x15, 0xd2, 0xf7, 0xe4, 0x63, 0xfb, 0xfe, 0xa4, 0x5a,
+ 0x47, 0xbb, 0x8f, 0xef, 0x63, 0x5f, 0x1f, 0x8d, 0x89, 0xcd, 0x31, 0xef, 0x1e, 0xf9, 0x7c, 0x38,
+ 0xf1, 0x6c, 0xd0, 0x59, 0xf2, 0x53, 0xc3, 0xb4, 0x15, 0xd8, 0x04, 0x3e, 0x5b, 0x2c, 0xcf, 0xe8,
+ 0x78, 0x36, 0xb5, 0x04, 0xf4, 0x40, 0x15, 0xe3, 0x25, 0xf9, 0x00, 0x57, 0x37, 0xec, 0xd2, 0xe3,
+ 0xce, 0x24, 0x41, 0xea, 0x86, 0x7d, 0xf7, 0x5b, 0x91, 0xfa, 0xe7, 0x34, 0x2c, 0xf3, 0x4e, 0xed,
+ 0x72, 0xf5, 0x51, 0x45, 0x5f, 0x06, 0x36, 0x1d, 0x15, 0x6d, 0xd5, 0x37, 0xab, 0x76, 0x55, 0xfd,
+ 0x66, 0xbf, 0xb1, 0x22, 0x8e, 0x77, 0x69, 0x9f, 0xb4, 0xa2, 0xf2, 0xaa, 0xe2, 0xf9, 0x9a, 0x76,
+ 0xcd, 0xe5, 0xb7, 0xde, 0x75, 0x41, 0x96, 0x6d, 0x62, 0xf5, 0x44, 0x2f, 0xcb, 0x73, 0x09, 0xa3,
+ 0xdb, 0x72, 0x6e, 0x33, 0xc2, 0x09, 0xb6, 0x2c, 0x21, 0xfa, 0xd8, 0xf3, 0x00, 0xe6, 0x72, 0xc8,
+ 0xe0, 0x8c, 0x9e, 0xeb, 0x79, 0x69, 0xe0, 0xb3, 0xd1, 0x23, 0xa7, 0x96, 0xeb, 0xdb, 0x35, 0xed,
+ 0xcc, 0xbb, 0xd5, 0x6d, 0xb5, 0xef, 0x54, 0x2f, 0x57, 0xe3, 0x9c, 0xad, 0x89, 0xe8, 0x80, 0x7f,
+ 0x97, 0x57, 0x8e, 0x55, 0xbf, 0x5d, 0x75, 0xb8, 0x4a, 0x5d, 0xd5, 0x53, 0xfd, 0xdb, 0x8a, 0xc6,
+ 0x58, 0xbd, 0x2a, 0x3d, 0xc6, 0x65, 0x74, 0xcd, 0x31, 0x75, 0x9a, 0xf7, 0x4e, 0x7c, 0x37, 0xc3,
+ 0x7a, 0xeb, 0xbc, 0x11, 0x4f, 0x9b, 0x7b, 0xcd, 0x18, 0xff, 0xbe, 0x41, 0x6a, 0xa7, 0x59, 0xe0,
+ 0xd2, 0x67, 0x6f, 0xb1, 0x74, 0x6c, 0x4a, 0x26, 0xf4, 0xf9, 0x13, 0x3b, 0x97, 0x6c, 0x1d, 0xf1,
+ 0x5c, 0x96, 0xc8, 0x0e, 0x0f, 0x6b, 0x5c, 0x1a, 0x97, 0x75, 0x60, 0x16, 0xc9, 0xe6, 0x2d, 0xe6,
+ 0x68, 0x0d, 0xc5, 0xbc, 0x53, 0xdd, 0x53, 0xfd, 0x72, 0xed, 0x9f, 0xf7, 0xff, 0x79, 0xff, 0xcb,
+ 0xb5, 0x3d, 0xb5, 0x9f, 0xed, 0x37, 0xec, 0x7f, 0xbb, 0x6a, 0xa4, 0xea, 0x12, 0x62, 0xb1, 0x3e,
+ 0x7e, 0x4d, 0x95, 0x42, 0x5e, 0xc1, 0x6d, 0x24, 0x8d, 0x1f, 0x69, 0x5e, 0x6f, 0xa9, 0x3b, 0x0f,
+ 0x15, 0x0c, 0xae, 0xa0, 0x31, 0xe7, 0xb7, 0xf9, 0xf6, 0x78, 0x0f, 0x0f, 0xd3, 0x09, 0xef, 0xec,
+ 0x65, 0xcf, 0xc7, 0x48, 0xe6, 0xb4, 0xd5, 0xbb, 0x79, 0x56, 0x37, 0xba, 0xcb, 0xa4, 0x45, 0xc9,
+ 0xdc, 0x0a, 0xf8, 0x8e, 0x16, 0x02, 0x97, 0x27, 0x87, 0x7b, 0x66, 0xc6, 0x66, 0x34, 0x6e, 0xeb,
+ 0x80, 0xff, 0x15, 0x4a, 0x33, 0x87, 0xd8, 0x7c, 0xa0, 0x30, 0x49, 0x1d, 0x8a, 0x8f, 0x98, 0x3d,
+ 0x8c, 0xbf, 0x1a, 0x46, 0x1d, 0xf3, 0x0b, 0x45, 0x63, 0x62, 0x14, 0x05, 0xc9, 0x6a, 0x23, 0xb2,
+ 0x58, 0x8f, 0xd6, 0x8c, 0x33, 0xef, 0x1d, 0x61, 0xcf, 0x9d, 0xf6, 0x41, 0x1d, 0x8a, 0xf2, 0x10,
+ 0x1e, 0x2b, 0x01, 0x9b, 0x4f, 0xe3, 0x4a, 0xcc, 0x13, 0x01, 0x2f, 0x8f, 0xa0, 0x67, 0xa7, 0xad,
+ 0x2f, 0x6c, 0xa6, 0x7e, 0x89, 0x92, 0x99, 0x0f, 0xf8, 0x3d, 0x09, 0x6f, 0xc7, 0x22, 0x2e, 0x47,
+ 0x67, 0x67, 0x22, 0x5f, 0xcc, 0xce, 0x80, 0x6c, 0x7e, 0xf5, 0xca, 0xbd, 0x5a, 0xcc, 0x66, 0xea,
+ 0x08, 0x58, 0x2c, 0x8f, 0x0f, 0x14, 0x6f, 0xd4, 0xdc, 0x62, 0x58, 0xcd, 0x77, 0xa7, 0xbe, 0x9b,
+ 0xc1, 0x95, 0x2b, 0x4c, 0xe1, 0xde, 0xe8, 0x30, 0x85, 0x37, 0x02, 0x94, 0xb7, 0xd5, 0x92, 0xf8,
+ 0xee, 0x4e, 0x52, 0x60, 0xf3, 0xbc, 0xf5, 0x60, 0x8c, 0xad, 0x0b, 0x3b, 0x93, 0x90, 0xd8, 0xbb,
+ 0x6d, 0x4b, 0xe0, 0x4f, 0x21, 0xf0, 0xdd, 0x49, 0x4a, 0x64, 0x23, 0xa3, 0x11, 0x0f, 0x54, 0x82,
+ 0x99, 0x9d, 0x29, 0x73, 0x59, 0x87, 0xbf, 0x7a, 0xf5, 0x5e, 0xed, 0x38, 0xc7, 0x66, 0x72, 0xb6,
+ 0x08, 0xd6, 0xaa, 0x98, 0xc7, 0x33, 0x35, 0xf7, 0x99, 0x76, 0x24, 0x91, 0xed, 0x17, 0xc7, 0x7d,
+ 0x1b, 0x01, 0xcc, 0x23, 0x5f, 0xbf, 0x62, 0x9e, 0xab, 0x40, 0x31, 0xe7, 0xbf, 0x34, 0x9a, 0xdc,
+ 0x37, 0xe3, 0x2c, 0xf9, 0x8c, 0xae, 0xdb, 0x32, 0x6d, 0x3d, 0x6f, 0x7d, 0x33, 0xae, 0xfe, 0x4f,
+ 0x3f, 0xc9, 0x77, 0xfb, 0xa2, 0x1f, 0xd3, 0x37, 0xf1, 0x63, 0x07, 0xce, 0x11, 0x51, 0xea, 0x98,
+ 0xcd, 0x93, 0x5e, 0x25, 0xb2, 0x4b, 0xa3, 0x94, 0x77, 0xdc, 0x0f, 0x95, 0x79, 0xc6, 0x10, 0x9b,
+ 0x6f, 0x0f, 0x7f, 0xfe, 0x2a, 0x96, 0xcd, 0xdb, 0x8a, 0xc6, 0x4a, 0xc1, 0xfe, 0x01, 0x0e, 0x8f,
+ 0x21, 0x16, 0x2b, 0x2a, 0xef, 0x20, 0x1e, 0x9f, 0xaf, 0xb1, 0x31, 0x54, 0xc3, 0x7f, 0x9c, 0x7a,
+ 0x6e, 0xfe, 0x8a, 0xbf, 0x3c, 0xca, 0xa3, 0x90, 0x4f, 0x89, 0x73, 0x9d, 0x4d, 0xe1, 0x7b, 0x5f,
+ 0x4c, 0x19, 0x92, 0xe7, 0x70, 0x80, 0x08, 0x52, 0xe7, 0xd4, 0x07, 0x55, 0xf1, 0x71, 0x2e, 0x3a,
+ 0x2a, 0x99, 0xa2, 0x35, 0x9b, 0x2b, 0x70, 0x57, 0xb6, 0x25, 0xe3, 0x9a, 0x91, 0xef, 0x95, 0x88,
+ 0xb8, 0x74, 0xd4, 0x79, 0x61, 0xad, 0x3b, 0xed, 0xc3, 0x6c, 0x8e, 0x8c, 0xfe, 0xe1, 0xe8, 0xbd,
+ 0x5a, 0x1b, 0xb3, 0xc1, 0x9c, 0xa9, 0xb9, 0xaa, 0xb8, 0x83, 0xc6, 0x03, 0x34, 0xee, 0x28, 0x6e,
+ 0x2b, 0x1c, 0x88, 0xc5, 0xfa, 0x1a, 0xc8, 0x82, 0xa6, 0x34, 0x7b, 0x8e, 0xfc, 0xd1, 0x7d, 0x9a,
+ 0xab, 0x0a, 0xc4, 0xd5, 0x93, 0x79, 0x98, 0x0c, 0x38, 0xdb, 0x70, 0x69, 0x34, 0xf7, 0x1a, 0xfd,
+ 0xd0, 0xf1, 0x74, 0x48, 0xec, 0xf6, 0x95, 0x23, 0x84, 0x5e, 0x89, 0x42, 0xde, 0x7a, 0x89, 0x6c,
+ 0xdd, 0x61, 0xf3, 0x95, 0x87, 0x1a, 0xd1, 0x0a, 0x67, 0xdb, 0x64, 0x73, 0xdd, 0xbc, 0x5c, 0x4f,
+ 0x69, 0x20, 0x73, 0xfd, 0x16, 0x1a, 0xf7, 0xb9, 0x9f, 0xb7, 0xd0, 0x23, 0x1b, 0x5a, 0x1f, 0xa9,
+ 0x86, 0x3d, 0x2d, 0x3f, 0x3f, 0x6f, 0x43, 0x36, 0x2b, 0xe8, 0xd6, 0xde, 0xf0, 0x7c, 0x9a, 0x5a,
+ 0x3f, 0x70, 0xe6, 0xef, 0xb4, 0x7f, 0xc9, 0x98, 0x7b, 0xed, 0xd2, 0x4e, 0x75, 0xa9, 0x59, 0xec,
+ 0xf6, 0x95, 0x1b, 0xa0, 0xaa, 0x33, 0xf4, 0x4a, 0x64, 0xcc, 0x42, 0xe6, 0x56, 0x89, 0x6c, 0xb7,
+ 0x0b, 0xd7, 0x6a, 0x32, 0x85, 0x57, 0x02, 0xed, 0xbe, 0x88, 0xa7, 0x87, 0xab, 0x51, 0xb8, 0xfb,
+ 0xd4, 0x1f, 0x5e, 0xfd, 0xea, 0x95, 0xff, 0xad, 0x8f, 0xd4, 0x47, 0x6a, 0x23, 0xb5, 0xf7, 0xd0,
+ 0x40, 0xff, 0xaa, 0xff, 0xf9, 0x91, 0x5f, 0x9d, 0x88, 0x0c, 0xdf, 0xf3, 0xe4, 0xc2, 0x24, 0xa0,
+ 0x37, 0xdc, 0xe3, 0xce, 0x5e, 0x83, 0x82, 0x47, 0x3f, 0x09, 0x7e, 0x76, 0xc8, 0x19, 0x11, 0xf5,
+ 0x6c, 0x66, 0xe0, 0x0e, 0xd1, 0x84, 0x0e, 0xb2, 0x32, 0x84, 0xab, 0x50, 0x77, 0xab, 0x3c, 0x04,
+ 0x8c, 0x4c, 0x44, 0x1a, 0x42, 0x73, 0x7e, 0x8e, 0x4d, 0x24, 0x9b, 0x5f, 0x3a, 0x46, 0x86, 0x0d,
+ 0x03, 0x3f, 0x39, 0xb5, 0xfb, 0xad, 0xdd, 0x6f, 0x95, 0xbd, 0xa5, 0x39, 0xd5, 0x76, 0xaa, 0xe7,
+ 0x8c, 0x7f, 0xe0, 0x57, 0xae, 0x88, 0xe7, 0x75, 0xdf, 0x69, 0x3f, 0xbf, 0x4a, 0xce, 0xa7, 0xac,
+ 0xf2, 0x14, 0xab, 0x67, 0x37, 0x02, 0xa9, 0xeb, 0x77, 0xa5, 0x46, 0x13, 0xd7, 0xef, 0x54, 0xec,
+ 0xf9, 0x9e, 0x0d, 0xb8, 0x43, 0xf4, 0x92, 0x91, 0x31, 0xc7, 0xe6, 0x39, 0x37, 0xa9, 0x96, 0x3d,
+ 0x7c, 0x6d, 0x90, 0x8f, 0x23, 0xe5, 0xa1, 0x71, 0x3f, 0xd4, 0x36, 0xec, 0x71, 0x6b, 0x5c, 0xeb,
+ 0x8e, 0x9b, 0x8e, 0x4b, 0xa3, 0x97, 0xd0, 0xcf, 0x75, 0x47, 0x99, 0xab, 0xcd, 0x3d, 0x36, 0xb3,
+ 0xec, 0xa1, 0xbc, 0xed, 0xbe, 0x71, 0x7f, 0xa6, 0x55, 0x32, 0x59, 0xcf, 0x52, 0xde, 0x5c, 0xce,
+ 0x23, 0x60, 0x68, 0x89, 0x66, 0xbd, 0x68, 0x01, 0x65, 0x03, 0xee, 0x10, 0xdd, 0xac, 0xef, 0xb6,
+ 0xc4, 0xeb, 0x3c, 0xa8, 0xd8, 0xc3, 0x6b, 0x49, 0xb0, 0x3d, 0x37, 0x02, 0x98, 0xcd, 0xb1, 0x99,
+ 0x36, 0xc4, 0x67, 0x19, 0x1a, 0x1a, 0x17, 0xd4, 0x88, 0x45, 0x7b, 0x50, 0x4f, 0x9d, 0xd7, 0x16,
+ 0xc3, 0x64, 0x20, 0x03, 0x83, 0xb1, 0x30, 0x85, 0x2f, 0x65, 0xa9, 0x0e, 0x13, 0x8b, 0x7e, 0x92,
+ 0x31, 0xf3, 0xfd, 0x4e, 0xe9, 0x22, 0x7f, 0x07, 0x4f, 0x07, 0x78, 0xfd, 0x0a, 0x56, 0x0f, 0x1d,
+ 0x73, 0xbd, 0x9f, 0x8c, 0xad, 0x96, 0xf5, 0x90, 0xdb, 0x17, 0x62, 0x36, 0x23, 0x9e, 0x59, 0x0f,
+ 0xae, 0xf2, 0x3b, 0x8b, 0xe4, 0x31, 0xc2, 0x49, 0x24, 0xae, 0x32, 0x8a, 0x99, 0x5c, 0x4d, 0xcb,
+ 0x5d, 0x32, 0xe6, 0xfc, 0xb9, 0xaf, 0x99, 0x48, 0xeb, 0xab, 0xba, 0x2d, 0xcd, 0xa2, 0x9e, 0x4d,
+ 0x03, 0x6c, 0xbf, 0x42, 0xff, 0x83, 0xc4, 0x5e, 0xb4, 0x4a, 0x9d, 0x29, 0x1c, 0xff, 0xbd, 0xc3,
+ 0xaa, 0x09, 0x75, 0x60, 0xdb, 0x91, 0x4d, 0x1b, 0xf1, 0x44, 0x38, 0x16, 0xa1, 0xe2, 0x2f, 0x96,
+ 0xc8, 0x8d, 0xbb, 0xd9, 0xed, 0x9d, 0x64, 0xcc, 0x47, 0xde, 0xde, 0x82, 0x64, 0xc2, 0x59, 0x6d,
+ 0x88, 0x9b, 0x88, 0xf6, 0x6c, 0x32, 0xe8, 0x68, 0x95, 0x82, 0x29, 0x43, 0xa9, 0x39, 0x7e, 0xb7,
+ 0x77, 0x50, 0x15, 0x5b, 0x27, 0x0b, 0x63, 0x15, 0xd9, 0x9e, 0xe5, 0x1c, 0x9b, 0x36, 0x5f, 0x9d,
+ 0xaf, 0xce, 0x0b, 0x15, 0x82, 0x81, 0x47, 0x5e, 0x22, 0xb7, 0xce, 0x24, 0x80, 0xf2, 0x6e, 0x45,
+ 0x32, 0x21, 0xd3, 0x12, 0xec, 0x59, 0xd1, 0xa3, 0x97, 0x08, 0x58, 0x29, 0x21, 0xfa, 0x0c, 0x95,
+ 0x60, 0xe8, 0x98, 0xeb, 0x4e, 0xf2, 0x83, 0xd1, 0x54, 0x76, 0xe8, 0x7c, 0x04, 0xb3, 0x39, 0xe7,
+ 0x1f, 0xf7, 0x9f, 0x46, 0x03, 0xf3, 0xb8, 0xc1, 0xdb, 0x3b, 0x59, 0x2c, 0xd7, 0xd4, 0x30, 0x85,
+ 0x2f, 0xe4, 0x50, 0xb7, 0x52, 0x40, 0xa7, 0x8a, 0x89, 0x7a, 0xf4, 0x44, 0x3d, 0x2b, 0x80, 0x5f,
+ 0x29, 0x21, 0xdb, 0x2d, 0xfe, 0x7b, 0x59, 0x33, 0xae, 0xa4, 0x31, 0x5f, 0x60, 0xd5, 0x2c, 0x0f,
+ 0xe1, 0xaa, 0xdb, 0x30, 0x80, 0xc7, 0xc6, 0x2d, 0xaf, 0x92, 0xb1, 0x58, 0x7d, 0x58, 0xe6, 0xda,
+ 0x4a, 0x1f, 0x5c, 0x2d, 0xa1, 0xd4, 0x95, 0x8a, 0x7a, 0x36, 0x0e, 0xfc, 0x4a, 0x09, 0x5e, 0xbb,
+ 0x78, 0xff, 0x67, 0x88, 0x5d, 0xf6, 0xa4, 0x97, 0x31, 0xf0, 0x1c, 0x34, 0x44, 0xe3, 0x57, 0x0d,
+ 0xa1, 0xc6, 0x70, 0xbe, 0xba, 0x55, 0xc0, 0x9c, 0x7f, 0x6b, 0xfd, 0xe0, 0x9c, 0x24, 0xcc, 0x19,
+ 0x32, 0x47, 0x44, 0x3d, 0x0b, 0xa0, 0xa3, 0x7b, 0x4a, 0xf0, 0xf4, 0xc4, 0x4b, 0x85, 0x5c, 0xf6,
+ 0xa5, 0x23, 0xd1, 0xea, 0x89, 0x97, 0x23, 0xd0, 0xb4, 0xbd, 0x61, 0x1c, 0xc5, 0x02, 0xcd, 0x9a,
+ 0xeb, 0x0e, 0x24, 0x1d, 0x26, 0x22, 0xb9, 0x54, 0x07, 0x8e, 0x9f, 0x63, 0x29, 0x17, 0xd3, 0x14,
+ 0xfd, 0xb3, 0x00, 0xb0, 0x79, 0x06, 0xd5, 0x5d, 0x88, 0xc9, 0x78, 0xcb, 0x43, 0x4b, 0xec, 0x34,
+ 0xcf, 0xf9, 0x57, 0x33, 0x7e, 0xf7, 0xc0, 0x26, 0xae, 0x88, 0x5f, 0x38, 0x8f, 0xf8, 0x7e, 0x6d,
+ 0xee, 0xad, 0x76, 0x8e, 0x87, 0x53, 0x60, 0x4a, 0x9d, 0xb8, 0x3b, 0xc1, 0x51, 0x67, 0xa8, 0xb7,
+ 0x2c, 0xc4, 0x2a, 0x79, 0x74, 0xaa, 0xc6, 0x66, 0x52, 0xd7, 0x58, 0x4f, 0xfc, 0xfe, 0x61, 0x14,
+ 0x0b, 0x2b, 0x81, 0xad, 0x76, 0xdd, 0x84, 0x6a, 0xf0, 0xd8, 0x0b, 0xb4, 0xbd, 0x57, 0x4d, 0x3e,
+ 0x26, 0x02, 0x36, 0x4f, 0x62, 0xa4, 0x70, 0xda, 0x9a, 0xce, 0xea, 0x79, 0x94, 0x98, 0x88, 0x74,
+ 0x5b, 0xe8, 0x2d, 0x7e, 0x0a, 0x27, 0x59, 0x6a, 0x9e, 0x32, 0x42, 0x27, 0xc6, 0xed, 0xbb, 0x6a,
+ 0xd2, 0x9b, 0xde, 0xd7, 0xf8, 0xca, 0x04, 0x80, 0x12, 0xd9, 0x6c, 0x4e, 0x52, 0x59, 0x6c, 0xac,
+ 0x3e, 0x1c, 0x9b, 0xd9, 0xaa, 0x96, 0x05, 0x7f, 0x31, 0x54, 0x01, 0xda, 0xbe, 0xab, 0x26, 0x1d,
+ 0xf5, 0xbe, 0x82, 0x86, 0x4a, 0xee, 0x5e, 0x38, 0x6d, 0x1d, 0xcf, 0xb2, 0x56, 0x3e, 0x2a, 0xa4,
+ 0xae, 0x87, 0x98, 0x19, 0x5a, 0x02, 0x7b, 0x1e, 0xb7, 0xeb, 0xee, 0x44, 0x4b, 0xf4, 0x73, 0x2b,
+ 0x25, 0xe4, 0x29, 0x26, 0x3e, 0xb7, 0x40, 0xad, 0x3b, 0xe2, 0xfb, 0x4f, 0x3c, 0x3e, 0x40, 0x8d,
+ 0x7e, 0x7a, 0xcb, 0x9f, 0x06, 0xa2, 0x9a, 0xd0, 0x49, 0x77, 0x3b, 0xc6, 0x4e, 0xf0, 0x4a, 0x09,
+ 0x1d, 0x4b, 0x87, 0x0c, 0x74, 0xd2, 0xb3, 0x4b, 0xc6, 0xd9, 0x99, 0xde, 0x0c, 0xbb, 0x91, 0x47,
+ 0x8b, 0x76, 0xdf, 0x56, 0x3c, 0x06, 0x3c, 0xa0, 0x57, 0x26, 0x8e, 0x9d, 0x6c, 0x37, 0x36, 0xf1,
+ 0x4e, 0x04, 0xf6, 0x94, 0xce, 0xa4, 0xef, 0x0d, 0x3a, 0x56, 0x50, 0xde, 0x27, 0xc7, 0x65, 0x6f,
+ 0x38, 0x5d, 0xa7, 0xea, 0xcc, 0x80, 0x5c, 0xe8, 0xed, 0x17, 0x3b, 0xc1, 0x3b, 0x91, 0x66, 0x7d,
+ 0xab, 0x25, 0x55, 0x04, 0x78, 0x91, 0x1d, 0x19, 0xad, 0xf3, 0x66, 0xf2, 0x12, 0x14, 0x0f, 0xab,
+ 0x31, 0x43, 0xb8, 0xb6, 0xee, 0xc8, 0xe7, 0x53, 0x69, 0x89, 0x2e, 0xfd, 0x76, 0xdb, 0x9d, 0xf0,
+ 0xfa, 0x35, 0xd9, 0xfb, 0x8a, 0x31, 0x65, 0xb8, 0xe9, 0xa0, 0xbc, 0xe5, 0xa1, 0xd5, 0xb4, 0x0c,
+ 0x14, 0x83, 0x43, 0xdc, 0x79, 0xaf, 0x8f, 0xf3, 0x1b, 0xe1, 0xd1, 0x1b, 0xe6, 0xdf, 0x71, 0x25,
+ 0x90, 0x5f, 0xcd, 0x10, 0x1c, 0xa3, 0xde, 0x4e, 0x3e, 0x3d, 0x5e, 0xbf, 0xae, 0x25, 0xed, 0x44,
+ 0x00, 0x0b, 0x54, 0x8b, 0xe5, 0xa6, 0xe3, 0xb2, 0x27, 0xb1, 0x6f, 0x57, 0xb1, 0x38, 0x04, 0x2f,
+ 0x91, 0x29, 0xdc, 0xc8, 0x79, 0x72, 0x37, 0xa2, 0x1d, 0x31, 0xe7, 0xfc, 0x73, 0x5c, 0x9c, 0xa5,
+ 0x21, 0x84, 0xab, 0x58, 0xce, 0x47, 0x6e, 0xd8, 0x93, 0x67, 0x96, 0x0b, 0xe4, 0xb2, 0x6e, 0xcb,
+ 0xf6, 0x89, 0x9d, 0xe0, 0x98, 0x48, 0xb3, 0x5e, 0xc8, 0x64, 0x8e, 0xc7, 0xa4, 0x3a, 0x6c, 0xbf,
+ 0xe9, 0xe8, 0x71, 0x43, 0x3e, 0x6c, 0x5f, 0xda, 0x1d, 0x26, 0x44, 0x30, 0x21, 0xc7, 0x6e, 0x3e,
+ 0xda, 0xdb, 0xb2, 0x37, 0x0c, 0x7d, 0x31, 0x33, 0xed, 0x48, 0x7f, 0x1f, 0xed, 0x7d, 0xd9, 0xc0,
+ 0xc5, 0x56, 0x20, 0x56, 0x66, 0xf3, 0xb5, 0xfb, 0xe0, 0xbc, 0x17, 0xf4, 0xaa, 0x85, 0x51, 0xe7,
+ 0x85, 0x8e, 0x99, 0xab, 0xdc, 0xab, 0x23, 0x9e, 0x7c, 0xec, 0x1f, 0xf8, 0x74, 0xcd, 0xdb, 0x28,
+ 0x46, 0x8d, 0xcf, 0x17, 0x80, 0xfd, 0x9a, 0xea, 0xdb, 0x3a, 0x40, 0x1c, 0xd2, 0xbf, 0x34, 0x70,
+ 0xc9, 0xd1, 0xe6, 0x8e, 0x78, 0x6c, 0xbe, 0x8d, 0x80, 0xa0, 0xf7, 0x12, 0x01, 0xdd, 0x2f, 0xaf,
+ 0x70, 0x71, 0xcb, 0x71, 0xee, 0x67, 0xa6, 0xd7, 0x82, 0x34, 0xf6, 0x72, 0x92, 0x08, 0x2c, 0xda,
+ 0x7c, 0x75, 0xde, 0x3d, 0xde, 0x65, 0x8f, 0xdf, 0x33, 0x3b, 0x33, 0x16, 0x37, 0x96, 0xd1, 0x7b,
+ 0x9a, 0xb8, 0xbb, 0x34, 0x84, 0x4a, 0xcd, 0xf9, 0x7d, 0x3e, 0x1c, 0xa3, 0x06, 0x2f, 0xd0, 0xd3,
+ 0x2e, 0x99, 0x58, 0x2a, 0xc1, 0x46, 0x48, 0x1d, 0xc3, 0x77, 0x92, 0x3b, 0xcd, 0xbf, 0x1c, 0xfe,
+ 0xcc, 0xa1, 0x71, 0x5d, 0x9e, 0x01, 0x39, 0x01, 0x86, 0xd2, 0x45, 0xbd, 0x20, 0x8b, 0xeb, 0x4a,
+ 0x00, 0x98, 0x5c, 0x09, 0x98, 0xd2, 0xf2, 0x18, 0xcb, 0xe5, 0x46, 0x94, 0xc9, 0x65, 0xc4, 0xe2,
+ 0x45, 0x34, 0x7a, 0x12, 0xc6, 0x45, 0x60, 0xd3, 0x6f, 0x0a, 0xe3, 0x58, 0x66, 0xb2, 0x85, 0x9d,
+ 0xdb, 0x27, 0x84, 0xbe, 0xc4, 0xdb, 0xe1, 0xd4, 0x09, 0xdf, 0xaf, 0xa2, 0x2b, 0xa5, 0xd5, 0x03,
+ 0xeb, 0xcd, 0xb4, 0xf5, 0xe4, 0xf0, 0x4d, 0x07, 0xf4, 0x86, 0xa6, 0xbc, 0x36, 0xee, 0xfc, 0x00,
+ 0x62, 0x33, 0x2d, 0x47, 0x90, 0x2d, 0xbb, 0x91, 0xa6, 0xcf, 0x69, 0x32, 0x9f, 0xa6, 0x18, 0x3e,
+ 0x23, 0x9e, 0x65, 0x4e, 0x2e, 0xe3, 0x39, 0x05, 0x36, 0xc7, 0xfd, 0x70, 0xbf, 0x8d, 0xc0, 0xd0,
+ 0xe6, 0x39, 0x13, 0x5a, 0x72, 0x96, 0x3c, 0x9b, 0x33, 0x33, 0x1d, 0xd1, 0x9c, 0xcb, 0xa7, 0xdb,
+ 0x3f, 0x2b, 0xac, 0x95, 0xa9, 0x7f, 0xe7, 0xe1, 0xec, 0x0d, 0xd2, 0xb0, 0xa3, 0x1a, 0x17, 0x74,
+ 0x1e, 0xb5, 0xf9, 0x70, 0xb6, 0x72, 0xa6, 0x4c, 0x01, 0xb0, 0x45, 0x33, 0x49, 0x64, 0x7a, 0x46,
+ 0xa3, 0xd9, 0x42, 0x5e, 0xc8, 0xfe, 0x02, 0x4e, 0x63, 0xd9, 0x5c, 0x09, 0x80, 0x9d, 0xfb, 0xa5,
+ 0x83, 0xb7, 0xcd, 0x68, 0xc9, 0x41, 0xd5, 0x21, 0xfd, 0x33, 0xba, 0x7d, 0x32, 0x3a, 0xa7, 0xcf,
+ 0x09, 0x95, 0x2a, 0xa6, 0x9e, 0xf2, 0x93, 0x9a, 0x50, 0xb3, 0x10, 0xd6, 0x4a, 0x65, 0x8a, 0x4e,
+ 0x13, 0x00, 0xe8, 0x85, 0x07, 0x76, 0x0f, 0xac, 0x95, 0x2b, 0x39, 0x9c, 0x1e, 0xc8, 0x17, 0x38,
+ 0x8a, 0xcd, 0x75, 0x10, 0x0f, 0xf0, 0xf9, 0x7c, 0x90, 0x6d, 0x7b, 0x31, 0xca, 0x66, 0xc4, 0x03,
+ 0x36, 0x50, 0x79, 0xa8, 0x2b, 0x26, 0xfe, 0xd5, 0xa9, 0x7a, 0xff, 0xff, 0xb9, 0xbb, 0xfe, 0x98,
+ 0x36, 0xae, 0x3c, 0x8f, 0x1a, 0xa4, 0xce, 0x69, 0xf9, 0x63, 0xb6, 0xa1, 0xed, 0x54, 0x25, 0x96,
+ 0xe7, 0x70, 0x13, 0x5c, 0xd1, 0x0a, 0xdf, 0xd1, 0x1c, 0xee, 0x11, 0x14, 0xbb, 0x21, 0x0a, 0x56,
+ 0xa9, 0x0e, 0xb7, 0x44, 0xc1, 0x0d, 0x24, 0x8e, 0x61, 0x53, 0xe4, 0xa2, 0x0a, 0x59, 0x5c, 0xc4,
+ 0x51, 0x60, 0x43, 0x0d, 0x55, 0x23, 0x97, 0xbd, 0x72, 0x0e, 0x51, 0x59, 0xc7, 0x28, 0x9c, 0x4c,
+ 0x14, 0x24, 0x13, 0x5d, 0x2a, 0xc3, 0x2d, 0x2b, 0x1b, 0x6d, 0xd8, 0x1a, 0x5d, 0x90, 0xcc, 0x5d,
+ 0x73, 0x67, 0x6b, 0x4b, 0xce, 0x96, 0x82, 0x2e, 0x96, 0xca, 0x49, 0xde, 0x3b, 0xaa, 0xf3, 0x4a,
+ 0x59, 0xc5, 0x37, 0xdf, 0x79, 0x33, 0x9e, 0x19, 0xff, 0x9a, 0x31, 0x06, 0xee, 0xcc, 0x7b, 0xaa,
+ 0x54, 0x83, 0x89, 0x3d, 0xef, 0xf3, 0xbe, 0xef, 0xfb, 0xe3, 0x7d, 0xbf, 0x9f, 0xaf, 0xfe, 0x81,
+ 0xe1, 0x98, 0xf6, 0xb1, 0x24, 0x26, 0x35, 0x88, 0xcf, 0x02, 0xbb, 0xc1, 0x41, 0xb5, 0x80, 0xb8,
+ 0x08, 0x41, 0x36, 0xef, 0xed, 0x10, 0x39, 0x61, 0x47, 0xfd, 0xda, 0x0b, 0xc9, 0xdb, 0x91, 0x8e,
+ 0xe8, 0x72, 0x9c, 0x93, 0xd2, 0xfe, 0x20, 0xc2, 0x13, 0xa1, 0x59, 0xe7, 0x07, 0x4b, 0x6a, 0xdb,
+ 0xc1, 0x3f, 0x3f, 0x66, 0xf0, 0x63, 0xda, 0x07, 0x86, 0x3b, 0xfa, 0x51, 0x95, 0xb8, 0xb4, 0x19,
+ 0xb1, 0x32, 0xd3, 0xda, 0x01, 0xe6, 0x1d, 0x31, 0x32, 0x52, 0x89, 0x65, 0x91, 0xca, 0x92, 0x92,
+ 0x2f, 0xf4, 0x7d, 0xee, 0xb6, 0x40, 0x45, 0x74, 0xef, 0x71, 0xe4, 0x23, 0x4a, 0x9d, 0xd3, 0x31,
+ 0xc8, 0x03, 0x03, 0x3d, 0x1a, 0x67, 0xa4, 0x73, 0xc1, 0x03, 0x5a, 0xb3, 0x22, 0x2a, 0xbc, 0x99,
+ 0x3e, 0x89, 0xcd, 0xaa, 0xee, 0x50, 0xd2, 0xe9, 0x57, 0x5f, 0x15, 0xb5, 0x8b, 0xba, 0x94, 0xcd,
+ 0x66, 0xe8, 0x4e, 0x7c, 0x10, 0x25, 0x13, 0x71, 0x10, 0x80, 0x55, 0xc0, 0x45, 0x08, 0xe4, 0xd4,
+ 0xea, 0xc8, 0x79, 0xef, 0x80, 0xd8, 0x1d, 0xd4, 0x00, 0xed, 0x1b, 0x90, 0x3c, 0x44, 0x9d, 0xf1,
+ 0x13, 0x51, 0xc8, 0x86, 0x27, 0xfc, 0x0b, 0xb4, 0x6c, 0x86, 0xbc, 0x4f, 0xc3, 0xbe, 0x78, 0xab,
+ 0x5b, 0x93, 0x72, 0x47, 0xde, 0x49, 0x9f, 0xb5, 0x7e, 0xb5, 0x58, 0x64, 0x48, 0x5e, 0x42, 0xe7,
+ 0x75, 0xd1, 0x8c, 0x88, 0xf2, 0xdc, 0x6f, 0x2d, 0xba, 0xc1, 0x5a, 0xb0, 0x55, 0x5a, 0x6e, 0x75,
+ 0x6e, 0xe1, 0x8f, 0x09, 0xae, 0xf2, 0x71, 0x56, 0xb5, 0xe0, 0x81, 0xf5, 0xdb, 0x7f, 0x24, 0x19,
+ 0x3c, 0xe9, 0x9c, 0xdb, 0x25, 0xba, 0xf6, 0x1a, 0x98, 0x2e, 0x20, 0x26, 0xdc, 0x1e, 0xeb, 0x4e,
+ 0xc9, 0x19, 0x91, 0x97, 0x54, 0x92, 0x67, 0x74, 0x1f, 0xe9, 0xd2, 0x59, 0xf3, 0x52, 0x47, 0x29,
+ 0xd9, 0x4c, 0xd7, 0x29, 0x1c, 0x34, 0xc9, 0xe4, 0x2c, 0x58, 0x2e, 0x2b, 0xfd, 0x16, 0xde, 0xa9,
+ 0x7c, 0x87, 0xe4, 0x56, 0x04, 0xb7, 0x2e, 0x05, 0xff, 0x2f, 0x72, 0x09, 0x78, 0x68, 0xd2, 0x59,
+ 0xb7, 0x1b, 0xe1, 0x3a, 0x1a, 0xcd, 0x05, 0xcf, 0x52, 0xd0, 0x17, 0x9f, 0xf4, 0xa4, 0x3f, 0xcd,
+ 0x26, 0xf1, 0x44, 0x03, 0xfd, 0x8c, 0xe5, 0x39, 0x9f, 0x19, 0xc5, 0xda, 0x0f, 0x5e, 0x57, 0x5b,
+ 0xc4, 0x08, 0xbb, 0x46, 0xf9, 0x95, 0xec, 0xd9, 0x64, 0xc4, 0x3a, 0x95, 0x7e, 0x75, 0x65, 0x12,
+ 0xd9, 0x55, 0x75, 0xc8, 0x5b, 0x28, 0x92, 0x28, 0x9b, 0x1d, 0xe6, 0x79, 0xc8, 0x95, 0xdd, 0x51,
+ 0x56, 0x17, 0x8a, 0x0e, 0xb6, 0x05, 0xc0, 0x4f, 0x21, 0xfc, 0xc0, 0x57, 0x91, 0x2a, 0x99, 0x30,
+ 0xee, 0xd3, 0x6c, 0x06, 0xb7, 0x44, 0xb4, 0x26, 0x74, 0x9b, 0x3e, 0x68, 0x51, 0x03, 0x74, 0x33,
+ 0x02, 0xd9, 0x76, 0x5c, 0x0f, 0xd9, 0x43, 0xa4, 0x5f, 0xed, 0x52, 0xb3, 0xab, 0x61, 0xc4, 0x5a,
+ 0x6c, 0x15, 0x05, 0x66, 0x12, 0xd4, 0x47, 0xcb, 0x5d, 0x20, 0x07, 0x63, 0xaa, 0x55, 0xf5, 0x35,
+ 0xfd, 0xbc, 0xe5, 0xb0, 0xab, 0xce, 0x2f, 0x2d, 0x8e, 0x90, 0x8a, 0xa6, 0x33, 0x0e, 0xb5, 0xf4,
+ 0x7f, 0xf0, 0x12, 0x7e, 0x38, 0x29, 0x6a, 0x5d, 0x99, 0x74, 0xe3, 0x2d, 0xfc, 0x39, 0xf2, 0x96,
+ 0x08, 0x46, 0xa8, 0x52, 0xf3, 0x60, 0x49, 0x26, 0xe2, 0x9d, 0x84, 0xda, 0x70, 0xd6, 0xee, 0xb9,
+ 0x8a, 0x8f, 0xaa, 0x9e, 0xa8, 0x4f, 0x29, 0xe5, 0xcc, 0x3b, 0x9a, 0x74, 0x84, 0x3f, 0x52, 0x10,
+ 0x92, 0x83, 0xb1, 0x1a, 0x2b, 0xb0, 0x68, 0xf3, 0xa7, 0x82, 0x9c, 0xd3, 0xb7, 0xd8, 0xe2, 0xde,
+ 0xdc, 0x11, 0xbe, 0x4c, 0xc3, 0x49, 0x57, 0xec, 0x42, 0x4d, 0xee, 0x89, 0xa8, 0x30, 0xcf, 0xf2,
+ 0x24, 0x76, 0x15, 0x43, 0xf1, 0x9c, 0x8b, 0xd8, 0x45, 0x51, 0xab, 0x46, 0xc1, 0xd4, 0x50, 0x1f,
+ 0x1c, 0x9d, 0xc9, 0xc6, 0xd3, 0xab, 0x74, 0x72, 0xfa, 0x35, 0x92, 0x4a, 0xbf, 0x9a, 0xf5, 0xde,
+ 0x56, 0x88, 0x5e, 0x7b, 0xa1, 0x77, 0xcf, 0xfd, 0x01, 0x60, 0x0e, 0x4e, 0x9f, 0x46, 0x6c, 0x54,
+ 0x55, 0x66, 0xaa, 0x75, 0x0d, 0xc6, 0x12, 0x79, 0x9d, 0xb9, 0xa8, 0x2e, 0x70, 0x29, 0x08, 0x31,
+ 0xc4, 0xde, 0x24, 0xd3, 0xda, 0x49, 0xec, 0x31, 0x51, 0x49, 0x56, 0x92, 0xcf, 0xbd, 0x02, 0x7a,
+ 0x5e, 0x4e, 0xe1, 0x99, 0x5b, 0x36, 0x59, 0x9d, 0x79, 0x50, 0xfc, 0x4c, 0xee, 0x84, 0x65, 0xe3,
+ 0xe9, 0x57, 0x71, 0x17, 0x2d, 0x95, 0xac, 0xdd, 0xd3, 0xa4, 0x2b, 0x34, 0xeb, 0x2e, 0x92, 0xa8,
+ 0xf3, 0x43, 0x85, 0x58, 0xe6, 0xa9, 0xa1, 0x3e, 0xff, 0x1a, 0xe5, 0xbb, 0x3a, 0xe3, 0xf9, 0xa0,
+ 0x89, 0xaa, 0x8f, 0x00, 0x4b, 0x75, 0x80, 0xed, 0x5d, 0xfd, 0x73, 0xfc, 0x1d, 0x72, 0x54, 0x35,
+ 0xaa, 0xb2, 0x2a, 0x2b, 0x49, 0x90, 0xca, 0xfb, 0x14, 0xb2, 0xf7, 0x73, 0xf6, 0x05, 0x43, 0xec,
+ 0x06, 0x07, 0xc5, 0xcf, 0x84, 0x78, 0x0f, 0x30, 0xfb, 0x6e, 0x19, 0xd0, 0xde, 0x04, 0xa9, 0x7c,
+ 0xc2, 0x93, 0xca, 0x52, 0x52, 0x58, 0xf7, 0xbc, 0x33, 0x2c, 0xa7, 0x82, 0x55, 0x19, 0xe5, 0x92,
+ 0xc3, 0x73, 0x85, 0x58, 0x33, 0xb4, 0x05, 0x7c, 0x79, 0xa0, 0x09, 0x76, 0x50, 0x7b, 0x6c, 0x88,
+ 0xc2, 0xb4, 0x9a, 0xb9, 0x01, 0x03, 0xdb, 0x1b, 0xb0, 0x1c, 0x55, 0x75, 0x2a, 0x81, 0xfb, 0xf9,
+ 0x31, 0xe1, 0xa2, 0xfe, 0x3f, 0x97, 0x77, 0x02, 0x7d, 0x87, 0x0e, 0x0e, 0xf3, 0x2c, 0x8a, 0xc2,
+ 0x96, 0x25, 0x73, 0x27, 0x59, 0xa9, 0x94, 0xd3, 0xaf, 0x20, 0x87, 0xbf, 0x50, 0xab, 0x07, 0x06,
+ 0xd4, 0xf5, 0x80, 0x57, 0x9e, 0x7b, 0xae, 0x10, 0xb8, 0x95, 0xe3, 0x3e, 0x90, 0x32, 0xd0, 0x5d,
+ 0xf7, 0x43, 0x26, 0xce, 0xfe, 0x9b, 0x24, 0x96, 0x56, 0xd5, 0x73, 0x24, 0xdc, 0x9f, 0xf8, 0xd5,
+ 0x67, 0x74, 0xa7, 0x72, 0xd6, 0xe0, 0x42, 0xa7, 0xbe, 0x83, 0xd1, 0xdd, 0x2d, 0xe9, 0x59, 0x9a,
+ 0x91, 0x1c, 0xa6, 0x4a, 0xe5, 0x0a, 0xb1, 0xc0, 0xeb, 0x14, 0xbb, 0xf3, 0x01, 0x19, 0xe7, 0x8d,
+ 0x4a, 0x31, 0x2c, 0xe5, 0xb4, 0x6d, 0x19, 0xf7, 0xe6, 0x1b, 0x25, 0xdc, 0x08, 0xa3, 0x9d, 0x98,
+ 0x2a, 0x97, 0x25, 0x25, 0xa3, 0xaa, 0x3b, 0xfa, 0x63, 0xda, 0x5c, 0x51, 0x20, 0x79, 0x09, 0xca,
+ 0xb6, 0x2c, 0xfe, 0x5b, 0x13, 0xc4, 0x88, 0x36, 0xa7, 0x67, 0x59, 0xe7, 0xae, 0x52, 0xab, 0xf1,
+ 0x44, 0xdd, 0x99, 0xb4, 0x60, 0xd7, 0x0c, 0xbb, 0x93, 0xd5, 0x0c, 0xe7, 0x21, 0x44, 0xed, 0xa5,
+ 0xa0, 0x39, 0xa6, 0x7a, 0x98, 0xb3, 0x1a, 0x30, 0x7d, 0x38, 0xe3, 0xe8, 0x36, 0xf3, 0x24, 0x56,
+ 0x49, 0x22, 0x24, 0x0f, 0x31, 0x51, 0x8e, 0x19, 0xfc, 0x0e, 0xf5, 0x6c, 0xb9, 0x25, 0x73, 0x4c,
+ 0x75, 0x30, 0x3a, 0x88, 0x1b, 0xe9, 0xde, 0x5c, 0xd5, 0x0c, 0xcb, 0x0b, 0x68, 0x18, 0xbf, 0xfa,
+ 0x89, 0x7a, 0x33, 0x79, 0x33, 0xb8, 0xe0, 0x8d, 0xec, 0x06, 0x94, 0xf4, 0x68, 0x0b, 0x74, 0x49,
+ 0x90, 0x4c, 0x64, 0x0b, 0xe1, 0x56, 0xd8, 0x43, 0x52, 0x3f, 0x3b, 0x92, 0x68, 0xb1, 0x21, 0x24,
+ 0xae, 0xe2, 0x60, 0xc7, 0xde, 0xe7, 0xc5, 0x1e, 0xcf, 0xe8, 0x20, 0x63, 0x3d, 0x97, 0xce, 0x84,
+ 0x0e, 0xe2, 0xc5, 0xef, 0x99, 0xc8, 0x19, 0x16, 0xfc, 0x6a, 0x13, 0x5a, 0x09, 0x23, 0x76, 0x8a,
+ 0x92, 0xca, 0xd9, 0xa4, 0xb5, 0xb0, 0x65, 0xd8, 0xbd, 0x3c, 0xd8, 0x48, 0x22, 0x9c, 0x28, 0x77,
+ 0x89, 0xeb, 0x4c, 0x34, 0x67, 0xf0, 0x66, 0x73, 0x3e, 0x68, 0xb6, 0x05, 0xb8, 0xfd, 0x27, 0x17,
+ 0x3c, 0x63, 0xa7, 0x72, 0xcb, 0xf0, 0x91, 0x2e, 0xb7, 0x35, 0xdb, 0xa4, 0x2b, 0x7e, 0xfb, 0x87,
+ 0x8b, 0xa8, 0xcb, 0x4b, 0x60, 0x15, 0x20, 0xf6, 0xf5, 0x44, 0xc3, 0x9e, 0x48, 0x1a, 0xac, 0xd6,
+ 0x25, 0x75, 0x2d, 0xa5, 0x60, 0x09, 0xf1, 0xd4, 0x6a, 0x93, 0x54, 0x34, 0x8d, 0xd8, 0x9c, 0x1e,
+ 0xa2, 0x08, 0xd2, 0xbe, 0xc1, 0x60, 0x2c, 0x1b, 0xcb, 0x88, 0xbc, 0xe4, 0x07, 0xc3, 0x1d, 0xfd,
+ 0x21, 0x32, 0xd7, 0x3a, 0xac, 0xd0, 0xbd, 0xfa, 0x14, 0x45, 0x6c, 0xff, 0xb0, 0x9e, 0x25, 0xcb,
+ 0x53, 0x78, 0x12, 0x3b, 0x44, 0x7e, 0x4b, 0x9d, 0xb0, 0xec, 0xed, 0xdf, 0x9c, 0x7e, 0x77, 0x6b,
+ 0x2c, 0x01, 0x95, 0x8a, 0xe8, 0xaa, 0x5a, 0x2a, 0x9a, 0x60, 0x43, 0x43, 0x3e, 0x88, 0xb4, 0x7f,
+ 0x3b, 0x5b, 0x65, 0x82, 0xbc, 0xe4, 0x8e, 0xfe, 0x07, 0xc3, 0xa8, 0x80, 0xff, 0x24, 0x75, 0x40,
+ 0xe7, 0x21, 0x64, 0xff, 0xe4, 0x7a, 0xd7, 0xff, 0xe7, 0xc1, 0x7a, 0x96, 0x6c, 0xfe, 0xe4, 0x55,
+ 0xfc, 0x1d, 0xe5, 0xb7, 0x6a, 0x17, 0x13, 0x93, 0xd5, 0x60, 0x2d, 0xb6, 0xdd, 0xbe, 0x17, 0x81,
+ 0x73, 0xb6, 0xd5, 0x9d, 0x1a, 0xcb, 0xcb, 0x25, 0x9b, 0xd7, 0xf4, 0xfd, 0x01, 0x69, 0x68, 0xd6,
+ 0x58, 0xb3, 0x3d, 0xe7, 0xf3, 0xda, 0x1f, 0x0c, 0xfe, 0x9c, 0x1a, 0x53, 0x5e, 0x02, 0xfd, 0xc9,
+ 0x8a, 0xb9, 0xbf, 0x1b, 0xeb, 0x59, 0x22, 0xce, 0x1e, 0x39, 0x65, 0xd1, 0x9f, 0x52, 0xba, 0x54,
+ 0x8f, 0x19, 0xcd, 0xf2, 0x33, 0xd5, 0xee, 0x78, 0x23, 0xa9, 0x68, 0x56, 0x44, 0xb7, 0x0c, 0x52,
+ 0xb1, 0x94, 0xd3, 0x5c, 0xf9, 0x75, 0x7e, 0x29, 0x27, 0x6d, 0x5b, 0x40, 0x9e, 0xe5, 0x39, 0x4f,
+ 0x29, 0x7f, 0x30, 0x3c, 0x11, 0xb9, 0x9d, 0xde, 0x24, 0xe8, 0xfe, 0x6e, 0x45, 0x7a, 0xca, 0xb2,
+ 0x99, 0x04, 0x5b, 0x86, 0x4d, 0x39, 0x7a, 0x7d, 0x9f, 0x38, 0xa5, 0xec, 0x54, 0xb2, 0x3b, 0x73,
+ 0x2d, 0x2b, 0x77, 0x4f, 0x61, 0x58, 0x82, 0x05, 0xb4, 0x29, 0x59, 0x32, 0x01, 0xcd, 0x2a, 0xad,
+ 0x14, 0x34, 0xdb, 0x63, 0xf2, 0x2c, 0x4f, 0x3a, 0x83, 0x3f, 0x10, 0xc5, 0x12, 0xf6, 0x4c, 0xf1,
+ 0xf6, 0x77, 0x03, 0xcf, 0x72, 0x36, 0xd9, 0x61, 0x0d, 0xb4, 0x25, 0x44, 0x2f, 0xb9, 0x3c, 0xb6,
+ 0x2f, 0x2d, 0x7b, 0x53, 0xcb, 0x45, 0xc7, 0xf3, 0x74, 0xd2, 0xb1, 0x04, 0x1f, 0x65, 0x56, 0x05,
+ 0x4c, 0x6d, 0xb9, 0xd1, 0xf4, 0xc5, 0xe5, 0x59, 0x9e, 0xf4, 0x2a, 0xfe, 0x85, 0x9e, 0xb2, 0x02,
+ 0x44, 0x4e, 0x4f, 0xb6, 0x8b, 0x42, 0xf1, 0x9d, 0xb2, 0xac, 0xdd, 0xb3, 0x65, 0x60, 0xed, 0xbf,
+ 0x93, 0xd8, 0x2d, 0x9c, 0xf3, 0xcb, 0x0a, 0x8b, 0xc2, 0x42, 0x06, 0x5d, 0xf6, 0xdf, 0x86, 0x13,
+ 0xb1, 0x01, 0x29, 0x51, 0x03, 0x3e, 0x9a, 0xa5, 0x24, 0xe8, 0xcd, 0x5c, 0x68, 0x46, 0x12, 0xd9,
+ 0x24, 0xcf, 0x88, 0x1d, 0xd3, 0x8a, 0x67, 0x00, 0x29, 0xc8, 0x2d, 0x43, 0x93, 0xae, 0x18, 0x63,
+ 0x79, 0x2c, 0x03, 0xfe, 0x35, 0x3d, 0xbb, 0x0f, 0xe5, 0x82, 0x1b, 0xbf, 0xa8, 0x5a, 0xaa, 0xcd,
+ 0x91, 0x69, 0x40, 0x26, 0x64, 0xae, 0x55, 0xef, 0x73, 0x2b, 0xc8, 0x7c, 0xb0, 0x84, 0x39, 0xa6,
+ 0x8a, 0xe7, 0x60, 0xf9, 0x82, 0x91, 0x8d, 0x2f, 0x46, 0x83, 0x3d, 0x51, 0x8f, 0xaa, 0xc4, 0xb0,
+ 0x84, 0x3a, 0x78, 0xc8, 0x80, 0x2e, 0xb6, 0x88, 0x01, 0xe8, 0x4a, 0xc4, 0xf6, 0xc2, 0xaf, 0xe6,
+ 0x82, 0x15, 0x63, 0x47, 0x21, 0x11, 0x75, 0x60, 0xd5, 0xce, 0xa5, 0x6b, 0x23, 0x74, 0xfc, 0x34,
+ 0x5f, 0x2c, 0x35, 0xd8, 0x6a, 0x4e, 0xce, 0xb6, 0x44, 0xa2, 0xc5, 0x96, 0xf9, 0x69, 0x35, 0x18,
+ 0x44, 0xf5, 0xc4, 0x23, 0x74, 0x70, 0x4a, 0xcd, 0x16, 0x5d, 0x5c, 0x96, 0xad, 0xb1, 0x9c, 0x4b,
+ 0x4a, 0xe5, 0x45, 0xec, 0x2a, 0xce, 0x59, 0xed, 0x46, 0x6c, 0xde, 0xb2, 0xf3, 0xfa, 0x4a, 0x67,
+ 0x1c, 0x38, 0x46, 0x73, 0xbd, 0xc3, 0x97, 0x80, 0x1b, 0xb6, 0xfc, 0xd1, 0xa4, 0x19, 0xf8, 0xb2,
+ 0x9e, 0xb4, 0x7d, 0xee, 0xcc, 0x4f, 0x0b, 0xb9, 0x79, 0x95, 0xa4, 0x78, 0x2f, 0x85, 0x31, 0xba,
+ 0xd7, 0x6e, 0x71, 0x69, 0x4c, 0x74, 0x37, 0x52, 0xa5, 0x6d, 0x36, 0x73, 0x59, 0x77, 0xf7, 0x89,
+ 0x77, 0x94, 0x8f, 0x79, 0xda, 0xb2, 0xd5, 0x9d, 0x6d, 0xc5, 0xc4, 0x47, 0x7b, 0x0c, 0xb8, 0xb8,
+ 0x73, 0xbd, 0x23, 0x42, 0x79, 0x83, 0x70, 0x96, 0xed, 0x44, 0x36, 0xe3, 0xde, 0x6c, 0x7a, 0xb3,
+ 0xce, 0x9f, 0xed, 0x79, 0xef, 0x13, 0xa9, 0x9d, 0x6c, 0x33, 0x8d, 0x4d, 0xa2, 0xd8, 0x34, 0x26,
+ 0x9f, 0x83, 0x89, 0xfb, 0x69, 0x25, 0xe9, 0xe2, 0x9d, 0x43, 0x5d, 0xca, 0xdc, 0x72, 0x95, 0x7b,
+ 0x54, 0x44, 0x43, 0x22, 0x58, 0x26, 0x12, 0x93, 0x1e, 0xe9, 0x11, 0x03, 0x21, 0x9a, 0xe8, 0xbb,
+ 0x65, 0x42, 0xb3, 0x3f, 0x98, 0xed, 0x99, 0x2f, 0x62, 0x3f, 0x97, 0xa0, 0x05, 0xe1, 0xf6, 0xeb,
+ 0x9a, 0xbe, 0x98, 0x62, 0xec, 0xa8, 0x6e, 0xa4, 0x5b, 0xd7, 0x63, 0xe6, 0x32, 0xd4, 0x4f, 0x62,
+ 0x9d, 0xca, 0x2a, 0x9d, 0x2b, 0x19, 0x53, 0x8f, 0xaa, 0x77, 0x7e, 0xd3, 0x05, 0xda, 0x70, 0xc1,
+ 0x93, 0xce, 0xf6, 0x2c, 0x7c, 0xcf, 0xd3, 0x70, 0xfe, 0xd6, 0x0f, 0x3b, 0x4b, 0xc9, 0xcc, 0xfe,
+ 0xe6, 0x54, 0x56, 0x2c, 0x4f, 0x4a, 0x94, 0xb4, 0x62, 0xf3, 0x31, 0xd1, 0x2d, 0x57, 0x99, 0x80,
+ 0x01, 0xff, 0x22, 0xe6, 0x52, 0xdd, 0xd1, 0xb3, 0xbd, 0x24, 0x35, 0xd8, 0xfa, 0xc0, 0xce, 0xfd,
+ 0x11, 0xf0, 0x1f, 0x27, 0x45, 0xb1, 0xf4, 0xc5, 0xb3, 0xe7, 0xff, 0x88, 0xcb, 0x66, 0x66, 0x9b,
+ 0x76, 0x29, 0x0b, 0x96, 0xe0, 0x39, 0x4b, 0xeb, 0x3c, 0x04, 0x8c, 0x46, 0xc5, 0x73, 0x5f, 0x82,
+ 0x62, 0xb0, 0xdd, 0x3a, 0x21, 0xb3, 0xc4, 0x2d, 0xdc, 0xaf, 0x86, 0x2a, 0x0c, 0xf4, 0x6a, 0x04,
+ 0xef, 0x2b, 0x40, 0x5b, 0xfa, 0x28, 0xcb, 0x67, 0xd2, 0x33, 0x15, 0xcc, 0x8d, 0x65, 0x22, 0x31,
+ 0xa7, 0xdf, 0x29, 0x96, 0xd9, 0x6c, 0xda, 0x6c, 0x58, 0x3e, 0x26, 0x3a, 0x95, 0xe2, 0xd5, 0x42,
+ 0x30, 0x20, 0x93, 0xab, 0x78, 0xe2, 0x05, 0x48, 0x2a, 0xb7, 0x0c, 0xab, 0x02, 0x0e, 0xd1, 0xfb,
+ 0xc4, 0x13, 0x35, 0xc4, 0x2c, 0xd1, 0xcf, 0x66, 0xf0, 0x73, 0x05, 0x68, 0x4b, 0x67, 0x1c, 0x6a,
+ 0x04, 0x96, 0x72, 0x62, 0x09, 0x63, 0xde, 0xb2, 0x73, 0x2c, 0xe5, 0x34, 0xc7, 0x5d, 0xdc, 0x1b,
+ 0x16, 0x9c, 0xb4, 0x1b, 0xe1, 0xcc, 0xcf, 0x0c, 0xb9, 0xbe, 0xb9, 0xef, 0x2f, 0xd9, 0x31, 0x83,
+ 0xb3, 0x5d, 0xa7, 0x0b, 0x5b, 0xe5, 0xfd, 0x18, 0xec, 0xdd, 0xf3, 0x9c, 0x5e, 0xc8, 0xf7, 0xf2,
+ 0x98, 0x80, 0xbb, 0x04, 0x0e, 0x4b, 0x71, 0x24, 0x72, 0x61, 0x09, 0xd5, 0x3b, 0xe2, 0xb1, 0xdc,
+ 0x09, 0x7b, 0x21, 0x58, 0x22, 0x0f, 0xa5, 0x4d, 0x10, 0x0b, 0xda, 0x08, 0x67, 0x96, 0xa7, 0x33,
+ 0xba, 0x2a, 0x91, 0xbb, 0x68, 0x6e, 0x7d, 0xe0, 0x1e, 0xb3, 0x38, 0x2c, 0x59, 0x94, 0xd5, 0x0c,
+ 0xbd, 0x1e, 0xf8, 0x3f, 0x95, 0x33, 0x58, 0xb2, 0x7c, 0xbf, 0x9b, 0x44, 0x21, 0x99, 0x77, 0x83,
+ 0xb1, 0xf8, 0xb7, 0x93, 0x9e, 0xa7, 0xa2, 0x58, 0xf6, 0xb9, 0x0b, 0xc3, 0x12, 0xc5, 0x69, 0xe1,
+ 0x7e, 0x93, 0x45, 0x73, 0x23, 0x7c, 0x3f, 0x43, 0x05, 0x1e, 0xdc, 0x45, 0x7f, 0xa4, 0x93, 0x76,
+ 0xc6, 0x96, 0x94, 0x40, 0xef, 0x04, 0x45, 0x11, 0x58, 0xb2, 0x2c, 0x4b, 0xc8, 0x5c, 0x0a, 0xdf,
+ 0x0b, 0xc2, 0xf2, 0x81, 0xe1, 0x79, 0x2d, 0xb2, 0x10, 0x56, 0xd5, 0x85, 0x44, 0xd5, 0xc1, 0xbb,
+ 0x9c, 0xf4, 0x88, 0xdb, 0xc1, 0xfd, 0x81, 0x42, 0xb1, 0x84, 0x39, 0xab, 0xe2, 0xf2, 0xb0, 0x9f,
+ 0x86, 0x33, 0x71, 0x10, 0x18, 0xb1, 0x8f, 0xcd, 0x67, 0x98, 0x8c, 0x7c, 0xf1, 0x01, 0xfc, 0xec,
+ 0xc5, 0xe0, 0x95, 0xa0, 0x3e, 0xcf, 0x73, 0x86, 0xa8, 0x26, 0xf5, 0x37, 0xa0, 0x2f, 0x1f, 0x18,
+ 0xce, 0x30, 0xbb, 0xf7, 0x9a, 0xbe, 0x10, 0x4e, 0xad, 0xfa, 0x68, 0x48, 0x12, 0x96, 0xf5, 0xd1,
+ 0xdd, 0xc0, 0x12, 0x3a, 0x57, 0xb4, 0x31, 0x91, 0x63, 0xa8, 0x93, 0x4e, 0xe7, 0x20, 0x18, 0x55,
+ 0xf5, 0x98, 0xa5, 0x73, 0xce, 0x42, 0x7e, 0x65, 0x31, 0xc4, 0x64, 0xd9, 0x13, 0x16, 0xdd, 0x57,
+ 0xf2, 0xc7, 0x2d, 0x1c, 0x7c, 0x92, 0x2f, 0xf4, 0x48, 0xab, 0x54, 0x9b, 0x0a, 0xc9, 0x27, 0xa8,
+ 0x88, 0x42, 0x3d, 0xdd, 0x09, 0x11, 0x2c, 0xc1, 0x2b, 0xd9, 0x49, 0xe4, 0x27, 0x7d, 0xc2, 0xcd,
+ 0x23, 0x42, 0xb3, 0x3e, 0x5a, 0x6d, 0x9a, 0x4d, 0xeb, 0xc8, 0xf6, 0xc0, 0xc0, 0xef, 0xd5, 0x29,
+ 0x36, 0xd6, 0x8a, 0x04, 0x4b, 0x64, 0xc3, 0xae, 0x19, 0xd2, 0x2d, 0x04, 0x88, 0x15, 0x50, 0x67,
+ 0xaf, 0x01, 0xc5, 0xf4, 0xc6, 0x0b, 0x88, 0xc5, 0xc2, 0x49, 0x07, 0x58, 0x8a, 0x9d, 0xd2, 0xa0,
+ 0xe5, 0x76, 0x1e, 0x2d, 0x48, 0x45, 0xf3, 0x9a, 0x1e, 0x4e, 0xda, 0xf3, 0xb1, 0xd8, 0x40, 0x2a,
+ 0x7b, 0xf3, 0x55, 0xfc, 0x5d, 0xf3, 0x5c, 0x06, 0x0e, 0xdc, 0x6c, 0xa3, 0x58, 0x22, 0x3f, 0x88,
+ 0x09, 0x3f, 0x53, 0x2f, 0x6d, 0x88, 0x3e, 0x03, 0x0b, 0x07, 0xca, 0x70, 0xfa, 0xb2, 0x60, 0x2c,
+ 0xa5, 0x70, 0x05, 0x47, 0x12, 0x63, 0x3b, 0x8e, 0x16, 0x64, 0x92, 0xcd, 0xa7, 0xe1, 0xf6, 0x58,
+ 0xaf, 0x0d, 0xf1, 0xf6, 0xc8, 0x93, 0x4f, 0x16, 0x55, 0x7f, 0x69, 0xf1, 0xe7, 0xc1, 0x37, 0x5b,
+ 0x2c, 0xfa, 0x32, 0x3b, 0x96, 0x28, 0x5a, 0x30, 0xa7, 0x3f, 0xa3, 0x03, 0xab, 0xa8, 0xc7, 0x5c,
+ 0x88, 0xed, 0xb3, 0x11, 0x9e, 0x94, 0x88, 0x65, 0xfe, 0xf7, 0x5e, 0xec, 0xd4, 0x60, 0x46, 0x6c,
+ 0x04, 0x9f, 0xc1, 0x21, 0x23, 0xb4, 0x4a, 0xdb, 0xad, 0xeb, 0xd6, 0x5f, 0xd3, 0xd7, 0x58, 0xa1,
+ 0x4b, 0x26, 0xc4, 0xe0, 0xee, 0x13, 0xdc, 0x9d, 0x2c, 0x75, 0xc2, 0x66, 0xe5, 0xb8, 0xc9, 0x34,
+ 0x50, 0xd6, 0x4f, 0xb1, 0x60, 0x09, 0x99, 0x53, 0xe9, 0x03, 0xb8, 0xab, 0x3e, 0xd2, 0x3d, 0xa0,
+ 0x4f, 0x59, 0x94, 0x65, 0xbc, 0xb3, 0x11, 0x61, 0xb0, 0x14, 0xd3, 0xb8, 0x70, 0xc6, 0x76, 0xe7,
+ 0x95, 0x29, 0xc2, 0xa2, 0xb8, 0x42, 0x40, 0xdd, 0x6f, 0x8d, 0x15, 0x7c, 0x58, 0x21, 0x57, 0x54,
+ 0x7b, 0xac, 0xc5, 0xc6, 0xf2, 0x70, 0xa3, 0x1b, 0xb5, 0x53, 0xca, 0x4c, 0x7c, 0xf1, 0xb9, 0x56,
+ 0x88, 0xad, 0x13, 0xda, 0xad, 0x35, 0xdf, 0xab, 0xa1, 0x61, 0x62, 0x3e, 0x99, 0x78, 0x61, 0x59,
+ 0xc9, 0xfc, 0x48, 0x67, 0xc4, 0xb6, 0x0a, 0xa8, 0x21, 0x89, 0x24, 0x96, 0x68, 0x2c, 0x87, 0x24,
+ 0xe8, 0xcb, 0xb5, 0x3c, 0xf2, 0xf1, 0xd0, 0x49, 0xda, 0xa5, 0xdc, 0x32, 0xdc, 0xb3, 0xb3, 0x5e,
+ 0x48, 0x44, 0x30, 0xc1, 0xea, 0x9a, 0x1f, 0x68, 0xd2, 0x8d, 0xa9, 0x4a, 0xc9, 0x15, 0x62, 0x06,
+ 0xbf, 0x4f, 0x1c, 0x22, 0xc1, 0xd3, 0x42, 0x79, 0x85, 0x46, 0x0c, 0x38, 0xf3, 0xc4, 0xb9, 0x45,
+ 0x8a, 0x25, 0x86, 0xc7, 0x66, 0xa9, 0x67, 0xb6, 0xd0, 0xa1, 0xc2, 0x0b, 0xe9, 0xcc, 0xc2, 0x72,
+ 0x0a, 0x96, 0x24, 0x9d, 0xb1, 0xb0, 0xfa, 0xd5, 0xa6, 0x7c, 0x90, 0x1c, 0x53, 0xad, 0x0f, 0x84,
+ 0xbc, 0xb9, 0x32, 0xd9, 0x37, 0xc2, 0x6b, 0x06, 0x4c, 0x3b, 0xab, 0x1a, 0x53, 0x45, 0xa9, 0x5d,
+ 0xf9, 0x13, 0xd3, 0xbb, 0xe6, 0x1e, 0x73, 0xb5, 0x69, 0x54, 0x85, 0xea, 0x10, 0x8f, 0xe9, 0x8e,
+ 0x69, 0x21, 0x57, 0x44, 0x41, 0x66, 0x8f, 0x1b, 0x80, 0x95, 0x5f, 0x1c, 0x99, 0x05, 0x28, 0xc7,
+ 0x07, 0x58, 0x28, 0xd1, 0xeb, 0xdf, 0x62, 0x7f, 0x5e, 0xfe, 0x01, 0x3d, 0x0f, 0x97, 0x6b, 0x4a,
+ 0xc0, 0x9a, 0x05, 0x8e, 0xc0, 0x3b, 0xfa, 0xa8, 0xba, 0x10, 0x2c, 0x7f, 0x4d, 0x63, 0x29, 0xae,
+ 0x71, 0x51, 0x77, 0x0a, 0x69, 0x13, 0xaa, 0x4b, 0x10, 0x6f, 0x5a, 0x36, 0x1c, 0x61, 0x40, 0x1d,
+ 0x3d, 0xa6, 0xad, 0xd2, 0xfe, 0xc4, 0x54, 0x63, 0x7d, 0xe8, 0xf8, 0xca, 0x1e, 0x1b, 0xa8, 0x36,
+ 0xdd, 0xd1, 0x43, 0x25, 0x29, 0x54, 0xd2, 0x03, 0x87, 0xd3, 0x0f, 0xd4, 0x04, 0x3f, 0x1a, 0x18,
+ 0x63, 0x32, 0xad, 0x50, 0xf1, 0x64, 0xfc, 0xa0, 0x3b, 0x92, 0x2d, 0xa6, 0xf7, 0xe1, 0x77, 0x87,
+ 0xbf, 0x7e, 0xd1, 0x29, 0xa3, 0xe6, 0x4b, 0xd4, 0x94, 0xd5, 0xbd, 0x38, 0xff, 0x02, 0xdc, 0x7d,
+ 0x9d, 0x52, 0xc2, 0xee, 0x2d, 0x04, 0x4b, 0xd0, 0x97, 0xe2, 0x3e, 0x09, 0xbc, 0x33, 0x36, 0x20,
+ 0x0d, 0xc9, 0x59, 0x55, 0xab, 0xbb, 0x5e, 0x42, 0x65, 0x49, 0xc8, 0x1b, 0x55, 0xc3, 0xbd, 0xec,
+ 0x77, 0x8e, 0xeb, 0x9e, 0x6d, 0x47, 0xec, 0x33, 0x88, 0xc7, 0x8d, 0xa9, 0x10, 0xb3, 0xd6, 0x49,
+ 0xca, 0x5a, 0x9a, 0xc1, 0x2b, 0xc9, 0x59, 0x15, 0x58, 0x05, 0x5b, 0x86, 0x77, 0xcd, 0x67, 0x74,
+ 0x8f, 0x53, 0x74, 0x0d, 0xf4, 0x58, 0xdc, 0xff, 0x7c, 0x67, 0x69, 0x6b, 0x90, 0x3a, 0x50, 0x96,
+ 0xcf, 0xd6, 0xa5, 0x71, 0xb3, 0xed, 0xf5, 0x78, 0x39, 0x8d, 0x21, 0x6f, 0xb6, 0xcb, 0xfe, 0xfb,
+ 0xb0, 0x86, 0x66, 0x6f, 0x38, 0xa5, 0x2c, 0x24, 0x07, 0x6f, 0x43, 0x92, 0x7f, 0x09, 0x58, 0xe2,
+ 0x56, 0x29, 0x12, 0x59, 0x46, 0xf7, 0xf3, 0x13, 0x47, 0xd2, 0x19, 0xef, 0xb5, 0x01, 0x92, 0xdb,
+ 0x8e, 0xa0, 0x17, 0x22, 0x4f, 0xb5, 0xae, 0x16, 0x1b, 0x30, 0x6b, 0x41, 0xef, 0x27, 0x21, 0x3a,
+ 0x46, 0x6c, 0x56, 0x35, 0x6f, 0x79, 0xe8, 0xa8, 0xb1, 0xba, 0x04, 0x55, 0x26, 0xa0, 0x7f, 0xf6,
+ 0x57, 0x5b, 0x22, 0x8b, 0x7c, 0x06, 0xa7, 0x27, 0xb1, 0x92, 0x32, 0x67, 0x08, 0xf4, 0x9b, 0x11,
+ 0x1c, 0xd9, 0x72, 0xfc, 0xbf, 0x33, 0x62, 0x9b, 0xf2, 0xa8, 0xba, 0xd9, 0xf4, 0x6f, 0x9d, 0x4f,
+ 0xdf, 0x48, 0x45, 0x12, 0xe6, 0x90, 0xec, 0xbb, 0xc3, 0x23, 0x25, 0xa8, 0x33, 0x7b, 0xfd, 0x8e,
+ 0xbd, 0x92, 0x8a, 0x68, 0x50, 0x52, 0x0c, 0x4f, 0x0a, 0x96, 0x2b, 0x44, 0x6c, 0x00, 0x9d, 0xac,
+ 0x62, 0x48, 0xc2, 0x0d, 0xf8, 0x96, 0xa1, 0xc7, 0xfc, 0x95, 0x1d, 0x72, 0x1a, 0x6a, 0xdd, 0xbd,
+ 0xb6, 0x73, 0x81, 0x49, 0xcf, 0x84, 0xbd, 0x27, 0x23, 0x9a, 0xc0, 0xb9, 0x59, 0x4d, 0xa1, 0x3e,
+ 0x3f, 0xc0, 0xb1, 0x51, 0xc9, 0xf7, 0x3d, 0xab, 0x00, 0x7a, 0x33, 0xad, 0x10, 0x0a, 0xb2, 0x4b,
+ 0x39, 0x46, 0xe9, 0xf8, 0xd9, 0x8c, 0x73, 0x4c, 0xd5, 0xa5, 0x6c, 0x54, 0x6e, 0x12, 0xa0, 0xc3,
+ 0xe5, 0xbc, 0xbf, 0xa4, 0x6f, 0xa1, 0xf5, 0x2f, 0x74, 0x56, 0x1c, 0x65, 0xd1, 0xf3, 0xbd, 0xe4,
+ 0x93, 0xa1, 0xc9, 0xa2, 0xf9, 0x2f, 0x87, 0x2f, 0x51, 0x4f, 0x85, 0x69, 0xf3, 0xad, 0x4c, 0xe6,
+ 0x46, 0x7d, 0x14, 0x62, 0xeb, 0xe2, 0xa7, 0xb4, 0x38, 0x96, 0x2b, 0x04, 0x54, 0x27, 0x65, 0x47,
+ 0x32, 0x12, 0x5f, 0x8e, 0x2e, 0x47, 0xd0, 0x1c, 0x0a, 0xb5, 0xcd, 0xff, 0x68, 0x9d, 0xb0, 0x5f,
+ 0xf7, 0x00, 0xeb, 0x4f, 0x93, 0xee, 0x10, 0x79, 0xcf, 0xde, 0x1f, 0x58, 0xa0, 0xd0, 0x84, 0x5b,
+ 0xac, 0x46, 0x65, 0x6a, 0x64, 0xaf, 0xa4, 0xe4, 0x89, 0xfa, 0x4b, 0xcb, 0xc7, 0x66, 0x2e, 0x2f,
+ 0xa6, 0x94, 0xdc, 0xdf, 0x38, 0x01, 0x20, 0x79, 0x88, 0x1c, 0x53, 0x61, 0x5a, 0x60, 0x56, 0x02,
+ 0xcd, 0xb7, 0x75, 0x29, 0x65, 0xd2, 0x3f, 0x9d, 0xd3, 0x37, 0xe9, 0x56, 0xd5, 0xfc, 0x27, 0x60,
+ 0x7b, 0x3e, 0x57, 0x9b, 0xa7, 0xde, 0x4a, 0xc5, 0x91, 0x99, 0x49, 0xd9, 0x84, 0xbf, 0x68, 0x54,
+ 0xf6, 0xda, 0x76, 0x86, 0xe6, 0x60, 0x4c, 0xda, 0xfd, 0xa5, 0x18, 0x96, 0x33, 0x78, 0x8d, 0xd5,
+ 0x97, 0x91, 0x25, 0x86, 0xf1, 0x42, 0x62, 0xd3, 0x91, 0xe9, 0x75, 0x7a, 0xae, 0x0e, 0x2f, 0x0f,
+ 0x2f, 0x0e, 0x2d, 0x36, 0x2c, 0xb6, 0xf9, 0xda, 0x02, 0x4f, 0xc3, 0x35, 0x56, 0xd8, 0xc5, 0x8d,
+ 0xca, 0x87, 0x0e, 0x40, 0xb3, 0xd7, 0x9e, 0xb9, 0x9b, 0x69, 0x25, 0xf9, 0x05, 0xe5, 0x81, 0xb1,
+ 0x6c, 0xb3, 0xf2, 0x92, 0x2a, 0xed, 0xb8, 0x65, 0x3f, 0xd9, 0x61, 0x50, 0x06, 0x5d, 0xb7, 0xae,
+ 0xd9, 0x8c, 0x5b, 0x7b, 0x6d, 0x13, 0xf6, 0xcc, 0xb3, 0xd7, 0x56, 0x63, 0x9d, 0xb7, 0x40, 0xae,
+ 0x27, 0xfb, 0x04, 0x5c, 0xee, 0xdd, 0xc2, 0x29, 0x64, 0xed, 0x24, 0x11, 0x3c, 0xca, 0x4c, 0x9e,
+ 0x6c, 0xfe, 0xd5, 0x61, 0xf8, 0x2c, 0x38, 0xdf, 0x4e, 0xec, 0x00, 0x4d, 0x67, 0xbc, 0x2e, 0x20,
+ 0x25, 0xaf, 0x20, 0x37, 0x96, 0xd0, 0x69, 0xea, 0x7c, 0x9a, 0xbd, 0xc3, 0xbe, 0x6e, 0x8f, 0x11,
+ 0xbe, 0x6d, 0x7b, 0x8b, 0x35, 0x66, 0x89, 0x59, 0x5a, 0x3e, 0xfd, 0xd1, 0x1e, 0x77, 0x57, 0xac,
+ 0x83, 0x74, 0x3a, 0x23, 0xed, 0xd1, 0x3e, 0xcf, 0x98, 0x0a, 0x76, 0x30, 0x64, 0x05, 0xd5, 0xba,
+ 0x20, 0xf7, 0xa8, 0xc5, 0xc6, 0xf6, 0x00, 0xe7, 0xa3, 0x09, 0x77, 0x43, 0x1c, 0x03, 0xe2, 0x0a,
+ 0x31, 0x6e, 0x89, 0x0d, 0xec, 0x9f, 0x5c, 0xb2, 0xcc, 0xcb, 0x3d, 0x16, 0xe0, 0x57, 0x86, 0x8e,
+ 0x1d, 0x6d, 0x81, 0xf4, 0x79, 0x8e, 0xee, 0x24, 0x50, 0xeb, 0xaa, 0xb1, 0x72, 0x9d, 0xe5, 0x98,
+ 0xf3, 0x55, 0xf7, 0xb7, 0xa6, 0x3f, 0xbe, 0xc6, 0x93, 0x49, 0xc0, 0xf0, 0x4d, 0x66, 0xf2, 0xd0,
+ 0xdc, 0x38, 0x72, 0xfa, 0x4f, 0xd0, 0xce, 0xd9, 0xc9, 0xed, 0x97, 0x2f, 0x3e, 0x15, 0x0c, 0x7a,
+ 0x73, 0xe7, 0xfb, 0x88, 0x61, 0xa9, 0xc1, 0xb6, 0x0c, 0xc0, 0x0d, 0x93, 0x8e, 0x64, 0x24, 0xd1,
+ 0x16, 0x18, 0xb7, 0x74, 0x29, 0x4b, 0x5f, 0x81, 0x78, 0xc0, 0x08, 0x8e, 0x22, 0x79, 0x9b, 0x04,
+ 0xe4, 0xfb, 0xb6, 0x58, 0xa7, 0x02, 0x6d, 0x7e, 0xa8, 0x75, 0x62, 0xff, 0x95, 0x31, 0x15, 0xb0,
+ 0x06, 0xb7, 0xba, 0xd9, 0xb5, 0xe0, 0xa3, 0x09, 0x9c, 0x23, 0x95, 0x94, 0xaf, 0xf9, 0x0f, 0x94,
+ 0x3d, 0xff, 0xf5, 0x8b, 0xdf, 0x1f, 0xa9, 0x78, 0xf3, 0x5f, 0xcf, 0xef, 0x5f, 0xe6, 0x16, 0xc3,
+ 0x13, 0x61, 0x9a, 0xb0, 0x87, 0xbc, 0xbd, 0xb6, 0x52, 0x32, 0xfb, 0xec, 0x31, 0x13, 0xfe, 0x3e,
+ 0x37, 0x6e, 0x45, 0x9d, 0x38, 0xe0, 0x79, 0xa1, 0xff, 0x61, 0xb3, 0x89, 0x38, 0x31, 0xc4, 0x49,
+ 0x25, 0x87, 0x63, 0x12, 0x4d, 0xc6, 0x43, 0x79, 0xe9, 0xe5, 0x17, 0x47, 0x98, 0xcf, 0x1c, 0x53,
+ 0xe5, 0x6b, 0xd3, 0x42, 0x85, 0xa5, 0xda, 0x2f, 0x45, 0x2e, 0x6b, 0xb2, 0x60, 0x09, 0x77, 0x92,
+ 0xa9, 0x9f, 0x8a, 0x2a, 0xe4, 0xeb, 0xfc, 0x6b, 0x86, 0x5c, 0x37, 0x65, 0x1a, 0x2c, 0xb5, 0xe6,
+ 0xa8, 0x51, 0x09, 0x9d, 0x13, 0xfa, 0x18, 0x34, 0x15, 0x24, 0x67, 0x43, 0x40, 0x2d, 0xd4, 0x45,
+ 0xec, 0x9f, 0x7e, 0x3a, 0x75, 0x84, 0xd9, 0xd5, 0xd4, 0xd3, 0xeb, 0xdf, 0x6d, 0x82, 0x4a, 0xf7,
+ 0x3d, 0x97, 0x4c, 0x36, 0x57, 0x67, 0x7d, 0x00, 0x4e, 0x8e, 0xdc, 0xf1, 0xaf, 0x4d, 0xa2, 0xd5,
+ 0x5d, 0xe7, 0xdf, 0x76, 0x8c, 0x5b, 0xc0, 0x8a, 0x2b, 0x25, 0x15, 0xd0, 0x9f, 0xeb, 0xc3, 0xf2,
+ 0x0f, 0x1e, 0xbd, 0x06, 0x1e, 0x65, 0x46, 0x24, 0x39, 0xd9, 0xa4, 0xe7, 0xf5, 0xf2, 0xdf, 0x32,
+ 0x9f, 0xdb, 0xa5, 0x5c, 0xf0, 0xe4, 0x97, 0x61, 0x39, 0x18, 0x83, 0x4e, 0x16, 0xe2, 0xef, 0xcb,
+ 0x26, 0x97, 0xa5, 0xe4, 0x07, 0xee, 0x74, 0x99, 0x1c, 0x8c, 0x6f, 0x3b, 0x76, 0x72, 0xb3, 0x32,
+ 0xab, 0x02, 0xae, 0xff, 0x5a, 0x6a, 0x67, 0x6f, 0x19, 0x9e, 0xd7, 0x02, 0x9a, 0x9c, 0x4d, 0xfb,
+ 0x59, 0xc9, 0x07, 0xe5, 0x4e, 0x6e, 0x2d, 0x8e, 0x9e, 0x90, 0xfd, 0xa7, 0x6e, 0x3f, 0x98, 0x7e,
+ 0x50, 0x56, 0xc0, 0x9a, 0xa1, 0xc5, 0x06, 0xfc, 0xd4, 0x62, 0xbc, 0x47, 0x70, 0xa3, 0x47, 0xe9,
+ 0x7d, 0x1b, 0xf4, 0x09, 0x8c, 0xaa, 0xab, 0xb4, 0x65, 0x1f, 0xfe, 0x97, 0xf9, 0xed, 0xc6, 0xa1,
+ 0xa3, 0x49, 0xfd, 0x28, 0x40, 0x31, 0x7c, 0x9c, 0x99, 0x6f, 0xb2, 0xbf, 0x77, 0x1e, 0xfd, 0xee,
+ 0xd5, 0xbf, 0x67, 0x22, 0xd4, 0x5d, 0xca, 0x72, 0x57, 0x3e, 0x67, 0xad, 0x2f, 0x0e, 0xbc, 0xae,
+ 0x62, 0xef, 0x8a, 0x24, 0xd6, 0x33, 0xc6, 0x0a, 0x8c, 0x58, 0xb3, 0x59, 0xc8, 0xd5, 0x14, 0xa1,
+ 0x2b, 0x70, 0x27, 0xec, 0xf9, 0x54, 0xe0, 0x0a, 0xa5, 0x3c, 0xe4, 0xa5, 0xfc, 0x14, 0x4a, 0xeb,
+ 0x80, 0xde, 0x6c, 0xe4, 0x79, 0x28, 0x5f, 0xbe, 0x70, 0x02, 0xf6, 0x75, 0x72, 0x2f, 0x3b, 0x65,
+ 0xe3, 0x1f, 0xee, 0x07, 0x07, 0x29, 0x8a, 0x8c, 0x37, 0x9b, 0x1f, 0x3a, 0xa0, 0xc7, 0x95, 0x58,
+ 0xfd, 0xe2, 0x08, 0x5e, 0xeb, 0xea, 0xa7, 0x35, 0x45, 0xb3, 0xb9, 0xcc, 0xd4, 0x6c, 0xfe, 0xe9,
+ 0xa7, 0xff, 0x78, 0xfe, 0x48, 0x83, 0xef, 0xb8, 0x8f, 0xc2, 0x8b, 0x9e, 0x80, 0x1b, 0xa0, 0x88,
+ 0x70, 0x6c, 0xa0, 0xe6, 0x69, 0x6a, 0x36, 0x24, 0x51, 0x3d, 0x5e, 0x71, 0xfc, 0xf5, 0x3f, 0x5d,
+ 0x21, 0x90, 0x9f, 0xda, 0xa8, 0xac, 0xb1, 0xe6, 0x83, 0xa6, 0x33, 0x67, 0xfd, 0x25, 0x8b, 0x50,
+ 0xe6, 0x18, 0x5e, 0xa3, 0x32, 0xf5, 0x7c, 0x06, 0x5c, 0x5b, 0xdd, 0x3b, 0x43, 0x12, 0xed, 0x8e,
+ 0x6b, 0x7a, 0x40, 0x93, 0x5a, 0x0d, 0x6a, 0x6f, 0x57, 0x25, 0xfd, 0xcd, 0xff, 0xc0, 0x16, 0x2b,
+ 0x9c, 0xc2, 0x13, 0x4a, 0xb6, 0x70, 0x6a, 0xef, 0xf3, 0xf0, 0x50, 0xed, 0x6b, 0x93, 0x6e, 0xde,
+ 0x02, 0x27, 0xec, 0x3d, 0xbb, 0x78, 0x2d, 0x6a, 0x54, 0x0d, 0x6c, 0xd6, 0xad, 0xee, 0x7b, 0x94,
+ 0x5d, 0xfb, 0x8d, 0xfd, 0x0f, 0x9f, 0x3e, 0xea, 0xf2, 0x9d, 0x7d, 0x76, 0xf6, 0xd9, 0x7b, 0xcf,
+ 0x4e, 0x3f, 0x3b, 0x4d, 0x63, 0x77, 0x9c, 0xc1, 0x94, 0x42, 0x91, 0xfa, 0xe9, 0x59, 0xd9, 0x05,
+ 0x98, 0xcf, 0x3a, 0x9e, 0x9d, 0x65, 0xe6, 0x7b, 0xbf, 0x6a, 0xc6, 0xfe, 0x4c, 0x41, 0x02, 0x9e,
+ 0xe0, 0xcf, 0x8c, 0x5b, 0xa4, 0x67, 0x8e, 0x48, 0xf1, 0xed, 0x23, 0x89, 0x66, 0x73, 0xa6, 0xef,
+ 0xdd, 0x6b, 0x4f, 0xff, 0xeb, 0xa9, 0xe0, 0xce, 0xb3, 0xdc, 0xd1, 0xce, 0x5e, 0x33, 0xd4, 0xf9,
+ 0xfb, 0x03, 0x7d, 0x6e, 0x88, 0x05, 0x9d, 0xa1, 0xd1, 0x1c, 0xc1, 0xf4, 0x95, 0x1d, 0x7c, 0xa9,
+ 0xa4, 0xb1, 0x7c, 0xf4, 0xda, 0xde, 0xfb, 0x25, 0x48, 0x5b, 0x5e, 0xd3, 0xe3, 0xf4, 0xbd, 0x9d,
+ 0x94, 0x8a, 0x37, 0x88, 0xde, 0x00, 0x9b, 0x35, 0x74, 0x53, 0xfa, 0x9d, 0xbb, 0x62, 0xdc, 0x37,
+ 0x26, 0x1b, 0x6e, 0x18, 0x96, 0x5d, 0x91, 0x7d, 0x22, 0xbb, 0x4c, 0x21, 0xc5, 0xca, 0x60, 0xc3,
+ 0xb3, 0xf7, 0x28, 0x0c, 0x3f, 0x69, 0x18, 0x6e, 0xf8, 0x3c, 0x39, 0x87, 0xd1, 0x94, 0x5d, 0xf9,
+ 0x5d, 0x4f, 0x95, 0x76, 0x4c, 0xa5, 0xa0, 0xac, 0xa9, 0x46, 0x25, 0xa6, 0x8d, 0x7d, 0x96, 0x3f,
+ 0x6b, 0x6f, 0x76, 0x24, 0x23, 0x89, 0xb2, 0x0c, 0xf7, 0x24, 0x5d, 0xca, 0xfa, 0xb4, 0xce, 0x9a,
+ 0xce, 0x78, 0x99, 0x29, 0xbf, 0x3a, 0xea, 0x4c, 0xb2, 0x59, 0x66, 0xfa, 0x3a, 0xd8, 0x1f, 0xbc,
+ 0x4e, 0xe9, 0x1d, 0x14, 0x3d, 0xe8, 0x79, 0xdd, 0xf1, 0x46, 0xd2, 0x6e, 0x60, 0x65, 0x53, 0x56,
+ 0x71, 0x74, 0xef, 0xfd, 0x12, 0xd0, 0x96, 0xb3, 0xaa, 0xad, 0x4b, 0xbd, 0xf6, 0xb8, 0x77, 0x29,
+ 0x2c, 0xc5, 0x06, 0x98, 0xc1, 0x43, 0x5e, 0xe8, 0x78, 0xf6, 0x6a, 0xf4, 0x51, 0xf0, 0xdf, 0x7d,
+ 0xb2, 0xe5, 0x8e, 0xc5, 0xe1, 0xc5, 0xe1, 0xbb, 0xc3, 0x77, 0x3b, 0xa6, 0x1b, 0x3e, 0x97, 0x7d,
+ 0xf2, 0xec, 0x2c, 0x75, 0xa2, 0x32, 0x48, 0x36, 0x5c, 0xb9, 0xf0, 0x8b, 0x8e, 0xdb, 0x43, 0x94,
+ 0xb7, 0x3d, 0xcc, 0x9f, 0x77, 0x3b, 0x6e, 0x37, 0xdc, 0xb8, 0x6b, 0xee, 0xd6, 0x61, 0xda, 0xe7,
+ 0xb5, 0xc0, 0x99, 0x1b, 0x1b, 0xa8, 0xa5, 0x63, 0xdc, 0xbb, 0x85, 0x65, 0xba, 0xfd, 0x66, 0xc4,
+ 0xee, 0x39, 0xc2, 0x69, 0x56, 0x4f, 0x2b, 0x53, 0x45, 0x0d, 0x91, 0xcb, 0x4d, 0x02, 0x59, 0xea,
+ 0x9b, 0x04, 0x77, 0xe3, 0x2c, 0x6d, 0x6a, 0x30, 0x88, 0xec, 0x82, 0xbf, 0x09, 0x68, 0xf6, 0xbe,
+ 0xff, 0x97, 0xcd, 0x4e, 0x84, 0xe1, 0x51, 0x9e, 0x7f, 0x26, 0xfb, 0xe3, 0x6b, 0x7b, 0x7f, 0x53,
+ 0x02, 0x71, 0x71, 0xa4, 0x2d, 0x81, 0x37, 0xbe, 0x94, 0x14, 0x4a, 0xe0, 0x26, 0x01, 0xcf, 0x26,
+ 0x7c, 0xb2, 0x52, 0xb2, 0x3d, 0x06, 0xfd, 0xb4, 0x36, 0x82, 0x21, 0xcf, 0xa2, 0x3b, 0xe4, 0x62,
+ 0xe6, 0xcd, 0x8e, 0x45, 0x0a, 0xcd, 0x61, 0xea, 0x34, 0x3d, 0x4d, 0x9f, 0xae, 0x67, 0x65, 0x57,
+ 0x3a, 0x6e, 0x0c, 0x2f, 0x56, 0x2c, 0xc3, 0x6f, 0xe3, 0xcc, 0x0c, 0xd1, 0xff, 0xfd, 0xcd, 0x7c,
+ 0xc7, 0xe2, 0xa3, 0xc9, 0xdf, 0x9b, 0x21, 0x92, 0x34, 0x6e, 0xe9, 0xb5, 0x41, 0xa7, 0xc4, 0x90,
+ 0x17, 0xba, 0xb2, 0x71, 0x53, 0xc8, 0x12, 0xec, 0x8b, 0x7f, 0x1d, 0xe4, 0x7e, 0xd7, 0x16, 0x68,
+ 0x67, 0x62, 0xa9, 0xce, 0xf8, 0xb9, 0x00, 0xf7, 0xf3, 0xfe, 0xc0, 0x4d, 0x3a, 0x9e, 0x73, 0x2d,
+ 0xad, 0xa2, 0x64, 0x55, 0x9d, 0xce, 0xcd, 0x74, 0x33, 0x1e, 0x1b, 0x98, 0x55, 0x41, 0x6e, 0x4b,
+ 0x8f, 0xb9, 0xc5, 0x56, 0xeb, 0x0a, 0x79, 0xe1, 0x5b, 0xf4, 0xb9, 0xef, 0x39, 0xa0, 0x97, 0x4a,
+ 0x3e, 0xb2, 0xa9, 0xc1, 0xc6, 0x2d, 0xd0, 0xb1, 0x66, 0xd2, 0xfd, 0x17, 0xd7, 0x7f, 0x39, 0xd8,
+ 0x7e, 0x96, 0xb1, 0xf5, 0x64, 0xbc, 0xb8, 0x09, 0x75, 0xc6, 0xee, 0x3d, 0x96, 0x34, 0x53, 0x84,
+ 0x6e, 0x9e, 0xf6, 0x47, 0x5a, 0x6c, 0x33, 0x02, 0x1f, 0x6b, 0xcb, 0xb0, 0xed, 0xd8, 0x76, 0xcc,
+ 0x5b, 0x84, 0xd6, 0x41, 0xb7, 0x0e, 0x3c, 0xb2, 0xe5, 0xf8, 0x43, 0xfb, 0xac, 0xaa, 0x51, 0xd9,
+ 0x48, 0xa2, 0xd9, 0xa5, 0x3c, 0xb1, 0x3e, 0x7c, 0x97, 0x92, 0xcc, 0xcb, 0xcf, 0xde, 0x03, 0x3d,
+ 0x29, 0xbb, 0xdc, 0xf0, 0xf9, 0xd0, 0xdd, 0xe9, 0xf5, 0x6f, 0x6c, 0xec, 0x3b, 0xb8, 0x19, 0xb3,
+ 0x9c, 0x58, 0xed, 0xb8, 0xfd, 0xca, 0x78, 0x6c, 0x00, 0xb7, 0xde, 0xb3, 0x4f, 0x7a, 0xa8, 0x55,
+ 0xf0, 0xcc, 0x51, 0x27, 0x10, 0x7f, 0x62, 0x5a, 0xe8, 0x36, 0x1c, 0x61, 0x64, 0xad, 0x3e, 0x0a,
+ 0x1c, 0x81, 0xec, 0x64, 0x99, 0x79, 0xc2, 0x89, 0x05, 0x0f, 0xfd, 0x1d, 0xe8, 0xd9, 0xa5, 0x9c,
+ 0xb7, 0xa0, 0x88, 0x4e, 0x93, 0x2e, 0x75, 0xad, 0x71, 0x6b, 0x3a, 0xdb, 0x28, 0xc4, 0x04, 0x09,
+ 0xff, 0x46, 0x98, 0x8d, 0xcc, 0xa2, 0x39, 0x18, 0x0f, 0x79, 0xc7, 0x2d, 0xf9, 0xda, 0x43, 0x23,
+ 0x78, 0x6c, 0x60, 0x29, 0xf8, 0x28, 0x78, 0x73, 0xe1, 0xe6, 0x64, 0xf8, 0x67, 0xd4, 0x0a, 0x1c,
+ 0xa7, 0xfd, 0x4a, 0x5e, 0x44, 0xf3, 0xd7, 0x6f, 0xa4, 0x66, 0x7f, 0xed, 0xf6, 0x10, 0x6a, 0xcb,
+ 0x54, 0xed, 0x81, 0x2a, 0x85, 0xb7, 0x1d, 0xc2, 0x27, 0x6b, 0xb1, 0x65, 0x62, 0xa0, 0xeb, 0x52,
+ 0x2e, 0x47, 0x86, 0x17, 0x1b, 0x7e, 0xc1, 0x60, 0x49, 0x49, 0xe5, 0x85, 0x1b, 0xc3, 0xcb, 0xce,
+ 0x08, 0xf6, 0x76, 0xfa, 0x93, 0xe3, 0x9f, 0xb6, 0xaf, 0x0f, 0x2f, 0x1e, 0xb9, 0x3d, 0x79, 0xb3,
+ 0x9c, 0x92, 0x86, 0x25, 0xea, 0x74, 0xc2, 0xb4, 0xa9, 0x7a, 0x4b, 0x83, 0xc5, 0x06, 0xb8, 0x15,
+ 0xee, 0x0f, 0xf0, 0x3d, 0xf9, 0x2a, 0x2d, 0x8a, 0xdd, 0x0c, 0xc6, 0xf8, 0x99, 0x3d, 0x0a, 0xf2,
+ 0xba, 0x07, 0xbd, 0x7b, 0x35, 0x25, 0x77, 0x4b, 0x41, 0x06, 0x33, 0xb2, 0x62, 0x46, 0xd2, 0xe6,
+ 0x52, 0x70, 0xdc, 0x32, 0xa6, 0x12, 0x7e, 0x17, 0x88, 0x02, 0x89, 0xa3, 0xb9, 0x49, 0xd4, 0x58,
+ 0x2b, 0x22, 0x0d, 0xeb, 0xb2, 0xbb, 0x70, 0x36, 0x85, 0x4f, 0xf3, 0x63, 0x24, 0x80, 0xe5, 0x2f,
+ 0xdf, 0xd8, 0xeb, 0xbb, 0x12, 0x74, 0x8b, 0xbc, 0x66, 0xe8, 0xb5, 0xc5, 0x29, 0xdb, 0x5a, 0xc8,
+ 0x76, 0x3d, 0x82, 0xa3, 0x1d, 0x3b, 0x6f, 0x11, 0x3e, 0x1b, 0x92, 0x89, 0xa7, 0x61, 0xe1, 0xbb,
+ 0xab, 0x4d, 0xcb, 0x21, 0x56, 0x2e, 0x19, 0xa9, 0xbc, 0x3d, 0xbd, 0xde, 0xef, 0x5b, 0xc9, 0xb0,
+ 0x0e, 0xdb, 0x76, 0x67, 0x04, 0xe2, 0xd6, 0x47, 0x96, 0xfb, 0xfd, 0xdf, 0x87, 0x27, 0x3d, 0x5d,
+ 0xca, 0x4c, 0xfa, 0x49, 0x41, 0x9e, 0x0b, 0xb0, 0x6b, 0xbc, 0xed, 0xe0, 0xa3, 0x5c, 0x66, 0x42,
+ 0xb1, 0xf1, 0x72, 0x17, 0xf7, 0xcd, 0x8c, 0x58, 0x8f, 0x99, 0x95, 0xb0, 0x54, 0x1f, 0x79, 0xcd,
+ 0x90, 0xeb, 0x76, 0x85, 0x43, 0xf2, 0x5c, 0x20, 0xaa, 0xe6, 0xe3, 0x66, 0xc4, 0xa2, 0xea, 0x7b,
+ 0x76, 0x88, 0x5c, 0x8a, 0x5b, 0xbb, 0xe0, 0xd9, 0x4d, 0xd8, 0xda, 0x23, 0x43, 0xab, 0xa0, 0x69,
+ 0x9e, 0x75, 0x84, 0x1b, 0x04, 0x68, 0xbe, 0xf4, 0xe8, 0xb5, 0x32, 0xd3, 0xde, 0xc6, 0xf1, 0x50,
+ 0xa6, 0x4e, 0x99, 0x09, 0xbe, 0x71, 0x9f, 0x5b, 0xc8, 0xc2, 0x5a, 0xa5, 0x8d, 0xd0, 0x71, 0x33,
+ 0x61, 0x3d, 0x23, 0x68, 0x4b, 0xf8, 0x79, 0xc8, 0xcb, 0x7f, 0xb7, 0x06, 0xab, 0xbd, 0x39, 0xbd,
+ 0x3e, 0x74, 0x9b, 0xd6, 0x97, 0xe0, 0x87, 0x7c, 0xd2, 0x71, 0x63, 0x68, 0x71, 0x39, 0xf2, 0xfb,
+ 0x0c, 0x7c, 0x3b, 0x46, 0x6c, 0xc1, 0xbd, 0x1c, 0x5d, 0x0e, 0x4d, 0xaf, 0x4f, 0x87, 0xea, 0x23,
+ 0xe5, 0xae, 0x52, 0x32, 0xb3, 0xa5, 0xa1, 0xc1, 0xd6, 0x0c, 0xec, 0x1d, 0x23, 0xdf, 0x32, 0x9d,
+ 0xc1, 0x27, 0x68, 0xef, 0xa2, 0x3e, 0xc6, 0xff, 0x06, 0x5d, 0x4a, 0x24, 0xab, 0x30, 0x39, 0x4d,
+ 0x61, 0xa4, 0x9e, 0xaf, 0x4a, 0x9b, 0x9b, 0xab, 0x16, 0x9d, 0xd6, 0xd0, 0x29, 0x48, 0xc1, 0xfb,
+ 0x26, 0x70, 0xaf, 0xdc, 0xea, 0x6a, 0xa7, 0xbb, 0x37, 0x0e, 0xc6, 0xa4, 0x64, 0x9d, 0x00, 0x9a,
+ 0x0f, 0xed, 0x43, 0xa1, 0xe1, 0xe5, 0x8e, 0x69, 0xd9, 0x15, 0xca, 0x06, 0x14, 0xa0, 0xd9, 0x2e,
+ 0xeb, 0x31, 0xef, 0x6d, 0x37, 0x45, 0xd0, 0x96, 0xcf, 0x6b, 0x7b, 0xcc, 0xe5, 0x94, 0xff, 0xdf,
+ 0x6b, 0x13, 0x6a, 0xfc, 0x1a, 0x2b, 0x3c, 0xe5, 0xcb, 0x29, 0x7d, 0x06, 0xd6, 0x0c, 0x68, 0xf7,
+ 0x4f, 0xd8, 0xf9, 0xba, 0x75, 0x06, 0x9f, 0xf2, 0x4f, 0xaf, 0x5e, 0x98, 0x6e, 0xb8, 0x42, 0xf9,
+ 0x91, 0xef, 0x3d, 0xeb, 0x90, 0x0d, 0x77, 0x4c, 0x4f, 0xaf, 0x9e, 0x08, 0x45, 0x33, 0x70, 0x47,
+ 0x96, 0x92, 0x84, 0x6f, 0x39, 0x46, 0xa1, 0x19, 0x75, 0x46, 0x1f, 0xe6, 0x8c, 0xb9, 0x94, 0x92,
+ 0xc0, 0x4d, 0x4a, 0x9d, 0xe7, 0x82, 0x4c, 0x74, 0x05, 0x09, 0x3d, 0x4d, 0x7c, 0x71, 0x3e, 0x2f,
+ 0x93, 0x11, 0x2b, 0x77, 0xb1, 0x48, 0xfa, 0x12, 0xe8, 0x36, 0x03, 0x76, 0x69, 0x6c, 0x60, 0x2a,
+ 0x28, 0xe6, 0x93, 0xb2, 0x48, 0xf2, 0xa5, 0x19, 0xf2, 0x80, 0xa8, 0x3d, 0xcb, 0xc8, 0x79, 0x7b,
+ 0xec, 0x0b, 0x89, 0xf5, 0xb9, 0x2b, 0x44, 0xf9, 0x4d, 0x27, 0xa0, 0x79, 0x03, 0xed, 0x6a, 0xe4,
+ 0x6d, 0x03, 0xa2, 0x43, 0x32, 0xfd, 0xc7, 0x73, 0xfa, 0x59, 0x55, 0xfa, 0xed, 0xf5, 0xee, 0x0c,
+ 0x96, 0x13, 0x7d, 0x7d, 0xa0, 0xcf, 0xfd, 0x75, 0xb0, 0xc7, 0xcc, 0x5f, 0x77, 0x0d, 0x86, 0xb4,
+ 0x65, 0xb9, 0x4b, 0x88, 0xf0, 0x84, 0x1d, 0x76, 0xea, 0xcd, 0xf8, 0xb8, 0x80, 0xb1, 0x1e, 0x7b,
+ 0xbb, 0x62, 0x7d, 0x9a, 0x7a, 0x02, 0xf0, 0x49, 0x28, 0xa9, 0xa4, 0xed, 0x9e, 0xe5, 0xd0, 0x5f,
+ 0xbb, 0x84, 0x76, 0x31, 0x9a, 0xb3, 0x10, 0x55, 0x8f, 0x53, 0x68, 0xc6, 0x96, 0x02, 0x4d, 0x39,
+ 0x7b, 0x18, 0xac, 0x10, 0xf7, 0xec, 0xe8, 0x3c, 0xe7, 0x7f, 0xd6, 0xac, 0x0a, 0x4e, 0x06, 0xc2,
+ 0xcf, 0x5f, 0xfb, 0x6e, 0x1d, 0x67, 0xc1, 0x00, 0x7f, 0xdd, 0x0c, 0xde, 0xa4, 0x9b, 0xb0, 0x23,
+ 0xb6, 0x7c, 0x71, 0x2c, 0x41, 0x4f, 0x36, 0xe9, 0xb8, 0xcf, 0xd8, 0x24, 0xd6, 0x2d, 0x83, 0x80,
+ 0x24, 0x9a, 0x94, 0xb6, 0x96, 0x6e, 0x0b, 0x6d, 0x12, 0x93, 0x2e, 0x1a, 0x4d, 0xb0, 0xe9, 0x2f,
+ 0x23, 0x34, 0x59, 0x0f, 0xf3, 0x9f, 0xdf, 0x6f, 0xd2, 0xed, 0x55, 0xd7, 0x5a, 0x96, 0x23, 0x0b,
+ 0x22, 0xb1, 0x84, 0x5f, 0xb8, 0xf7, 0x14, 0x24, 0xac, 0x84, 0x93, 0xda, 0xfd, 0xfc, 0x75, 0x1c,
+ 0xc1, 0x11, 0xc2, 0xdf, 0x87, 0x85, 0xf9, 0xc4, 0xe3, 0xe6, 0xf6, 0x10, 0x6d, 0xf9, 0x20, 0x2c,
+ 0xa9, 0x13, 0x96, 0xb2, 0x7b, 0x42, 0xf3, 0x0c, 0x0f, 0xfa, 0x0a, 0x01, 0x59, 0x6c, 0xac, 0x26,
+ 0x6a, 0xd2, 0x2d, 0x05, 0xd1, 0x2a, 0x85, 0x3c, 0xdc, 0x29, 0x09, 0xf1, 0xb0, 0x79, 0x0b, 0xdc,
+ 0x8e, 0x72, 0x9f, 0xd7, 0xa5, 0x64, 0xf7, 0x13, 0x7f, 0x8f, 0x6d, 0x19, 0xe0, 0x9e, 0x91, 0xcf,
+ 0xb1, 0x5e, 0x4a, 0x86, 0xbc, 0x9c, 0xd6, 0xdb, 0x08, 0x6f, 0x12, 0xd0, 0xef, 0x2d, 0x9c, 0x90,
+ 0x92, 0x03, 0x92, 0xa0, 0xed, 0x38, 0xfe, 0x29, 0xa3, 0x20, 0x5b, 0x6c, 0xed, 0x1c, 0x92, 0x71,
+ 0xb0, 0xf2, 0xa4, 0x22, 0x09, 0x73, 0x4c, 0x45, 0xe9, 0x90, 0x74, 0x34, 0x8f, 0x3a, 0x65, 0x53,
+ 0x6f, 0x7d, 0xf2, 0x3e, 0x7b, 0x7b, 0x8d, 0x9e, 0x85, 0x9b, 0xf2, 0x82, 0xb1, 0x44, 0x77, 0x5d,
+ 0xdf, 0x39, 0xe0, 0x96, 0x57, 0x18, 0x27, 0x98, 0xd3, 0x83, 0x7d, 0xff, 0x34, 0x2c, 0xf4, 0xbb,
+ 0x67, 0x55, 0x28, 0xdf, 0x29, 0x9e, 0xa2, 0x2d, 0x7f, 0x74, 0x38, 0x59, 0xcb, 0xa7, 0x43, 0x76,
+ 0xa1, 0x81, 0x3e, 0x61, 0x97, 0xfc, 0xac, 0x75, 0xd4, 0xa4, 0xab, 0xa3, 0x7c, 0x57, 0xf6, 0x9c,
+ 0xdc, 0x32, 0x20, 0x6f, 0x23, 0x92, 0x78, 0xe8, 0xe0, 0x2c, 0x8d, 0x46, 0x25, 0xe4, 0xa4, 0x0f,
+ 0xc6, 0xf8, 0x6c, 0xdb, 0xc0, 0x3a, 0x92, 0x1a, 0x93, 0xa3, 0xbc, 0x7e, 0xbb, 0x90, 0x2b, 0x0d,
+ 0x18, 0x2d, 0x58, 0xbd, 0x0a, 0x73, 0x2a, 0xb8, 0xed, 0xe0, 0x5e, 0x67, 0x1a, 0xe1, 0x04, 0x44,
+ 0x21, 0x21, 0x0f, 0x6b, 0x81, 0xf6, 0x6b, 0x5b, 0xdd, 0xdc, 0xce, 0x5c, 0x21, 0xa0, 0xe6, 0x80,
+ 0xfa, 0xcb, 0xa4, 0x54, 0xb6, 0xba, 0x67, 0x24, 0xd8, 0xb1, 0xfc, 0xd5, 0xc0, 0xde, 0x26, 0x16,
+ 0x92, 0x68, 0x5e, 0xe0, 0xd0, 0x1c, 0x94, 0xfd, 0xcf, 0xbb, 0xe8, 0xf6, 0x7a, 0x06, 0x2f, 0x25,
+ 0xc1, 0xb7, 0xad, 0x62, 0x26, 0xa6, 0x05, 0xdf, 0x73, 0xe7, 0x48, 0xc2, 0xba, 0xc0, 0x4d, 0x2b,
+ 0x8a, 0xc4, 0x6e, 0x3b, 0x84, 0x96, 0x37, 0xca, 0x88, 0x69, 0x0b, 0x08, 0x11, 0xae, 0x36, 0xa1,
+ 0xd5, 0xe5, 0x5b, 0x90, 0x20, 0x17, 0x71, 0xcf, 0xf4, 0x7a, 0x07, 0x58, 0x3e, 0x97, 0xe9, 0xb8,
+ 0x1d, 0x78, 0x96, 0xa1, 0xb7, 0x6e, 0xa2, 0x13, 0x16, 0x7c, 0xaf, 0x48, 0x82, 0x8b, 0x43, 0x40,
+ 0xb5, 0x17, 0xf2, 0xe4, 0xd6, 0x79, 0x32, 0xdf, 0x0d, 0xd2, 0x4a, 0x9d, 0x03, 0xdc, 0x1d, 0x07,
+ 0x48, 0x20, 0xf2, 0x7e, 0xf8, 0x1a, 0xdb, 0x88, 0xf5, 0x07, 0x5e, 0x8d, 0xf2, 0xa5, 0x97, 0xad,
+ 0x48, 0x67, 0xcf, 0x53, 0xe8, 0x2b, 0xc2, 0x21, 0x9b, 0x49, 0x0e, 0x9b, 0xcd, 0x8d, 0x4a, 0x85,
+ 0xe0, 0x5e, 0x96, 0x7d, 0x76, 0xc8, 0xad, 0x67, 0xe2, 0x10, 0x0c, 0x96, 0x71, 0x2f, 0xca, 0x26,
+ 0xc8, 0x67, 0xd2, 0xd5, 0x7e, 0xbe, 0xe5, 0xd0, 0xd0, 0xf2, 0x85, 0x1b, 0x32, 0xca, 0xa6, 0x45,
+ 0x71, 0x4d, 0x40, 0xb3, 0xfd, 0xe8, 0xdf, 0x9d, 0xdf, 0xba, 0x84, 0x69, 0x21, 0x3a, 0xb3, 0xed,
+ 0x58, 0xf0, 0x84, 0xbc, 0x68, 0x42, 0xcc, 0xa8, 0x49, 0xb7, 0x73, 0x34, 0x59, 0xf6, 0x65, 0xdc,
+ 0x0a, 0x77, 0xe4, 0xa9, 0xf7, 0x44, 0xd0, 0xbb, 0x09, 0xea, 0x59, 0xf8, 0xf6, 0x45, 0xb7, 0x0e,
+ 0x71, 0x3a, 0x0e, 0xc6, 0x84, 0xfc, 0x0e, 0x4d, 0x3a, 0xb0, 0x7c, 0xa8, 0x5d, 0x78, 0x85, 0xc2,
+ 0xf2, 0xb2, 0xec, 0x4a, 0xc7, 0xf4, 0xf0, 0x6a, 0x7b, 0x68, 0x9c, 0xd1, 0xbf, 0x0a, 0x12, 0xb8,
+ 0x7f, 0x7b, 0x99, 0x38, 0x04, 0xb0, 0x3a, 0xa3, 0xb5, 0xde, 0xe0, 0x9d, 0xd3, 0x10, 0x39, 0xb9,
+ 0x49, 0x5b, 0x8c, 0x5c, 0x5d, 0xcf, 0x08, 0xfe, 0x15, 0xad, 0x2d, 0xdb, 0x02, 0x7c, 0xad, 0xab,
+ 0x20, 0x9d, 0x71, 0xfe, 0xbe, 0x5b, 0x21, 0x1e, 0x3a, 0x22, 0x02, 0xa4, 0x84, 0x33, 0x7d, 0xa4,
+ 0x46, 0xb7, 0xf8, 0x53, 0x41, 0xc6, 0x79, 0xa7, 0xb5, 0x33, 0xde, 0xea, 0xce, 0xec, 0x2f, 0x89,
+ 0xcb, 0xe6, 0x9c, 0x9e, 0x5a, 0x13, 0x4a, 0xef, 0x50, 0x36, 0x04, 0x65, 0x0f, 0x86, 0x4f, 0x73,
+ 0x27, 0xed, 0x37, 0x9d, 0xf3, 0x96, 0x16, 0x1b, 0xe1, 0x87, 0xde, 0xd8, 0xf5, 0xd1, 0x8a, 0x68,
+ 0x7d, 0xd4, 0x49, 0xed, 0xbe, 0x8a, 0x68, 0xad, 0xab, 0x2a, 0x67, 0xbf, 0x93, 0x5c, 0x83, 0xa9,
+ 0x1c, 0xb8, 0xd4, 0x6b, 0x7f, 0xd9, 0xdf, 0x1f, 0x10, 0xab, 0xa7, 0x31, 0xfe, 0x2f, 0x75, 0xd7,
+ 0x1b, 0xd3, 0xd6, 0xb9, 0xde, 0xf7, 0x21, 0xd2, 0xfc, 0x21, 0x52, 0x7d, 0x75, 0xd9, 0x7a, 0xba,
+ 0x10, 0x6e, 0x33, 0xa5, 0x51, 0xb8, 0x82, 0x28, 0x08, 0x37, 0x17, 0x6e, 0x80, 0x0a, 0x22, 0x2a,
+ 0x85, 0x96, 0xae, 0xd0, 0x90, 0xc5, 0x21, 0x36, 0x62, 0x5e, 0x5a, 0xa5, 0x16, 0xb7, 0xca, 0xb8,
+ 0xb4, 0x23, 0x80, 0x2d, 0x51, 0x2f, 0xd1, 0x45, 0x2e, 0x59, 0x99, 0x21, 0x0a, 0x35, 0xb6, 0x84,
+ 0xe6, 0x20, 0xa5, 0x72, 0xd8, 0x98, 0x6c, 0x26, 0xdf, 0xfa, 0xf8, 0x03, 0xba, 0xf6, 0x87, 0x48,
+ 0xc7, 0x9b, 0x90, 0xec, 0xde, 0x90, 0x1c, 0x7f, 0x40, 0xca, 0x99, 0x94, 0x49, 0xe7, 0x4e, 0x54,
+ 0x73, 0x54, 0x27, 0x61, 0xef, 0xef, 0x7d, 0x7d, 0x7c, 0xce, 0xf1, 0x1f, 0x02, 0xac, 0xba, 0x52,
+ 0x79, 0xd4, 0x2a, 0xc1, 0xc4, 0x1c, 0xbf, 0xcf, 0xfb, 0xfc, 0xff, 0x3d, 0xcf, 0x43, 0x22, 0x84,
+ 0xf9, 0x3c, 0x9e, 0x34, 0x27, 0x9e, 0x2d, 0xb2, 0x96, 0xad, 0x49, 0x67, 0x8c, 0x58, 0x4b, 0xf0,
+ 0x92, 0x48, 0xa5, 0x73, 0xd9, 0x9f, 0x34, 0xf3, 0x8c, 0x2b, 0x98, 0xe4, 0x80, 0x5c, 0xab, 0x62,
+ 0xdf, 0x26, 0x8d, 0x38, 0x7b, 0x50, 0x93, 0xc6, 0x7b, 0x59, 0x34, 0x2a, 0x5e, 0x8e, 0x96, 0x4b,
+ 0x5c, 0x9c, 0x69, 0x62, 0xad, 0x8e, 0x7b, 0x72, 0x31, 0x92, 0x52, 0xf9, 0xcd, 0x7a, 0x54, 0xb4,
+ 0x3c, 0xd3, 0xf2, 0xd1, 0x22, 0x4f, 0x94, 0x54, 0x60, 0x26, 0x76, 0xcc, 0xa7, 0x5f, 0x6f, 0xb0,
+ 0x14, 0xb4, 0x73, 0xb5, 0x74, 0xd2, 0xb5, 0xff, 0x7a, 0x18, 0xb4, 0xca, 0x86, 0xc0, 0xb8, 0xd9,
+ 0xc6, 0xb8, 0x79, 0x8a, 0x71, 0x53, 0x3c, 0x95, 0x5e, 0xc0, 0x56, 0xea, 0x16, 0xa9, 0x2f, 0x98,
+ 0x1c, 0xeb, 0xb6, 0xdf, 0x1b, 0x46, 0xad, 0x02, 0xbf, 0xaf, 0xc7, 0xdd, 0x59, 0xd8, 0xdf, 0xb2,
+ 0x57, 0x5e, 0x6e, 0x16, 0x32, 0xb1, 0x5c, 0x7c, 0xe7, 0xfe, 0x53, 0x96, 0x3f, 0xa6, 0x9a, 0xa7,
+ 0x44, 0x52, 0x26, 0x8d, 0x2b, 0x6e, 0x5f, 0xda, 0xb1, 0x8a, 0xcc, 0x3a, 0x95, 0xca, 0x9b, 0x8e,
+ 0x55, 0x5f, 0xc6, 0xb4, 0xc0, 0x38, 0x80, 0x18, 0x1e, 0xbe, 0x8a, 0x72, 0x57, 0xd8, 0x44, 0x3c,
+ 0x44, 0x0e, 0x7d, 0xc1, 0x41, 0x8d, 0x97, 0x13, 0xa6, 0xf2, 0xa0, 0x9d, 0x1b, 0xd1, 0x59, 0xcb,
+ 0x74, 0xb1, 0x7e, 0x93, 0xcc, 0x8a, 0xe7, 0xa4, 0x4b, 0x95, 0x14, 0x20, 0x35, 0xf4, 0xb2, 0xc7,
+ 0xf8, 0x30, 0x91, 0x1d, 0x15, 0xaa, 0x02, 0xd3, 0xc3, 0xc5, 0xbb, 0xdf, 0x8a, 0xe3, 0xe2, 0x62,
+ 0x52, 0xa2, 0x54, 0x9e, 0xe8, 0xd6, 0x83, 0xb6, 0xdd, 0xf5, 0x57, 0x6f, 0x12, 0xcf, 0x0e, 0x19,
+ 0xc6, 0x62, 0xf9, 0x6d, 0x37, 0x74, 0xdb, 0x5a, 0x49, 0x14, 0xed, 0x58, 0x66, 0x3e, 0x21, 0xe3,
+ 0xa6, 0x78, 0xaa, 0x66, 0xc0, 0xb9, 0x8a, 0xaa, 0xfa, 0x55, 0xb7, 0xd1, 0x35, 0x12, 0x44, 0x1e,
+ 0x71, 0xc5, 0x83, 0x0d, 0x55, 0x7c, 0x36, 0x1c, 0x82, 0x37, 0xbd, 0x77, 0x4e, 0xea, 0xad, 0xa5,
+ 0xf6, 0x5c, 0x4b, 0x09, 0x1d, 0x67, 0xf4, 0x33, 0xe6, 0xfd, 0x3a, 0x6c, 0xc6, 0xd6, 0x9e, 0xf9,
+ 0x5c, 0x20, 0x86, 0x27, 0x06, 0x2f, 0x3f, 0x81, 0xdf, 0xe3, 0x23, 0x91, 0xe5, 0x90, 0x5d, 0xe1,
+ 0x34, 0xe6, 0x33, 0x8d, 0x0a, 0x4a, 0x5e, 0x0d, 0x93, 0xad, 0x70, 0x5a, 0xc8, 0x6c, 0xab, 0xef,
+ 0x71, 0xbc, 0x63, 0x43, 0x24, 0x51, 0x9e, 0xae, 0x8a, 0x3c, 0xd5, 0x4b, 0x33, 0x02, 0x92, 0x8a,
+ 0x99, 0xc2, 0x93, 0xf4, 0x05, 0xd5, 0x7b, 0x34, 0x58, 0x76, 0x8e, 0xd7, 0x05, 0x61, 0xcb, 0x8b,
+ 0xb8, 0x7c, 0x8d, 0xeb, 0xac, 0xad, 0xd6, 0xd5, 0xb9, 0x98, 0x75, 0xd8, 0xe9, 0x93, 0x2e, 0x1a,
+ 0xa7, 0x87, 0xfb, 0x82, 0x55, 0x81, 0xe4, 0xd8, 0xee, 0x50, 0x23, 0x93, 0x24, 0xf6, 0xd9, 0xf2,
+ 0x8e, 0x0a, 0x39, 0x71, 0x24, 0xa8, 0x7d, 0xce, 0xc2, 0xf3, 0x0d, 0x5b, 0xd2, 0xfe, 0x84, 0x53,
+ 0xcb, 0xcd, 0xb6, 0xb7, 0x9c, 0xb1, 0x74, 0x26, 0x3b, 0x17, 0x44, 0xec, 0x3b, 0x64, 0x07, 0x2a,
+ 0x81, 0x8b, 0x23, 0xb7, 0xcf, 0x93, 0xfb, 0x87, 0xfb, 0xb3, 0x1f, 0x5e, 0x22, 0x13, 0xfb, 0x9b,
+ 0x5e, 0x99, 0xc4, 0x96, 0x91, 0xd4, 0xce, 0x1d, 0x18, 0x83, 0x06, 0x58, 0x3c, 0xc5, 0x1b, 0xc0,
+ 0x36, 0x34, 0xed, 0xab, 0xc7, 0x3b, 0xae, 0xc5, 0x89, 0xe7, 0x03, 0x9f, 0xed, 0x13, 0xea, 0xf7,
+ 0x2c, 0xf9, 0x93, 0x91, 0xc2, 0x26, 0x1f, 0x96, 0x27, 0x52, 0x23, 0x71, 0x36, 0x0b, 0x98, 0x65,
+ 0xcb, 0xd5, 0x1b, 0x4c, 0xb3, 0x72, 0xe4, 0x9d, 0x57, 0xbc, 0x88, 0x4b, 0x18, 0x8d, 0x84, 0x60,
+ 0x57, 0xb9, 0xb8, 0xf6, 0x54, 0xb1, 0x03, 0x51, 0xfd, 0xdb, 0xf5, 0x86, 0xdc, 0xe3, 0x62, 0xbf,
+ 0x06, 0x73, 0xb7, 0x36, 0xf3, 0x95, 0x1d, 0x64, 0xf5, 0xf4, 0xaf, 0xee, 0xb4, 0x61, 0x91, 0x3d,
+ 0x09, 0x22, 0xee, 0x4d, 0x6e, 0x77, 0x55, 0x4d, 0xc2, 0x79, 0xfb, 0xbc, 0xc0, 0xcb, 0x19, 0x19,
+ 0x37, 0xdc, 0x54, 0x26, 0x9a, 0x5e, 0xe3, 0x1a, 0x5c, 0x0e, 0xc2, 0x4d, 0xc7, 0x12, 0xf5, 0xf1,
+ 0xcf, 0x23, 0x53, 0xed, 0xf4, 0x67, 0x24, 0x9f, 0x3c, 0xe3, 0x81, 0x66, 0x3d, 0x48, 0x64, 0x24,
+ 0x39, 0x36, 0x17, 0xca, 0x46, 0x81, 0xaf, 0xc8, 0x89, 0xf2, 0xd8, 0x81, 0x23, 0xfb, 0xe1, 0x25,
+ 0x8b, 0x2d, 0xdf, 0x27, 0xb1, 0xe5, 0x03, 0xb1, 0xb8, 0xb2, 0x50, 0xfc, 0x09, 0xa5, 0x66, 0x35,
+ 0x76, 0x9e, 0x90, 0xb5, 0xdb, 0x43, 0x09, 0x1f, 0xfa, 0x2d, 0xcc, 0xff, 0x46, 0x35, 0x9a, 0x68,
+ 0x58, 0xa2, 0x41, 0xd2, 0xa6, 0x05, 0xe5, 0x8e, 0xde, 0xa5, 0xd2, 0xb5, 0x52, 0x88, 0xdf, 0xae,
+ 0x74, 0xb1, 0xc9, 0x39, 0x88, 0x02, 0xd5, 0x33, 0xe9, 0x71, 0x23, 0x7b, 0xd0, 0x22, 0xa1, 0x0e,
+ 0x38, 0x4a, 0xfe, 0x8b, 0xa4, 0x36, 0xc4, 0x16, 0x69, 0x81, 0x6e, 0xba, 0xd3, 0xda, 0xac, 0x41,
+ 0x0d, 0x1e, 0x8e, 0x6d, 0xac, 0x29, 0xd6, 0xa1, 0x7c, 0x56, 0xb9, 0x35, 0x83, 0x86, 0xb9, 0x90,
+ 0xde, 0x92, 0xfa, 0xb2, 0x27, 0xdd, 0xfb, 0xf1, 0x64, 0xca, 0xd3, 0xa4, 0x11, 0xf9, 0x57, 0xe4,
+ 0xaf, 0x08, 0x91, 0xd3, 0x49, 0x47, 0x4b, 0xb1, 0x52, 0xed, 0x86, 0x03, 0xaf, 0x11, 0x0b, 0x94,
+ 0x21, 0x9e, 0x61, 0x9e, 0x9b, 0x44, 0xc3, 0x2e, 0x65, 0x64, 0x74, 0xcd, 0x63, 0x56, 0x11, 0x2a,
+ 0x6e, 0xf0, 0x9c, 0x47, 0x85, 0xe4, 0x18, 0xb6, 0xc7, 0xaf, 0x53, 0x14, 0xd9, 0x5e, 0xbf, 0xd8,
+ 0xec, 0x8f, 0x83, 0xb6, 0x19, 0x0f, 0x6a, 0x85, 0x2f, 0xb3, 0x0c, 0xf0, 0xcb, 0x2c, 0x12, 0x8b,
+ 0xb7, 0x72, 0xa2, 0xf6, 0xd6, 0x12, 0x3e, 0xb8, 0x50, 0x21, 0xb1, 0xc2, 0xf3, 0x21, 0x1a, 0x76,
+ 0x80, 0x44, 0x96, 0xbe, 0xcc, 0x54, 0xe1, 0x6e, 0xc0, 0x3a, 0xf2, 0x9a, 0x2c, 0xd1, 0x93, 0x7c,
+ 0x8e, 0x75, 0x2e, 0xa4, 0xbe, 0x07, 0xf5, 0x1e, 0xe5, 0x58, 0xc6, 0x97, 0x36, 0xc7, 0x51, 0x43,
+ 0xc4, 0x94, 0xd8, 0xdb, 0x29, 0xcc, 0x09, 0x28, 0xce, 0x2f, 0x69, 0x9f, 0x48, 0xc9, 0x26, 0xea,
+ 0x79, 0xb9, 0x21, 0x2a, 0xd2, 0x61, 0xe8, 0x88, 0x88, 0x7a, 0x5e, 0x8e, 0x0a, 0x3f, 0xd4, 0x24,
+ 0x03, 0x74, 0xdf, 0x66, 0x43, 0xb1, 0x8c, 0x1f, 0x59, 0x65, 0xa0, 0xa1, 0x25, 0x3e, 0x5b, 0xb5,
+ 0xa0, 0x9e, 0x22, 0x30, 0x98, 0x4a, 0x45, 0xfb, 0xc0, 0x6b, 0x5b, 0x1e, 0x07, 0xe1, 0xe6, 0xc0,
+ 0x12, 0xad, 0xd5, 0x5b, 0x07, 0x6e, 0xc4, 0x32, 0x7c, 0x76, 0xc5, 0xb3, 0xee, 0x85, 0x5c, 0x5a,
+ 0x64, 0xa3, 0x0b, 0x55, 0xd3, 0xab, 0x6e, 0xec, 0x2f, 0xdf, 0x9f, 0xf7, 0x03, 0xcf, 0xc7, 0xd0,
+ 0x81, 0xee, 0x25, 0xb3, 0xb0, 0x9b, 0x49, 0x55, 0xc0, 0x7b, 0x33, 0x1f, 0xaf, 0x4f, 0xf7, 0xd3,
+ 0x47, 0x8f, 0xcc, 0x05, 0x88, 0xb7, 0xb6, 0x4c, 0x79, 0xf9, 0x59, 0xdb, 0x4d, 0xf8, 0xb0, 0xb9,
+ 0xc2, 0xdd, 0x58, 0x34, 0xc2, 0x62, 0x1d, 0x92, 0x94, 0x8c, 0x03, 0x62, 0x0f, 0xe6, 0x9d, 0x68,
+ 0x63, 0xa0, 0x3b, 0x0d, 0x2d, 0x19, 0x9a, 0x6d, 0x4f, 0x3c, 0xe3, 0xcf, 0x05, 0x4d, 0x81, 0xbe,
+ 0x60, 0x38, 0x84, 0xfd, 0xdb, 0x44, 0x4e, 0xc5, 0xd2, 0xba, 0xb2, 0x72, 0x9a, 0xe5, 0x66, 0xf7,
+ 0x42, 0x27, 0x33, 0x39, 0x56, 0x32, 0x08, 0x5a, 0x89, 0xed, 0xd9, 0x51, 0x2a, 0x95, 0xfc, 0xcb,
+ 0x6e, 0xce, 0x62, 0x8a, 0xc4, 0x8f, 0xac, 0xd6, 0xe3, 0x8c, 0xf9, 0x13, 0xb1, 0x74, 0x4c, 0xaa,
+ 0xce, 0x28, 0xf9, 0xff, 0x45, 0x63, 0xa2, 0x61, 0xaa, 0xb7, 0xdb, 0x56, 0x4f, 0xf7, 0xd2, 0xb2,
+ 0x33, 0xea, 0x0b, 0x50, 0xd9, 0xa4, 0xc8, 0x8b, 0xb7, 0x3e, 0xf3, 0xc7, 0xb6, 0xb3, 0x5c, 0x1c,
+ 0x1d, 0xbc, 0x88, 0xcf, 0xc2, 0xa1, 0x15, 0x0f, 0xfe, 0x0c, 0x7b, 0xd9, 0x6d, 0x5f, 0xdc, 0x87,
+ 0xbd, 0x84, 0xe7, 0x03, 0xc4, 0xd6, 0x39, 0x62, 0x2d, 0xf5, 0xf6, 0x0f, 0xf6, 0x7c, 0xc8, 0x3e,
+ 0x64, 0x2f, 0x8e, 0x52, 0x88, 0x8f, 0x43, 0x75, 0xd6, 0x90, 0x0e, 0x19, 0x95, 0x68, 0x20, 0x9e,
+ 0x77, 0x92, 0x6a, 0x90, 0xcf, 0x88, 0xdf, 0x43, 0xab, 0x23, 0x2b, 0x85, 0x89, 0x74, 0x2c, 0x4f,
+ 0x6a, 0x16, 0x94, 0x28, 0x62, 0xd2, 0xc8, 0x32, 0xf6, 0x99, 0x6d, 0x55, 0x4f, 0x43, 0xc2, 0xd0,
+ 0x8d, 0x43, 0xee, 0x78, 0xc2, 0xba, 0x9a, 0x26, 0x9e, 0xc7, 0xb9, 0xe0, 0x1c, 0xe3, 0xa5, 0x9c,
+ 0xad, 0x58, 0x6d, 0x6a, 0x37, 0x94, 0xdf, 0x1a, 0x7e, 0x2e, 0xbf, 0x3d, 0x68, 0x93, 0x1b, 0x09,
+ 0xea, 0xa5, 0xb2, 0x5a, 0xaa, 0x2c, 0x95, 0xa8, 0x8a, 0xd4, 0xd9, 0x92, 0x63, 0x43, 0x76, 0xa9,
+ 0xf9, 0x65, 0xb6, 0x72, 0xd1, 0xd8, 0x6d, 0x8b, 0x08, 0x31, 0x70, 0x72, 0xd9, 0xb9, 0xec, 0x58,
+ 0xf6, 0xc7, 0xfc, 0x69, 0x5e, 0x62, 0x51, 0x2b, 0xe6, 0x5c, 0x5e, 0x75, 0x5d, 0x8b, 0xfb, 0xa0,
+ 0x75, 0x65, 0x9f, 0xbc, 0xe5, 0x65, 0x5a, 0x82, 0xe6, 0xf5, 0x32, 0x2c, 0x13, 0xf4, 0xb3, 0x4f,
+ 0x06, 0x6e, 0x11, 0x1d, 0x24, 0x9b, 0x02, 0x46, 0xd7, 0x96, 0x97, 0x61, 0xc7, 0xb7, 0xbc, 0x24,
+ 0x7e, 0x92, 0xfb, 0x82, 0xfb, 0x89, 0x30, 0x95, 0x0d, 0xeb, 0xaf, 0xb8, 0xa0, 0xb5, 0xf5, 0x73,
+ 0x37, 0xe0, 0xe7, 0x23, 0x77, 0x82, 0xcd, 0xd7, 0x7a, 0x09, 0x64, 0xd1, 0x84, 0xf6, 0x74, 0xa1,
+ 0x7b, 0x95, 0x1b, 0x07, 0x94, 0x96, 0x75, 0x89, 0x68, 0x58, 0x49, 0xad, 0x6c, 0xb2, 0x4c, 0x7c,
+ 0x38, 0xaa, 0x44, 0x3c, 0x9b, 0x1c, 0x8b, 0x2e, 0x27, 0x64, 0x6d, 0x5d, 0x6a, 0xc6, 0xc3, 0x3a,
+ 0xab, 0xfc, 0x49, 0x67, 0xe2, 0x70, 0x2c, 0x1d, 0x0a, 0x87, 0x50, 0x4d, 0xcd, 0x89, 0xc8, 0xe8,
+ 0x55, 0x46, 0x6b, 0xf4, 0x95, 0xe0, 0x96, 0xf1, 0xa5, 0xe4, 0x24, 0xf4, 0xbb, 0xa8, 0xf1, 0xa7,
+ 0xca, 0xbb, 0xf8, 0x80, 0xa6, 0x0b, 0x47, 0x61, 0x9f, 0x1d, 0x32, 0x17, 0xdf, 0x39, 0xd2, 0x5e,
+ 0x34, 0xca, 0x63, 0xb9, 0x14, 0xb9, 0x79, 0x49, 0xc7, 0xea, 0xc0, 0x92, 0xd5, 0x4f, 0xf4, 0x50,
+ 0x2c, 0x96, 0xb1, 0x64, 0x3e, 0xee, 0x7a, 0x9d, 0x4e, 0xa3, 0xe4, 0xc2, 0x3c, 0x3e, 0x49, 0x9a,
+ 0xc8, 0x2a, 0xd1, 0x35, 0x16, 0x49, 0xb9, 0xf9, 0x89, 0x06, 0x33, 0x9f, 0x8f, 0x36, 0x9d, 0x6f,
+ 0x39, 0xfd, 0xab, 0xf0, 0x7f, 0xb8, 0x78, 0x55, 0xa0, 0x2a, 0x60, 0x0a, 0x64, 0xa3, 0x13, 0x72,
+ 0x4c, 0x6e, 0x8a, 0x0f, 0xd9, 0x3b, 0x6b, 0xf7, 0x1e, 0x93, 0xa8, 0xf8, 0xe6, 0x6c, 0x74, 0x3e,
+ 0xa5, 0x3f, 0x2f, 0x96, 0x05, 0xdd, 0x2e, 0x41, 0x40, 0x31, 0x0f, 0x34, 0x27, 0x6a, 0x7f, 0x7a,
+ 0xd2, 0x68, 0x1c, 0x8f, 0x65, 0x1c, 0x31, 0xc6, 0x4b, 0x48, 0xa5, 0x9f, 0xd8, 0x3c, 0xc5, 0x5b,
+ 0x59, 0xe3, 0x58, 0xdd, 0x5a, 0xcd, 0xf8, 0x11, 0x8d, 0x4c, 0x65, 0x9b, 0x8b, 0x6b, 0x65, 0xc2,
+ 0x2c, 0x10, 0x3b, 0x4c, 0xab, 0x60, 0xb0, 0x99, 0xd5, 0xe9, 0x88, 0x58, 0x2d, 0x5d, 0x22, 0x71,
+ 0xfe, 0x04, 0xb1, 0x25, 0x95, 0xb5, 0x1e, 0xf4, 0x53, 0xa9, 0x5c, 0x4e, 0xd3, 0x98, 0x03, 0x33,
+ 0xfa, 0xb5, 0xaf, 0x42, 0xc3, 0x56, 0x9a, 0x14, 0x33, 0x49, 0xe2, 0x10, 0x44, 0x15, 0x39, 0xf2,
+ 0x5b, 0x7d, 0x32, 0xf1, 0x8f, 0x76, 0xf8, 0x9d, 0x24, 0x96, 0xf6, 0x58, 0x88, 0xcc, 0x11, 0x1d,
+ 0x12, 0x73, 0x12, 0x4e, 0x5a, 0xfd, 0xe4, 0x13, 0x27, 0x63, 0x12, 0xb0, 0xa8, 0x9b, 0x9c, 0x71,
+ 0x3c, 0x97, 0xe2, 0x71, 0x23, 0x63, 0xce, 0x55, 0x67, 0xcc, 0x97, 0x20, 0x76, 0x51, 0xee, 0xcb,
+ 0x7f, 0x76, 0xec, 0xc5, 0x85, 0xbf, 0x4f, 0xe2, 0x70, 0xc2, 0xcd, 0x81, 0x9b, 0xfe, 0x58, 0x46,
+ 0xda, 0xce, 0xf2, 0xb2, 0x85, 0xfc, 0x4e, 0xf2, 0xe9, 0x25, 0xe7, 0xea, 0xba, 0xe7, 0xf8, 0xbe,
+ 0xe6, 0xeb, 0x33, 0xcf, 0xa7, 0xce, 0xb6, 0xe2, 0x6d, 0x12, 0x4c, 0x01, 0xad, 0xe7, 0x83, 0xf8,
+ 0x80, 0x49, 0x8e, 0x3e, 0xa6, 0xa6, 0x12, 0x48, 0x64, 0x4c, 0xff, 0xd3, 0x6b, 0x1c, 0xad, 0x09,
+ 0xe0, 0xb6, 0xdd, 0x20, 0x52, 0xe9, 0xc7, 0x1d, 0x35, 0x8e, 0xab, 0x15, 0x11, 0x44, 0xa5, 0x0b,
+ 0x59, 0xb5, 0x27, 0xe0, 0x72, 0x03, 0xe3, 0xae, 0xb6, 0xe3, 0x63, 0x93, 0xe3, 0xa9, 0x7f, 0x7c,
+ 0xd2, 0x75, 0xa7, 0xe1, 0x7a, 0xed, 0xf5, 0xda, 0x0f, 0x6b, 0x2f, 0xd7, 0x32, 0xdb, 0xac, 0xdf,
+ 0xd0, 0x85, 0xee, 0x15, 0xed, 0x29, 0x0f, 0xd9, 0xf9, 0x12, 0x0c, 0x4f, 0x66, 0x1b, 0x1b, 0x18,
+ 0x14, 0x1d, 0xa2, 0xfd, 0x1a, 0x09, 0x95, 0xf7, 0xef, 0x88, 0x37, 0xea, 0xd9, 0x10, 0x81, 0x0c,
+ 0x43, 0xf6, 0xab, 0x8d, 0xe8, 0xbe, 0x86, 0x0a, 0xbc, 0x84, 0x87, 0x81, 0x28, 0x90, 0xd9, 0x03,
+ 0x27, 0x95, 0x4a, 0xeb, 0x92, 0x23, 0x16, 0x4b, 0x6f, 0x08, 0x47, 0x8f, 0x1c, 0x3d, 0xb2, 0xe5,
+ 0x75, 0x48, 0x4c, 0x5e, 0xad, 0xf4, 0x15, 0x27, 0xe5, 0x72, 0x36, 0xaa, 0xdc, 0x6c, 0x9c, 0x20,
+ 0xec, 0x91, 0x63, 0x79, 0x80, 0xf8, 0x16, 0x6f, 0xdd, 0x70, 0x2e, 0xf9, 0x57, 0x15, 0x72, 0xfa,
+ 0x7f, 0xf6, 0xd1, 0x1f, 0xec, 0xfb, 0xe9, 0x9d, 0xd6, 0xe3, 0x9b, 0xa7, 0x87, 0xf5, 0x7e, 0x29,
+ 0xd3, 0x82, 0xea, 0x33, 0x14, 0x24, 0xd0, 0xc5, 0xac, 0xa5, 0xf6, 0x93, 0x1e, 0x3d, 0x62, 0xc9,
+ 0xe0, 0xe9, 0xac, 0x37, 0x09, 0x2f, 0x6f, 0x5a, 0x89, 0xdf, 0xd3, 0x92, 0x36, 0xfc, 0x52, 0xf9,
+ 0x89, 0x7b, 0xc3, 0x39, 0x12, 0x59, 0xcc, 0xa7, 0x54, 0x64, 0x42, 0xa2, 0x99, 0xe5, 0x55, 0xb4,
+ 0x31, 0xd0, 0xfd, 0x8b, 0x2c, 0xde, 0x54, 0xbd, 0x9c, 0x76, 0xc3, 0x55, 0x9a, 0xd9, 0xd7, 0xfa,
+ 0x9d, 0xb8, 0x63, 0xc9, 0x31, 0x6d, 0x36, 0x6f, 0xaa, 0xb7, 0x14, 0x8f, 0x55, 0x2d, 0xc1, 0x0e,
+ 0xa3, 0x3b, 0x40, 0x8f, 0x0a, 0xf1, 0x65, 0xaf, 0x74, 0x95, 0x72, 0x08, 0xb8, 0xf9, 0x91, 0x60,
+ 0xee, 0x31, 0x30, 0x15, 0x40, 0xa9, 0xad, 0x86, 0x9e, 0xa7, 0xac, 0x52, 0xa5, 0x0e, 0x06, 0x4c,
+ 0x7c, 0xa6, 0x75, 0xb4, 0x2c, 0xe4, 0x92, 0xd8, 0x3e, 0xa6, 0x61, 0x13, 0x8e, 0x4c, 0x37, 0xe1,
+ 0x02, 0xb9, 0xa3, 0xa8, 0xc9, 0x66, 0xfc, 0xf8, 0x3e, 0x39, 0x0d, 0xeb, 0x4d, 0xc7, 0x12, 0x91,
+ 0x4c, 0xc2, 0x4b, 0x35, 0xea, 0x44, 0x5e, 0xef, 0xb7, 0x71, 0x1f, 0xc3, 0xb8, 0x21, 0xdf, 0x39,
+ 0xc0, 0xb0, 0xdf, 0xc0, 0x89, 0x8b, 0x27, 0x92, 0xfb, 0x9a, 0x1a, 0xc3, 0xf2, 0x04, 0x77, 0x29,
+ 0x62, 0x2b, 0x22, 0xea, 0xf3, 0x15, 0x9b, 0xdc, 0x28, 0xcd, 0xba, 0xea, 0x71, 0x03, 0xf8, 0x3e,
+ 0x90, 0x51, 0x0b, 0x59, 0x83, 0xee, 0xa7, 0xaf, 0x74, 0x91, 0x9b, 0x98, 0xc8, 0x3f, 0xfd, 0x2d,
+ 0xe7, 0x2a, 0xea, 0xcf, 0x6a, 0x36, 0x10, 0x33, 0x7f, 0x30, 0x07, 0x4e, 0xbd, 0x15, 0xc7, 0x3b,
+ 0x70, 0xfe, 0xd5, 0x92, 0x36, 0x63, 0xc8, 0x10, 0x1f, 0x4d, 0x71, 0x15, 0x71, 0xb5, 0x68, 0x64,
+ 0x9a, 0x38, 0x1c, 0x52, 0x6f, 0x19, 0xbc, 0x26, 0x3d, 0x8a, 0xec, 0x4e, 0xc3, 0x44, 0x09, 0xa6,
+ 0xd6, 0x2c, 0xc0, 0x9a, 0x43, 0xc3, 0xea, 0xfd, 0x9e, 0xb9, 0x32, 0xf9, 0x74, 0xa0, 0x79, 0xc2,
+ 0xa1, 0x6a, 0x09, 0x3d, 0x04, 0x57, 0xdd, 0xf2, 0x98, 0xfc, 0xf9, 0x5f, 0x07, 0x1e, 0x09, 0x87,
+ 0xd3, 0xbf, 0x2a, 0x83, 0x7a, 0x47, 0x5d, 0x81, 0x8b, 0xb3, 0x8a, 0x68, 0x8b, 0xb4, 0x91, 0xa2,
+ 0xf1, 0xff, 0xf2, 0xc0, 0x12, 0x78, 0x79, 0x8d, 0xbf, 0x37, 0xcc, 0xf2, 0x9b, 0x0a, 0x2f, 0xdb,
+ 0xe8, 0xcd, 0x1e, 0x20, 0xbe, 0x03, 0x2f, 0x8d, 0x04, 0xf4, 0x08, 0xa2, 0x21, 0x7b, 0x75, 0xb2,
+ 0x10, 0x9f, 0x28, 0x79, 0x3d, 0x5a, 0xab, 0x5e, 0xde, 0x57, 0xc7, 0x89, 0x82, 0xf2, 0x99, 0xf1,
+ 0xbc, 0x1a, 0xe7, 0xe2, 0x7a, 0x5d, 0x7a, 0xbd, 0x01, 0x9a, 0x4b, 0xdc, 0x3e, 0x58, 0xb4, 0xe7,
+ 0x95, 0x65, 0x2a, 0x8b, 0x37, 0x33, 0x23, 0xb6, 0x64, 0x37, 0x91, 0x10, 0xb9, 0x87, 0xbe, 0xcc,
+ 0xf2, 0x0e, 0x39, 0x32, 0x78, 0xac, 0xdb, 0x94, 0x47, 0x2a, 0x4f, 0xda, 0x0d, 0xac, 0x62, 0x65,
+ 0xd2, 0xec, 0xc8, 0xc3, 0xc6, 0x34, 0x44, 0xf6, 0x3d, 0x1a, 0xef, 0x0b, 0x5a, 0x73, 0x36, 0xa4,
+ 0xbd, 0x03, 0x6b, 0x5c, 0x29, 0x2f, 0x59, 0x7e, 0x69, 0x93, 0x4b, 0x47, 0xb7, 0x0b, 0xbc, 0x2c,
+ 0xbf, 0x1d, 0x7c, 0x90, 0xee, 0x75, 0xb7, 0xc8, 0x1b, 0x62, 0x3a, 0xba, 0xe2, 0x11, 0xc6, 0xea,
+ 0xec, 0xdd, 0xf6, 0x5f, 0xcc, 0x46, 0xe3, 0x0f, 0x85, 0x52, 0xd4, 0x3b, 0x32, 0xf8, 0x4a, 0x5d,
+ 0x6d, 0x2e, 0xd4, 0x6d, 0xbf, 0xdb, 0x3b, 0xb2, 0x60, 0x25, 0xbc, 0x74, 0x2c, 0x11, 0x2f, 0x36,
+ 0xb1, 0x11, 0xb7, 0x64, 0x68, 0x9e, 0x1a, 0xbc, 0x24, 0x3a, 0x96, 0xc4, 0x67, 0xb7, 0x88, 0x8e,
+ 0xba, 0xe5, 0x5c, 0xf6, 0x25, 0x2d, 0x19, 0x3d, 0x52, 0x08, 0x13, 0xc0, 0xe1, 0x03, 0x53, 0x8f,
+ 0x96, 0x65, 0x82, 0x0a, 0x28, 0x92, 0xf7, 0x3e, 0xd8, 0x0f, 0xb6, 0x6b, 0x90, 0xc6, 0x96, 0xd3,
+ 0xc3, 0x55, 0x81, 0x51, 0x41, 0xf1, 0x9a, 0x15, 0xaa, 0xb3, 0xb1, 0x1a, 0x81, 0xa1, 0x43, 0xff,
+ 0x0c, 0x57, 0xba, 0xb0, 0x57, 0xa7, 0x18, 0x5f, 0xd9, 0xc4, 0xe3, 0xb9, 0x06, 0x0a, 0x5e, 0x40,
+ 0x24, 0xbe, 0x13, 0xea, 0x63, 0x30, 0x1f, 0x5d, 0x6a, 0xf7, 0xc1, 0x74, 0xd2, 0xde, 0x00, 0x9e,
+ 0xd8, 0x54, 0xf5, 0xb4, 0xef, 0x5f, 0xcc, 0x3d, 0x46, 0x95, 0x43, 0x8b, 0x1a, 0x4b, 0x34, 0xcf,
+ 0xa7, 0xf4, 0xf7, 0xae, 0xdd, 0xc0, 0x30, 0x20, 0x5a, 0x6b, 0xb9, 0xee, 0x85, 0x67, 0x46, 0xb3,
+ 0x54, 0xf9, 0xef, 0x30, 0x7b, 0x51, 0x1c, 0x8d, 0x60, 0xcf, 0xb0, 0x59, 0xf0, 0x65, 0x2d, 0x72,
+ 0x44, 0x0c, 0x87, 0xbe, 0xf4, 0x0c, 0xd9, 0x9f, 0x5c, 0x3c, 0x68, 0xbb, 0x30, 0xbb, 0xc0, 0x7f,
+ 0x15, 0xff, 0xba, 0x28, 0xa2, 0x45, 0x4c, 0xcc, 0x72, 0x55, 0x7c, 0x76, 0xcb, 0xcb, 0x6a, 0x60,
+ 0xc9, 0xe1, 0xd6, 0x04, 0xfc, 0x58, 0x12, 0x93, 0x10, 0x7b, 0x19, 0x63, 0xc8, 0xa0, 0x6c, 0x4e,
+ 0x34, 0x2d, 0x5c, 0x0b, 0x3b, 0x62, 0xcc, 0x5e, 0xc2, 0x0f, 0xdc, 0x48, 0xe9, 0x9f, 0xf8, 0x78,
+ 0x47, 0x3a, 0xe4, 0x93, 0xa9, 0xbd, 0x55, 0xb8, 0xc9, 0x2a, 0xd5, 0xc7, 0xfe, 0xbe, 0xf5, 0xeb,
+ 0x7d, 0x6c, 0x09, 0x57, 0xa6, 0x30, 0xd3, 0x4c, 0xac, 0x78, 0x6f, 0x58, 0xef, 0x13, 0x30, 0x0c,
+ 0x54, 0x36, 0x5a, 0xec, 0xf9, 0x30, 0x6b, 0xa9, 0xcf, 0x4c, 0xaf, 0x71, 0x16, 0xf8, 0xdf, 0xe4,
+ 0x53, 0x39, 0x96, 0xa1, 0x6d, 0x62, 0x99, 0xbe, 0xb2, 0x08, 0x1f, 0x85, 0x26, 0x8d, 0xe8, 0xcf,
+ 0xe1, 0xb7, 0xef, 0x6b, 0x2a, 0xc9, 0x2c, 0x0f, 0xa4, 0xf5, 0x72, 0x80, 0x8c, 0x85, 0x26, 0x6e,
+ 0x91, 0xb4, 0xd8, 0x01, 0x58, 0xc7, 0x48, 0x51, 0x27, 0x4f, 0xf1, 0x36, 0x91, 0x0c, 0xdd, 0xb3,
+ 0x87, 0x67, 0x55, 0xa4, 0x92, 0x55, 0x21, 0xb5, 0xf7, 0x44, 0xf9, 0xad, 0x39, 0xe4, 0xf2, 0xb3,
+ 0xc8, 0x81, 0x66, 0x89, 0x5c, 0xde, 0x1b, 0x3e, 0x48, 0x62, 0xfb, 0xd1, 0xd9, 0x28, 0x7f, 0x2d,
+ 0xfe, 0xb1, 0x2e, 0x26, 0x19, 0x24, 0x4f, 0xc3, 0x66, 0x00, 0x41, 0x4f, 0xb0, 0x4f, 0xb7, 0xc6,
+ 0x55, 0xcd, 0xc2, 0xea, 0x0d, 0xf8, 0x07, 0x28, 0xc7, 0x62, 0x12, 0xf2, 0xb1, 0x73, 0x24, 0x3a,
+ 0x3c, 0xf0, 0xda, 0x8c, 0x9b, 0xbc, 0x82, 0xf3, 0x58, 0x65, 0xe7, 0xa1, 0xad, 0x0b, 0x60, 0x17,
+ 0x2e, 0xf3, 0xf3, 0x78, 0x44, 0xd3, 0x1a, 0x6e, 0x4e, 0x9c, 0xf8, 0x9f, 0x77, 0x60, 0x2d, 0xf7,
+ 0x8a, 0xeb, 0x52, 0x6a, 0xd0, 0x40, 0xf9, 0xc0, 0x2f, 0xd1, 0x23, 0xb6, 0xe6, 0x53, 0x13, 0x24,
+ 0x6a, 0x9d, 0xf1, 0xe8, 0xe3, 0x14, 0x96, 0x65, 0xd1, 0xfa, 0x27, 0x20, 0x22, 0xab, 0x32, 0x8b,
+ 0xf1, 0x7d, 0x09, 0x3c, 0xb9, 0x25, 0x73, 0xaf, 0x42, 0xc6, 0x8d, 0xd1, 0xa2, 0x11, 0xde, 0xa5,
+ 0x76, 0x7f, 0x5a, 0xbb, 0x81, 0x45, 0xa0, 0x66, 0x41, 0xb5, 0x96, 0x9b, 0x1c, 0xbb, 0x4f, 0x5c,
+ 0xbc, 0x5d, 0x63, 0x2d, 0x81, 0x4d, 0xb8, 0x24, 0xeb, 0xe3, 0x8a, 0xaa, 0xc0, 0xb6, 0x8e, 0x97,
+ 0x13, 0x32, 0xf4, 0x63, 0xbb, 0x01, 0xbd, 0x79, 0x99, 0x82, 0x54, 0x62, 0x6a, 0x96, 0xf6, 0x13,
+ 0xc2, 0x66, 0xb1, 0x3c, 0x22, 0x4f, 0x24, 0x89, 0x8b, 0xdf, 0xa6, 0x1d, 0x88, 0x5f, 0x0c, 0xff,
+ 0xc7, 0xf0, 0xfc, 0x42, 0x94, 0x37, 0xf3, 0x67, 0x35, 0x59, 0x8c, 0x4d, 0x6e, 0xc5, 0xc3, 0x7e,
+ 0xb6, 0x45, 0xba, 0x37, 0xcc, 0xfc, 0x68, 0x62, 0x29, 0xe0, 0x8f, 0x12, 0x1d, 0x6b, 0x2d, 0xf0,
+ 0xb2, 0x35, 0xff, 0x6a, 0xbb, 0x61, 0x95, 0xf8, 0xf5, 0xbe, 0x44, 0x3e, 0x1b, 0x24, 0xab, 0xe7,
+ 0x35, 0x69, 0xec, 0xb6, 0x33, 0x54, 0xbd, 0x98, 0xc5, 0xa9, 0x7f, 0xe7, 0xf1, 0x11, 0x6e, 0x22,
+ 0xe7, 0xfe, 0xe2, 0xc3, 0x85, 0xb7, 0x3d, 0xe7, 0xa6, 0xba, 0xf6, 0xd3, 0xa1, 0xa0, 0xc5, 0xc4,
+ 0xa6, 0xa3, 0x7a, 0x8c, 0x37, 0x36, 0x21, 0x81, 0x8a, 0x7b, 0x48, 0xd6, 0xb8, 0x05, 0x5a, 0xb3,
+ 0xd0, 0xcb, 0x05, 0x45, 0x08, 0xc8, 0x85, 0xf9, 0x29, 0xd2, 0xa8, 0xb0, 0xf3, 0xb4, 0xcf, 0x35,
+ 0x0e, 0x56, 0x67, 0x4e, 0x63, 0xf5, 0x16, 0xf3, 0x58, 0xb0, 0xb9, 0x90, 0xea, 0x69, 0xdd, 0x29,
+ 0x1b, 0xb7, 0x30, 0x4c, 0xfa, 0x59, 0x9d, 0x37, 0x0a, 0x5d, 0xa1, 0xfd, 0x02, 0x9a, 0x0e, 0x1a,
+ 0x76, 0x3b, 0x8f, 0x28, 0x60, 0xbc, 0xd4, 0x46, 0x51, 0xed, 0x86, 0xa3, 0x47, 0x66, 0x3c, 0x13,
+ 0x59, 0x16, 0x75, 0x8d, 0x04, 0x31, 0xa3, 0x6e, 0x54, 0xe0, 0xe2, 0x5b, 0xde, 0x93, 0x2e, 0x8f,
+ 0x6b, 0x23, 0x10, 0xe5, 0x2f, 0xf2, 0x8a, 0x8f, 0x0d, 0xdf, 0x68, 0x24, 0xc8, 0xbc, 0x07, 0x54,
+ 0xa3, 0x94, 0x38, 0x91, 0xd6, 0xf8, 0x88, 0x97, 0xc0, 0x7c, 0x1f, 0x1f, 0x89, 0xc2, 0x9e, 0x15,
+ 0x3c, 0xf5, 0xa5, 0x86, 0x8d, 0x54, 0x8c, 0x4d, 0x21, 0x21, 0x1c, 0xce, 0xa5, 0x94, 0x7f, 0x73,
+ 0xe0, 0xc8, 0xfb, 0x6e, 0x05, 0xab, 0xc0, 0x72, 0xf0, 0x97, 0x6b, 0xfb, 0x02, 0xf0, 0xa0, 0xac,
+ 0xfe, 0x6f, 0xae, 0xff, 0xd9, 0x48, 0x9d, 0x6d, 0x3f, 0x52, 0xa9, 0xd6, 0xa0, 0xb7, 0xfe, 0xb9,
+ 0xd4, 0x5a, 0x56, 0xa2, 0xb3, 0x5d, 0x38, 0x99, 0x9f, 0x16, 0x65, 0x61, 0x88, 0xc5, 0x5d, 0x60,
+ 0x94, 0x4b, 0xc5, 0x64, 0xc4, 0xc5, 0xca, 0xa9, 0xb5, 0xd3, 0x29, 0xa4, 0x20, 0xed, 0x5d, 0xc1,
+ 0x1e, 0x84, 0xcc, 0xb6, 0xb6, 0x6b, 0x05, 0xc8, 0xfd, 0xaa, 0xc0, 0x4f, 0x03, 0xda, 0x7e, 0x06,
+ 0x4c, 0x40, 0x2c, 0x8e, 0x5b, 0x3a, 0xf3, 0x35, 0x62, 0x7d, 0x4f, 0x61, 0x9d, 0x4d, 0x2b, 0x97,
+ 0x8a, 0x5d, 0xec, 0xc9, 0x9f, 0xda, 0x76, 0x1e, 0x5b, 0xa0, 0xe6, 0x1c, 0xb1, 0xdf, 0xc0, 0x14,
+ 0x60, 0x19, 0xf9, 0x48, 0x4a, 0xfe, 0x9c, 0x65, 0xdd, 0x30, 0x9f, 0x72, 0x2e, 0xb4, 0xe2, 0xf9,
+ 0xc5, 0xec, 0xa1, 0x3b, 0x8f, 0xf8, 0x87, 0x42, 0xb7, 0xad, 0x9d, 0x76, 0xf9, 0x0e, 0xd9, 0x59,
+ 0x75, 0x0e, 0xd8, 0x59, 0xd5, 0xd7, 0x87, 0x86, 0xf0, 0x51, 0x7b, 0x47, 0x7c, 0x1f, 0x62, 0x2d,
+ 0xfd, 0xc9, 0xf9, 0xb8, 0xf2, 0x54, 0x34, 0x07, 0x9c, 0x61, 0xbc, 0x24, 0x77, 0x5b, 0xee, 0x71,
+ 0xb1, 0x3b, 0x91, 0x68, 0x3e, 0x17, 0x64, 0xb8, 0x18, 0x54, 0x42, 0x94, 0xaa, 0xf5, 0x52, 0x43,
+ 0x38, 0xe8, 0x48, 0x1f, 0x4e, 0x84, 0xe9, 0x3c, 0x12, 0xe6, 0xc3, 0xee, 0x8d, 0x97, 0xaf, 0xe7,
+ 0xa7, 0xbd, 0x4e, 0x0f, 0x9b, 0x82, 0xa3, 0xa9, 0x52, 0x4b, 0x52, 0x8e, 0x18, 0xe6, 0xb8, 0x18,
+ 0x5f, 0xa9, 0x95, 0xb7, 0x74, 0x28, 0x93, 0xd5, 0x9e, 0xda, 0x22, 0xed, 0x95, 0x99, 0x4f, 0xa1,
+ 0xca, 0xad, 0xe5, 0x08, 0xbf, 0x3d, 0x91, 0xed, 0xb6, 0xef, 0xa4, 0x87, 0xa1, 0x01, 0x79, 0x5a,
+ 0xab, 0xd6, 0x7a, 0x59, 0x67, 0xbb, 0x18, 0x7f, 0xf4, 0xf6, 0xfa, 0x78, 0x87, 0xd6, 0x5b, 0x85,
+ 0x04, 0x62, 0x06, 0x88, 0xb9, 0xd0, 0xb9, 0xc0, 0x78, 0xa6, 0x58, 0x7e, 0x78, 0x1e, 0x61, 0x5a,
+ 0x13, 0x45, 0x35, 0xfd, 0x4a, 0x97, 0x72, 0xef, 0xd0, 0xa1, 0xc0, 0xc5, 0x4d, 0x81, 0xdb, 0x81,
+ 0xea, 0x3b, 0x51, 0xbe, 0x2d, 0xfd, 0x34, 0xf4, 0x87, 0x31, 0x44, 0x6b, 0x4c, 0xb7, 0x5a, 0x88,
+ 0xbd, 0xd1, 0xd6, 0xb2, 0xce, 0x76, 0xd1, 0x0c, 0x1e, 0xd3, 0xa3, 0x31, 0x74, 0x59, 0x3c, 0xe9,
+ 0x55, 0xde, 0x69, 0x93, 0x9b, 0x0b, 0x52, 0x9b, 0x03, 0xa9, 0xcc, 0x4c, 0x48, 0xd0, 0x52, 0x93,
+ 0xc6, 0xbb, 0xbd, 0x5c, 0x9c, 0x71, 0xb2, 0x5a, 0x32, 0xba, 0xb4, 0xd1, 0xa6, 0xa1, 0xa3, 0x89,
+ 0x67, 0xf6, 0x1a, 0x9d, 0x9b, 0x7b, 0xef, 0xb4, 0x55, 0xf1, 0xcd, 0x73, 0xa1, 0xa6, 0x32, 0xfe,
+ 0x77, 0x29, 0x75, 0xd6, 0x6e, 0x79, 0x7d, 0x65, 0xf0, 0x95, 0x2a, 0x49, 0xcd, 0xb7, 0x05, 0xd8,
+ 0x41, 0xf5, 0x33, 0x1f, 0xcd, 0x6f, 0x39, 0xc3, 0xf9, 0x6a, 0xcf, 0x1e, 0x67, 0x53, 0x67, 0xab,
+ 0xcc, 0x4b, 0xc8, 0x03, 0xad, 0x7b, 0x6f, 0xeb, 0xbb, 0xed, 0xe5, 0xcf, 0xd9, 0xbb, 0xf5, 0xb8,
+ 0xb5, 0x9e, 0x5a, 0x67, 0x6d, 0x46, 0xc3, 0x4b, 0x64, 0x90, 0xc1, 0xaf, 0x16, 0x49, 0xe1, 0x23,
+ 0xbc, 0x1b, 0x53, 0xc1, 0xfb, 0x50, 0x90, 0x67, 0xc8, 0x8e, 0x68, 0xbb, 0x0d, 0x2e, 0xd7, 0xd2,
+ 0x7e, 0xbb, 0xd0, 0x83, 0x60, 0xcb, 0xbd, 0x68, 0xb8, 0x2d, 0xe9, 0xc8, 0xf8, 0x64, 0x05, 0xc9,
+ 0x37, 0x9f, 0xea, 0xb6, 0x6b, 0x75, 0xd1, 0xa2, 0x91, 0x8b, 0x53, 0xab, 0x92, 0x66, 0x7a, 0xf4,
+ 0x1a, 0xff, 0x75, 0xaf, 0xfa, 0x44, 0x53, 0xc4, 0x8e, 0x52, 0xa9, 0x4c, 0x20, 0xe3, 0x93, 0x0e,
+ 0x61, 0x42, 0xd9, 0xbd, 0xe1, 0x07, 0x22, 0x8b, 0x4b, 0x73, 0x62, 0x5d, 0x51, 0x2f, 0x20, 0x9e,
+ 0x96, 0xfc, 0x6e, 0x72, 0xdf, 0x31, 0x99, 0x25, 0xb1, 0x67, 0x2d, 0xab, 0xa2, 0xef, 0xd2, 0xd1,
+ 0x54, 0xf4, 0xe5, 0xd3, 0xac, 0xaf, 0x37, 0x8c, 0x04, 0x69, 0xc6, 0x30, 0x6b, 0xae, 0x58, 0x93,
+ 0x3f, 0x68, 0x83, 0x56, 0x54, 0x4f, 0x0d, 0x37, 0x4e, 0xc1, 0x91, 0x6b, 0x11, 0x0b, 0x88, 0x77,
+ 0xc4, 0x6c, 0x38, 0x54, 0x19, 0x71, 0x73, 0xf4, 0x48, 0x3a, 0x4a, 0x7f, 0xdb, 0xf6, 0x55, 0x4d,
+ 0x7d, 0xaa, 0xdd, 0x90, 0xca, 0xa3, 0xe3, 0xaa, 0x02, 0x8b, 0xba, 0x0c, 0xa2, 0x3a, 0x2d, 0x14,
+ 0xfd, 0x25, 0x75, 0x76, 0xd8, 0xd0, 0x85, 0x2c, 0x4f, 0xa4, 0x9a, 0x44, 0xf4, 0x22, 0xea, 0xd9,
+ 0xca, 0xfd, 0x63, 0x35, 0xf0, 0x09, 0xa2, 0xe3, 0x12, 0x45, 0x95, 0x90, 0x35, 0xce, 0x14, 0xd8,
+ 0x10, 0x39, 0xfe, 0x74, 0xf8, 0x12, 0xe1, 0x65, 0x4d, 0xc2, 0x91, 0x61, 0x31, 0x06, 0x4f, 0x2c,
+ 0xdb, 0xf1, 0xa2, 0xfe, 0xb3, 0x57, 0xc6, 0xb5, 0x1e, 0xc2, 0x33, 0xe1, 0x7e, 0xaf, 0x36, 0x9b,
+ 0xd1, 0xe3, 0xf2, 0xb1, 0x6c, 0x6c, 0x0c, 0x3a, 0x56, 0x1e, 0x86, 0x17, 0xa7, 0x60, 0xc1, 0xb0,
+ 0x17, 0xa3, 0x34, 0x8b, 0x88, 0x88, 0xfb, 0x81, 0x08, 0x7b, 0x2d, 0x8c, 0x4d, 0xf5, 0x62, 0xf6,
+ 0xe5, 0x5e, 0xb8, 0xa9, 0x60, 0xd5, 0xaf, 0xba, 0xa1, 0x57, 0x76, 0xc6, 0x99, 0x31, 0x2d, 0x80,
+ 0x6e, 0x01, 0x54, 0x70, 0x46, 0x82, 0xe5, 0x33, 0x9a, 0x0a, 0x4a, 0x52, 0x8b, 0xf9, 0xe8, 0x41,
+ 0x04, 0x53, 0xd2, 0xd7, 0x7a, 0xd2, 0xc5, 0x90, 0x09, 0x2b, 0x9e, 0x72, 0xd5, 0x0f, 0xd4, 0x8b,
+ 0x14, 0xc4, 0x45, 0x26, 0x3b, 0xd5, 0xab, 0xf5, 0x62, 0x27, 0x64, 0x4c, 0x9d, 0xc0, 0xe9, 0xea,
+ 0xa5, 0x04, 0x92, 0x86, 0x9a, 0x0e, 0x08, 0x98, 0x22, 0x64, 0x8c, 0x5a, 0xa4, 0x0b, 0x02, 0x26,
+ 0x5a, 0x66, 0x7f, 0x17, 0x49, 0x3d, 0xc8, 0xe3, 0xfa, 0xc0, 0x49, 0xec, 0x03, 0xbb, 0xd2, 0x55,
+ 0xda, 0xf3, 0x8c, 0xf9, 0x22, 0xd5, 0xd2, 0xbc, 0xe0, 0x8d, 0x2f, 0x84, 0x1f, 0xf1, 0x90, 0x4b,
+ 0x62, 0xfb, 0xb3, 0xd5, 0x19, 0xc5, 0x6f, 0x55, 0x9f, 0x6f, 0xaa, 0xb7, 0x85, 0xd6, 0xe3, 0x69,
+ 0x37, 0x8c, 0x6c, 0xc9, 0xe8, 0xad, 0xf7, 0xf5, 0x86, 0x6c, 0x28, 0x96, 0xb7, 0xa3, 0x7e, 0x12,
+ 0x75, 0x46, 0x84, 0xea, 0x0c, 0x93, 0x6f, 0x6c, 0x95, 0xbb, 0x53, 0x01, 0x65, 0x8b, 0x1e, 0x79,
+ 0x44, 0xce, 0xe8, 0x73, 0xfd, 0xcd, 0x1e, 0xb9, 0xa9, 0xcc, 0x60, 0x06, 0x92, 0x72, 0xa7, 0x8a,
+ 0x80, 0x82, 0xf1, 0xa4, 0xb5, 0x73, 0xa2, 0xfd, 0x1d, 0x99, 0xca, 0x53, 0x73, 0x10, 0x69, 0x54,
+ 0x4b, 0xda, 0x1b, 0x3a, 0x4f, 0x3b, 0x46, 0xf0, 0xb9, 0xb5, 0x32, 0xd8, 0x17, 0x60, 0x7d, 0x24,
+ 0x3e, 0xb9, 0xd4, 0x66, 0xc2, 0xae, 0x44, 0x04, 0x7a, 0xe3, 0xc9, 0x39, 0x55, 0x67, 0xb4, 0xff,
+ 0xce, 0xd0, 0xb1, 0x40, 0xac, 0x71, 0x8b, 0x0c, 0x2c, 0x85, 0xbe, 0x4a, 0x33, 0x12, 0x6c, 0x91,
+ 0x72, 0x62, 0x24, 0x15, 0x49, 0x55, 0x4b, 0xf0, 0x85, 0xc9, 0xdd, 0x8b, 0x47, 0x52, 0x14, 0x91,
+ 0x1e, 0x6a, 0x8a, 0xe7, 0x44, 0x65, 0xb7, 0xd7, 0xbd, 0x61, 0x2e, 0x6e, 0xac, 0x88, 0x90, 0x4c,
+ 0x34, 0x9b, 0xc9, 0xb9, 0x3f, 0x4f, 0x3d, 0x17, 0x6a, 0x92, 0xd6, 0xb4, 0x4f, 0x6a, 0x21, 0xef,
+ 0x55, 0xdc, 0xc3, 0x09, 0x5d, 0xcc, 0x30, 0x9e, 0xec, 0x3e, 0x5a, 0xa4, 0x64, 0x51, 0xef, 0xd7,
+ 0x95, 0xae, 0x67, 0x02, 0xab, 0x84, 0x39, 0x96, 0x58, 0xf5, 0x84, 0xdd, 0x66, 0x5f, 0x56, 0x99,
+ 0xbe, 0x56, 0x9e, 0xa0, 0x87, 0x47, 0x85, 0x57, 0xe3, 0xeb, 0x5e, 0xcc, 0xcd, 0xfb, 0x87, 0x92,
+ 0x3d, 0x28, 0x2f, 0x97, 0xcb, 0x1e, 0xf7, 0x6c, 0xa8, 0xce, 0x36, 0x69, 0x5c, 0xac, 0x40, 0x6b,
+ 0xdc, 0x93, 0xde, 0x67, 0x02, 0x6a, 0xfd, 0x98, 0x31, 0xe0, 0x4f, 0x3c, 0x8b, 0x1f, 0xec, 0x57,
+ 0x5e, 0x1b, 0x34, 0xa8, 0x04, 0x69, 0x6a, 0xe2, 0x33, 0xf2, 0x8a, 0x66, 0x23, 0xda, 0x9d, 0x06,
+ 0x9e, 0x55, 0xb0, 0xa4, 0xea, 0x8c, 0x56, 0x27, 0x12, 0x19, 0xcf, 0x6b, 0xa7, 0xea, 0xb4, 0x5e,
+ 0xbb, 0xaf, 0x71, 0x43, 0xb6, 0xdf, 0xc6, 0x0b, 0xb6, 0x26, 0x1d, 0x0e, 0x1c, 0x78, 0x4d, 0x7d,
+ 0x35, 0x39, 0x0c, 0x24, 0x10, 0x30, 0x40, 0x5a, 0x94, 0x10, 0xcd, 0x3d, 0xb8, 0x23, 0x29, 0xcc,
+ 0x77, 0x03, 0x2f, 0xc1, 0xb7, 0x6e, 0x3b, 0x6c, 0x1f, 0xa4, 0x32, 0x1d, 0x1d, 0x15, 0xa0, 0xd7,
+ 0x94, 0xf7, 0xdf, 0xe4, 0x2a, 0x9f, 0xe6, 0x1a, 0x77, 0xd5, 0x6d, 0x91, 0xac, 0x92, 0x95, 0xdc,
+ 0x58, 0x87, 0xd4, 0x1c, 0x2f, 0xee, 0x04, 0x67, 0x3f, 0x33, 0xe3, 0xd1, 0xf6, 0x1f, 0x5d, 0x75,
+ 0x17, 0x6b, 0xa9, 0x27, 0x17, 0xa1, 0x61, 0x09, 0x2f, 0x59, 0xce, 0x07, 0xbc, 0x94, 0x81, 0x8e,
+ 0x5a, 0xf7, 0xbe, 0x0c, 0x2f, 0xbd, 0xc9, 0xf5, 0xb8, 0xe7, 0x53, 0xd9, 0x28, 0x9d, 0x7d, 0xd9,
+ 0x55, 0x3a, 0x2d, 0xb1, 0xd2, 0x97, 0x32, 0x65, 0x4b, 0x18, 0xdb, 0xf2, 0x5e, 0x75, 0xcb, 0x9f,
+ 0x1b, 0x5d, 0x27, 0x8b, 0xc9, 0xdd, 0xe3, 0x9e, 0x71, 0x7f, 0xe7, 0x7e, 0xc8, 0x83, 0x8f, 0xe4,
+ 0xc9, 0x6e, 0x59, 0x6f, 0x0d, 0x2c, 0xb5, 0xae, 0x7e, 0x3a, 0xbb, 0xee, 0x62, 0x34, 0xa3, 0xa1,
+ 0xbf, 0x1b, 0x7f, 0x73, 0xb6, 0x95, 0x58, 0x87, 0xd5, 0x40, 0xcf, 0xb8, 0x42, 0x9f, 0xce, 0xe6,
+ 0x7d, 0x83, 0x64, 0x75, 0x62, 0xa6, 0xf0, 0xdd, 0x9e, 0x5f, 0x1f, 0x4e, 0xf8, 0x13, 0xbe, 0x98,
+ 0x2f, 0x06, 0x7e, 0x3d, 0x0d, 0xaa, 0x3f, 0xdf, 0x33, 0xfe, 0x9d, 0x7b, 0x83, 0xd6, 0xf6, 0x1c,
+ 0x4b, 0x56, 0x12, 0xb3, 0x39, 0x63, 0xe6, 0x3b, 0xec, 0xdf, 0x35, 0x10, 0xfa, 0xc9, 0xf8, 0xd3,
+ 0xd0, 0x57, 0x42, 0x3a, 0xca, 0x2a, 0xd4, 0xf2, 0x98, 0x8a, 0xd4, 0x43, 0x67, 0xbe, 0x59, 0xc0,
+ 0x4c, 0x96, 0x0d, 0x31, 0x27, 0x3e, 0xf9, 0x1b, 0xf0, 0x16, 0x9d, 0x22, 0xe0, 0xe5, 0xab, 0x44,
+ 0x3e, 0x9b, 0xe2, 0xbb, 0xc3, 0x2a, 0x23, 0x56, 0xe9, 0x71, 0x7f, 0x1a, 0x0c, 0x87, 0xaa, 0x16,
+ 0x96, 0x87, 0xff, 0xab, 0xb9, 0xd4, 0x96, 0x0c, 0x16, 0xe6, 0xe8, 0x31, 0x49, 0x5b, 0xf1, 0x94,
+ 0xc6, 0x72, 0xf7, 0x7b, 0x27, 0x32, 0xa8, 0x85, 0x11, 0xa9, 0xcc, 0xd7, 0xbb, 0x80, 0xd1, 0x3a,
+ 0xe9, 0xda, 0xcd, 0xe6, 0x9b, 0xa3, 0x47, 0xd6, 0xbd, 0x11, 0x3a, 0x2d, 0xb1, 0x2e, 0x3f, 0x2d,
+ 0x71, 0x37, 0x92, 0xc9, 0x62, 0x12, 0x54, 0x30, 0x8c, 0xae, 0x75, 0xef, 0xb9, 0xe0, 0x88, 0x8e,
+ 0x66, 0xc9, 0x29, 0xa4, 0xa2, 0x5c, 0xfc, 0x5a, 0xbc, 0x2d, 0x86, 0x1c, 0xd5, 0x5b, 0x37, 0x6b,
+ 0x9c, 0x14, 0xc7, 0xe3, 0x24, 0x1c, 0x5d, 0x72, 0xae, 0xee, 0x8e, 0x90, 0x75, 0x76, 0x32, 0xae,
+ 0x40, 0xa6, 0xe1, 0xbb, 0x13, 0x7f, 0xc0, 0x41, 0x27, 0x88, 0x20, 0x73, 0x6b, 0xf5, 0x23, 0xc7,
+ 0x45, 0x7d, 0xfa, 0x3c, 0x61, 0xba, 0x08, 0xb9, 0x35, 0x37, 0xf3, 0xe8, 0x84, 0x5b, 0x88, 0xc2,
+ 0xad, 0xab, 0x6d, 0xb1, 0x9a, 0xd8, 0x73, 0x3e, 0xca, 0x8f, 0x87, 0x7f, 0x1f, 0xc4, 0x94, 0xcc,
+ 0x15, 0xcf, 0x96, 0xfe, 0x89, 0x43, 0x23, 0x41, 0x48, 0x20, 0x30, 0x08, 0x11, 0x11, 0xb3, 0x6f,
+ 0x81, 0x0f, 0xcd, 0x32, 0x0d, 0x2b, 0xe4, 0x1e, 0xef, 0x7e, 0x0f, 0x38, 0xb4, 0x15, 0x26, 0x1e,
+ 0xb0, 0x69, 0x4a, 0xa5, 0xa4, 0xe0, 0x63, 0x32, 0x34, 0x5a, 0x5a, 0xf7, 0x6a, 0xfd, 0x60, 0x85,
+ 0x0c, 0xbf, 0x1c, 0x8d, 0x53, 0xe4, 0x08, 0xd5, 0x63, 0xc8, 0x15, 0x4c, 0xc8, 0x43, 0xf6, 0xca,
+ 0xb8, 0x88, 0xe2, 0xdf, 0xd0, 0x17, 0x9c, 0xa7, 0x1e, 0x2d, 0x76, 0x88, 0xee, 0xb6, 0xe7, 0x96,
+ 0x3d, 0xb7, 0xa1, 0xe3, 0xfe, 0xc5, 0x6e, 0xfb, 0x34, 0xb9, 0xdd, 0xc2, 0x58, 0x52, 0x43, 0xf2,
+ 0xd8, 0x49, 0x17, 0xb0, 0x9b, 0xfd, 0x73, 0x94, 0x8b, 0x1f, 0xd1, 0xfa, 0xda, 0xf9, 0x17, 0xd6,
+ 0x9a, 0x4f, 0x30, 0xc5, 0x47, 0x33, 0xab, 0x67, 0x27, 0x72, 0x16, 0xe8, 0x86, 0xf5, 0x06, 0xad,
+ 0xa1, 0x10, 0xa2, 0x95, 0xa0, 0xfc, 0xcd, 0x20, 0x44, 0xfe, 0x6e, 0xa5, 0xff, 0x69, 0x5e, 0xf9,
+ 0xe8, 0x85, 0x15, 0x04, 0x6c, 0x66, 0xcd, 0x8d, 0x17, 0xd3, 0xd1, 0xe9, 0x85, 0xe9, 0x4b, 0xd3,
+ 0xcf, 0xbe, 0xf8, 0xea, 0x8b, 0x6f, 0x5d, 0xe8, 0x6e, 0xa9, 0xb3, 0x0d, 0x69, 0x9e, 0x58, 0x1e,
+ 0x7b, 0xc5, 0xd5, 0xe3, 0x5e, 0xf7, 0x8e, 0x04, 0x9b, 0x88, 0x36, 0x1d, 0x09, 0xa2, 0x72, 0x7f,
+ 0x41, 0xb8, 0x4d, 0xad, 0x25, 0x34, 0xec, 0x86, 0x58, 0x8a, 0x3e, 0xde, 0x1f, 0xa1, 0xb2, 0xb0,
+ 0x90, 0x55, 0x65, 0xb2, 0xbc, 0xbe, 0x5e, 0x34, 0xce, 0xb8, 0x29, 0x3e, 0x04, 0x99, 0x02, 0x8a,
+ 0xe6, 0xc2, 0xfc, 0xf9, 0xdd, 0xff, 0x16, 0xf4, 0x08, 0x9b, 0x85, 0xaa, 0x80, 0x3c, 0x76, 0x97,
+ 0x4e, 0x8e, 0xdc, 0x8d, 0x0f, 0xc4, 0xe6, 0xd9, 0x1c, 0x38, 0x72, 0xbd, 0x21, 0xd1, 0xfc, 0xa7,
+ 0x1d, 0x06, 0x1d, 0x1d, 0xef, 0x38, 0xde, 0x85, 0x89, 0xd2, 0x43, 0xf6, 0x06, 0xf7, 0xed, 0xa1,
+ 0x89, 0xf7, 0x7c, 0x6f, 0xfb, 0xda, 0x7c, 0xa7, 0x08, 0xb5, 0xf1, 0xef, 0xf1, 0xe7, 0x09, 0x59,
+ 0x15, 0x12, 0x55, 0x3a, 0x2f, 0x9e, 0x7f, 0x51, 0x4c, 0xef, 0xe5, 0xe9, 0x3c, 0xbd, 0x07, 0x03,
+ 0xf8, 0x4f, 0x37, 0x7b, 0x0b, 0x1c, 0xfb, 0xe8, 0xc5, 0x87, 0xb4, 0x97, 0x68, 0x80, 0xd6, 0x64,
+ 0x51, 0x8f, 0x65, 0x73, 0x9e, 0x30, 0x75, 0xed, 0x3d, 0xf1, 0xfc, 0x82, 0xd5, 0xf2, 0xe1, 0xb3,
+ 0xcb, 0x5f, 0x5d, 0xee, 0xbf, 0xfc, 0xfb, 0xbf, 0xfd, 0xdf, 0xfe, 0x44, 0xf3, 0x9d, 0x86, 0x78,
+ 0xb3, 0x54, 0x78, 0xe2, 0xe3, 0x1d, 0x67, 0xbb, 0xee, 0xf6, 0x76, 0xdb, 0x4f, 0xba, 0x4c, 0x81,
+ 0xa6, 0x78, 0x8b, 0x84, 0x1c, 0xdb, 0x90, 0x3d, 0xf7, 0xd8, 0x4c, 0xb5, 0x31, 0x17, 0x8f, 0x88,
+ 0x7d, 0xc1, 0xdd, 0x68, 0xb7, 0xdd, 0x90, 0x52, 0x0f, 0x85, 0x9d, 0xac, 0x84, 0xf1, 0x64, 0xb2,
+ 0x45, 0xe2, 0x37, 0xe2, 0xb9, 0xf1, 0x92, 0x25, 0x33, 0x17, 0x4c, 0x94, 0xe9, 0x09, 0xdf, 0x99,
+ 0x80, 0xe9, 0x6f, 0x8a, 0x53, 0x6e, 0xee, 0xda, 0xa3, 0x7d, 0x3d, 0x3f, 0x91, 0x7b, 0x93, 0xdb,
+ 0x7c, 0xbd, 0x74, 0xae, 0x68, 0x67, 0x2d, 0xe6, 0x3b, 0xdf, 0xbf, 0xb8, 0x3c, 0xfc, 0xd9, 0xb9,
+ 0xbf, 0xe8, 0xec, 0x7f, 0xd3, 0x4b, 0xe8, 0x9b, 0xd6, 0x87, 0x84, 0x9e, 0x75, 0x3e, 0xeb, 0x7c,
+ 0xde, 0x79, 0xf8, 0x6d, 0x50, 0x2b, 0x25, 0x0b, 0xa1, 0x89, 0x36, 0x07, 0x21, 0xc2, 0xf3, 0x36,
+ 0x1e, 0x74, 0x8a, 0xce, 0xc6, 0x63, 0xbd, 0xc0, 0xf4, 0x4f, 0xf9, 0xa9, 0x78, 0x6d, 0xf9, 0xf9,
+ 0x6a, 0xea, 0xdf, 0x19, 0xef, 0x0a, 0xdf, 0xcf, 0xcf, 0xa9, 0x3a, 0xc6, 0x9f, 0xf0, 0x9d, 0xf0,
+ 0x9d, 0x9a, 0x68, 0x6b, 0x6d, 0x7b, 0xd6, 0xe9, 0xed, 0x3c, 0xdd, 0xfd, 0xe0, 0x5d, 0xf3, 0xbb,
+ 0x23, 0x67, 0x30, 0xd7, 0x55, 0xfb, 0xc4, 0xd0, 0xa8, 0xd8, 0x55, 0xf4, 0x0a, 0xe1, 0x25, 0xd0,
+ 0x3a, 0x98, 0xb2, 0xb4, 0xe2, 0xc9, 0x89, 0x4d, 0x02, 0xf0, 0xb5, 0xd0, 0xba, 0xc2, 0xd8, 0x0f,
+ 0xb3, 0x6f, 0x8f, 0xc9, 0xe5, 0xab, 0x71, 0x6c, 0xab, 0x7e, 0xf2, 0x92, 0x2d, 0x36, 0x9d, 0xb5,
+ 0x3d, 0xee, 0x34, 0xd1, 0xfc, 0xdd, 0xf6, 0xfd, 0x74, 0x15, 0xb5, 0xd3, 0x9a, 0x6a, 0x13, 0x8d,
+ 0x4f, 0xae, 0x74, 0x5d, 0xde, 0x75, 0x3f, 0x3c, 0xc3, 0x83, 0x0e, 0x96, 0x21, 0xf8, 0xb6, 0xe8,
+ 0xf4, 0x3c, 0xdb, 0x55, 0x6f, 0x5b, 0xf9, 0xe0, 0xcf, 0xdf, 0x6d, 0x6a, 0x31, 0x9b, 0xe6, 0x4d,
+ 0x0f, 0x4c, 0xdf, 0x9b, 0x0e, 0xb5, 0x1e, 0x7a, 0xf3, 0x34, 0xa1, 0x7e, 0x42, 0xe3, 0x84, 0x08,
+ 0x8f, 0x09, 0x3d, 0x7c, 0xf3, 0x39, 0xa1, 0xc3, 0x27, 0x0e, 0x9f, 0x68, 0x3d, 0x61, 0x39, 0x61,
+ 0x3d, 0xe1, 0x38, 0xe6, 0xa3, 0xc4, 0x57, 0x24, 0x91, 0xd1, 0x09, 0xb1, 0xf8, 0x15, 0x36, 0x99,
+ 0xf4, 0x98, 0xe3, 0x58, 0x2b, 0x79, 0xb7, 0x47, 0xe4, 0xfd, 0xfb, 0xdf, 0xfc, 0xbe, 0x65, 0xb4,
+ 0x85, 0x6b, 0xa9, 0x6a, 0x9c, 0xcc, 0xf7, 0x0f, 0x6b, 0x9f, 0x11, 0x5b, 0xe3, 0xdf, 0x77, 0x63,
+ 0xd6, 0x33, 0x30, 0x76, 0xb8, 0xd5, 0x1b, 0xe2, 0x05, 0x21, 0xfb, 0x3b, 0xc4, 0x25, 0x2f, 0xef,
+ 0x5c, 0xdb, 0x0b, 0x01, 0x81, 0x7a, 0xb9, 0x56, 0x1f, 0x6f, 0x56, 0xe2, 0xc7, 0xee, 0x66, 0xc8,
+ 0x94, 0xa7, 0x49, 0xe3, 0x93, 0x8b, 0xac, 0x5b, 0xa8, 0xd2, 0x6c, 0xfe, 0x9d, 0x79, 0x5a, 0xee,
+ 0x79, 0x30, 0x7f, 0xa3, 0xb3, 0x16, 0x5b, 0x72, 0xea, 0xfb, 0xbf, 0xec, 0x5f, 0xff, 0x20, 0x75,
+ 0xe6, 0xdb, 0xc6, 0xa7, 0x8d, 0x9c, 0xc9, 0x6c, 0x1a, 0x25, 0x7c, 0x9d, 0x37, 0x45, 0x08, 0x6f,
+ 0x1f, 0x98, 0x72, 0x26, 0xc2, 0xdb, 0xfa, 0xd3, 0xf5, 0xfd, 0xf5, 0xe3, 0xf5, 0x5e, 0x42, 0xdf,
+ 0xd4, 0x3f, 0xac, 0x7f, 0x5e, 0xff, 0xfc, 0x8d, 0xc3, 0xc7, 0x5a, 0x8f, 0x59, 0x8e, 0x39, 0x6a,
+ 0x1c, 0xf9, 0x99, 0xb1, 0x0a, 0xf1, 0x15, 0x48, 0xfb, 0x33, 0x8e, 0x1a, 0x4b, 0x4d, 0xeb, 0xb1,
+ 0xe7, 0x6f, 0x3c, 0x24, 0xef, 0xd7, 0x5f, 0x7f, 0xa8, 0x3e, 0x42, 0x7e, 0xe7, 0xb7, 0x8d, 0xeb,
+ 0x3f, 0x6f, 0xd7, 0x3d, 0x2f, 0x7b, 0xbe, 0xb3, 0x5d, 0xd3, 0xc3, 0xeb, 0x5e, 0xcc, 0x5b, 0x42,
+ 0x66, 0xe1, 0x6c, 0x57, 0xee, 0xf1, 0x86, 0xc8, 0xfc, 0xda, 0xdc, 0xe3, 0x1f, 0x4e, 0xc3, 0xfe,
+ 0x71, 0x69, 0xd1, 0x38, 0x64, 0x87, 0x9d, 0xb8, 0xea, 0xc1, 0xac, 0xc4, 0xdd, 0xc7, 0x27, 0x3b,
+ 0x4b, 0xed, 0x24, 0xb9, 0xf9, 0x97, 0xe9, 0x34, 0xfd, 0x83, 0xfd, 0x7f, 0x65, 0xfb, 0x57, 0xdb,
+ 0xba, 0x2d, 0xf4, 0xce, 0xdc, 0xe9, 0x5b, 0x8d, 0x69, 0xca, 0xd5, 0x66, 0x72, 0xc6, 0xe6, 0xba,
+ 0x6b, 0x75, 0xf3, 0x75, 0x91, 0xba, 0x07, 0x84, 0x72, 0x75, 0x87, 0xf2, 0x5c, 0x1d, 0x07, 0x4f,
+ 0xdf, 0xc8, 0x73, 0x54, 0xe5, 0x67, 0x99, 0x5d, 0x17, 0x3a, 0x4e, 0xd3, 0xbf, 0x83, 0x93, 0x87,
+ 0x09, 0x27, 0xbf, 0x21, 0xef, 0x02, 0x4e, 0x3e, 0x20, 0xef, 0xdf, 0x6c, 0x5a, 0x6d, 0x5c, 0xf9,
+ 0x79, 0xf1, 0xb3, 0xd1, 0x29, 0xc4, 0xb6, 0x1e, 0x2a, 0x95, 0x40, 0xf3, 0x00, 0xb3, 0x70, 0x49,
+ 0xde, 0x10, 0x47, 0x89, 0x44, 0x3e, 0x10, 0x73, 0x8f, 0xe5, 0x32, 0xd3, 0x68, 0x7e, 0x1c, 0x84,
+ 0xba, 0x04, 0xf2, 0xc3, 0x88, 0x4f, 0xca, 0xcd, 0xe6, 0xdf, 0x1f, 0x3f, 0x99, 0x8f, 0xd4, 0x59,
+ 0x8b, 0xfd, 0x81, 0x53, 0xbd, 0xff, 0x7d, 0xb1, 0xdb, 0x76, 0xd3, 0xfe, 0x9f, 0xf6, 0xf5, 0xfe,
+ 0xd9, 0x33, 0x9f, 0x36, 0xce, 0x35, 0xae, 0x12, 0x82, 0xb4, 0xbe, 0x66, 0x6a, 0xae, 0x33, 0xd7,
+ 0x8d, 0x52, 0xae, 0x46, 0xea, 0xbe, 0xa7, 0x5c, 0x65, 0x92, 0xfa, 0xcd, 0x1b, 0x8f, 0xf4, 0x1c,
+ 0x2d, 0xc7, 0x4f, 0x0d, 0x67, 0x19, 0x27, 0x1f, 0x51, 0x4e, 0x9e, 0xce, 0x73, 0xd2, 0x6c, 0x7a,
+ 0xda, 0x78, 0xab, 0xf1, 0xfd, 0xbf, 0x54, 0x9f, 0x8b, 0xdd, 0x32, 0xec, 0x4e, 0x35, 0xba, 0xfa,
+ 0x82, 0x66, 0xe1, 0x90, 0x54, 0x67, 0xc3, 0x93, 0x62, 0xf7, 0xc9, 0x46, 0x3e, 0x07, 0xf4, 0xc3,
+ 0x6a, 0xd8, 0x3f, 0x36, 0xa1, 0xdf, 0x58, 0x9d, 0xcd, 0xff, 0xc3, 0xcc, 0x04, 0x62, 0xda, 0x16,
+ 0x5e, 0x12, 0xe3, 0x28, 0xe6, 0x38, 0xc3, 0xcb, 0x45, 0x6c, 0xf0, 0x2f, 0xf6, 0x15, 0x9b, 0xe7,
+ 0x83, 0x91, 0x33, 0x23, 0xa7, 0xe7, 0x4e, 0x2b, 0x5c, 0xe5, 0xea, 0x54, 0xae, 0x2a, 0x72, 0x0a,
+ 0xcd, 0xab, 0x72, 0xb4, 0x58, 0xeb, 0xaa, 0x9a, 0xd5, 0x51, 0x63, 0x25, 0xba, 0x55, 0xe5, 0x64,
+ 0x8e, 0xbc, 0xc7, 0x35, 0xc2, 0x49, 0xce, 0x94, 0x6e, 0x3c, 0xdf, 0xf8, 0xf1, 0x4f, 0x14, 0x3e,
+ 0x2e, 0x12, 0x89, 0xc4, 0xc6, 0x86, 0x21, 0xfb, 0x8c, 0x27, 0x1c, 0x42, 0xcf, 0x49, 0x15, 0x45,
+ 0xfe, 0x1d, 0x38, 0x12, 0x11, 0x27, 0xe4, 0x16, 0x19, 0x93, 0x9f, 0x27, 0xb2, 0xda, 0xda, 0xf6,
+ 0x8f, 0x91, 0x80, 0xc0, 0x18, 0xcd, 0x4f, 0x73, 0x67, 0xd1, 0xe6, 0xcb, 0x36, 0xf9, 0xed, 0x95,
+ 0xa3, 0x9b, 0x1c, 0xf3, 0x72, 0x13, 0xcd, 0xe8, 0x04, 0x46, 0xb7, 0x59, 0xb7, 0xfd, 0xa6, 0xfd,
+ 0x4b, 0xdb, 0x3f, 0x7d, 0xf0, 0xeb, 0x77, 0x66, 0xcf, 0x84, 0xcf, 0xdc, 0x22, 0x5c, 0xfd, 0x77,
+ 0x45, 0x03, 0xe7, 0xb5, 0x2f, 0x38, 0xaa, 0xca, 0x28, 0xe3, 0xa9, 0xb5, 0x40, 0x0e, 0xfa, 0x7f,
+ 0x7c, 0xa7, 0xb5, 0x06, 0xaf, 0x3e, 0x7c, 0xc3, 0x5b, 0x7f, 0x89, 0x48, 0x24, 0x38, 0x39, 0x4a,
+ 0x6e, 0xc6, 0x53, 0x72, 0x4b, 0x3e, 0x6b, 0xfc, 0xb7, 0x9f, 0x77, 0xfc, 0x09, 0xab, 0xef, 0x5c,
+ 0xe9, 0x42, 0xd7, 0x47, 0x8f, 0x7b, 0xcb, 0x3b, 0x17, 0xba, 0x40, 0x7c, 0xd5, 0x4b, 0x72, 0x36,
+ 0xca, 0xa2, 0x48, 0xa9, 0x19, 0x48, 0xac, 0x16, 0x09, 0xbc, 0x6c, 0xa9, 0x80, 0x71, 0xfd, 0xf1,
+ 0x10, 0xf0, 0x1d, 0x23, 0xc1, 0x51, 0xa1, 0x2f, 0x28, 0x7f, 0x8e, 0x3d, 0x05, 0xfa, 0x4d, 0x0b,
+ 0xff, 0x5f, 0x7e, 0x2a, 0x7e, 0x2f, 0xdb, 0xf5, 0x00, 0x9e, 0x5e, 0x86, 0xa4, 0xb6, 0x9f, 0xed,
+ 0x9a, 0x22, 0x3c, 0xad, 0xb3, 0xfd, 0xca, 0xfe, 0x8f, 0xff, 0x57, 0xde, 0xd5, 0x84, 0x44, 0x15,
+ 0x45, 0x61, 0x77, 0x05, 0x09, 0x19, 0xb5, 0x50, 0x6a, 0x61, 0xe1, 0xa6, 0x18, 0x41, 0xd3, 0x8d,
+ 0x4c, 0x9b, 0xc9, 0x55, 0xfe, 0x91, 0x4e, 0x06, 0x3a, 0xab, 0xb8, 0xb8, 0x90, 0x47, 0x98, 0x3c,
+ 0x66, 0x44, 0x6a, 0x16, 0x89, 0xb8, 0x88, 0xc9, 0x1c, 0x1d, 0x47, 0x90, 0x71, 0x13, 0xe5, 0x62,
+ 0x60, 0xac, 0x46, 0xa7, 0x62, 0xc0, 0x36, 0x81, 0x2e, 0x02, 0x23, 0x05, 0x93, 0x04, 0x37, 0x2d,
+ 0x5c, 0xb8, 0x70, 0xe1, 0x62, 0x20, 0x11, 0x3a, 0xdf, 0xb9, 0xef, 0xfa, 0xde, 0x1b, 0xb5, 0x9c,
+ 0x71, 0xfc, 0xab, 0xfb, 0x21, 0x38, 0xef, 0xcd, 0x8f, 0xe3, 0xf7, 0xce, 0x3d, 0x3f, 0xf7, 0xbc,
+ 0xfb, 0x89, 0x41, 0xcf, 0x90, 0x7b, 0xca, 0x1d, 0xae, 0x1e, 0x31, 0xec, 0x14, 0x56, 0x6a, 0xda,
+ 0xa8, 0x62, 0x74, 0x8b, 0x39, 0x4d, 0xc7, 0x16, 0x1d, 0x07, 0x93, 0xf0, 0x92, 0xbf, 0xd8, 0x26,
+ 0xab, 0x2a, 0x25, 0x93, 0xf1, 0x6b, 0x67, 0x2e, 0x60, 0x4e, 0x8d, 0xd2, 0x95, 0x53, 0xaf, 0xd1,
+ 0x9c, 0xa0, 0xe3, 0x5e, 0x1a, 0xa8, 0x5b, 0x24, 0x17, 0xe3, 0x21, 0x55, 0x0f, 0xc0, 0xde, 0x15,
+ 0xb7, 0xd6, 0xaf, 0x30, 0x97, 0xcb, 0x2b, 0x07, 0xdb, 0xad, 0xf9, 0x24, 0x00, 0x6b, 0x54, 0x58,
+ 0x1f, 0xc0, 0x3d, 0xda, 0xd8, 0xaf, 0x0b, 0xaa, 0x13, 0xc5, 0xb9, 0x21, 0xd3, 0xc2, 0xa9, 0xb2,
+ 0x53, 0xa5, 0xdf, 0x21, 0x2d, 0x55, 0xce, 0xbe, 0xf9, 0xa2, 0x41, 0x3c, 0x12, 0x41, 0x31, 0x49,
+ 0x3e, 0xb5, 0x8b, 0xfc, 0xdc, 0x12, 0xdb, 0xa8, 0x39, 0xeb, 0x9a, 0x11, 0x2f, 0x81, 0xb8, 0x53,
+ 0xc0, 0xe3, 0x88, 0x25, 0xde, 0xe9, 0xa6, 0x57, 0x2d, 0xd1, 0xeb, 0xef, 0x57, 0x04, 0x6f, 0x9c,
+ 0xbb, 0x79, 0x87, 0xdf, 0x19, 0x9a, 0x45, 0xb8, 0x72, 0xea, 0xb4, 0x32, 0xf6, 0x93, 0xd0, 0xa1,
+ 0x30, 0xb3, 0xb8, 0xe6, 0x18, 0xf6, 0x27, 0x06, 0x97, 0xfe, 0xf5, 0x70, 0xe2, 0xb4, 0xc6, 0x3d,
+ 0x56, 0xa0, 0xef, 0x33, 0x35, 0x5d, 0x38, 0xb3, 0x40, 0xd9, 0xe6, 0xb3, 0xa6, 0xfd, 0x56, 0x82,
+ 0xb2, 0x65, 0xd5, 0xb4, 0xd4, 0x9f, 0x86, 0xa5, 0xca, 0xd9, 0xf7, 0x4b, 0x6b, 0xa9, 0xe8, 0x10,
+ 0xef, 0x28, 0x4a, 0x0a, 0x13, 0xa3, 0x1f, 0x38, 0x3e, 0xa2, 0x6c, 0x86, 0xe7, 0x5c, 0xe5, 0x47,
+ 0x3d, 0x34, 0x97, 0x3e, 0xb1, 0x00, 0x47, 0xb6, 0xe3, 0x1d, 0xb6, 0xc9, 0x91, 0x0a, 0x5f, 0xc5,
+ 0x94, 0x7b, 0x40, 0xcb, 0x17, 0x6b, 0xad, 0xd0, 0x5c, 0x80, 0x9a, 0x18, 0x7b, 0x4a, 0x3d, 0x1e,
+ 0x41, 0xe6, 0x1e, 0xb5, 0xac, 0x03, 0xa3, 0x57, 0xd6, 0x6f, 0xcc, 0xb0, 0xe8, 0x42, 0x39, 0x6e,
+ 0x1e, 0x72, 0x83, 0x9e, 0x02, 0x87, 0xe8, 0xa6, 0x7c, 0x59, 0xb2, 0xa9, 0x54, 0x1a, 0x0f, 0x73,
+ 0xc8, 0xff, 0xa5, 0x39, 0xfb, 0x22, 0xab, 0x86, 0x9d, 0x52, 0x2e, 0x43, 0x33, 0xef, 0x37, 0x2d,
+ 0xe4, 0xf6, 0x39, 0x47, 0x98, 0xd1, 0x2a, 0x4b, 0x16, 0xb3, 0xc9, 0xb8, 0x5c, 0x6a, 0x62, 0x93,
+ 0x8e, 0x26, 0x39, 0x72, 0x2d, 0x32, 0x6c, 0x72, 0xd2, 0xf3, 0x46, 0x07, 0x8f, 0xe3, 0xe5, 0x25,
+ 0xbc, 0x77, 0x36, 0x2a, 0x18, 0xe8, 0x88, 0xf0, 0xc6, 0x46, 0x17, 0xed, 0x7d, 0xbd, 0x7d, 0xe5,
+ 0xfe, 0x94, 0x3f, 0x85, 0xbb, 0xc4, 0xfd, 0xf4, 0x93, 0xd9, 0xae, 0xcc, 0x27, 0x19, 0xd8, 0x5d,
+ 0x23, 0xb9, 0x92, 0x9a, 0x96, 0x6b, 0x9b, 0x6d, 0x47, 0xa6, 0x6c, 0x2b, 0x39, 0x95, 0xba, 0x8b,
+ 0x2a, 0xf2, 0xe5, 0xec, 0x54, 0xf4, 0x6b, 0x83, 0x1e, 0x8a, 0x8e, 0x0c, 0x46, 0x8b, 0xb6, 0xa3,
+ 0x5d, 0x99, 0xc5, 0x28, 0x8c, 0x22, 0x6e, 0x25, 0x8b, 0x2c, 0x64, 0x26, 0x7d, 0xce, 0xb8, 0xa7,
+ 0x5e, 0x6b, 0x67, 0x1e, 0x51, 0xfd, 0x78, 0x60, 0x64, 0x22, 0x0e, 0x01, 0xed, 0x8d, 0x70, 0xc2,
+ 0xee, 0x11, 0xf3, 0x05, 0xfa, 0x0e, 0xc6, 0x08, 0xd8, 0x5f, 0xe9, 0xb8, 0x19, 0xc8, 0x25, 0xd0,
+ 0x41, 0x9c, 0xe4, 0xfe, 0x2e, 0x54, 0x82, 0x72, 0x93, 0x6d, 0x66, 0xca, 0xa9, 0xca, 0x65, 0xd8,
+ 0x46, 0x6b, 0xa2, 0x34, 0xeb, 0x0e, 0x68, 0x43, 0xee, 0x10, 0x57, 0x1b, 0x3e, 0x1a, 0x7e, 0x14,
+ 0x76, 0x6a, 0x01, 0x3d, 0x2e, 0x32, 0xe2, 0x1d, 0x2f, 0x31, 0x89, 0x4c, 0xb9, 0xed, 0x3a, 0x7c,
+ 0xbe, 0xcb, 0xd8, 0xe5, 0xa9, 0x04, 0xbb, 0x89, 0xeb, 0x14, 0xad, 0xcf, 0x7d, 0x4d, 0xab, 0xb5,
+ 0x76, 0x06, 0x54, 0xa7, 0xc8, 0xa7, 0x54, 0xa6, 0xca, 0xdf, 0x27, 0x1d, 0x9f, 0x0b, 0x37, 0x22,
+ 0x49, 0x43, 0xdf, 0x47, 0xe9, 0xa8, 0x1d, 0xed, 0x50, 0x8c, 0xc2, 0x97, 0x96, 0x5c, 0x85, 0x6a,
+ 0x76, 0x7b, 0xcd, 0x5a, 0x6b, 0x03, 0xc7, 0x45, 0x89, 0x5a, 0x39, 0xeb, 0x2e, 0x71, 0xb4, 0x6b,
+ 0x62, 0x89, 0x8e, 0xc1, 0x4b, 0x7a, 0xab, 0x83, 0x22, 0x5d, 0x89, 0xc7, 0xdc, 0x4d, 0x1c, 0xea,
+ 0xb0, 0x67, 0xd3, 0xee, 0x5a, 0x41, 0xaf, 0xa4, 0xec, 0x08, 0x4a, 0x2e, 0xfe, 0x4d, 0xf9, 0xe8,
+ 0xb4, 0x01, 0xf9, 0x09, 0xd6, 0x0f, 0x9a, 0x63, 0xe7, 0x7b, 0xe1, 0x35, 0x8f, 0x46, 0xe3, 0x6d,
+ 0x2f, 0x46, 0x65, 0x74, 0x24, 0xeb, 0x47, 0x51, 0x9a, 0x73, 0x3b, 0x88, 0xd1, 0x05, 0xcf, 0x70,
+ 0xad, 0x8f, 0x78, 0x43, 0xb4, 0xab, 0xd0, 0x45, 0x3e, 0xd2, 0xe7, 0x1c, 0x72, 0x77, 0x08, 0xe8,
+ 0xa6, 0x5b, 0xf5, 0xce, 0xf0, 0x4e, 0xb2, 0x7f, 0xb0, 0xac, 0x17, 0xde, 0xc3, 0x5e, 0x09, 0xe8,
+ 0x29, 0x68, 0x99, 0x83, 0xb7, 0xf4, 0xaf, 0x8f, 0xa5, 0xe2, 0xa1, 0xd3, 0x5d, 0x25, 0xd8, 0x9d,
+ 0x4d, 0x74, 0xd0, 0x17, 0xce, 0xcc, 0x47, 0x8e, 0xcb, 0x32, 0xad, 0x8c, 0xda, 0xe7, 0x5c, 0xac,
+ 0x3c, 0x96, 0x52, 0x5c, 0xf4, 0x56, 0x9b, 0x17, 0x53, 0x64, 0xa5, 0xde, 0x6a, 0x9f, 0xd3, 0xe7,
+ 0x1c, 0xae, 0x9e, 0x72, 0xc7, 0xc5, 0x0b, 0xb2, 0xc8, 0xf6, 0x9a, 0xd9, 0x2a, 0x3b, 0x93, 0x79,
+ 0x79, 0x6a, 0x87, 0x05, 0x44, 0x3e, 0x0f, 0x35, 0x7b, 0x6f, 0x52, 0x5f, 0x39, 0xd6, 0xb8, 0xd0,
+ 0x0d, 0x84, 0x1e, 0xde, 0xbd, 0x3a, 0x98, 0x76, 0xa2, 0x67, 0x1f, 0xeb, 0x1e, 0x27, 0x03, 0xb8,
+ 0xc3, 0x10, 0xfb, 0x81, 0x61, 0x3f, 0xb1, 0xa3, 0x53, 0x45, 0xdd, 0x7b, 0xa4, 0x33, 0xaa, 0x6a,
+ 0x47, 0x0e, 0x51, 0x2f, 0x50, 0x05, 0xa8, 0x27, 0x16, 0xa1, 0x77, 0x0e, 0xdd, 0x5b, 0xe9, 0x25,
+ 0xed, 0xaf, 0x66, 0x7f, 0x79, 0xbb, 0x5f, 0xdf, 0x88, 0x7c, 0x9f, 0xc6, 0x5a, 0x88, 0x09, 0xca,
+ 0x35, 0x79, 0x05, 0xfa, 0xfd, 0x34, 0xd6, 0xbb, 0x5a, 0xe6, 0xba, 0xb3, 0x07, 0xf7, 0xda, 0xa3,
+ 0xa6, 0x9b, 0xe4, 0x6b, 0x03, 0x57, 0x87, 0xc2, 0xb2, 0x81, 0x1f, 0x5c, 0xf3, 0xc5, 0xf3, 0xa0,
+ 0x17, 0x94, 0xf9, 0x67, 0x58, 0x15, 0x55, 0xf6, 0x8b, 0x14, 0xef, 0x4b, 0x8a, 0xfe, 0xf6, 0xb3,
+ 0x87, 0xae, 0x0a, 0xb6, 0xdf, 0x51, 0x6c, 0x63, 0x14, 0xd9, 0xcb, 0x78, 0xf9, 0x6c, 0xd5, 0xaa,
+ 0x01, 0x28, 0x52, 0x23, 0xfb, 0xe8, 0x29, 0xd8, 0xf9, 0xd7, 0x2a, 0x05, 0xdc, 0x68, 0xd3, 0x84,
+ 0xde, 0x19, 0x58, 0x88, 0x6c, 0xbc, 0xc2, 0x1e, 0x1c, 0x00, 0xee, 0x4e, 0x87, 0xb6, 0xd8, 0xdd,
+ 0x40, 0x63, 0x20, 0x18, 0x42, 0x4f, 0xd0, 0xc5, 0xd7, 0x97, 0xb2, 0x46, 0x25, 0xe1, 0x5e, 0xac,
+ 0x99, 0xfb, 0x89, 0xc2, 0x09, 0x74, 0x0e, 0x99, 0xc0, 0xe3, 0xe1, 0x84, 0x97, 0xce, 0x36, 0xc7,
+ 0x2a, 0xf9, 0x99, 0xd9, 0x7f, 0x4e, 0x66, 0xd8, 0x88, 0xcc, 0x47, 0x1a, 0x03, 0x66, 0xcd, 0xe0,
+ 0x38, 0xb8, 0xdb, 0x7d, 0x98, 0x8c, 0xbe, 0x34, 0xaa, 0x47, 0x12, 0x52, 0x11, 0x56, 0x56, 0x00,
+ 0x76, 0x0e, 0xb9, 0xd2, 0x35, 0xcb, 0x31, 0x94, 0x83, 0x2d, 0x19, 0xbb, 0x10, 0xc9, 0xba, 0x1e,
+ 0xea, 0x09, 0x52, 0xe7, 0xda, 0x21, 0xea, 0x34, 0x75, 0x2e, 0x5b, 0x3c, 0xd7, 0xfb, 0x75, 0x6b,
+ 0x27, 0xd4, 0x3a, 0x03, 0xbf, 0xcd, 0x3d, 0x9e, 0xe0, 0x73, 0xfd, 0xfa, 0x41, 0xde, 0x3f, 0x53,
+ 0xc8, 0xef, 0xb8, 0xd6, 0x2a, 0x7d, 0x4f, 0xee, 0x2a, 0xb3, 0xb9, 0x1c, 0x92, 0x53, 0x3b, 0x8a,
+ 0xff, 0xf0, 0x6c, 0x17, 0xaf, 0xc1, 0xd9, 0x6d, 0x59, 0x62, 0x96, 0x6d, 0x1a, 0xfa, 0xf3, 0xe9,
+ 0x67, 0xb2, 0x82, 0xcb, 0xd2, 0xff, 0x94, 0x06, 0x79, 0x7c, 0xd5, 0x95, 0x83, 0x4f, 0xc9, 0x08,
+ 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2,
+ 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8,
+ 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c,
+ 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00
+};
+
+fastimage_t bfin_logo = {
+		DEF_BFIN_LOGO_DATA,
+		DEF_BFIN_LOGO_WIDTH,
+		DEF_BFIN_LOGO_HEIGHT,
+		DEF_BFIN_LOGO_BPP,
+		DEF_BFIN_LOGO_PIXEL_SIZE,
+		DEF_BFIN_LOGO_SIZE
+};
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
new file mode 100644
index 0000000..ab1fea5
--- /dev/null
+++ b/arch/blackfin/include/asm/bitops.h
@@ -0,0 +1,371 @@
+/*
+ * U-boot - bitops.h Routines for bit operations
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/config.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+
+#ifdef __KERNEL__
+/*
+ * Function prototypes to keep gcc -Wall happy
+ */
+
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while (word & 1) {
+		result++;
+		word >>= 1;
+	}
+	return result;
+}
+
+static __inline__ void set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a |= mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+#define PLATFORM__SET_BIT
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+	int mask, flags;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	local_irq_save(flags);
+	*ADDR ^= mask;
+	local_irq_restore(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
+{
+	return ((1UL << (nr & 31)) &
+		(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, volatile void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	return ((mask & *a) != 0);
+}
+
+#define	test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define	find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x)	generic_hweight32(x)
+#define hweight16(x)	generic_hweight16(x)
+#define hweight8(x)	generic_hweight8(x)
+
+static __inline__ int ext2_set_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	local_irq_save(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
+{
+	int mask, retval;
+	unsigned long flags;
+	volatile unsigned char *ADDR = (unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	local_irq_save(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
+{
+	int mask;
+	const volatile unsigned char *ADDR = (const unsigned char *)addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+							unsigned long size,
+							unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32 - offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+      found_first:
+	tmp |= ~0UL >> size;
+      found_middle:
+	return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)		test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)			set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)			test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
new file mode 100644
index 0000000..204d02b
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -0,0 +1,15 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_GLOB_BLACKFIN__
+#define __MACH_GLOB_BLACKFIN__
+
+#include "blackfin_def.h"
+#ifndef __ASSEMBLY__
+#include "blackfin_cdef.h"
+#endif
+#include "blackfin_local.h"
+
+#endif /* __MACH_GLOB_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
new file mode 100644
index 0000000..aa03f2c
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_cdef.h
@@ -0,0 +1,67 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_CDEF_BLACKFIN__
+#define __MACH_CDEF_BLACKFIN__
+
+#ifdef __ADSPBF522__
+# include "mach-bf527/BF522_cdef.h"
+#endif
+#ifdef __ADSPBF523__
+# include "mach-bf527/BF523_cdef.h"
+#endif
+#ifdef __ADSPBF524__
+# include "mach-bf527/BF524_cdef.h"
+#endif
+#ifdef __ADSPBF525__
+# include "mach-bf527/BF525_cdef.h"
+#endif
+#ifdef __ADSPBF526__
+# include "mach-bf527/BF526_cdef.h"
+#endif
+#ifdef __ADSPBF527__
+# include "mach-bf527/BF527_cdef.h"
+#endif
+#ifdef __ADSPBF531__
+# include "mach-bf533/BF531_cdef.h"
+#endif
+#ifdef __ADSPBF532__
+# include "mach-bf533/BF532_cdef.h"
+#endif
+#ifdef __ADSPBF533__
+# include "mach-bf533/BF533_cdef.h"
+#endif
+#ifdef __ADSPBF534__
+# include "mach-bf537/BF534_cdef.h"
+#endif
+#ifdef __ADSPBF536__
+# include "mach-bf537/BF536_cdef.h"
+#endif
+#ifdef __ADSPBF537__
+# include "mach-bf537/BF537_cdef.h"
+#endif
+#ifdef __ADSPBF541__
+# include "mach-bf548/BF541_cdef.h"
+#endif
+#ifdef __ADSPBF542__
+# include "mach-bf548/BF542_cdef.h"
+#endif
+#ifdef __ADSPBF544__
+# include "mach-bf548/BF544_cdef.h"
+#endif
+#ifdef __ADSPBF547__
+# include "mach-bf548/BF547_cdef.h"
+#endif
+#ifdef __ADSPBF548__
+# include "mach-bf548/BF548_cdef.h"
+#endif
+#ifdef __ADSPBF549__
+# include "mach-bf548/BF549_cdef.h"
+#endif
+#ifdef __ADSPBF561__
+# include "mach-bf561/BF561_cdef.h"
+#endif
+
+#endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
new file mode 100644
index 0000000..18372f6
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_def.h
@@ -0,0 +1,105 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __MACH_DEF_BLACKFIN__
+#define __MACH_DEF_BLACKFIN__
+
+#ifdef __ADSPBF522__
+# include "mach-bf527/BF522_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF523__
+# include "mach-bf527/BF523_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF524__
+# include "mach-bf527/BF524_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF525__
+# include "mach-bf527/BF525_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF526__
+# include "mach-bf527/BF526_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF527__
+# include "mach-bf527/BF527_def.h"
+# include "mach-bf527/anomaly.h"
+# include "mach-bf527/def_local.h"
+#endif
+#ifdef __ADSPBF531__
+# include "mach-bf533/BF531_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF532__
+# include "mach-bf533/BF532_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF533__
+# include "mach-bf533/BF533_def.h"
+# include "mach-bf533/anomaly.h"
+# include "mach-bf533/def_local.h"
+#endif
+#ifdef __ADSPBF534__
+# include "mach-bf537/BF534_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF536__
+# include "mach-bf537/BF536_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF537__
+# include "mach-bf537/BF537_def.h"
+# include "mach-bf537/anomaly.h"
+# include "mach-bf537/def_local.h"
+#endif
+#ifdef __ADSPBF541__
+# include "mach-bf548/BF541_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF542__
+# include "mach-bf548/BF542_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF544__
+# include "mach-bf548/BF544_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF547__
+# include "mach-bf548/BF547_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF548__
+# include "mach-bf548/BF548_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF549__
+# include "mach-bf548/BF549_def.h"
+# include "mach-bf548/anomaly.h"
+# include "mach-bf548/def_local.h"
+#endif
+#ifdef __ADSPBF561__
+# include "mach-bf561/BF561_def.h"
+# include "mach-bf561/anomaly.h"
+# include "mach-bf561/def_local.h"
+#endif
+
+#endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
new file mode 100644
index 0000000..3fd34b3
--- /dev/null
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -0,0 +1,220 @@
+/*
+ * U-boot - blackfin_local.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __BLACKFIN_LOCAL_H__
+#define __BLACKFIN_LOCAL_H__
+
+#include <asm/mem_map.h>
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+#define OFFSET_(x) (x & 0x0000FFFF)
+#define MK_BMSK_(x) (1 << x)
+
+/* Ideally this should be USEC not MSEC, but the USEC multiplication
+ * likes to overflow 32bit quantities which is all our assembler
+ * currently supports ;(
+ */
+#define USEC_PER_MSEC 1000
+#define MSEC_PER_SEC 1000
+#define BFIN_SCLK (100000000)
+#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
+#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
+
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+
+#include <asm/linkage.h>
+
+#ifndef __ASSEMBLY__
+# ifdef SHARED_RESOURCES
+#  include <asm/shared_resources.h>
+# endif
+
+# include <linux/types.h>
+
+extern u_long get_vco(void);
+extern u_long get_cclk(void);
+extern u_long get_sclk(void);
+
+# define bfin_revid() (bfin_read_CHIPID() >> 28)
+
+extern bool bfin_os_log_check(void);
+extern void bfin_os_log_dump(void);
+
+extern void blackfin_icache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_range(const void *, const void *);
+extern void blackfin_icache_dcache_flush_range(const void *, const void *);
+extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
+
+/* Use DMA to move data from on chip to external memory.  The L1 instruction
+ * regions can only be accessed via DMA, so if the address in question is in
+ * that region, make sure we attempt to DMA indirectly.
+ */
+# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+
+# include <asm/system.h>
+
+#if ANOMALY_05000198
+# define NOP_PAD_ANOMALY_05000198 "nop;"
+#else
+# define NOP_PAD_ANOMALY_05000198
+#endif
+
+#define bfin_read8(addr) ({ \
+	uint8_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = b[%1] (z);" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_read16(addr) ({ \
+	uint16_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = w[%1] (z);" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_read32(addr) ({ \
+	uint32_t __v; \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"%0 = [%1];" \
+		: "=d" (__v) \
+		: "a" (addr) \
+	); \
+	__v; })
+
+#define bfin_readPTR(addr) bfin_read32(addr)
+
+#define bfin_write8(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"b[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_write16(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"w[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_write32(addr, val) \
+	__asm__ __volatile__( \
+		NOP_PAD_ANOMALY_05000198 \
+		"[%0] = %1;" \
+		: \
+		: "a" (addr), "d" (val) \
+		: "memory" \
+	)
+
+#define bfin_writePTR(addr, val) bfin_write32(addr, val)
+
+/* SSYNC implementation for C file */
+static inline void SSYNC(void)
+{
+	int _tmp;
+	if (ANOMALY_05000312)
+		__asm__ __volatile__(
+			"cli %0;"
+			"nop;"
+			"nop;"
+			"ssync;"
+			"sti %0;"
+			: "=d" (_tmp)
+		);
+	else if (ANOMALY_05000244)
+		__asm__ __volatile__(
+			"nop;"
+			"nop;"
+			"nop;"
+			"ssync;"
+		);
+	else
+		__asm__ __volatile__("ssync;");
+}
+
+/* CSYNC implementation for C file */
+static inline void CSYNC(void)
+{
+	int _tmp;
+	if (ANOMALY_05000312)
+		__asm__ __volatile__(
+			"cli %0;"
+			"nop;"
+			"nop;"
+			"csync;"
+			"sti %0;"
+			: "=d" (_tmp)
+		);
+	else if (ANOMALY_05000244)
+		__asm__ __volatile__(
+			"nop;"
+			"nop;"
+			"nop;"
+			"csync;"
+		);
+	else
+		__asm__ __volatile__("csync;");
+}
+
+#else  /* __ASSEMBLY__ */
+
+/* SSYNC & CSYNC implementations for assembly files */
+
+#define ssync(x) SSYNC(x)
+#define csync(x) CSYNC(x)
+
+#if ANOMALY_05000312
+#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
+#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
+
+#elif ANOMALY_05000244
+#define SSYNC(scratch) nop; nop; nop; SSYNC;
+#define CSYNC(scratch) nop; nop; nop; CSYNC;
+
+#else
+#define SSYNC(scratch) SSYNC;
+#define CSYNC(scratch) CSYNC;
+
+#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h
new file mode 100644
index 0000000..a1a52a5
--- /dev/null
+++ b/arch/blackfin/include/asm/byteorder.h
@@ -0,0 +1,40 @@
+/*
+ * U-boot -  byteorder.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif
diff --git a/arch/blackfin/include/asm/config-pre.h b/arch/blackfin/include/asm/config-pre.h
new file mode 100644
index 0000000..4531519
--- /dev/null
+++ b/arch/blackfin/include/asm/config-pre.h
@@ -0,0 +1,80 @@
+/*
+ * config-pre.h - common defines for Blackfin boards in config.h
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
+#define __ASM_BLACKFIN_CONFIG_PRE_H__
+
+/* Misc helper functions */
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
+ * Depending on your cpu, some of these may not be valid, check your HRM.
+ * The actual values here are meaningless as long as they're unique.
+ */
+#define BFIN_BOOT_BYPASS      1       /* bypass bootrom */
+#define BFIN_BOOT_PARA        2       /* boot ldr out of parallel flash */
+#define BFIN_BOOT_SPI_MASTER  3       /* boot ldr out of serial flash */
+#define BFIN_BOOT_SPI_SLAVE   4       /* boot ldr as spi slave */
+#define BFIN_BOOT_TWI_MASTER  5       /* boot ldr over twi device */
+#define BFIN_BOOT_TWI_SLAVE   6       /* boot ldr over twi slave */
+#define BFIN_BOOT_UART        7       /* boot ldr over uart */
+#define BFIN_BOOT_IDLE        8       /* do nothing, just idle */
+#define BFIN_BOOT_FIFO        9       /* boot ldr out of FIFO */
+#define BFIN_BOOT_MEM         10      /* boot ldr out of memory (warmboot) */
+#define BFIN_BOOT_16HOST_DMA  11      /* boot ldr from 16-bit host dma */
+#define BFIN_BOOT_8HOST_DMA   12      /* boot ldr from 8-bit host dma */
+#define BFIN_BOOT_NAND        13      /* boot ldr from nand flash */
+
+#ifndef __ASSEMBLY__
+static inline const char *get_bfin_boot_mode(int bfin_boot)
+{
+	switch (bfin_boot) {
+	case BFIN_BOOT_BYPASS:     return "bypass";
+	case BFIN_BOOT_PARA:       return "parallel flash";
+	case BFIN_BOOT_SPI_MASTER: return "spi flash";
+	case BFIN_BOOT_SPI_SLAVE:  return "spi slave";
+	case BFIN_BOOT_TWI_MASTER: return "i2c flash";
+	case BFIN_BOOT_TWI_SLAVE:  return "i2c slave";
+	case BFIN_BOOT_UART:       return "uart";
+	case BFIN_BOOT_IDLE:       return "idle";
+	case BFIN_BOOT_FIFO:       return "fifo";
+	case BFIN_BOOT_MEM:        return "memory";
+	case BFIN_BOOT_16HOST_DMA: return "16bit dma";
+	case BFIN_BOOT_8HOST_DMA:  return "8bit dma";
+	case BFIN_BOOT_NAND:       return "nand flash";
+	default:                   return "INVALID";
+	}
+}
+#endif
+
+/* Most bootroms allow for EVT1 redirection */
+#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
+     && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
+# undef CONFIG_BFIN_BOOTROM_USES_EVT1
+#else
+# define CONFIG_BFIN_BOOTROM_USES_EVT1
+#endif
+
+/* Define the default SPI CS used when booting out of SPI */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
+    defined(__ADSPBF51x__)
+# define BFIN_BOOT_SPI_SSEL 2
+#else
+# define BFIN_BOOT_SPI_SSEL 1
+#endif
+
+/* There is no Blackfin/NetBSD port */
+#undef CONFIG_BOOTM_NETBSD
+
+/* We rarely use interrupts, so favor throughput over latency */
+#define CONFIG_BFIN_INS_LOWOVERHEAD
+
+#endif
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
new file mode 100644
index 0000000..7455685
--- /dev/null
+++ b/arch/blackfin/include/asm/config.h
@@ -0,0 +1,169 @@
+/*
+ * config.h - setup common defines for Blackfin boards based on config.h
+ *
+ * Copyright (c) 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
+#define __ASM_BLACKFIN_CONFIG_POST_H__
+
+/* Sanity check CONFIG_BFIN_CPU */
+#ifndef CONFIG_BFIN_CPU
+# error CONFIG_BFIN_CPU: your board config needs to define this
+#endif
+
+#ifndef CONFIG_BFIN_SCRATCH_REG
+# define CONFIG_BFIN_SCRATCH_REG retn
+#endif
+
+/* Relocation to SDRAM works on all Blackfin boards */
+#define CONFIG_RELOC_FIXUP_WORKS
+
+/* Make sure the structure is properly aligned */
+#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
+# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
+#endif
+
+/* Set default CONFIG_VCO_HZ if need be */
+#if !defined(CONFIG_VCO_HZ)
+# if (CONFIG_CLKIN_HALF == 0)
+#  define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+# else
+#  define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
+# endif
+#endif
+
+/* Set default CONFIG_CCLK_HZ if need be */
+#if !defined(CONFIG_CCLK_HZ)
+# if (CONFIG_PLL_BYPASS == 0)
+#  define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
+# else
+#  define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
+# endif
+#endif
+
+/* Set default CONFIG_SCLK_HZ if need be */
+#if !defined(CONFIG_SCLK_HZ)
+# if (CONFIG_PLL_BYPASS == 0)
+#  define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
+# else
+#  define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
+# endif
+#endif
+
+/* Since we use these to program PLL registers directly,
+ * make sure the values are sane and won't screw us up.
+ */
+#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
+# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
+#endif
+#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
+# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
+#endif
+#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
+# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
+#endif
+
+/* If we are using KGDB, make sure we defer exceptions */
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_EXCEPTION_DEFER	1
+#endif
+
+/* Using L1 scratch pad makes sense for everyone by default. */
+#ifndef CONFIG_LINUX_CMDLINE_ADDR
+# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
+#endif
+#ifndef CONFIG_LINUX_CMDLINE_SIZE
+# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
+#endif
+
+/* Set default SPI flash CS to the one we boot from */
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
+# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
+#endif
+
+/* We need envcrc to embed the env into LDRs */
+#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
+# define CONFIG_BUILD_ENVCRC
+#endif
+
+/* Default/common Blackfin memory layout */
+#ifndef CONFIG_SYS_SDRAM_BASE
+# define CONFIG_SYS_SDRAM_BASE 0
+#endif
+#ifndef CONFIG_SYS_MAX_RAM_SIZE
+# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
+#endif
+#ifndef CONFIG_SYS_MONITOR_BASE
+# if CONFIG_SYS_MAX_RAM_SIZE
+#  define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
+# else
+#  define CONFIG_SYS_MONITOR_BASE 0
+# endif
+#endif
+#ifndef CONFIG_SYS_MALLOC_BASE
+# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_SIZE
+# define CONFIG_SYS_GBL_DATA_SIZE (128)
+#endif
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
+#endif
+#ifndef CONFIG_STACKBASE
+# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)
+#endif
+#ifndef CONFIG_SYS_MEMTEST_START
+# define CONFIG_SYS_MEMTEST_START 0
+#endif
+#ifndef CONFIG_SYS_MEMTEST_END
+# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
+#endif
+
+/* Check to make sure everything fits in external RAM */
+#if CONFIG_SYS_MAX_RAM_SIZE && \
+    ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
+# error Memory Map does not fit into configuration
+#endif
+
+/* Default/common Blackfin environment settings */
+#ifndef CONFIG_LOADADDR
+# define CONFIG_LOADADDR 0x1000000
+#endif
+#ifndef CONFIG_SYS_LOAD_ADDR
+# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#endif
+#ifndef CONFIG_SYS_BOOTM_LEN
+# define CONFIG_SYS_BOOTM_LEN 0x4000000
+#endif
+#ifndef CONFIG_SYS_PROMPT
+# define CONFIG_SYS_PROMPT "bfin> "
+#endif
+#ifndef CONFIG_SYS_CBSIZE
+# define CONFIG_SYS_CBSIZE 1024
+#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
+# error "kgdb needs cbsize to be >= 1024"
+#endif
+#ifndef CONFIG_SYS_BARGSIZE
+# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#endif
+#ifndef CONFIG_SYS_PBSIZE
+# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#endif
+#ifndef CONFIG_SYS_MAXARGS
+# define CONFIG_SYS_MAXARGS 16
+#endif
+#if defined(CONFIG_SYS_HZ)
+# if (CONFIG_SYS_HZ != 1000)
+#  warning "CONFIG_SYS_HZ must always be 1000"
+# endif
+# undef CONFIG_SYS_HZ
+#endif
+#define CONFIG_SYS_HZ 1000
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
new file mode 100644
index 0000000..cc21e93
--- /dev/null
+++ b/arch/blackfin/include/asm/cplb.h
@@ -0,0 +1,76 @@
+/*
+ * cplb.h - defines for managing CPLB tables
+ *
+ * Copyright (c) 2002-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_CPLB_H__
+#define __ASM_BLACKFIN_CPLB_H__
+
+#include <asm/mach-common/bits/mpu.h>
+
+#define CPLB_ENABLE_ICACHE_P	0
+#define CPLB_ENABLE_DCACHE_P	1
+#define CPLB_ENABLE_DCACHE2_P	2
+#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
+#define CPLB_ENABLE_ICPLBS_P	4
+#define CPLB_ENABLE_DCPLBS_P	5
+
+#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
+				CPLB_ENABLE_ICPLBS | \
+				CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED		0x0000
+#define CPLB_NO_UNLOCKED	0x0001
+#define CPLB_NO_ADDR_MATCH	0x0002
+#define CPLB_PROT_VIOL		0x0003
+
+#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
+
+/* Data Attibutes*/
+
+#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
+
+#if ANOMALY_05000158
+# define ANOMALY_05000158_WORKAROUND 0x200
+#else
+# define ANOMALY_05000158_WORKAROUND 0
+#endif
+
+#ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+
+#else				/*Write Through */
+#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
+#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
+
+#endif				/* _CPLB_H */
diff --git a/arch/blackfin/include/asm/deferred.h b/arch/blackfin/include/asm/deferred.h
new file mode 100644
index 0000000..82ceda3
--- /dev/null
+++ b/arch/blackfin/include/asm/deferred.h
@@ -0,0 +1,20 @@
+/*
+ * U-boot - deferred register layout
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_DEFER_H
+#define _BLACKFIN_DEFER_H
+
+#define deferred_regs_DCPLB_FAULT_ADDR	0
+#define deferred_regs_ICPLB_FAULT_ADDR	1
+#define deferred_regs_retx		2
+#define deferred_regs_SEQSTAT		3
+#define deferred_regs_SYSCFG		4
+#define deferred_regs_IMASK		5
+#define deferred_regs_last		6
+
+#endif /* _BLACKFIN_DEFER_H */
diff --git a/arch/blackfin/include/asm/delay.h b/arch/blackfin/include/asm/delay.h
new file mode 100644
index 0000000..3af6ad3
--- /dev/null
+++ b/arch/blackfin/include/asm/delay.h
@@ -0,0 +1,55 @@
+/*
+ * U-boot - delay.h Routines for introducing delays
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+/*
+ * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
+ * Copyright (C) 1994 Hamish Macdonald
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+
+extern __inline__ void __delay(unsigned long loops)
+{
+	__asm__ __volatile__("1:\t%0 += -1;\n\t"
+			     "cc = %0 == 0;\n\t"
+			     "if ! cc jump 1b;\n":"=d"(loops)
+			     :"0"(loops));
+}
+
+/*
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern __inline__ void __udelay(unsigned long usecs)
+{
+	__delay(usecs);
+}
+
+#endif
diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h
new file mode 100644
index 0000000..404144f
--- /dev/null
+++ b/arch/blackfin/include/asm/entry.h
@@ -0,0 +1,259 @@
+/*
+ * entry.h - routines for context saving and restoring (for interrupts/exceptions)
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __BLACKFIN_ENTRY_H
+#define __BLACKFIN_ENTRY_H
+#ifdef __ASSEMBLY__
+
+#define SAVE_ALL_INT		save_context_no_interrupts
+#define SAVE_ALL_SYS		save_context_no_interrupts
+#define SAVE_CONTEXT		save_context_with_interrupts
+
+#define RESTORE_ALL		restore_context_no_interrupts
+#define RESTORE_ALL_SYS		restore_context_no_interrupts
+#define RESTORE_CONTEXT		restore_context_with_interrupts
+
+/*
+ * Code to save processor context.
+ * We even save the register which are preserved by a function call
+ * - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	[--sp] = RETI;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+#ifdef CONFIG_CMD_KGDB
+	p0.l = lo(IPEND)
+	p0.h = hi(IPEND)
+	r0 = [p0];
+#endif
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro save_context_no_interrupts
+	[--sp] = R0;
+	[--sp] = ( R7:0, P5:0 );
+	[--sp] = fp;
+	[--sp] = usp;
+
+	[--sp] = i0;
+	[--sp] = i1;
+	[--sp] = i2;
+	[--sp] = i3;
+
+	[--sp] = m0;
+	[--sp] = m1;
+	[--sp] = m2;
+	[--sp] = m3;
+
+	[--sp] = l0;
+	[--sp] = l1;
+	[--sp] = l2;
+	[--sp] = l3;
+
+	[--sp] = b0;
+	[--sp] = b1;
+	[--sp] = b2;
+	[--sp] = b3;
+	[--sp] = a0.x;
+	[--sp] = a0.w;
+	[--sp] = a1.x;
+	[--sp] = a1.w;
+
+	[--sp] = LC0;
+	[--sp] = LC1;
+	[--sp] = LT0;
+	[--sp] = LT1;
+	[--sp] = LB0;
+	[--sp] = LB1;
+
+	[--sp] = ASTAT;
+
+	[--sp] = r0;	/* Skip reserved */
+	[--sp] = RETS;
+	r0 = RETI;
+	[--sp] = r0;
+	[--sp] = RETX;
+	[--sp] = RETN;
+	[--sp] = RETE;
+	[--sp] = SEQSTAT;
+	[--sp] = SYSCFG;
+#ifdef CONFIG_CMD_KGDB
+	p0.l = lo(IPEND)
+	p0.h = hi(IPEND)
+	r0 = [p0];
+#endif
+	[--sp] = r0;	/* Skip IPEND as well. */
+.endm
+
+.macro restore_context_no_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	r0 = [sp++];
+	RETI = r0;
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+.macro restore_context_with_interrupts
+	sp += 4;
+	SYSCFG = [sp++];
+	SEQSTAT = [sp++];
+	RETE = [sp++];
+	RETN = [sp++];
+	RETX = [sp++];
+	RETI = [sp++];
+	RETS = [sp++];
+
+	sp += 4;
+
+	ASTAT = [sp++];
+
+	LB1 = [sp++];
+	LB0 = [sp++];
+	LT1 = [sp++];
+	LT0 = [sp++];
+	LC1 = [sp++];
+	LC0 = [sp++];
+
+	a1.w = [sp++];
+	a1.x = [sp++];
+	a0.w = [sp++];
+	a0.x = [sp++];
+	b3 = [sp++];
+	b2 = [sp++];
+	b1 = [sp++];
+	b0 = [sp++];
+
+	l3 = [sp++];
+	l2 = [sp++];
+	l1 = [sp++];
+	l0 = [sp++];
+
+	m3 = [sp++];
+	m2 = [sp++];
+	m1 = [sp++];
+	m0 = [sp++];
+
+	i3 = [sp++];
+	i2 = [sp++];
+	i1 = [sp++];
+	i0 = [sp++];
+
+	sp += 4;
+	fp = [sp++];
+
+	( R7 : 0, P5 : 0) = [ SP ++ ];
+	sp += 4;
+.endm
+
+#endif
+#endif
diff --git a/arch/blackfin/include/asm/errno.h b/arch/blackfin/include/asm/errno.h
new file mode 100644
index 0000000..4c82b50
--- /dev/null
+++ b/arch/blackfin/include/asm/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
new file mode 100644
index 0000000..c7099e6
--- /dev/null
+++ b/arch/blackfin/include/asm/global_data.h
@@ -0,0 +1,72 @@
+/*
+ * U-boot - global_data.h Declarations for global data of u-boot
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/u-boot.h>
+
+/*
+ * The following data structure is placed in some memory wich is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
+ */
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned long board_type;
+	unsigned long baudrate;
+	unsigned long have_console;	/* serial_init() was called */
+	phys_size_t ram_size;		/* RAM size */
+	unsigned long env_addr;	/* Address  of Environment struct */
+	unsigned long env_valid;	/* Checksum of Environment valid? */
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long post_log_word;	/* Record POST activities */
+	unsigned long post_init_f_time;	/* When post_init_f started */
+#endif
+
+	void **jt;		/* jump table */
+} gd_t;
+
+/*
+ * Global Data Flags
+ */
+#define	GD_FLG_RELOC	0x00001	/* Code was relocated to RAM     */
+#define	GD_FLG_DEVINIT	0x00002	/* Devices have been initialized */
+#define	GD_FLG_SILENT	0x00004	/* Silent mode                   */
+#define	GD_FLG_POSTFAIL	0x00008	/* Critical POST test failed     */
+#define	GD_FLG_POSTSTOP	0x00010	/* POST seqeunce aborted	 */
+#define	GD_FLG_LOGINIT	0x00020	/* Log Buf has been initialized	 */
+#define GD_FLG_DISABLE_CONSOLE	0x00040		/* Disable console (in & out)	 */
+
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P3")
+
+#endif
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
new file mode 100644
index 0000000..75244a0
--- /dev/null
+++ b/arch/blackfin/include/asm/io.h
@@ -0,0 +1,227 @@
+/*
+ * U-boot - io.h IO routines
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BLACKFIN_IO_H
+#define _BLACKFIN_IO_H
+
+#ifdef __KERNEL__
+
+#include <asm/blackfin.h>
+
+#define __iomem
+
+static inline void sync(void)
+{
+	SSYNC();
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the bfin architecture, we just read/write the
+ * memory location directly.
+ */
+#ifndef __ASSEMBLY__
+
+static inline unsigned char readb(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = b [%2] (z);"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return (unsigned char) val;
+}
+
+static inline unsigned short readw(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = w [%2] (z);"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return (unsigned short) val;
+}
+
+static inline unsigned int readl(const volatile void __iomem *addr)
+{
+	unsigned int val;
+	int tmp;
+
+	__asm__ __volatile__ (
+		"cli %1;"
+		"NOP; NOP; SSYNC;"
+		"%0 = [%2];"
+		"sti %1;"
+		: "=d"(val), "=d"(tmp)
+		: "a"(addr)
+	);
+
+	return val;
+}
+
+#endif /*  __ASSEMBLY__ */
+
+#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
+
+/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
+#define __io(port) ((void *)(unsigned long)(port))
+
+#define inb(port)    readb(__io(port))
+#define inw(port)    readw(__io(port))
+#define inl(port)    readl(__io(port))
+#define outb(x, port) writeb(x, __io(port))
+#define outw(x, port) writew(x, __io(port))
+#define outl(x, port) writel(x, __io(port))
+
+#define inb_p(port)    inb(__io(port))
+#define inw_p(port)    inw(__io(port))
+#define inl_p(port)    inl(__io(port))
+#define outb_p(x, port) outb(x, __io(port))
+#define outw_p(x, port) outw(x, __io(port))
+#define outl_p(x, port) outl(x, __io(port))
+
+#define ioread8_rep(a, d, c)	readsb(a, d, c)
+#define ioread16_rep(a, d, c)	readsw(a, d, c)
+#define ioread32_rep(a, d, c)	readsl(a, d, c)
+#define iowrite8_rep(a, s, c)	writesb(a, s, c)
+#define iowrite16_rep(a, s, c)	writesw(a, s, c)
+#define iowrite32_rep(a, s, c)	writesl(a, s, c)
+
+#define ioread8(x)			readb(x)
+#define ioread16(x)			readw(x)
+#define ioread32(x)			readl(x)
+#define iowrite8(val, x)		writeb(val, x)
+#define iowrite16(val, x)		writew(val, x)
+#define iowrite32(val, x)		writel(val, x)
+
+#define mmiowb() wmb()
+
+#ifndef __ASSEMBLY__
+
+extern void outsb(unsigned long port, const void *addr, unsigned long count);
+extern void outsw(unsigned long port, const void *addr, unsigned long count);
+extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
+extern void outsl(unsigned long port, const void *addr, unsigned long count);
+
+extern void insb(unsigned long port, void *addr, unsigned long count);
+extern void insw(unsigned long port, void *addr, unsigned long count);
+extern void insw_8(unsigned long port, void *addr, unsigned long count);
+extern void insl(unsigned long port, void *addr, unsigned long count);
+extern void insl_16(unsigned long port, void *addr, unsigned long count);
+
+static inline void readsl(const void __iomem *addr, void *buf, int len)
+{
+	insl((unsigned long)addr, buf, len);
+}
+
+static inline void readsw(const void __iomem *addr, void *buf, int len)
+{
+	insw((unsigned long)addr, buf, len);
+}
+
+static inline void readsb(const void __iomem *addr, void *buf, int len)
+{
+	insb((unsigned long)addr, buf, len);
+}
+
+static inline void writesl(const void __iomem *addr, const void *buf, int len)
+{
+	outsl((unsigned long)addr, buf, len);
+}
+
+static inline void writesw(const void __iomem *addr, const void *buf, int len)
+{
+	outsw((unsigned long)addr, buf, len);
+}
+
+static inline void writesb(const void __iomem *addr, const void *buf, int len)
+{
+	outsb((unsigned long)addr, buf, len);
+}
+
+#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
+/* This hack for CF/IDE needs to be addressed at some point */
+extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
+extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
+extern unsigned char cf_inb(volatile unsigned char *addr);
+extern void cf_outb(unsigned char val, volatile unsigned char *addr);
+#undef inb
+#undef outb
+#undef insw
+#undef outsw
+#define inb(addr) cf_inb((void *)(addr))
+#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
+#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
+#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
+#endif
+
+#endif
+
+#endif				/* __KERNEL__ */
+
+#endif
diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h
new file mode 100644
index 0000000..fbb497c
--- /dev/null
+++ b/arch/blackfin/include/asm/linkage.h
@@ -0,0 +1,74 @@
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <linux/config.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE		extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X)	#X
+#define SYMBOL_NAME(X)		X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)	X##:
+#else
+#define SYMBOL_NAME_LABEL(X)	X:
+#endif
+
+#define __ALIGN .align		4
+#define __ALIGN_STR		".align 4"
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define LENTRY(name) \
+	ALIGN; \
+	SYMBOL_NAME_LABEL(name)
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name); \
+	LENTRY(name)
+#endif
+
+#ifndef END
+#define END(name) \
+	.size name, .-name
+#endif
+
+#ifndef ENDPROC
+#define ENDPROC(name) \
+	.type name, @function; \
+	END(name)
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
new file mode 100644
index 0000000..f65b439
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -0,0 +1,1505 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
+
+#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
+#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
+#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
+#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
+#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
+#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
+#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
+#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
+#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
+#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
+#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
+#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
+#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
+#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
+#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
+#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
+#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
+#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
+#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
+#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
+#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
+#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
+#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
+#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
+#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
+#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
+#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
+#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
+#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
+#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
+#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
+#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
+#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
+#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
+#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
+#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
+#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
+#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
+#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
+#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
+#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
+#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
+#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
+#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
+#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
+#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
+#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
+#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
+#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
+#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
+#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
+#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
+#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
+#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
+#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
+#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
+#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
+#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
+#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
+#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
+#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
+#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
+#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
+#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
+#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
+#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
+#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
+#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
+#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
+#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
+#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
+#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
+#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
+#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
+#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
+#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
+#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
+#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
+#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
+#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
+#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
+#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
+#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
+#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
+#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
+#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
+#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
+#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
+#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
+#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
+#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
+#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
+#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
+#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
+#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
+#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
+#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
+#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
+#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
+#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
+#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
+#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
+#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
+#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
+#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
+#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
+#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
+#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
+#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
+#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
+#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
+#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
+#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
+#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pPORTF_MUX                     ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */
+#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
+#define pPORTG_MUX                     ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */
+#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
+#define pPORTH_MUX                     ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */
+#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
+#define pPORTF_DRIVE                   ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */
+#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
+#define pPORTG_DRIVE                   ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */
+#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
+#define pPORTH_DRIVE                   ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */
+#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
+#define pPORTF_SLEW                    ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */
+#define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
+#define pPORTG_SLEW                    ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */
+#define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
+#define pPORTH_SLEW                    ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */
+#define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
+#define pPORTF_HYSTERESIS              ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */
+#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define pPORTG_HYSTERESIS              ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */
+#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define pPORTH_HYSTERESIS              ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */
+#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
+#define pNONGPIO_DRIVE                 ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */
+#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
+#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
+#define pNONGPIO_SLEW                  ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */
+#define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
+#define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
+#define pNONGPIO_HYSTERESIS            ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */
+#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
+#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
+#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
+#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
+#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF52x_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
new file mode 100644
index 0000000..0b38480
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
@@ -0,0 +1,509 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF52x_extended__
+#define __BFIN_DEF_ADSP_EDN_BF52x_extended__
+
+#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
+#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
+#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
+#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
+#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
+#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
+#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
+#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
+#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
+#define SPI_STAT                       0xFFC00508 /* SPI Status register */
+#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
+#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
+#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
+#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
+#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
+#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
+#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
+#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
+#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
+#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
+#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
+#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
+#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
+#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
+#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
+#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
+#define PORTF_SLEW                     0xFFC03230 /* Port F slew control */
+#define PORTG_SLEW                     0xFFC03234 /* Port G slew control */
+#define PORTH_SLEW                     0xFFC03238 /* Port H slew control */
+#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
+#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
+#define NONGPIO_SLEW                   0xFFC03284 /* Non-GPIO Port slew control */
+#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
+#define HOST_CONTROL                   0xFFC03400 /* HOST Control Register */
+#define HOST_STATUS                    0xFFC03404 /* HOST Status Register */
+#define HOST_TIMEOUT                   0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
+#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
+#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC03508 /* Status Register */
+#define CNT_COMMAND                    0xFFC0350C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
+#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
+#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
+#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
+#define OTP_CONTROL                    0xFFC03600 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC03604 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC03608 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0360C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
+#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
+#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define NFC_CTL                        0xFFC03700 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03704 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03708 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC0370C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03710 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03714 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03718 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC0371C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03720 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03724 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03728 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC0372C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03740 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03744 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define DMA_TC_CNT                     0xFFC00B0C
+#define DMA_TC_PER                     0xFFC00B10
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF52x_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
new file mode 100644
index 0000000..987cc86
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
@@ -0,0 +1,341 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF522_proc__
+#define __BFIN_CDEF_ADSP_BF522_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
new file mode 100644
index 0000000..bc05029
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
@@ -0,0 +1,123 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF522_proc__
+#define __BFIN_DEF_ADSP_BF522_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+
+#endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
new file mode 100644
index 0000000..390f3dc
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
@@ -0,0 +1,341 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF523_proc__
+#define __BFIN_CDEF_ADSP_BF523_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
new file mode 100644
index 0000000..c27fd64
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_def.h
@@ -0,0 +1,123 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF523_proc__
+#define __BFIN_DEF_ADSP_BF523_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+
+#endif /* __BFIN_DEF_ADSP_BF523_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
new file mode 100644
index 0000000..9ec89c6
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
@@ -0,0 +1,848 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF524_proc__
+#define __BFIN_CDEF_ADSP_BF524_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
new file mode 100644
index 0000000..bd6aa8f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
@@ -0,0 +1,292 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF524_proc__
+#define __BFIN_DEF_ADSP_BF524_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define USB_FADDR                      0xFFC03800 /* Function address register */
+#define USB_POWER                      0xFFC03804 /* Power management register */
+#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03820 /* USB frame number */
+#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_BF524_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
new file mode 100644
index 0000000..8fe29db
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
@@ -0,0 +1,848 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF525_proc__
+#define __BFIN_CDEF_ADSP_BF525_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF525_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_def.h b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
new file mode 100644
index 0000000..5e88b3b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF525_def.h
@@ -0,0 +1,292 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF525_proc__
+#define __BFIN_DEF_ADSP_BF525_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define USB_FADDR                      0xFFC03800 /* Function address register */
+#define USB_POWER                      0xFFC03804 /* Power management register */
+#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03820 /* USB frame number */
+#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_BF525_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
new file mode 100644
index 0000000..9438862
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
@@ -0,0 +1,1085 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF526_proc__
+#define __BFIN_CDEF_ADSP_BF526_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
+#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
+#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
+#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
+#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
+#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
+#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
+#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
+#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
+#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
+#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
+#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
+#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
+#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
+#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
+#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
+#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
+#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
+#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
+#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
+#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
+#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
+#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
+#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
+#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
+#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
+#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
+#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
+#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
+#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
+#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
+#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
+#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
+#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
+#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
+#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
+#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
+#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
+#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
+#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
+#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
+#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
+#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
+#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
+#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
+#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
+#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
+#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
+#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
+#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
+#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
+#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
+#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
+#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
+#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
+#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
+#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
+#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
+#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
+#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
+#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
+#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
+#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
+#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
+#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
+#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
+#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
+#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
+#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
+#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
+#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
+#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
+#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
+#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
+#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
+#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
+#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
+#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
+#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
+#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
+#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
+#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
+#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
+#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
+#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
+#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
+#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
+#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
+#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
+#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
+#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
+#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
+#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
+#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
+#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
+#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
+#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
+#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
+#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
+#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
+#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
+#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
+#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
+#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
+#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
+#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
+#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
+#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
+#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
+#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
+#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
+#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
+#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
+#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
+#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
+#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
+#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
+#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
+#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
+#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
+#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
+#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
+#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
+#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
+#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
+#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
+#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
new file mode 100644
index 0000000..2644abf
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
@@ -0,0 +1,371 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF526_proc__
+#define __BFIN_DEF_ADSP_BF526_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
+#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
+#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
+#define USB_FADDR                      0xFFC03800 /* Function address register */
+#define USB_POWER                      0xFFC03804 /* Power management register */
+#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03820 /* USB frame number */
+#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_BF526_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
new file mode 100644
index 0000000..fb9b307
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
@@ -0,0 +1,1085 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF527_proc__
+#define __BFIN_CDEF_ADSP_BF527_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF52x-extended_cdef.h"
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
+#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
+#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
+#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
+#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
+#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
+#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
+#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
+#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
+#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
+#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
+#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
+#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
+#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
+#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
+#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
+#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
+#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
+#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
+#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
+#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
+#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
+#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
+#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
+#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
+#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
+#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
+#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
+#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
+#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
+#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
+#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
+#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
+#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
+#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
+#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
+#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
+#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
+#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
+#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
+#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
+#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
+#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
+#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
+#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
+#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
+#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
+#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
+#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
+#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
+#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
+#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
+#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
+#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
+#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
+#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
+#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
+#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
+#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
+#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
+#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
+#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
+#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
+#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
+#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
+#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
+#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
+#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
+#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
+#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
+#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
+#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
+#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
+#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
+#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
+#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
+#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
+#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
+#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
+#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
+#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
+#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
+#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
+#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
+#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
+#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
+#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
+#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
+#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
+#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
+#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
+#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
+#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
+#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
+#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
+#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
+#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
+#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
+#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
+#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
+#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
+#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
+#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
+#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
+#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
+#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
+#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
+#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
+#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
+#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
+#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
+#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
+#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
+#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
+#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
+#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
+#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
+#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
+#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
+#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
+#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
+#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
+#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
+#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
+#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
+#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
+#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF527_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_def.h b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
new file mode 100644
index 0000000..c46c2b0
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/BF527_def.h
@@ -0,0 +1,371 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF527_proc__
+#define __BFIN_DEF_ADSP_BF527_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF52x-extended_def.h"
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
+#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
+#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
+#define USB_FADDR                      0xFFC03800 /* Function address register */
+#define USB_POWER                      0xFFC03804 /* Power management register */
+#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03820 /* USB frame number */
+#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_BF527_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h
new file mode 100644
index 0000000..0fd7e31
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h
@@ -0,0 +1,206 @@
+/*
+ * File: include/asm-blackfin/mach-bf527/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file should be up to date with:
+ *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
+# define ANOMALY_BF526 1
+#else
+# define ANOMALY_BF526 0
+#endif
+#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
+# define ANOMALY_BF527 1
+#else
+# define ANOMALY_BF527 0
+#endif
+
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
+#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0xE510
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Security Features Are Not Functional */
+#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (ANOMALY_BF526)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Incorrect Default CSEL Value in PLL_DIV */
+#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Authentication Fails To Initiate */
+#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Data Read From L3 Memory by USB DMA May be Corrupted */
+#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
+#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
+#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
+#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* Incorrect Default Internal Voltage Regulator Setting */
+#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* DEB2_URGENT Bit Not Functional */
+#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
+#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
+#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
+#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
+#define ANOMALY_05000421 (1)
+/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
+#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
+#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+/* Internal Voltage Regulator Not Trimmed */
+#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (1)
+/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
+#define ANOMALY_05000432 (ANOMALY_BF526)
+/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
+#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+/* Preboot Cannot be Used to Alter the PLL_DIV Register */
+#define ANOMALY_05000439 (1)
+/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
+#define ANOMALY_05000440 (1)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* The WURESET Bit in the SYSCR Register is not Functional */
+#define ANOMALY_05000445 (1)
+/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
+#define ANOMALY_05000451 (1)
+/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
+#define ANOMALY_05000452 (1)
+/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
+#define ANOMALY_05000456 (1)
+/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
+#define ANOMALY_05000457 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/def_local.h b/arch/blackfin/include/asm/mach-bf527/def_local.h
new file mode 100644
index 0000000..81eca83
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/def_local.h
@@ -0,0 +1,2 @@
+#include "mem_map.h"
+#include "ports.h"
diff --git a/arch/blackfin/include/asm/mach-bf527/mem_map.h b/arch/blackfin/include/asm/mach-bf527/mem_map.h
new file mode 100644
index 0000000..8386b4b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/mem_map.h
@@ -0,0 +1,21 @@
+/*
+ * Common Blackfin memory map
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BF52X_MEM_MAP_H__
+#define __BF52X_MEM_MAP_H__
+
+#define L1_DATA_A_SRAM      (0xFF800000)
+#define L1_DATA_A_SRAM_SIZE (0x4000)
+#define L1_DATA_A_SRAM_END  (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM      (0xFF900000)
+#define L1_DATA_B_SRAM_SIZE (0x4000)
+#define L1_DATA_B_SRAM_END  (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM        (0xFFA00000)
+#define L1_INST_SRAM_SIZE   (0xC000)
+#define L1_INST_SRAM_END    (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf527/ports.h b/arch/blackfin/include/asm/mach-bf527/ports.h
new file mode 100644
index 0000000..e6b1df8
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf527/ports.h
@@ -0,0 +1,60 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x0003
+#define PORT_x_MUX_1_MASK	0x000C
+#define PORT_x_MUX_2_MASK	0x0030
+#define PORT_x_MUX_3_MASK	0x00C0
+#define PORT_x_MUX_4_MASK	0x0300
+#define PORT_x_MUX_5_MASK	0x0C00
+#define PORT_x_MUX_6_MASK	0x3000
+#define PORT_x_MUX_7_MASK	0xC000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-j.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
new file mode 100644
index 0000000..49a2b2e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
@@ -0,0 +1,14 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF531_proc__
+#define __BFIN_CDEF_ADSP_BF531_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "../mach-common/ADSP-EDN-extended_cdef.h"
+
+
+#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h
new file mode 100644
index 0000000..d7278e5
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h
@@ -0,0 +1,23 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF531_proc__
+#define __BFIN_DEF_ADSP_BF531_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "../mach-common/ADSP-EDN-extended_def.h"
+
+#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF531_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
new file mode 100644
index 0000000..47b48ac
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
@@ -0,0 +1,14 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF532_proc__
+#define __BFIN_CDEF_ADSP_BF532_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "../mach-common/ADSP-EDN-extended_cdef.h"
+
+
+#endif /* __BFIN_CDEF_ADSP_BF532_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h
new file mode 100644
index 0000000..86944d0
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF532_def.h
@@ -0,0 +1,23 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF532_proc__
+#define __BFIN_DEF_ADSP_BF532_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "../mach-common/ADSP-EDN-extended_def.h"
+
+#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF532_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
new file mode 100644
index 0000000..f270d01
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
@@ -0,0 +1,14 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF533_proc__
+#define __BFIN_CDEF_ADSP_BF533_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "../mach-common/ADSP-EDN-extended_cdef.h"
+
+
+#endif /* __BFIN_CDEF_ADSP_BF533_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h
new file mode 100644
index 0000000..17b5d7f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/BF533_def.h
@@ -0,0 +1,29 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF533_proc__
+#define __BFIN_DEF_ADSP_BF533_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "../mach-common/ADSP-EDN-extended_def.h"
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF533_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h
new file mode 100644
index 0000000..c98747f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h
@@ -0,0 +1,338 @@
+/*
+ * File: include/asm-blackfin/mach-bf533/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file should be up to date with:
+ *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.2 silicon - sorry */
+#if __SILICON_REVISION__ < 3
+# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
+#endif
+
+#if defined(__ADSPBF531__)
+# define ANOMALY_BF531 1
+#else
+# define ANOMALY_BF531 0
+#endif
+#if defined(__ADSPBF532__)
+# define ANOMALY_BF532 1
+#else
+# define ANOMALY_BF532 0
+#endif
+#if defined(__ADSPBF533__)
+# define ANOMALY_BF533 1
+#else
+# define ANOMALY_BF533 0
+#endif
+
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
+#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
+/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
+#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
+#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
+#define ANOMALY_05000167 (1)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
+/* False Protection Exceptions */
+#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
+/* Restarting SPORT in Specific Modes May Cause Data Corruption */
+#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
+/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
+/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
+#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
+/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
+#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
+/* Possible Infinite Stall with Specific Dual-DAG Situation */
+#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
+/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
+#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
+/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
+/* Recovery from "Brown-Out" Condition */
+#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
+/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
+#define ANOMALY_05000208 (1)
+/* Speed Path in Computational Unit Affects Certain Instructions */
+#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
+/* UART TX Interrupt Masked Erroneously */
+#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (1)
+/* Incorrect Pulse-Width of UART Start Bit */
+#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
+/* Scratchpad Memory Bank Reads May Return Incorrect Data */
+#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
+/* SPI Slave Boot Mode Modifies Registers from Reset Value */
+#define ANOMALY_05000229 (1)
+/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
+#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
+/* UART STB Bit Incorrectly Affects Receiver Setting */
+#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
+/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
+#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
+/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Data CPLBs Should Prevent Spurious Hardware Errors */
+#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
+/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
+#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
+#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
+/* Spontaneous Reset of Internal Voltage Regulator */
+#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM Memory May Be Lost */
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
+/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
+#define ANOMALY_05000276 (1)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
+/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
+#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
+#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
+/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
+#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
+/* PPI Does Not Start Properly In Specific Mode */
+#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+
+/* These anomalies have been "phased" out of analog.com anomaly sheets and are
+ * here to show running on older silicon just isn't feasible.
+ */
+
+/* Internal voltage regulator can't be modified via register writes */
+#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
+/* Watchpoints (Hardware Breakpoints) are not supported */
+#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
+/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
+#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
+/* Writing FIO_DIR can corrupt a programmable flag's data */
+#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
+/* Timer Auto-Baud Mode requires the UART clock to be enabled */
+#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
+/* Internal Clocking Modes on SPORT0 not supported */
+#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
+/* Internal voltage regulator does not wake up from an RTC wakeup */
+#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
+/* The IFLUSH instruction must be preceded by a CSYNC instruction */
+#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
+/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */
+#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
+/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */
+#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
+/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
+#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
+/* 32-bit SPORT DMA will be word reversed */
+#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
+/* Incorrect status in the UART_IIR register */
+#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
+/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
+#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
+/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
+#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
+/* Incorrect value written to the cycle counters */
+#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
+/* Stores to L1 Data memory incorrect when a specific sequence is followed */
+#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
+/* Programmable Flag (PF3) functionality not supported in all PPI modes */
+#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
+/* Data store can be lost when targeting a cache line fill */
+#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
+/* Reserved bits in SYSCFG register not set at power on */
+#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
+/* Infinite Core Stall */
+#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
+/* PPI_FSx may glitch when generated by the on chip Timers */
+#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
+/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
+#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
+/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
+#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
+/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
+#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
+/* Erroneous exception when enabling cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* SPI clock polarity and phase bits incorrect during booting */
+#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL is not set on Reset */
+#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
+/* SPI boot will not complete if there is a zero fill block in the loader file */
+#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
+/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */
+#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
+#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
+#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* SPORT transmit data is not gated by external frame sync in certain conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
+/* DATA CPLB page miss can result in lost write-through cache data writes */
+#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
+/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
+/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
+/* Disabling the PPI resets the PPI configuration registers */
+#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
+/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* In PPI Transmit Modes with External Frame Syncs POLC */
+#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
+/* Internal Voltage Regulator may not start up */
+#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000430 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf533/def_local.h b/arch/blackfin/include/asm/mach-bf533/def_local.h
new file mode 100644
index 0000000..14c111f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/def_local.h
@@ -0,0 +1 @@
+#include "ports.h"
diff --git a/arch/blackfin/include/asm/mach-bf533/ports.h b/arch/blackfin/include/asm/mach-bf533/ports.h
new file mode 100644
index 0000000..512d6df
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf533/ports.h
@@ -0,0 +1,10 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-f.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
new file mode 100644
index 0000000..0700875
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
@@ -0,0 +1,2750 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF534_extended__
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration Register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
+#define pSIC_IMASK                     ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
+#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_ISR                       ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
+#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
+#define pSIC_IWR                       ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
+#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
+#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
+#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
+#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
+#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
+#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
+#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
+#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
+#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
+#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
+#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
+#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
+#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
+#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
+#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
+#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
+#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
+#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
+#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
+#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
+#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
+#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
+#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
+#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
+#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
+#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
+#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
+#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
+#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
+#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
+#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
+#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
+#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
+#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
+#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
+#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
+#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
+#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
+#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
+#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
+#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
+#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
+#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
+#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
+#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
+#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
+#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
+#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
+#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
+#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
+#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
+#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
+#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
+#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
+#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
+#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
+#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
+#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
+#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
+#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
+#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
+#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
+#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
+#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
+#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
+#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
+#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
+#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
+#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
+#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
+#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
+#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
+#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
+#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
+#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
+#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
+#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
+#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
+#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
+#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
+#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
+#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
+#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
+#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
+#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
+#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
+#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
+#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
+#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
+#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
+#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
+#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
+#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
+#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
+#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
+#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
+#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
+#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
+#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
+#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
+#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
+#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
+#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
+#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
+#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
+#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
+#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
+#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
+#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
+#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
+#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
+#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
+#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
+#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
+#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
+#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
+#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
+#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
+#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
+#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pCAN_MC1                       ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */
+#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
+#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
+#define pCAN_MD1                       ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */
+#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
+#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
+#define pCAN_TRS1                      ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */
+#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
+#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
+#define pCAN_TRR1                      ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */
+#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
+#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
+#define pCAN_TA1                       ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */
+#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
+#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
+#define pCAN_AA1                       ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */
+#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
+#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
+#define pCAN_RMP1                      ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */
+#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
+#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
+#define pCAN_RML1                      ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */
+#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
+#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
+#define pCAN_MBTIF1                    ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */
+#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
+#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
+#define pCAN_MBRIF1                    ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive  Interrupt Flag reg 1 */
+#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
+#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
+#define pCAN_MBIM1                     ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */
+#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
+#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
+#define pCAN_RFH1                      ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */
+#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
+#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
+#define pCAN_OPSS1                     ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */
+#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
+#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
+#define pCAN_MC2                       ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */
+#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
+#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
+#define pCAN_MD2                       ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */
+#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
+#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
+#define pCAN_TRS2                      ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */
+#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
+#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
+#define pCAN_TRR2                      ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */
+#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
+#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
+#define pCAN_TA2                       ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */
+#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
+#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
+#define pCAN_AA2                       ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */
+#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
+#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
+#define pCAN_RMP2                      ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */
+#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
+#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
+#define pCAN_RML2                      ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */
+#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
+#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
+#define pCAN_MBTIF2                    ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */
+#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
+#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
+#define pCAN_MBRIF2                    ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive  Interrupt Flag reg 2 */
+#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
+#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
+#define pCAN_MBIM2                     ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */
+#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
+#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
+#define pCAN_RFH2                      ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */
+#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
+#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
+#define pCAN_OPSS2                     ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */
+#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
+#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
+#define pCAN_CLOCK                     ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */
+#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
+#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
+#define pCAN_TIMING                    ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */
+#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
+#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
+#define pCAN_DEBUG                     ((uint16_t volatile *)CAN_DEBUG) /* Config register */
+#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
+#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
+#define pCAN_STATUS                    ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */
+#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
+#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
+#define pCAN_CEC                       ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */
+#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
+#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
+#define pCAN_GIS                       ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */
+#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
+#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
+#define pCAN_GIM                       ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */
+#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
+#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
+#define pCAN_GIF                       ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */
+#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
+#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
+#define pCAN_CONTROL                   ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */
+#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
+#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
+#define pCAN_INTR                      ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */
+#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
+#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
+#define pCAN_VERSION                   ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */
+#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
+#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
+#define pCAN_MBTD                      ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */
+#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
+#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
+#define pCAN_EWR                       ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */
+#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
+#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
+#define pCAN_ESR                       ((uint16_t volatile *)CAN_ESR) /* Error Status Register */
+#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
+#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
+#define pCAN_UCREG                     ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */
+#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
+#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
+#define pCAN_UCCNT                     ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */
+#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
+#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
+#define pCAN_UCRC                      ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */
+#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
+#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
+#define pCAN_UCCNF                     ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */
+#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
+#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
+#define pCAN_VERSION2                  ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */
+#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
+#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
+#define pCAN_AM00L                     ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */
+#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
+#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
+#define pCAN_AM00H                     ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */
+#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
+#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
+#define pCAN_AM01L                     ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask  */
+#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
+#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
+#define pCAN_AM01H                     ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */
+#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
+#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
+#define pCAN_AM02L                     ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask  */
+#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
+#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
+#define pCAN_AM02H                     ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */
+#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
+#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
+#define pCAN_AM03L                     ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask  */
+#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
+#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
+#define pCAN_AM03H                     ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */
+#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
+#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
+#define pCAN_AM04L                     ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask  */
+#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
+#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
+#define pCAN_AM04H                     ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */
+#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
+#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
+#define pCAN_AM05L                     ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask  */
+#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
+#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
+#define pCAN_AM05H                     ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */
+#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
+#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
+#define pCAN_AM06L                     ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask  */
+#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
+#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
+#define pCAN_AM06H                     ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */
+#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
+#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
+#define pCAN_AM07L                     ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask  */
+#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
+#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
+#define pCAN_AM07H                     ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */
+#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
+#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
+#define pCAN_AM08L                     ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask  */
+#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
+#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
+#define pCAN_AM08H                     ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */
+#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
+#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
+#define pCAN_AM09L                     ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask  */
+#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
+#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
+#define pCAN_AM09H                     ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */
+#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
+#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
+#define pCAN_AM10L                     ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask  */
+#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
+#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
+#define pCAN_AM10H                     ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */
+#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
+#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
+#define pCAN_AM11L                     ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask  */
+#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
+#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
+#define pCAN_AM11H                     ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */
+#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
+#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
+#define pCAN_AM12L                     ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask  */
+#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
+#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
+#define pCAN_AM12H                     ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */
+#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
+#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
+#define pCAN_AM13L                     ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask  */
+#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
+#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
+#define pCAN_AM13H                     ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */
+#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
+#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
+#define pCAN_AM14L                     ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask  */
+#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
+#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
+#define pCAN_AM14H                     ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */
+#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
+#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
+#define pCAN_AM15L                     ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask  */
+#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
+#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
+#define pCAN_AM15H                     ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */
+#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
+#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
+#define pCAN_AM16L                     ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask  */
+#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
+#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
+#define pCAN_AM16H                     ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */
+#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
+#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
+#define pCAN_AM17L                     ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask  */
+#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
+#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
+#define pCAN_AM17H                     ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */
+#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
+#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
+#define pCAN_AM18L                     ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask  */
+#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
+#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
+#define pCAN_AM18H                     ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */
+#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
+#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
+#define pCAN_AM19L                     ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask  */
+#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
+#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
+#define pCAN_AM19H                     ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */
+#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
+#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
+#define pCAN_AM20L                     ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask  */
+#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
+#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
+#define pCAN_AM20H                     ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */
+#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
+#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
+#define pCAN_AM21L                     ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask  */
+#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
+#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
+#define pCAN_AM21H                     ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */
+#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
+#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
+#define pCAN_AM22L                     ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask  */
+#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
+#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
+#define pCAN_AM22H                     ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */
+#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
+#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
+#define pCAN_AM23L                     ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask  */
+#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
+#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
+#define pCAN_AM23H                     ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */
+#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
+#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
+#define pCAN_AM24L                     ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask  */
+#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
+#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
+#define pCAN_AM24H                     ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */
+#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
+#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
+#define pCAN_AM25L                     ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask  */
+#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
+#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
+#define pCAN_AM25H                     ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */
+#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
+#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
+#define pCAN_AM26L                     ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask  */
+#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
+#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
+#define pCAN_AM26H                     ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */
+#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
+#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
+#define pCAN_AM27L                     ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask  */
+#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
+#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
+#define pCAN_AM27H                     ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */
+#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
+#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
+#define pCAN_AM28L                     ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask  */
+#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
+#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
+#define pCAN_AM28H                     ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */
+#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
+#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
+#define pCAN_AM29L                     ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask  */
+#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
+#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
+#define pCAN_AM29H                     ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */
+#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
+#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
+#define pCAN_AM30L                     ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask  */
+#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
+#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
+#define pCAN_AM30H                     ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */
+#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
+#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
+#define pCAN_AM31L                     ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask  */
+#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
+#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
+#define pCAN_AM31H                     ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */
+#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
+#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
+#define pCAN_MB00_DATA0                ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
+#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
+#define pCAN_MB00_DATA1                ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
+#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
+#define pCAN_MB00_DATA2                ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
+#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
+#define pCAN_MB00_DATA3                ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
+#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
+#define pCAN_MB00_LENGTH               ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */
+#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
+#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
+#define pCAN_MB00_TIMESTAMP            ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */
+#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
+#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
+#define pCAN_MB00_ID0                  ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */
+#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
+#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
+#define pCAN_MB00_ID1                  ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */
+#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
+#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
+#define pCAN_MB01_DATA0                ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register  */
+#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
+#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
+#define pCAN_MB01_DATA1                ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
+#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
+#define pCAN_MB01_DATA2                ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
+#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
+#define pCAN_MB01_DATA3                ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
+#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
+#define pCAN_MB01_LENGTH               ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */
+#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
+#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
+#define pCAN_MB01_TIMESTAMP            ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */
+#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
+#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
+#define pCAN_MB01_ID0                  ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */
+#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
+#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
+#define pCAN_MB01_ID1                  ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */
+#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
+#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
+#define pCAN_MB02_DATA0                ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register  */
+#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
+#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
+#define pCAN_MB02_DATA1                ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
+#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
+#define pCAN_MB02_DATA2                ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
+#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
+#define pCAN_MB02_DATA3                ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
+#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
+#define pCAN_MB02_LENGTH               ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register    */
+#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
+#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
+#define pCAN_MB02_TIMESTAMP            ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */
+#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
+#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
+#define pCAN_MB02_ID0                  ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */
+#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
+#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
+#define pCAN_MB02_ID1                  ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */
+#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
+#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
+#define pCAN_MB03_DATA0                ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register  */
+#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
+#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
+#define pCAN_MB03_DATA1                ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
+#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
+#define pCAN_MB03_DATA2                ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
+#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
+#define pCAN_MB03_DATA3                ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
+#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
+#define pCAN_MB03_LENGTH               ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */
+#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
+#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
+#define pCAN_MB03_TIMESTAMP            ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */
+#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
+#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
+#define pCAN_MB03_ID0                  ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */
+#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
+#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
+#define pCAN_MB03_ID1                  ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */
+#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
+#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
+#define pCAN_MB04_DATA0                ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
+#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
+#define pCAN_MB04_DATA1                ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
+#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
+#define pCAN_MB04_DATA2                ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
+#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
+#define pCAN_MB04_DATA3                ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
+#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
+#define pCAN_MB04_LENGTH               ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */
+#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
+#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
+#define pCAN_MB04_TIMESTAMP            ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */
+#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
+#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
+#define pCAN_MB04_ID0                  ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */
+#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
+#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
+#define pCAN_MB04_ID1                  ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */
+#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
+#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
+#define pCAN_MB05_DATA0                ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register  */
+#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
+#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
+#define pCAN_MB05_DATA1                ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
+#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
+#define pCAN_MB05_DATA2                ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
+#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
+#define pCAN_MB05_DATA3                ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
+#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
+#define pCAN_MB05_LENGTH               ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */
+#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
+#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
+#define pCAN_MB05_TIMESTAMP            ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */
+#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
+#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
+#define pCAN_MB05_ID0                  ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */
+#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
+#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
+#define pCAN_MB05_ID1                  ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */
+#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
+#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
+#define pCAN_MB06_DATA0                ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register  */
+#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
+#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
+#define pCAN_MB06_DATA1                ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
+#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
+#define pCAN_MB06_DATA2                ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
+#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
+#define pCAN_MB06_DATA3                ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
+#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
+#define pCAN_MB06_LENGTH               ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */
+#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
+#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
+#define pCAN_MB06_TIMESTAMP            ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */
+#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
+#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
+#define pCAN_MB06_ID0                  ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */
+#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
+#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
+#define pCAN_MB06_ID1                  ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */
+#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
+#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
+#define pCAN_MB07_DATA0                ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
+#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
+#define pCAN_MB07_DATA1                ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
+#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
+#define pCAN_MB07_DATA2                ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
+#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
+#define pCAN_MB07_DATA3                ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
+#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
+#define pCAN_MB07_LENGTH               ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */
+#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
+#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
+#define pCAN_MB07_TIMESTAMP            ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */
+#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
+#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
+#define pCAN_MB07_ID0                  ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */
+#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
+#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
+#define pCAN_MB07_ID1                  ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */
+#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
+#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
+#define pCAN_MB08_DATA0                ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
+#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
+#define pCAN_MB08_DATA1                ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
+#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
+#define pCAN_MB08_DATA2                ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
+#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
+#define pCAN_MB08_DATA3                ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
+#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
+#define pCAN_MB08_LENGTH               ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */
+#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
+#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
+#define pCAN_MB08_TIMESTAMP            ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */
+#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
+#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
+#define pCAN_MB08_ID0                  ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */
+#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
+#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
+#define pCAN_MB08_ID1                  ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */
+#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
+#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
+#define pCAN_MB09_DATA0                ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
+#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
+#define pCAN_MB09_DATA1                ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
+#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
+#define pCAN_MB09_DATA2                ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
+#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
+#define pCAN_MB09_DATA3                ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
+#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
+#define pCAN_MB09_LENGTH               ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */
+#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
+#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
+#define pCAN_MB09_TIMESTAMP            ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */
+#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
+#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
+#define pCAN_MB09_ID0                  ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */
+#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
+#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
+#define pCAN_MB09_ID1                  ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */
+#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
+#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
+#define pCAN_MB10_DATA0                ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
+#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
+#define pCAN_MB10_DATA1                ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
+#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
+#define pCAN_MB10_DATA2                ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
+#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
+#define pCAN_MB10_DATA3                ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
+#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
+#define pCAN_MB10_LENGTH               ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */
+#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
+#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
+#define pCAN_MB10_TIMESTAMP            ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */
+#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
+#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
+#define pCAN_MB10_ID0                  ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */
+#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
+#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
+#define pCAN_MB10_ID1                  ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */
+#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
+#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
+#define pCAN_MB11_DATA0                ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
+#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
+#define pCAN_MB11_DATA1                ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
+#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
+#define pCAN_MB11_DATA2                ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
+#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
+#define pCAN_MB11_DATA3                ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
+#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
+#define pCAN_MB11_LENGTH               ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */
+#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
+#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
+#define pCAN_MB11_TIMESTAMP            ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */
+#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
+#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
+#define pCAN_MB11_ID0                  ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */
+#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
+#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
+#define pCAN_MB11_ID1                  ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */
+#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
+#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
+#define pCAN_MB12_DATA0                ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
+#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
+#define pCAN_MB12_DATA1                ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
+#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
+#define pCAN_MB12_DATA2                ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
+#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
+#define pCAN_MB12_DATA3                ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
+#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
+#define pCAN_MB12_LENGTH               ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */
+#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
+#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
+#define pCAN_MB12_TIMESTAMP            ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */
+#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
+#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
+#define pCAN_MB12_ID0                  ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */
+#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
+#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
+#define pCAN_MB12_ID1                  ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */
+#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
+#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
+#define pCAN_MB13_DATA0                ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
+#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
+#define pCAN_MB13_DATA1                ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
+#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
+#define pCAN_MB13_DATA2                ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
+#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
+#define pCAN_MB13_DATA3                ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
+#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
+#define pCAN_MB13_LENGTH               ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */
+#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
+#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
+#define pCAN_MB13_TIMESTAMP            ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */
+#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
+#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
+#define pCAN_MB13_ID0                  ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */
+#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
+#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
+#define pCAN_MB13_ID1                  ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */
+#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
+#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
+#define pCAN_MB14_DATA0                ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
+#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
+#define pCAN_MB14_DATA1                ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
+#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
+#define pCAN_MB14_DATA2                ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
+#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
+#define pCAN_MB14_DATA3                ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
+#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
+#define pCAN_MB14_LENGTH               ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */
+#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
+#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
+#define pCAN_MB14_TIMESTAMP            ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */
+#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
+#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
+#define pCAN_MB14_ID0                  ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */
+#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
+#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
+#define pCAN_MB14_ID1                  ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */
+#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
+#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
+#define pCAN_MB15_DATA0                ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
+#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
+#define pCAN_MB15_DATA1                ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
+#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
+#define pCAN_MB15_DATA2                ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
+#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
+#define pCAN_MB15_DATA3                ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
+#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
+#define pCAN_MB15_LENGTH               ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */
+#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
+#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
+#define pCAN_MB15_TIMESTAMP            ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */
+#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
+#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
+#define pCAN_MB15_ID0                  ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */
+#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
+#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
+#define pCAN_MB15_ID1                  ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */
+#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
+#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
+#define pCAN_MB16_DATA0                ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
+#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
+#define pCAN_MB16_DATA1                ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
+#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
+#define pCAN_MB16_DATA2                ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
+#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
+#define pCAN_MB16_DATA3                ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
+#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
+#define pCAN_MB16_LENGTH               ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */
+#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
+#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
+#define pCAN_MB16_TIMESTAMP            ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */
+#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
+#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
+#define pCAN_MB16_ID0                  ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */
+#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
+#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
+#define pCAN_MB16_ID1                  ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */
+#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
+#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
+#define pCAN_MB17_DATA0                ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
+#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
+#define pCAN_MB17_DATA1                ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
+#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
+#define pCAN_MB17_DATA2                ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
+#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
+#define pCAN_MB17_DATA3                ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
+#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
+#define pCAN_MB17_LENGTH               ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */
+#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
+#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
+#define pCAN_MB17_TIMESTAMP            ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */
+#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
+#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
+#define pCAN_MB17_ID0                  ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */
+#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
+#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
+#define pCAN_MB17_ID1                  ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */
+#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
+#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
+#define pCAN_MB18_DATA0                ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
+#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
+#define pCAN_MB18_DATA1                ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
+#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
+#define pCAN_MB18_DATA2                ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
+#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
+#define pCAN_MB18_DATA3                ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
+#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
+#define pCAN_MB18_LENGTH               ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */
+#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
+#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
+#define pCAN_MB18_TIMESTAMP            ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */
+#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
+#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
+#define pCAN_MB18_ID0                  ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */
+#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
+#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
+#define pCAN_MB18_ID1                  ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */
+#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
+#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
+#define pCAN_MB19_DATA0                ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
+#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
+#define pCAN_MB19_DATA1                ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
+#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
+#define pCAN_MB19_DATA2                ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
+#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
+#define pCAN_MB19_DATA3                ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
+#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
+#define pCAN_MB19_LENGTH               ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */
+#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
+#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
+#define pCAN_MB19_TIMESTAMP            ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */
+#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
+#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
+#define pCAN_MB19_ID0                  ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */
+#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
+#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
+#define pCAN_MB19_ID1                  ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */
+#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
+#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
+#define pCAN_MB20_DATA0                ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
+#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
+#define pCAN_MB20_DATA1                ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
+#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
+#define pCAN_MB20_DATA2                ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
+#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
+#define pCAN_MB20_DATA3                ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
+#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
+#define pCAN_MB20_LENGTH               ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */
+#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
+#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
+#define pCAN_MB20_TIMESTAMP            ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */
+#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
+#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
+#define pCAN_MB20_ID0                  ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */
+#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
+#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
+#define pCAN_MB20_ID1                  ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */
+#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
+#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
+#define pCAN_MB21_DATA0                ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
+#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
+#define pCAN_MB21_DATA1                ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
+#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
+#define pCAN_MB21_DATA2                ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
+#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
+#define pCAN_MB21_DATA3                ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
+#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
+#define pCAN_MB21_LENGTH               ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */
+#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
+#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
+#define pCAN_MB21_TIMESTAMP            ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */
+#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
+#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
+#define pCAN_MB21_ID0                  ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */
+#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
+#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
+#define pCAN_MB21_ID1                  ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */
+#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
+#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
+#define pCAN_MB22_DATA0                ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
+#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
+#define pCAN_MB22_DATA1                ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
+#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
+#define pCAN_MB22_DATA2                ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
+#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
+#define pCAN_MB22_DATA3                ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
+#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
+#define pCAN_MB22_LENGTH               ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */
+#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
+#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
+#define pCAN_MB22_TIMESTAMP            ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */
+#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
+#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
+#define pCAN_MB22_ID0                  ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */
+#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
+#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
+#define pCAN_MB22_ID1                  ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */
+#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
+#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
+#define pCAN_MB23_DATA0                ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
+#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
+#define pCAN_MB23_DATA1                ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
+#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
+#define pCAN_MB23_DATA2                ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
+#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
+#define pCAN_MB23_DATA3                ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
+#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
+#define pCAN_MB23_LENGTH               ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */
+#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
+#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
+#define pCAN_MB23_TIMESTAMP            ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */
+#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
+#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
+#define pCAN_MB23_ID0                  ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */
+#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
+#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
+#define pCAN_MB23_ID1                  ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */
+#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
+#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
+#define pCAN_MB24_DATA0                ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
+#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
+#define pCAN_MB24_DATA1                ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
+#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
+#define pCAN_MB24_DATA2                ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
+#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
+#define pCAN_MB24_DATA3                ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
+#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
+#define pCAN_MB24_LENGTH               ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */
+#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
+#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
+#define pCAN_MB24_TIMESTAMP            ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */
+#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
+#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
+#define pCAN_MB24_ID0                  ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */
+#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
+#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
+#define pCAN_MB24_ID1                  ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */
+#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
+#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
+#define pCAN_MB25_DATA0                ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
+#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
+#define pCAN_MB25_DATA1                ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
+#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
+#define pCAN_MB25_DATA2                ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
+#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
+#define pCAN_MB25_DATA3                ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
+#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
+#define pCAN_MB25_LENGTH               ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */
+#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
+#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
+#define pCAN_MB25_TIMESTAMP            ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */
+#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
+#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
+#define pCAN_MB25_ID0                  ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */
+#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
+#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
+#define pCAN_MB25_ID1                  ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */
+#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
+#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
+#define pCAN_MB26_DATA0                ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
+#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
+#define pCAN_MB26_DATA1                ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
+#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
+#define pCAN_MB26_DATA2                ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
+#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
+#define pCAN_MB26_DATA3                ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
+#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
+#define pCAN_MB26_LENGTH               ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */
+#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
+#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
+#define pCAN_MB26_TIMESTAMP            ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */
+#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
+#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
+#define pCAN_MB26_ID0                  ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */
+#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
+#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
+#define pCAN_MB26_ID1                  ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */
+#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
+#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
+#define pCAN_MB27_DATA0                ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
+#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
+#define pCAN_MB27_DATA1                ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
+#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
+#define pCAN_MB27_DATA2                ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
+#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
+#define pCAN_MB27_DATA3                ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
+#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
+#define pCAN_MB27_LENGTH               ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */
+#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
+#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
+#define pCAN_MB27_TIMESTAMP            ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */
+#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
+#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
+#define pCAN_MB27_ID0                  ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */
+#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
+#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
+#define pCAN_MB27_ID1                  ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */
+#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
+#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
+#define pCAN_MB28_DATA0                ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
+#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
+#define pCAN_MB28_DATA1                ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
+#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
+#define pCAN_MB28_DATA2                ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
+#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
+#define pCAN_MB28_DATA3                ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
+#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
+#define pCAN_MB28_LENGTH               ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */
+#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
+#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
+#define pCAN_MB28_TIMESTAMP            ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */
+#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
+#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
+#define pCAN_MB28_ID0                  ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */
+#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
+#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
+#define pCAN_MB28_ID1                  ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */
+#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
+#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
+#define pCAN_MB29_DATA0                ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
+#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
+#define pCAN_MB29_DATA1                ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
+#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
+#define pCAN_MB29_DATA2                ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
+#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
+#define pCAN_MB29_DATA3                ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
+#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
+#define pCAN_MB29_LENGTH               ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */
+#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
+#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
+#define pCAN_MB29_TIMESTAMP            ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */
+#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
+#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
+#define pCAN_MB29_ID0                  ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */
+#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
+#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
+#define pCAN_MB29_ID1                  ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */
+#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
+#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
+#define pCAN_MB30_DATA0                ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
+#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
+#define pCAN_MB30_DATA1                ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
+#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
+#define pCAN_MB30_DATA2                ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
+#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
+#define pCAN_MB30_DATA3                ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
+#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
+#define pCAN_MB30_LENGTH               ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */
+#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
+#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
+#define pCAN_MB30_TIMESTAMP            ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */
+#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
+#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
+#define pCAN_MB30_ID0                  ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */
+#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
+#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
+#define pCAN_MB30_ID1                  ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */
+#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
+#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
+#define pCAN_MB31_DATA0                ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */
+#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
+#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
+#define pCAN_MB31_DATA1                ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */
+#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
+#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
+#define pCAN_MB31_DATA2                ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */
+#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
+#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
+#define pCAN_MB31_DATA3                ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */
+#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
+#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
+#define pCAN_MB31_LENGTH               ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */
+#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
+#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
+#define pCAN_MB31_TIMESTAMP            ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */
+#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
+#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
+#define pCAN_MB31_ID0                  ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */
+#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
+#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
+#define pCAN_MB31_ID1                  ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */
+#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
+#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORT_MUX                      ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */
+#define bfin_read_PORT_MUX()           bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)       bfin_write16(PORT_MUX, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR)
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
+#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
+#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
+#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF534_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h
new file mode 100644
index 0000000..61ffa14
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h
@@ -0,0 +1,924 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__
+#define __BFIN_DEF_ADSP_EDN_BF534_extended__
+
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration Register */
+#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
+#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
+#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
+#define SPI_STAT                       0xFFC00508 /* SPI Status register */
+#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
+#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
+#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
+#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
+#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
+#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
+#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
+#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
+#define CAN_MC1                        0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1                        0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1                       0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1                       0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1                        0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1                        0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1                       0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1                       0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1                     0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1                     0xFFC02A24 /* Mailbox Receive  Interrupt Flag reg 1 */
+#define CAN_MBIM1                      0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1                       0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1                      0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
+#define CAN_MC2                        0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2                        0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2                       0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2                       0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2                        0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2                        0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2                       0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2                       0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2                     0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2                     0xFFC02A64 /* Mailbox Receive  Interrupt Flag reg 2 */
+#define CAN_MBIM2                      0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2                       0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2                      0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
+#define CAN_CLOCK                      0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING                     0xFFC02A84 /* Bit Timing Configuration register 1 */
+#define CAN_DEBUG                      0xFFC02A88 /* Config register */
+#define CAN_STATUS                     0xFFC02A8C /* Global Status Register */
+#define CAN_CEC                        0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS                        0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM                        0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF                        0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL                    0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR                       0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_VERSION                    0xFFC02AA8 /* Version Code Register */
+#define CAN_MBTD                       0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR                        0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR                        0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG                      0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT                      0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC                       0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF                      0xFFC02ACC /* Universal Counter Configuration Register */
+#define CAN_VERSION2                   0xFFC02AD4 /* Version Code Register 2 */
+#define CAN_AM00L                      0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H                      0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L                      0xFFC02B08 /* Mailbox 1 Low Acceptance Mask  */
+#define CAN_AM01H                      0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L                      0xFFC02B10 /* Mailbox 2 Low Acceptance Mask  */
+#define CAN_AM02H                      0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L                      0xFFC02B18 /* Mailbox 3 Low Acceptance Mask  */
+#define CAN_AM03H                      0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L                      0xFFC02B20 /* Mailbox 4 Low Acceptance Mask  */
+#define CAN_AM04H                      0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L                      0xFFC02B28 /* Mailbox 5 Low Acceptance Mask  */
+#define CAN_AM05H                      0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L                      0xFFC02B30 /* Mailbox 6 Low Acceptance Mask  */
+#define CAN_AM06H                      0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L                      0xFFC02B38 /* Mailbox 7 Low Acceptance Mask  */
+#define CAN_AM07H                      0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L                      0xFFC02B40 /* Mailbox 8 Low Acceptance Mask  */
+#define CAN_AM08H                      0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L                      0xFFC02B48 /* Mailbox 9 Low Acceptance Mask  */
+#define CAN_AM09H                      0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L                      0xFFC02B50 /* Mailbox 10 Low Acceptance Mask  */
+#define CAN_AM10H                      0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L                      0xFFC02B58 /* Mailbox 11 Low Acceptance Mask  */
+#define CAN_AM11H                      0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L                      0xFFC02B60 /* Mailbox 12 Low Acceptance Mask  */
+#define CAN_AM12H                      0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L                      0xFFC02B68 /* Mailbox 13 Low Acceptance Mask  */
+#define CAN_AM13H                      0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L                      0xFFC02B70 /* Mailbox 14 Low Acceptance Mask  */
+#define CAN_AM14H                      0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L                      0xFFC02B78 /* Mailbox 15 Low Acceptance Mask  */
+#define CAN_AM15H                      0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+#define CAN_AM16L                      0xFFC02B80 /* Mailbox 16 Low Acceptance Mask  */
+#define CAN_AM16H                      0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L                      0xFFC02B88 /* Mailbox 17 Low Acceptance Mask  */
+#define CAN_AM17H                      0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L                      0xFFC02B90 /* Mailbox 18 Low Acceptance Mask  */
+#define CAN_AM18H                      0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L                      0xFFC02B98 /* Mailbox 19 Low Acceptance Mask  */
+#define CAN_AM19H                      0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L                      0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask  */
+#define CAN_AM20H                      0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L                      0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask  */
+#define CAN_AM21H                      0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L                      0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask  */
+#define CAN_AM22H                      0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L                      0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask  */
+#define CAN_AM23H                      0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L                      0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask  */
+#define CAN_AM24H                      0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L                      0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask  */
+#define CAN_AM25H                      0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L                      0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask  */
+#define CAN_AM26H                      0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L                      0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask  */
+#define CAN_AM27H                      0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L                      0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask  */
+#define CAN_AM28H                      0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L                      0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask  */
+#define CAN_AM29H                      0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L                      0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask  */
+#define CAN_AM30H                      0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L                      0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask  */
+#define CAN_AM31H                      0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+#define CAN_MB00_DATA0                 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1                 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2                 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3                 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH                0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP             0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0                   0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1                   0xFFC02C1C /* Mailbox 0 Identifier High Register */
+#define CAN_MB01_DATA0                 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register  */
+#define CAN_MB01_DATA1                 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2                 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3                 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH                0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP             0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0                   0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1                   0xFFC02C3C /* Mailbox 1 Identifier High Register */
+#define CAN_MB02_DATA0                 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register  */
+#define CAN_MB02_DATA1                 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2                 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3                 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH                0xFFC02C50 /* Mailbox 2 Data Length Code Register    */
+#define CAN_MB02_TIMESTAMP             0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0                   0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1                   0xFFC02C5C /* Mailbox 2 Identifier High Register */
+#define CAN_MB03_DATA0                 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register  */
+#define CAN_MB03_DATA1                 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2                 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3                 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH                0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP             0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0                   0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1                   0xFFC02C7C /* Mailbox 3 Identifier High Register */
+#define CAN_MB04_DATA0                 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1                 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2                 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3                 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH                0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP             0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0                   0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1                   0xFFC02C9C /* Mailbox 4 Identifier High Register */
+#define CAN_MB05_DATA0                 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register  */
+#define CAN_MB05_DATA1                 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2                 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3                 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH                0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP             0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0                   0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1                   0xFFC02CBC /* Mailbox 5 Identifier High Register */
+#define CAN_MB06_DATA0                 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register  */
+#define CAN_MB06_DATA1                 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2                 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3                 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH                0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP             0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0                   0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1                   0xFFC02CDC /* Mailbox 6 Identifier High Register */
+#define CAN_MB07_DATA0                 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1                 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2                 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3                 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH                0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP             0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0                   0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1                   0xFFC02CFC /* Mailbox 7 Identifier High Register */
+#define CAN_MB08_DATA0                 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1                 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2                 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3                 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH                0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP             0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0                   0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1                   0xFFC02D1C /* Mailbox 8 Identifier High Register */
+#define CAN_MB09_DATA0                 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1                 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2                 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3                 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH                0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP             0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0                   0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1                   0xFFC02D3C /* Mailbox 9 Identifier High Register */
+#define CAN_MB10_DATA0                 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1                 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2                 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3                 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH                0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP             0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0                   0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1                   0xFFC02D5C /* Mailbox 10 Identifier High Register */
+#define CAN_MB11_DATA0                 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1                 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2                 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3                 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH                0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP             0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0                   0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1                   0xFFC02D7C /* Mailbox 11 Identifier High Register */
+#define CAN_MB12_DATA0                 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1                 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2                 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3                 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH                0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP             0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0                   0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1                   0xFFC02D9C /* Mailbox 12 Identifier High Register */
+#define CAN_MB13_DATA0                 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1                 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2                 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3                 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH                0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP             0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0                   0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1                   0xFFC02DBC /* Mailbox 13 Identifier High Register */
+#define CAN_MB14_DATA0                 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1                 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2                 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3                 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH                0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP             0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0                   0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1                   0xFFC02DDC /* Mailbox 14 Identifier High Register */
+#define CAN_MB15_DATA0                 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1                 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2                 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3                 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH                0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP             0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0                   0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1                   0xFFC02DFC /* Mailbox 15 Identifier High Register */
+#define CAN_MB16_DATA0                 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1                 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2                 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3                 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH                0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP             0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0                   0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1                   0xFFC02E1C /* Mailbox 16 Identifier High Register */
+#define CAN_MB17_DATA0                 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1                 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2                 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3                 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH                0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP             0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0                   0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1                   0xFFC02E3C /* Mailbox 17 Identifier High Register */
+#define CAN_MB18_DATA0                 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1                 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2                 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3                 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH                0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP             0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0                   0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1                   0xFFC02E5C /* Mailbox 18 Identifier High Register */
+#define CAN_MB19_DATA0                 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1                 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2                 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3                 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH                0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP             0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0                   0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1                   0xFFC02E7C /* Mailbox 19 Identifier High Register */
+#define CAN_MB20_DATA0                 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1                 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2                 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3                 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH                0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP             0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0                   0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1                   0xFFC02E9C /* Mailbox 20 Identifier High Register */
+#define CAN_MB21_DATA0                 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1                 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2                 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3                 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH                0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP             0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0                   0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1                   0xFFC02EBC /* Mailbox 21 Identifier High Register */
+#define CAN_MB22_DATA0                 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1                 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2                 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3                 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH                0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP             0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0                   0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1                   0xFFC02EDC /* Mailbox 22 Identifier High Register */
+#define CAN_MB23_DATA0                 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1                 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2                 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3                 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH                0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP             0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0                   0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1                   0xFFC02EFC /* Mailbox 23 Identifier High Register */
+#define CAN_MB24_DATA0                 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1                 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2                 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3                 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH                0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP             0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0                   0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1                   0xFFC02F1C /* Mailbox 24 Identifier High Register */
+#define CAN_MB25_DATA0                 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1                 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2                 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3                 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH                0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP             0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0                   0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1                   0xFFC02F3C /* Mailbox 25 Identifier High Register */
+#define CAN_MB26_DATA0                 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1                 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2                 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3                 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH                0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP             0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0                   0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1                   0xFFC02F5C /* Mailbox 26 Identifier High Register */
+#define CAN_MB27_DATA0                 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1                 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2                 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3                 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH                0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP             0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0                   0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1                   0xFFC02F7C /* Mailbox 27 Identifier High Register */
+#define CAN_MB28_DATA0                 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1                 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2                 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3                 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH                0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP             0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0                   0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1                   0xFFC02F9C /* Mailbox 28 Identifier High Register */
+#define CAN_MB29_DATA0                 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1                 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2                 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3                 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH                0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP             0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0                   0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1                   0xFFC02FBC /* Mailbox 29 Identifier High Register */
+#define CAN_MB30_DATA0                 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1                 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2                 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3                 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH                0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP             0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0                   0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1                   0xFFC02FDC /* Mailbox 30 Identifier High Register */
+#define CAN_MB31_DATA0                 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1                 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2                 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3                 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH                0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP             0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0                   0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1                   0xFFC02FFC /* Mailbox 31 Identifier High Register */
+#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define PORT_MUX                       0xFFC0320C /* Port Multiplexer Control Register */
+#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
+#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* L1 Data Memory Controller Register */
+#define DCPLB_FAULT_ADDR               0xFFE0000C
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008
+#define ICPLB_FAULT_ADDR               0xFFE0100C
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define CHIPID                         0xFFC00014
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define DMA_TC_CNT                     0xFFC00B0C
+#define DMA_TC_PER                     0xFFC00B10
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF534_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
new file mode 100644
index 0000000..27842cc
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF534_cdef.h
@@ -0,0 +1,14 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF534_proc__
+#define __BFIN_CDEF_ADSP_BF534_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF534-extended_cdef.h"
+
+
+#endif /* __BFIN_CDEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h
new file mode 100644
index 0000000..5f0437b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF534_def.h
@@ -0,0 +1,29 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF534_proc__
+#define __BFIN_DEF_ADSP_BF534_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF534-extended_def.h"
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF534_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
new file mode 100644
index 0000000..d753b5e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
@@ -0,0 +1,251 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF536_proc__
+#define __BFIN_CDEF_ADSP_BF536_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF534-extended_cdef.h"
+
+#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
+#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
+#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
+#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
+#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
+#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
+#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
+#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
+#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
+#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
+#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
+#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
+#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
+#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
+#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
+#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
+#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
+#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
+#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
+#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
+#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
+#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
+#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
+#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
+#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
+#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
+#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
+#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
+#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
+#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
+#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
+#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
+#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
+#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
+#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
+#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
+#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
+#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
+#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
+#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
+#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
+#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
+#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
+#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
+#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
+#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
+#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
+#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
+#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
+#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
+#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
+#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
+#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
+#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
+#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
+#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
+#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
+#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
+#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
+#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
+#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
+#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
+#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
+#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
+#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
+#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
+#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
+#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
+#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
+#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
+#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
+#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
+#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
+#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
+#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
+#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
+#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
+#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
+#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
+#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
+#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
+#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
+#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
+#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
+#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
+#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
+#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
+#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
+#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
+#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
+#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
+#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
+#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
+#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
+#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
+#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
+#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
+#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
+#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
+#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
+#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
+#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
+#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
+#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
+#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
+#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
+#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
+#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
+#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
+#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
+#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
+#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
+#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
+#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
+#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
+#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
+#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
+#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
+#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
+#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
+#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
+#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
+#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
+#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
+#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
+#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
+#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_def.h b/arch/blackfin/include/asm/mach-bf537/BF536_def.h
new file mode 100644
index 0000000..810fe91
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF536_def.h
@@ -0,0 +1,102 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF536_proc__
+#define __BFIN_DEF_ADSP_BF536_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF534-extended_def.h"
+
+#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
+#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
+#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF536_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
new file mode 100644
index 0000000..5eff57d
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
@@ -0,0 +1,251 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF537_proc__
+#define __BFIN_CDEF_ADSP_BF537_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF534-extended_cdef.h"
+
+#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
+#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
+#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
+#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
+#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
+#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
+#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
+#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
+#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
+#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
+#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
+#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
+#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
+#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
+#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
+#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
+#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
+#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
+#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
+#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
+#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
+#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
+#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
+#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
+#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
+#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
+#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
+#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
+#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
+#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
+#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
+#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
+#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
+#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
+#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
+#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
+#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
+#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
+#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
+#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
+#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
+#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
+#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
+#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
+#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
+#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
+#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
+#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
+#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
+#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
+#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
+#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
+#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
+#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
+#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
+#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
+#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
+#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
+#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
+#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
+#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
+#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
+#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
+#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
+#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
+#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
+#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
+#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
+#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
+#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
+#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
+#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
+#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
+#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
+#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
+#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
+#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
+#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
+#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
+#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
+#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
+#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
+#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
+#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
+#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
+#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
+#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
+#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
+#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
+#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
+#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
+#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
+#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
+#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
+#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
+#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
+#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
+#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
+#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
+#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
+#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
+#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
+#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
+#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
+#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
+#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
+#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
+#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
+#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
+#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
+#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
+#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
+#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
+#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
+#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
+#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
+#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
+#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
+#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
+#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
+#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
+#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
+#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
+#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
+#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
+#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
+#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
+#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
+#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
+#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
+#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
+#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
+#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
+#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
+#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
+#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
+#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
+#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF537_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_def.h b/arch/blackfin/include/asm/mach-bf537/BF537_def.h
new file mode 100644
index 0000000..030fa64
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/BF537_def.h
@@ -0,0 +1,108 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF537_proc__
+#define __BFIN_DEF_ADSP_BF537_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF534-extended_def.h"
+
+#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
+#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
+#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
+#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF537_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h
new file mode 100644
index 0000000..b7f1a3f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h
@@ -0,0 +1,182 @@
+/*
+ * File: include/asm-blackfin/mach-bf537/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file should be up to date with:
+ *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 silicon - sorry */
+#if __SILICON_REVISION__ < 2
+# error will not work on BF537 silicon version 0.0 or 0.1
+#endif
+
+#if defined(__ADSPBF534__)
+# define ANOMALY_BF534 1
+#else
+# define ANOMALY_BF534 0
+#endif
+#if defined(__ADSPBF536__)
+# define ANOMALY_BF536 1
+#else
+# define ANOMALY_BF536 0
+#endif
+#if defined(__ADSPBF537__)
+# define ANOMALY_BF537 1
+#else
+# define ANOMALY_BF537 0
+#endif
+
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
+#define ANOMALY_05000247 (1)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
+/* EMAC Tx DMA error after an early frame abort */
+#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
+/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
+#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
+/* EMAC MDIO input latched on wrong MDC edge */
+#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
+#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM Memory May Be Lost */
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
+/* SPI Master boot mode does not work well with Atmel Data flash devices */
+#define ANOMALY_05000280 (1)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
+/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
+#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
+/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
+#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode: collisions occur in Full Duplex mode */
+#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
+#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
+#define ANOMALY_05000322 (1)
+/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
+#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
+/* New Feature: UART Remains Enabled after UART Boot */
+#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000359 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
+#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000430 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf537/def_local.h b/arch/blackfin/include/asm/mach-bf537/def_local.h
new file mode 100644
index 0000000..14c111f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/def_local.h
@@ -0,0 +1 @@
+#include "ports.h"
diff --git a/arch/blackfin/include/asm/mach-bf537/ports.h b/arch/blackfin/include/asm/mach-bf537/ports.h
new file mode 100644
index 0000000..2f62934
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf537/ports.h
@@ -0,0 +1,28 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORT_MUX Masks */
+#define PJSE			0x0001
+#define PJCE_MASK		0x0006
+#define PJCE_SPORT		0x0000
+#define PJCE_CAN		0x0001
+#define PJCE_SPI		0x0002
+#define PFDE			0x0008
+#define PFTE			0x0010
+#define PFS6E			0x0020
+#define PFS5E			0x0040
+#define PFS4E			0x0080
+#define PFFE			0x0100
+#define PGSE			0x0200
+#define PGRE			0x0400
+#define PGTE			0x0800
+
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
new file mode 100644
index 0000000..51d9cf2
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
@@ -0,0 +1,4378 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF542_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
new file mode 100644
index 0000000..f294a85
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h
@@ -0,0 +1,1467 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__
+#define __BFIN_DEF_ADSP_EDN_BF542_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF542_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
new file mode 100644
index 0000000..4c0fdf5
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
@@ -0,0 +1,4972 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF544_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
new file mode 100644
index 0000000..3c14d22
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h
@@ -0,0 +1,1665 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF544_extended__
+#define __BFIN_DEF_ADSP_EDN_BF544_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF544_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
new file mode 100644
index 0000000..e0f76ae
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
@@ -0,0 +1,3615 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF547_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
new file mode 100644
index 0000000..0e48279
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h
@@ -0,0 +1,1213 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF547_extended__
+#define __BFIN_DEF_ADSP_EDN_BF547_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF547_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
new file mode 100644
index 0000000..caf2f6f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
@@ -0,0 +1,5787 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF548_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
new file mode 100644
index 0000000..a92479b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h
@@ -0,0 +1,1937 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF548_extended__
+#define __BFIN_DEF_ADSP_EDN_BF548_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF548_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
new file mode 100644
index 0000000..af90e4c
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
@@ -0,0 +1,6135 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
+#define __BFIN_CDEF_ADSP_EDN_BF549_extended__
+
+#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
+#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
+#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
+#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
+#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
+#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
+#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
+#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
+#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
+#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
+#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
+#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
+#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
+#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
+#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
+#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
+#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
+#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
+#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
+#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
+#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
+#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
+#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
+#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
+#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
+#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
+#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
+#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
+#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
+#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
+#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
+#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
+#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
+#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
+#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
+#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
+#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
+#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
+#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
+#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
+#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
+#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
+#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
+#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
+#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
+#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
+#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
+#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
+#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
+#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
+#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
+#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
+#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
+#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
+#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
+#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
+#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
+#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
+#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
+#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
+#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
+#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
+#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
+#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
+#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
+#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
+#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
+#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
+#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
+#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
+#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
+#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
+#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
+#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
+#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
+#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
+#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
+#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
+#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
+#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
+#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
+#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
+#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
+#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
+#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
+#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
+#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
+#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
+#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
+#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
+#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
+#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
+#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
+#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
+#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
+#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
+#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
+#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
+#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
+#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
+#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
+#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
+#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
+#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
+#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
+#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
+#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
+#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
+#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
+#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
+#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
+#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
+#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
+#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
+#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
+#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
+#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
+#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
+#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
+#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
+#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
+#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
+#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
+#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
+#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
+#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
+#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
+#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
+#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
+#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
+#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
+#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
+#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
+#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
+#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
+#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
+#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
+#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
+#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
+#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
+#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
+#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
+#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
+#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
+#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
+#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
+#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
+#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
+#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
+#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
+#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
+#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
+#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
+#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
+#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
+#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
+#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
+#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
+#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
+#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
+#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
+#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
+#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
+#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
+#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
+#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
+#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
+#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
+#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
+#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
+#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
+#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
+#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
+#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
+#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
+#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
+#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
+#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
+#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
+#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
+#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
+#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
+#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
+#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
+#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
+#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
+#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
+#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
+#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
+#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
+#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
+#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
+#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
+#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
+#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
+#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
+#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
+#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
+#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
+#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
+#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
+#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
+#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
+#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
+#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
+#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
+#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
+#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
+#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
+#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
+#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
+#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
+#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
+#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
+#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
+#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
+#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
+#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
+#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
+#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
+#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
+#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
+#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
+#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
+#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
+#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
+#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
+#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
+#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
+#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
+#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
+#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
+#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
+#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
+#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
+#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
+#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
+#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
+#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
+#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
+#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
+#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
+#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
+#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
+#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
+#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
+#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
+#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
+#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
+#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
+#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
+#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
+#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
+#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
+#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
+#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
+#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
+#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
+#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
+#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
+#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
+#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
+#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
+#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
+#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
+#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
+#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
+#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
+#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
+#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
+#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
+#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
+#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
+#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
+#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
+#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
+#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
+#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
+#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
+#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
+#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
+#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
+#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
+#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
+#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
+#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
+#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
+#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
+#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
+#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
+#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
+#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
+#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
+#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
+#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
+#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
+#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
+#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
+#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
+#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
+#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
+#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
+#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
+#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
+#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
+#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
+#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
+#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
+#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
+#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
+#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
+#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
+#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
+#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
+#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
+#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
+#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
+#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
+#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
+#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
+#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
+#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
+#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
+#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
+#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
+#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
+#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
+#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
+#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
+#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
+#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
+#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
+#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
+#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
+#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
+#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
+#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
+#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
+#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
+#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
+#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
+#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
+#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
+#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
+#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
+#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
+#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
+#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
+#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
+#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
+#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
+#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
+#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
+#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
+#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
+#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
+#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
+#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
+#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
+#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
+#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
+#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
+#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
+#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
+#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
+#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
+#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
+#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
+#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
+#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
+#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
+#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
+#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
+#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
+#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
+#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
+#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
+#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
+#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
+#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
+#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
+#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
+#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
+#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
+#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
+#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
+#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
+#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
+#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
+#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
+#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
+#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
+#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
+#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
+#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
+#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
+#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
+#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
+#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
+#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
+#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
+#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
+#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
+#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
+#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
+#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
+#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
+#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
+#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
+#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
+#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
+#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
+#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
+#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
+#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
+#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
+#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
+#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
+#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
+#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
+#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
+#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
+#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
+#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
+#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
+#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
+#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
+#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
+#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
+#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
+#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
+#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
+#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
+#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
+#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
+#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
+#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
+#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
+#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
+#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
+#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
+#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
+#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
+#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
+#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
+#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
+#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
+#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
+#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
+#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
+#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
+#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
+#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
+#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
+#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
+#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
+#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
+#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
+#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
+#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
+#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
+#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
+#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
+#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
+#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
+#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
+#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
+#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
+#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
+#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
+#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
+#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
+#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
+#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
+#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
+#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
+#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
+#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
+#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
+#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
+#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
+#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
+#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
+#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
+#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
+#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
+#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
+#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
+#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
+#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
+#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
+#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
+#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
+#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
+#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
+#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
+#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
+#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
+#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
+#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
+#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
+#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
+#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
+#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
+#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
+#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
+#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
+#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
+#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
+#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
+#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
+#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
+#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
+#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
+#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
+#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
+#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
+#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
+#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
+#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
+#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
+#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
+#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
+#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
+#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
+#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
+#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
+#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
+#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
+#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
+#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
+#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
+#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
+#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
+#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
+#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
+#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
+#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
+#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
+#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
+#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
+#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
+#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
+#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
+#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
+#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
+#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
+#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
+#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
+#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
+#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
+#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
+#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
+#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
+#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
+#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
+#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
+#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
+#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
+#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
+#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
+#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
+#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
+#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
+#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
+#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
+#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
+#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
+#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
+#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
+#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
+#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
+#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
+#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
+#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
+#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
+#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
+#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
+#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
+#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
+#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
+#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
+#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
+#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
+#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
+#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
+#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
+#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
+#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
+#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
+#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
+#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
+#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
+#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
+#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
+#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
+#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
+#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
+#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
+#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
+#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
+#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
+#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
+#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
+#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
+#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
+#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
+#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
+#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
+#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
+#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
+#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
+#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
+#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
+#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
+#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
+#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
+#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
+#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
+#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
+#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
+#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
+#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
+#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
+#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
+#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
+#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
+#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
+#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
+#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
+#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
+#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
+#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
+#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
+#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
+#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
+#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
+#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
+#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
+#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
+#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
+#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
+#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
+#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
+#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
+#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
+#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
+#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
+#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
+#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
+#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
+#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
+#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
+#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
+#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
+#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
+#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
+#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
+#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
+#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
+#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
+#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
+#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
+#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
+#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
+#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
+#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
+#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
+#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
+#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
+#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
+#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
+#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
+#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
+#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
+#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
+#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
+#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
+#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
+#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
+#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
+#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
+#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
+#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
+#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
+#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
+#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
+#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
+#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
+#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
+#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
+#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
+#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
+#define bfin_read_PORTA()              bfin_read16(PORTA)
+#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
+#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
+#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
+#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
+#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
+#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
+#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
+#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
+#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
+#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
+#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
+#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
+#define bfin_read_PORTB()              bfin_read16(PORTB)
+#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
+#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
+#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
+#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
+#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
+#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
+#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
+#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
+#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
+#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
+#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
+#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
+#define bfin_read_PORTC()              bfin_read16(PORTC)
+#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
+#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
+#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
+#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
+#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
+#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
+#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
+#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
+#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
+#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
+#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
+#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
+#define bfin_read_PORTD()              bfin_read16(PORTD)
+#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
+#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
+#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
+#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
+#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
+#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
+#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
+#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
+#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
+#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
+#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
+#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
+#define bfin_read_PORTE()              bfin_read16(PORTE)
+#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
+#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
+#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
+#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
+#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
+#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
+#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
+#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
+#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
+#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
+#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
+#define bfin_read_PORTF()              bfin_read16(PORTF)
+#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
+#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
+#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
+#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
+#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
+#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
+#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
+#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
+#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
+#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
+#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
+#define bfin_read_PORTG()              bfin_read16(PORTG)
+#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
+#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
+#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
+#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
+#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
+#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
+#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
+#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
+#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
+#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
+#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
+#define bfin_read_PORTH()              bfin_read16(PORTH)
+#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
+#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
+#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
+#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
+#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
+#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
+#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
+#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
+#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
+#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
+#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
+#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
+#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
+#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
+#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
+#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
+#define bfin_read_PORTI()              bfin_read16(PORTI)
+#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
+#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
+#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
+#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
+#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
+#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
+#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
+#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
+#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
+#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
+#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
+#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
+#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
+#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
+#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
+#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
+#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
+#define bfin_read_PORTJ()              bfin_read16(PORTJ)
+#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
+#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
+#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
+#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
+#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
+#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
+#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
+#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
+#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
+#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
+#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
+#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
+#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
+#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
+#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
+#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
+#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
+#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
+#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
+#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
+#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
+#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
+#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
+#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
+#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
+#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
+#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
+#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
+#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
+#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
+#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
+#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
+#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
+#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
+#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
+#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
+#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
+#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
+#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
+#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
+#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
+#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
+#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
+#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
+#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
+#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
+#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
+#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
+#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
+#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
+#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
+#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
+#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
+#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
+#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
+#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
+#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
+#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
+#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
+#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
+#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
+#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
+#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
+#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
+#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
+#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
+#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
+#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
+#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
+#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
+#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
+#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
+#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
+#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
+#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
+#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
+#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
+#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
+#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
+#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
+#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
+#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
+#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
+#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
+#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
+#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
+#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
+#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
+#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
+#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
+#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
+#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
+#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
+#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
+#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
+#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
+#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
+#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
+#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
+#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
+#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
+#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
+#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
+#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
+#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
+#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
+#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
+#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
+#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
+#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
+#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
+#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
+#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
+#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
+#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
+#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
+#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
+#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
+#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
+#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
+#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
+#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
+#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
+#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
+#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
+#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
+#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
+#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
+#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
+#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
+#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
+#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
+#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
+#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
+#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
+#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
+#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
+#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
+#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
+#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
+#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
+#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
+#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
+#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
+#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
+#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
+#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
+#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pMXVR_CONFIG                   ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */
+#define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
+#define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
+#define pMXVR_STATE_0                  ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */
+#define bfin_read_MXVR_STATE_0()       bfin_read32(MXVR_STATE_0)
+#define bfin_write_MXVR_STATE_0(val)   bfin_write32(MXVR_STATE_0, val)
+#define pMXVR_STATE_1                  ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */
+#define bfin_read_MXVR_STATE_1()       bfin_read32(MXVR_STATE_1)
+#define bfin_write_MXVR_STATE_1(val)   bfin_write32(MXVR_STATE_1, val)
+#define pMXVR_INT_STAT_0               ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */
+#define bfin_read_MXVR_INT_STAT_0()    bfin_read32(MXVR_INT_STAT_0)
+#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
+#define pMXVR_INT_STAT_1               ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */
+#define bfin_read_MXVR_INT_STAT_1()    bfin_read32(MXVR_INT_STAT_1)
+#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
+#define pMXVR_INT_EN_0                 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */
+#define bfin_read_MXVR_INT_EN_0()      bfin_read32(MXVR_INT_EN_0)
+#define bfin_write_MXVR_INT_EN_0(val)  bfin_write32(MXVR_INT_EN_0, val)
+#define pMXVR_INT_EN_1                 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */
+#define bfin_read_MXVR_INT_EN_1()      bfin_read32(MXVR_INT_EN_1)
+#define bfin_write_MXVR_INT_EN_1(val)  bfin_write32(MXVR_INT_EN_1, val)
+#define pMXVR_POSITION                 ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */
+#define bfin_read_MXVR_POSITION()      bfin_read16(MXVR_POSITION)
+#define bfin_write_MXVR_POSITION(val)  bfin_write16(MXVR_POSITION, val)
+#define pMXVR_MAX_POSITION             ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */
+#define bfin_read_MXVR_MAX_POSITION()  bfin_read16(MXVR_MAX_POSITION)
+#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
+#define pMXVR_DELAY                    ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */
+#define bfin_read_MXVR_DELAY()         bfin_read16(MXVR_DELAY)
+#define bfin_write_MXVR_DELAY(val)     bfin_write16(MXVR_DELAY, val)
+#define pMXVR_MAX_DELAY                ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */
+#define bfin_read_MXVR_MAX_DELAY()     bfin_read16(MXVR_MAX_DELAY)
+#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
+#define pMXVR_LADDR                    ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */
+#define bfin_read_MXVR_LADDR()         bfin_read32(MXVR_LADDR)
+#define bfin_write_MXVR_LADDR(val)     bfin_write32(MXVR_LADDR, val)
+#define pMXVR_GADDR                    ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */
+#define bfin_read_MXVR_GADDR()         bfin_read16(MXVR_GADDR)
+#define bfin_write_MXVR_GADDR(val)     bfin_write16(MXVR_GADDR, val)
+#define pMXVR_AADDR                    ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */
+#define bfin_read_MXVR_AADDR()         bfin_read32(MXVR_AADDR)
+#define bfin_write_MXVR_AADDR(val)     bfin_write32(MXVR_AADDR, val)
+#define pMXVR_ALLOC_0                  ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */
+#define bfin_read_MXVR_ALLOC_0()       bfin_read32(MXVR_ALLOC_0)
+#define bfin_write_MXVR_ALLOC_0(val)   bfin_write32(MXVR_ALLOC_0, val)
+#define pMXVR_ALLOC_1                  ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */
+#define bfin_read_MXVR_ALLOC_1()       bfin_read32(MXVR_ALLOC_1)
+#define bfin_write_MXVR_ALLOC_1(val)   bfin_write32(MXVR_ALLOC_1, val)
+#define pMXVR_ALLOC_2                  ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */
+#define bfin_read_MXVR_ALLOC_2()       bfin_read32(MXVR_ALLOC_2)
+#define bfin_write_MXVR_ALLOC_2(val)   bfin_write32(MXVR_ALLOC_2, val)
+#define pMXVR_ALLOC_3                  ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */
+#define bfin_read_MXVR_ALLOC_3()       bfin_read32(MXVR_ALLOC_3)
+#define bfin_write_MXVR_ALLOC_3(val)   bfin_write32(MXVR_ALLOC_3, val)
+#define pMXVR_ALLOC_4                  ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */
+#define bfin_read_MXVR_ALLOC_4()       bfin_read32(MXVR_ALLOC_4)
+#define bfin_write_MXVR_ALLOC_4(val)   bfin_write32(MXVR_ALLOC_4, val)
+#define pMXVR_ALLOC_5                  ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */
+#define bfin_read_MXVR_ALLOC_5()       bfin_read32(MXVR_ALLOC_5)
+#define bfin_write_MXVR_ALLOC_5(val)   bfin_write32(MXVR_ALLOC_5, val)
+#define pMXVR_ALLOC_6                  ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */
+#define bfin_read_MXVR_ALLOC_6()       bfin_read32(MXVR_ALLOC_6)
+#define bfin_write_MXVR_ALLOC_6(val)   bfin_write32(MXVR_ALLOC_6, val)
+#define pMXVR_ALLOC_7                  ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */
+#define bfin_read_MXVR_ALLOC_7()       bfin_read32(MXVR_ALLOC_7)
+#define bfin_write_MXVR_ALLOC_7(val)   bfin_write32(MXVR_ALLOC_7, val)
+#define pMXVR_ALLOC_8                  ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */
+#define bfin_read_MXVR_ALLOC_8()       bfin_read32(MXVR_ALLOC_8)
+#define bfin_write_MXVR_ALLOC_8(val)   bfin_write32(MXVR_ALLOC_8, val)
+#define pMXVR_ALLOC_9                  ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */
+#define bfin_read_MXVR_ALLOC_9()       bfin_read32(MXVR_ALLOC_9)
+#define bfin_write_MXVR_ALLOC_9(val)   bfin_write32(MXVR_ALLOC_9, val)
+#define pMXVR_ALLOC_10                 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */
+#define bfin_read_MXVR_ALLOC_10()      bfin_read32(MXVR_ALLOC_10)
+#define bfin_write_MXVR_ALLOC_10(val)  bfin_write32(MXVR_ALLOC_10, val)
+#define pMXVR_ALLOC_11                 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */
+#define bfin_read_MXVR_ALLOC_11()      bfin_read32(MXVR_ALLOC_11)
+#define bfin_write_MXVR_ALLOC_11(val)  bfin_write32(MXVR_ALLOC_11, val)
+#define pMXVR_ALLOC_12                 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */
+#define bfin_read_MXVR_ALLOC_12()      bfin_read32(MXVR_ALLOC_12)
+#define bfin_write_MXVR_ALLOC_12(val)  bfin_write32(MXVR_ALLOC_12, val)
+#define pMXVR_ALLOC_13                 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */
+#define bfin_read_MXVR_ALLOC_13()      bfin_read32(MXVR_ALLOC_13)
+#define bfin_write_MXVR_ALLOC_13(val)  bfin_write32(MXVR_ALLOC_13, val)
+#define pMXVR_ALLOC_14                 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */
+#define bfin_read_MXVR_ALLOC_14()      bfin_read32(MXVR_ALLOC_14)
+#define bfin_write_MXVR_ALLOC_14(val)  bfin_write32(MXVR_ALLOC_14, val)
+#define pMXVR_SYNC_LCHAN_0             ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define bfin_read_MXVR_SYNC_LCHAN_0()  bfin_read32(MXVR_SYNC_LCHAN_0)
+#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
+#define pMXVR_SYNC_LCHAN_1             ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define bfin_read_MXVR_SYNC_LCHAN_1()  bfin_read32(MXVR_SYNC_LCHAN_1)
+#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
+#define pMXVR_SYNC_LCHAN_2             ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define bfin_read_MXVR_SYNC_LCHAN_2()  bfin_read32(MXVR_SYNC_LCHAN_2)
+#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
+#define pMXVR_SYNC_LCHAN_3             ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define bfin_read_MXVR_SYNC_LCHAN_3()  bfin_read32(MXVR_SYNC_LCHAN_3)
+#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
+#define pMXVR_SYNC_LCHAN_4             ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define bfin_read_MXVR_SYNC_LCHAN_4()  bfin_read32(MXVR_SYNC_LCHAN_4)
+#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
+#define pMXVR_SYNC_LCHAN_5             ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define bfin_read_MXVR_SYNC_LCHAN_5()  bfin_read32(MXVR_SYNC_LCHAN_5)
+#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
+#define pMXVR_SYNC_LCHAN_6             ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define bfin_read_MXVR_SYNC_LCHAN_6()  bfin_read32(MXVR_SYNC_LCHAN_6)
+#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
+#define pMXVR_SYNC_LCHAN_7             ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */
+#define bfin_read_MXVR_SYNC_LCHAN_7()  bfin_read32(MXVR_SYNC_LCHAN_7)
+#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
+#define pMXVR_DMA0_CONFIG              ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */
+#define bfin_read_MXVR_DMA0_CONFIG()   bfin_read32(MXVR_DMA0_CONFIG)
+#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
+#define pMXVR_DMA0_START_ADDR          ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */
+#define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
+#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
+#define pMXVR_DMA0_COUNT               ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */
+#define bfin_read_MXVR_DMA0_COUNT()    bfin_read16(MXVR_DMA0_COUNT)
+#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
+#define pMXVR_DMA0_CURR_ADDR           ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */
+#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
+#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
+#define pMXVR_DMA0_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */
+#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
+#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
+#define pMXVR_DMA1_CONFIG              ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */
+#define bfin_read_MXVR_DMA1_CONFIG()   bfin_read32(MXVR_DMA1_CONFIG)
+#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
+#define pMXVR_DMA1_START_ADDR          ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */
+#define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
+#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
+#define pMXVR_DMA1_COUNT               ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */
+#define bfin_read_MXVR_DMA1_COUNT()    bfin_read16(MXVR_DMA1_COUNT)
+#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
+#define pMXVR_DMA1_CURR_ADDR           ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */
+#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
+#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
+#define pMXVR_DMA1_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */
+#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
+#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
+#define pMXVR_DMA2_CONFIG              ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */
+#define bfin_read_MXVR_DMA2_CONFIG()   bfin_read32(MXVR_DMA2_CONFIG)
+#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
+#define pMXVR_DMA2_START_ADDR          ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */
+#define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
+#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
+#define pMXVR_DMA2_COUNT               ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */
+#define bfin_read_MXVR_DMA2_COUNT()    bfin_read16(MXVR_DMA2_COUNT)
+#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
+#define pMXVR_DMA2_CURR_ADDR           ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */
+#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
+#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
+#define pMXVR_DMA2_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */
+#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
+#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
+#define pMXVR_DMA3_CONFIG              ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */
+#define bfin_read_MXVR_DMA3_CONFIG()   bfin_read32(MXVR_DMA3_CONFIG)
+#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
+#define pMXVR_DMA3_START_ADDR          ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */
+#define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
+#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
+#define pMXVR_DMA3_COUNT               ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */
+#define bfin_read_MXVR_DMA3_COUNT()    bfin_read16(MXVR_DMA3_COUNT)
+#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
+#define pMXVR_DMA3_CURR_ADDR           ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */
+#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
+#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
+#define pMXVR_DMA3_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */
+#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
+#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
+#define pMXVR_DMA4_CONFIG              ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */
+#define bfin_read_MXVR_DMA4_CONFIG()   bfin_read32(MXVR_DMA4_CONFIG)
+#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
+#define pMXVR_DMA4_START_ADDR          ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */
+#define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
+#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
+#define pMXVR_DMA4_COUNT               ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */
+#define bfin_read_MXVR_DMA4_COUNT()    bfin_read16(MXVR_DMA4_COUNT)
+#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
+#define pMXVR_DMA4_CURR_ADDR           ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */
+#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
+#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
+#define pMXVR_DMA4_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */
+#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
+#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
+#define pMXVR_DMA5_CONFIG              ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */
+#define bfin_read_MXVR_DMA5_CONFIG()   bfin_read32(MXVR_DMA5_CONFIG)
+#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
+#define pMXVR_DMA5_START_ADDR          ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */
+#define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
+#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
+#define pMXVR_DMA5_COUNT               ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */
+#define bfin_read_MXVR_DMA5_COUNT()    bfin_read16(MXVR_DMA5_COUNT)
+#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
+#define pMXVR_DMA5_CURR_ADDR           ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */
+#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
+#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
+#define pMXVR_DMA5_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */
+#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
+#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
+#define pMXVR_DMA6_CONFIG              ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */
+#define bfin_read_MXVR_DMA6_CONFIG()   bfin_read32(MXVR_DMA6_CONFIG)
+#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
+#define pMXVR_DMA6_START_ADDR          ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */
+#define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
+#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
+#define pMXVR_DMA6_COUNT               ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */
+#define bfin_read_MXVR_DMA6_COUNT()    bfin_read16(MXVR_DMA6_COUNT)
+#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
+#define pMXVR_DMA6_CURR_ADDR           ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */
+#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
+#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
+#define pMXVR_DMA6_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */
+#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
+#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
+#define pMXVR_DMA7_CONFIG              ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */
+#define bfin_read_MXVR_DMA7_CONFIG()   bfin_read32(MXVR_DMA7_CONFIG)
+#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
+#define pMXVR_DMA7_START_ADDR          ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */
+#define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
+#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
+#define pMXVR_DMA7_COUNT               ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */
+#define bfin_read_MXVR_DMA7_COUNT()    bfin_read16(MXVR_DMA7_COUNT)
+#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
+#define pMXVR_DMA7_CURR_ADDR           ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */
+#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
+#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
+#define pMXVR_DMA7_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */
+#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
+#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
+#define pMXVR_AP_CTL                   ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */
+#define bfin_read_MXVR_AP_CTL()        bfin_read16(MXVR_AP_CTL)
+#define bfin_write_MXVR_AP_CTL(val)    bfin_write16(MXVR_AP_CTL, val)
+#define pMXVR_APRB_START_ADDR          ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */
+#define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
+#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
+#define pMXVR_APRB_CURR_ADDR           ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */
+#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
+#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
+#define pMXVR_APTB_START_ADDR          ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */
+#define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
+#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
+#define pMXVR_APTB_CURR_ADDR           ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */
+#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
+#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
+#define pMXVR_CM_CTL                   ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */
+#define bfin_read_MXVR_CM_CTL()        bfin_read32(MXVR_CM_CTL)
+#define bfin_write_MXVR_CM_CTL(val)    bfin_write32(MXVR_CM_CTL, val)
+#define pMXVR_CMRB_START_ADDR          ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */
+#define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
+#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
+#define pMXVR_CMRB_CURR_ADDR           ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */
+#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
+#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
+#define pMXVR_CMTB_START_ADDR          ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */
+#define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
+#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
+#define pMXVR_CMTB_CURR_ADDR           ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */
+#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
+#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
+#define pMXVR_RRDB_START_ADDR          ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */
+#define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
+#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
+#define pMXVR_RRDB_CURR_ADDR           ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */
+#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
+#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
+#define pMXVR_PAT_DATA_0               ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */
+#define bfin_read_MXVR_PAT_DATA_0()    bfin_read32(MXVR_PAT_DATA_0)
+#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
+#define pMXVR_PAT_EN_0                 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */
+#define bfin_read_MXVR_PAT_EN_0()      bfin_read32(MXVR_PAT_EN_0)
+#define bfin_write_MXVR_PAT_EN_0(val)  bfin_write32(MXVR_PAT_EN_0, val)
+#define pMXVR_PAT_DATA_1               ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */
+#define bfin_read_MXVR_PAT_DATA_1()    bfin_read32(MXVR_PAT_DATA_1)
+#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
+#define pMXVR_PAT_EN_1                 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */
+#define bfin_read_MXVR_PAT_EN_1()      bfin_read32(MXVR_PAT_EN_1)
+#define bfin_write_MXVR_PAT_EN_1(val)  bfin_write32(MXVR_PAT_EN_1, val)
+#define pMXVR_FRAME_CNT_0              ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */
+#define bfin_read_MXVR_FRAME_CNT_0()   bfin_read16(MXVR_FRAME_CNT_0)
+#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
+#define pMXVR_FRAME_CNT_1              ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */
+#define bfin_read_MXVR_FRAME_CNT_1()   bfin_read16(MXVR_FRAME_CNT_1)
+#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
+#define pMXVR_ROUTING_0                ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */
+#define bfin_read_MXVR_ROUTING_0()     bfin_read32(MXVR_ROUTING_0)
+#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
+#define pMXVR_ROUTING_1                ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */
+#define bfin_read_MXVR_ROUTING_1()     bfin_read32(MXVR_ROUTING_1)
+#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
+#define pMXVR_ROUTING_2                ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */
+#define bfin_read_MXVR_ROUTING_2()     bfin_read32(MXVR_ROUTING_2)
+#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
+#define pMXVR_ROUTING_3                ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */
+#define bfin_read_MXVR_ROUTING_3()     bfin_read32(MXVR_ROUTING_3)
+#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
+#define pMXVR_ROUTING_4                ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */
+#define bfin_read_MXVR_ROUTING_4()     bfin_read32(MXVR_ROUTING_4)
+#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
+#define pMXVR_ROUTING_5                ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */
+#define bfin_read_MXVR_ROUTING_5()     bfin_read32(MXVR_ROUTING_5)
+#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
+#define pMXVR_ROUTING_6                ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */
+#define bfin_read_MXVR_ROUTING_6()     bfin_read32(MXVR_ROUTING_6)
+#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
+#define pMXVR_ROUTING_7                ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */
+#define bfin_read_MXVR_ROUTING_7()     bfin_read32(MXVR_ROUTING_7)
+#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
+#define pMXVR_ROUTING_8                ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */
+#define bfin_read_MXVR_ROUTING_8()     bfin_read32(MXVR_ROUTING_8)
+#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
+#define pMXVR_ROUTING_9                ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */
+#define bfin_read_MXVR_ROUTING_9()     bfin_read32(MXVR_ROUTING_9)
+#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
+#define pMXVR_ROUTING_10               ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */
+#define bfin_read_MXVR_ROUTING_10()    bfin_read32(MXVR_ROUTING_10)
+#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
+#define pMXVR_ROUTING_11               ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */
+#define bfin_read_MXVR_ROUTING_11()    bfin_read32(MXVR_ROUTING_11)
+#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
+#define pMXVR_ROUTING_12               ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */
+#define bfin_read_MXVR_ROUTING_12()    bfin_read32(MXVR_ROUTING_12)
+#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
+#define pMXVR_ROUTING_13               ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */
+#define bfin_read_MXVR_ROUTING_13()    bfin_read32(MXVR_ROUTING_13)
+#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
+#define pMXVR_ROUTING_14               ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */
+#define bfin_read_MXVR_ROUTING_14()    bfin_read32(MXVR_ROUTING_14)
+#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
+#define pMXVR_BLOCK_CNT                ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */
+#define bfin_read_MXVR_BLOCK_CNT()     bfin_read16(MXVR_BLOCK_CNT)
+#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
+#define pMXVR_CLK_CTL                  ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */
+#define bfin_read_MXVR_CLK_CTL()       bfin_read32(MXVR_CLK_CTL)
+#define bfin_write_MXVR_CLK_CTL(val)   bfin_write32(MXVR_CLK_CTL, val)
+#define pMXVR_CDRPLL_CTL               ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */
+#define bfin_read_MXVR_CDRPLL_CTL()    bfin_read32(MXVR_CDRPLL_CTL)
+#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
+#define pMXVR_FMPLL_CTL                ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */
+#define bfin_read_MXVR_FMPLL_CTL()     bfin_read32(MXVR_FMPLL_CTL)
+#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
+#define pMXVR_PIN_CTL                  ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */
+#define bfin_read_MXVR_PIN_CTL()       bfin_read16(MXVR_PIN_CTL)
+#define bfin_write_MXVR_PIN_CTL(val)   bfin_write16(MXVR_PIN_CTL, val)
+#define pMXVR_SCLK_CNT                 ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */
+#define bfin_read_MXVR_SCLK_CNT()      bfin_read16(MXVR_SCLK_CNT)
+#define bfin_write_MXVR_SCLK_CNT(val)  bfin_write16(MXVR_SCLK_CNT, val)
+#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
+#define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
+#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
+#define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
+#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
+#define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
+#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
+#define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
+#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
+#define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
+#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
+#define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
+#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
+#define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
+#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
+#define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
+#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
+#define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
+#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
+#define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
+#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
+#define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
+#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
+#define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
+#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
+#define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
+#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
+#define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
+#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
+#define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
+#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
+#define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
+#define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
+#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
+#define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
+#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
+#define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
+#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
+#define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
+#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
+#define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
+#define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
+#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
+#define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
+#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
+#define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
+#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
+#define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
+#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
+#define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
+#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
+#define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
+#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
+#define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
+#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
+#define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
+#define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
+#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
+#define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
+#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
+#define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
+#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
+#define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
+#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
+#define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
+#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
+#define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
+#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
+#define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
+#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
+#define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
+#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
+#define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
+#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
+#define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
+#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
+#define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
+#define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
+#define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
+#define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
+#define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
+#define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
+#define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
+#define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
+#define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
+#define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
+#define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
+#define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
+#define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
+#define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
+#define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
+#define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
+#define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
+#define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
+#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
+#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
+#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
+#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
+#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
+#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
+#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
+#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
+#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
+#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
+#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
+#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
+#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
+#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
+#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
+#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
+#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
+#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
+#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
+#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
+#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
+#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
+#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
+#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
+#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
+#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
+#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
+#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
+#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
+#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
+#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
+#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
+#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
+#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
+#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
+#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
+#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
+#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
+#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
+#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
+#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
+#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
+#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
+#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
+#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
+#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
+#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
+#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
+#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
+#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
+#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
+#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
+#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
+#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
+#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
+#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
+#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
+#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
+#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
+#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
+#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
+#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
+#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
+#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
+#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
+#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
+#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
+#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
+#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
+#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
+#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
+#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
+#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
+#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
+#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
+#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
+#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
+#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
+#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
+#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
+#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
+#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
+#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
+#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
+#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
+#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
+#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
+#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
+#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
+#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
+#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
+#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
+#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
+#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
+#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
+#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
+#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
+#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
+#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
+#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
+#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
+#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
+#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
+#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
+#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
+#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
+#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
+#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
+#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
+#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
+#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
+#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
+#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
+#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
+#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
+#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
+#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
+#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
+#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
+#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
+#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
+#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
+#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
+#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
+#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
+#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
+#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
+#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
+#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
+#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
+#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
+#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
+#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
+#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
+#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
+#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
+#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
+#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
+#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
+#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
+#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
+#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
+#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
+#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
+#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
+#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
+#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
+#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
+#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
+#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
+#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
+#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
+#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
+#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
+#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
+#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
+#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
+#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
+#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
+#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
+#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
+#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
+#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
+#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
+#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
+#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
+#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
+#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
+#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
+#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
+#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
+#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
+#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
+#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
+#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
+#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
+#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
+#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
+#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
+#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
+#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
+#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
+#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
+#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
+#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
+#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
+#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
+#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
+#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
+#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
+#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
+#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
+#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
+#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
+#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
+#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
+#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
+#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
+#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
+#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
+#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
+#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
+#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
+#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
+#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
+#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
+#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
+#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
+#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
+#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
+#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
+#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
+#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
+#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
+#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
+#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
+#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
+#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
+#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
+#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
+#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
+#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
+#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
+#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
+#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
+#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
+#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
+#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
+#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
+#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
+#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
+#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
+#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
+#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
+#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
+#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
+#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
+#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
+#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
+#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
+#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
+#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
+#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
+#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
+#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
+#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
+#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
+#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
+#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
+#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
+#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
+#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
+#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
+#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
+#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
+#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
+#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
+#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
+#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
+#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
+#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
+#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
+#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
+#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
+#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
+#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
+#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
+#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
+#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
+#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
+#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
+#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
+#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
+#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
+#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
+#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
+#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
+#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
+#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
+#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
+#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
+#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
+#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
+#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
+#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
+#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
+#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
+#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
+#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
+#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
+#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
+#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
+#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
+#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
+#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
+#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
+#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
+#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
+#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
+#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
+#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
+#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
+#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
+#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
+#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
+#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
+#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
+#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
+#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
+#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
+#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
+#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
+#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
+#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
+#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
+#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
+#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
+#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
+#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
+#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
+#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
+#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
+#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
+#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
+#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
+#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
+#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
+#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
+#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
+#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
+#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
+#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
+#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
+#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
+#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
+#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
+#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
+#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
+#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
+#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
+#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
+#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
+#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
+#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
+#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
+#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
+#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
+#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
+#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
+#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
+#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
+#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
+#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
+#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
+#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
+#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
+#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
+#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
+#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
+#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
+#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
+#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
+#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
+#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
+#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
+#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
+#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
+#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
+#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
+#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
+#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
+#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
+#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
+#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
+#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
+#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
+#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
+#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
+#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
+#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
+#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
+#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
+#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
+#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
+#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
+#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
+#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
+#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
+#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
+#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
+#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
+#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
+#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
+#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
+#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
+#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
+#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
+#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
+#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
+#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
+#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
+#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
+#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
+#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
+#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
+#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
+#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
+#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
+#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
+#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
+#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
+#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
+#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
+#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
+#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
+#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
+#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
+#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
+#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
+#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
+#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
+#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
+#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
+#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
+#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
+#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
+#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
+#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
+#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
+#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
+#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
+#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
+#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
+#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
+#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
+#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
+#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
+#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
+#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
+#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
+#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
+#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
+#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
+#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
+#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
+#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
+#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
+#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
+#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
+#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
+#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
+#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
+#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
+#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
+#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
+#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
+#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
+#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
+#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
+#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
+#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
+#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
+#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
+#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
+#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
+#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
+#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
+#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
+#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
+#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
+#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
+#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
+#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
+#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
+#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
+#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
+#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
+#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
+#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
+#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
+#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
+#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
+#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
+#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
+#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
+#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
+#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
+#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
+#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
+#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
+#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
+#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
+#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
+#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
+#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
+#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
+#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
+#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
+#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
+#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
+#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
+#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
+#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
+#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
+#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
+#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
+#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
+#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
+#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
+#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
+#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
+#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
+#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
+#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
+#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
+#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
+#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
+#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
+#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
+#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
+#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
+#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
+#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
+#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
+#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
+#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
+#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
+#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
+#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
+#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
+#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
+#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
+#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
+#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
+#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
+#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
+#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
+#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
+#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
+#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
+#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
+#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
+#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
+#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
+#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
+#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
+#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
+#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
+#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
+#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
+#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
+#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
+#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
+#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
+#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
+#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
+#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
+#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
+#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
+#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
+#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
+#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
+#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
+#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
+#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
+#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
+#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
+#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
+#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
+#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
+#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
+#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
+#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
+#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
+#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
+#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
+#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
+#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
+#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
+#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
+#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
+#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
+#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
+#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
+#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
+#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
+#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
+#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
+#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
+#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
+#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
+#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
+#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
+#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
+#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
+#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
+#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
+#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
+#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
+#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
+#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
+#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
+#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
+#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
+#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
+#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
+#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
+#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
+#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
+#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
+#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
+#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
+#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
+#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
+#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
+#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
+#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
+#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
+#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
+#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
+#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
+#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
+#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
+#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
+#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
+#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
+#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
+#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
+#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
+#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
+#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
+#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
+#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
+#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
+#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
+#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
+#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
+#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
+#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
+#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
+#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
+#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
+#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
+#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
+#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
+#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
+#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
+#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
+#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
+#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
+#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
+#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
+#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
+#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
+#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
+#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
+#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
+#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
+#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
+#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
+#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
+#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
+#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
+#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
+#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
+#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
+#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
+#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
+#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
+#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
+#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
+#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
+#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
+#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
+#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
+#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
+#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
+#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
+#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
+#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
+#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
+#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
+#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
+#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
+#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
+#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
+#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
+#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
+#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
+#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
+#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
+#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
+#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
+#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
+#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
+#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
+#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
+#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
+#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
+#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
+#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
+#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
+#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
+#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
+#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
+#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
+#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
+#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
+#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
+#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
+#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
+#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
+#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
+#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
+#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
+#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
+#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
+#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
+#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
+#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
+#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
+#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
+#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
+#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
+#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
+#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
+#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
+#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
+#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
+#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
+#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
+#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
+#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
+#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
+#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
+#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
+#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
+#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
+#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
+#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
+#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
+#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
+#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
+#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
+#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
+#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
+#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
+#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
+#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
+#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
+#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
+#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
+#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
+#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
+#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
+#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
+#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
+#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
+#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
+#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
+#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
+#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
+#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
+#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
+#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
+#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
+#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
+#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
+#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
+#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
+#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
+#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
+#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
+#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
+#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
+#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
+#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
+#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
+#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
+#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
+#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
+#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
+#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
+#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
+#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
+#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
+#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
+#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
+#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
+#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
+#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
+#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
+#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
+#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
+#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
+#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
+#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
+#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
+#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
+#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
+#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
+#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
+#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
+#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
+#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
+#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
+#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
+#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
+#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
+#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
+#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
+#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
+#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
+#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
+#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
+#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
+#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
+#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
+#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
+#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
+#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
+#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
+#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
+#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
+#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
+#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
+#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
+#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
+#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
+#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
+#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
+#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
+#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
+#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
+#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
+#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
+#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
+#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
+#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
+#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
+#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
+#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
+#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
+#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
+#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
+#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
+#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
+#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
+#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
+#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
+#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
+#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
+#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
+#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
+#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
+#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
+#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
+#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
+#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
+#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
+#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
+#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
+#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
+#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
+#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
+#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
+#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
+#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
+#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
+#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
+#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
+#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
+#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
+#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
+#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
+#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
+#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
+#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
+#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
+#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
+#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
+#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
+#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
+#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
+#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
+#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
+#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
+#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
+#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
+#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
+#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
+#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
+#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
+#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
+#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
+#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
+#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
+#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
+#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
+#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
+#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
+#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
+#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
+#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
+#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
+#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
+#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
+#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
+#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
+#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
+#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
+#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
+#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
+#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
+#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
+#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
+#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
+#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
+#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
+#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
+#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
+#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
+#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
+#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
+#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
+#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
+#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
+#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
+#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
+#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
+#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
+#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
+#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
+#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
+#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
+#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
+#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
+#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
+#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
+#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
+#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
+#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
+#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
+#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
+#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
+#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
+#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
+#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
+#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
+#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
+#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
+#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
+#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
+#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
+#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
+#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
+#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
+#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
+#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
+#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
+#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
+#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
+#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
+#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
+#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
+#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
+#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
+#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
+#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
+#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
+#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
+#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
+#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
+#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
+#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
+#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
+#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
+#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
+#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
+#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
+#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
+#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
+#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
+#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
+#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
+#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
+#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
+#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
+#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
+#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
+#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
+#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
+#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
+#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
+#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
+#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
+#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
+#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
+#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
+#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
+#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
+#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
+#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
+#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
+#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
+#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
+#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
+#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
+#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
+#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
+#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
+#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
+#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
+#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
+#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
+#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
+#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
+#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
+#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
+#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
+#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
+#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
+#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
+#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
+#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
+#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
+#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
+#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
+#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
+#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
+#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
+#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
+#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
+#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
+#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
+#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
+#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
+#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
+#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
+#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
+#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
+#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
+#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
+#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
+#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
+#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
+#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
+#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
+#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
+#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
+#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
+#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
+#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
+#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
+#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
+#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
+#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
+#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
+#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
+#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
+#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
+#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
+#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
+#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
+#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
+#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
+#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
+#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
+#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
+#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
+#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
+#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
+#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
+#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
+#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
+#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
+#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
+#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
+#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
+#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
+#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
+#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
+#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
+#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
+#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
+#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
+#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
+#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
+#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
+#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
+#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
+#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
+#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
+#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
+#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
+#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
+#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
+#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
+#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
+#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
+#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
+#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
+#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
+#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
+#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
+#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
+#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
+#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
+#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
+#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
+#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
+#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
+#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
+#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
+#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
+#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
+#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
+#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
+#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
+#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
+#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
+#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
+#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
+#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
+#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
+#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
+#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
+#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
+#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
+#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
+#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
+#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
+#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
+#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
+#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
+#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
+#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
+#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
+#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
+#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
+#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
+#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
+#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
+#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
+#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
+#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
+#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
+#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
+#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
+#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
+#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
+#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
+#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
+#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
+#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
+#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
+#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
+#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
+#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
+#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
+#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
+#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
+#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
+#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
+#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
+#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
+#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
+#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
+#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
+#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
+#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
+#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
+#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
+#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
+#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
+#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
+#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
+#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
+#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
+#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
+#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
+#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
+#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
+#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
+#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
+#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
+#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
+#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
+#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
+#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
+#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
+#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
+#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
+#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
+#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
+#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
+#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
+#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
+#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
+#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
+#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
+#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
+#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
+#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
+#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
+#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
+#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
+#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
+#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
+#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
+#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
+#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
+#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
+#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
+#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
+#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
+#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
+#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
+#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
+#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
+#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
+#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
+#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
+#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
+#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
+#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
+#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
+#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
+#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
+#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
+#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
+#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
+#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
+#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
+#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
+#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
+#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
+#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
+#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
+#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
+#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
+#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
+#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
+#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
+#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
+#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
+#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
+#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
+#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
+#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
+#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
+#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
+#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
+#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
+#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
+#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
+#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
+#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
+#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
+#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
+#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
+#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
+#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
+#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
+#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
+#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
+#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
+#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
+#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
+#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
+#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
+#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
+#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
+#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
+#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
+#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
+#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
+#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
+#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
+#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
+#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
+#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
+#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
+#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
+#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
+#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
+#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
+#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
+#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
+#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
+#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
+#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
+#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
+#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
+#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
+#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
+#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
+#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
+#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
+#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
+#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
+#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
+#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
+#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
+#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
+#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
+#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
+#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
+#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
+#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
+#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
+#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
+#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
+#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
+#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
+#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
+#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
+#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
+#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
+#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
+#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
+#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
+#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
+#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
+#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
+#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
+#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
+#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
+#define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
+#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
+#define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
+#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
+#define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
+#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
+#define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
+#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
+#define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
+#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
+#define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
+#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
+#define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
+#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
+#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
+#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
+#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
+#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
+#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
+#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
+#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
+#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
+#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
+#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
+#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
+#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
+#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
+#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
+#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
+#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
+#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
+#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
+#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
+#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
+#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
+#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
+#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
+#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
+#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
+#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
+#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
+#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
+#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
+#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
+#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
+#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
+#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
+#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
+#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
+#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
+#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
+#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
+#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
+#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
+#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
+#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
+#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
+#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
+#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
+#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
+#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
+#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
+#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
+#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
+#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
+#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
+#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
+#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
+#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
+#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
+#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
+#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
+#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
+#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
+#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
+#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
+#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
+#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
+#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
+#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
+#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
+#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
+#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
+#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
+#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
+#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
+#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
+#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
+#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
+#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
+#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
+#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
+#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
+#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
+#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
+#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
+#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
+#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
+#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
+#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
+#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
+#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
+#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
+#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
+#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
+#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
+#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
+#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
+#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
+#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
+#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
+#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
+#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
+#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
+#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
+#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
+#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
+#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
+#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
+#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
+#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
+#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
+#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
+#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
+#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
+#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
+#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
+#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
+#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
+#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
+#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
+#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
+#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
+#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
+#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
+#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
+#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
+#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
+#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
+#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
+#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
+#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
+#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
+#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
+#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
+#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
+#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
+#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
+#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
+#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
+#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
+#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
+#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
+#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
+#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
+#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
+#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
+#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
+#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
+#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
+#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
+#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
+#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
+#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
+#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
+#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
+#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
+#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
+#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
+#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
+#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
+#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
+#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
+#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
+#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
+#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
+#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
+#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
+#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
+#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
+#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
+#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
+#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
+#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
+#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
+#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
+#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
+#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
+#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
+#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
+#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
+#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
+#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
+#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
+#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
+#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
+#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
+#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
+#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
+#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
+#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
+#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
+#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
+#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
+#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
+#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
+#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
+#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
+#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
+#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
+#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
+#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
+#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
+#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
+#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
+#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
+#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
+#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
+#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
+#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
+#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
+#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
+#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
+#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
+#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
+#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
+#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
+#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
+#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
+#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
+#define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
+#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
+#define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
+#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
+#define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
+#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
+#define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
+#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
+#define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
+#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
+#define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
+#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
+#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
+#define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
+#define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
+#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
+#define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
+#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
+#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
+#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
+#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
+#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
+#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
+#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
+#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
+#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
+#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
+#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
+#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
+#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
+#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
+#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
+#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
+#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
+#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
+#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
+#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
+#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
+#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
+#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
+#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
+#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
+#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
+#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
+#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
+#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
+#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
+#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
+#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
+#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
+#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
+#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
+#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
+#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
+#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
+#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
+#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
+#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
+#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
+#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
+#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
+#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
+#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
+#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
+#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
+#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
+#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
+#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
+#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
+#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
+#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
+#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
+#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
+#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
+#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
+#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
+#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
+#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
+#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
+#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
+#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
+#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
+#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
+#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
+#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
+#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
+#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
+#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
+#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
+#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
+#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
+#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
+#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
+#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
+#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
+#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
+#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
+#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
+#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
+#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
+#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
+#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
+#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
+#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
+#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
+#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
+#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
+#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
+#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
+#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
+#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
+#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
+#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
+#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
+#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
+#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
+#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
+#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
+#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
+#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
+#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
+#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
+#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
+#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
+#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
+#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
+#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
+#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
+#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
+#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
+#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
+#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
+#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
+#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
+#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
+#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
+#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
+#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
+#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
+#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
+#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
+#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
+#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
+#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
+#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
+#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
+#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
+#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
+#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
+#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
+#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
+#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
+#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
+#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
+#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
+#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
+#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
+#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
+#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
+#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
+#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
+#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
+#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
+#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
+#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
+#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
+#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
+#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
+#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
+#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
+#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
+#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
+#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
+#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
+#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
+#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
+#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
+#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
+#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
+#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
+#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
+#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
+#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
+#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
+#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
+#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
+#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
+#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
+#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
+#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
+#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
+#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
+#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
+#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
+#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
+#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
+#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
+#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
+#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
+#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
+#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
+#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
+#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
+#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
+#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
+#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
+#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
+#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
+#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
+#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
+#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
+#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
+#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
+#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
new file mode 100644
index 0000000..6163eb2
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h
@@ -0,0 +1,2053 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_BF549_extended__
+#define __BFIN_DEF_ADSP_EDN_BF549_extended__
+
+#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */
+#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */
+#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */
+#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */
+#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+#define DMA12_NEXT_DESC_PTR            0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR               0xFFC01C04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                   0xFFC01C08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC01C10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                 0xFFC01C14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                  0xFFC01C18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                 0xFFC01C1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR            0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                0xFFC01C24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS               0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP           0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT             0xFFC01C30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT             0xFFC01C38 /* DMA Channel 12 Current Y Count Register */
+#define DMA13_NEXT_DESC_PTR            0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR               0xFFC01C44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                   0xFFC01C48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC01C50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                 0xFFC01C54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                  0xFFC01C58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                 0xFFC01C5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR            0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                0xFFC01C64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS               0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP           0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT             0xFFC01C70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT             0xFFC01C78 /* DMA Channel 13 Current Y Count Register */
+#define DMA14_NEXT_DESC_PTR            0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR               0xFFC01C84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                   0xFFC01C88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC01C90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                 0xFFC01C94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                  0xFFC01C98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                 0xFFC01C9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR            0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                0xFFC01CA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS               0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP           0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT             0xFFC01CB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT             0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */
+#define DMA15_NEXT_DESC_PTR            0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR               0xFFC01CC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                   0xFFC01CC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC01CD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                 0xFFC01CD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                  0xFFC01CD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                 0xFFC01CDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR            0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                0xFFC01CE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS               0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP           0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT             0xFFC01CF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT             0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */
+#define DMA16_NEXT_DESC_PTR            0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR               0xFFC01D04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                   0xFFC01D08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC01D10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                 0xFFC01D14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                  0xFFC01D18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                 0xFFC01D1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR            0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                0xFFC01D24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS               0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP           0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT             0xFFC01D30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT             0xFFC01D38 /* DMA Channel 16 Current Y Count Register */
+#define DMA17_NEXT_DESC_PTR            0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR               0xFFC01D44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                   0xFFC01D48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC01D50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                 0xFFC01D54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                  0xFFC01D58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                 0xFFC01D5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR            0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                0xFFC01D64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS               0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP           0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT             0xFFC01D70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT             0xFFC01D78 /* DMA Channel 17 Current Y Count Register */
+#define DMA18_NEXT_DESC_PTR            0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR               0xFFC01D84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                   0xFFC01D88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC01D90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                 0xFFC01D94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                  0xFFC01D98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                 0xFFC01D9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR            0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                0xFFC01DA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS               0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP           0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT             0xFFC01DB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */
+#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */
+#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */
+#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */
+#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */
+#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */
+#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */
+#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */
+#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */
+#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */
+#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */
+#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */
+#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */
+#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */
+#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */
+#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */
+#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */
+#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */
+#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */
+#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */
+#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */
+#define PORTA                          0xFFC014C4 /* GPIO Data Register */
+#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */
+#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */
+#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */
+#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */
+#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */
+#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */
+#define PORTB                          0xFFC014E4 /* GPIO Data Register */
+#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */
+#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */
+#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */
+#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */
+#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */
+#define PORTC_FER                      0xFFC01500 /* Function Enable Register */
+#define PORTC                          0xFFC01504 /* GPIO Data Register */
+#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */
+#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */
+#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */
+#define PORTD_FER                      0xFFC01520 /* Function Enable Register */
+#define PORTD                          0xFFC01524 /* GPIO Data Register */
+#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */
+#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */
+#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */
+#define PORTE_FER                      0xFFC01540 /* Function Enable Register */
+#define PORTE                          0xFFC01544 /* GPIO Data Register */
+#define PORTE_SET                      0xFFC01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR                    0xFFC0154C /* GPIO Data Clear Register */
+#define PORTE_DIR_SET                  0xFFC01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR                0xFFC01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN                     0xFFC01558 /* GPIO Input Enable Register */
+#define PORTE_MUX                      0xFFC0155C /* Multiplexer Control Register */
+#define PORTF_FER                      0xFFC01560 /* Function Enable Register */
+#define PORTF                          0xFFC01564 /* GPIO Data Register */
+#define PORTF_SET                      0xFFC01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR                    0xFFC0156C /* GPIO Data Clear Register */
+#define PORTF_DIR_SET                  0xFFC01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR                0xFFC01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN                     0xFFC01578 /* GPIO Input Enable Register */
+#define PORTF_MUX                      0xFFC0157C /* Multiplexer Control Register */
+#define PORTG_FER                      0xFFC01580 /* Function Enable Register */
+#define PORTG                          0xFFC01584 /* GPIO Data Register */
+#define PORTG_SET                      0xFFC01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR                    0xFFC0158C /* GPIO Data Clear Register */
+#define PORTG_DIR_SET                  0xFFC01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR                0xFFC01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN                     0xFFC01598 /* GPIO Input Enable Register */
+#define PORTG_MUX                      0xFFC0159C /* Multiplexer Control Register */
+#define PORTH_FER                      0xFFC015A0 /* Function Enable Register */
+#define PORTH                          0xFFC015A4 /* GPIO Data Register */
+#define PORTH_SET                      0xFFC015A8 /* GPIO Data Set Register */
+#define PORTH_CLEAR                    0xFFC015AC /* GPIO Data Clear Register */
+#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
+#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
+#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
+#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
+#define PORTI                          0xFFC015C4 /* GPIO Data Register */
+#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
+#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
+#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
+#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
+#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
+#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
+#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
+#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
+#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
+#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
+#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
+#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
+#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
+#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
+#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
+#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
+#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
+#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
+#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
+#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
+#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
+#define TIMER8_CONFIG                  0xFFC00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER                 0xFFC00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD                  0xFFC00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH                   0xFFC0060C /* Timer 8 Width Register */
+#define TIMER9_CONFIG                  0xFFC00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER                 0xFFC00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD                  0xFFC00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH                   0xFFC0061C /* Timer 9 Width Register */
+#define TIMER10_CONFIG                 0xFFC00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER                0xFFC00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD                 0xFFC00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH                  0xFFC0062C /* Timer 10 Width Register */
+#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
+#define TIMER_ENABLE1                  0xFFC00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1                 0xFFC00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1                  0xFFC00648 /* Timer Group of 3 Status Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
+#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
+#define CNT_STATUS                     0xFFC04208 /* Status Register  */
+#define CNT_COMMAND                    0xFFC0420C /* Command Register */
+#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
+#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
+#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
+#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
+#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
+#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
+#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
+#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
+#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
+#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
+#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
+#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
+#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
+#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
+#define MXVR_CONFIG                    0xFFC02700 /* MXVR Configuration Register */
+#define MXVR_STATE_0                   0xFFC02708 /* MXVR State Register 0 */
+#define MXVR_STATE_1                   0xFFC0270C /* MXVR State Register 1 */
+#define MXVR_INT_STAT_0                0xFFC02710 /* MXVR Interrupt Status Register 0 */
+#define MXVR_INT_STAT_1                0xFFC02714 /* MXVR Interrupt Status Register 1 */
+#define MXVR_INT_EN_0                  0xFFC02718 /* MXVR Interrupt Enable Register 0 */
+#define MXVR_INT_EN_1                  0xFFC0271C /* MXVR Interrupt Enable Register 1 */
+#define MXVR_POSITION                  0xFFC02720 /* MXVR Node Position Register */
+#define MXVR_MAX_POSITION              0xFFC02724 /* MXVR Maximum Node Position Register */
+#define MXVR_DELAY                     0xFFC02728 /* MXVR Node Frame Delay Register */
+#define MXVR_MAX_DELAY                 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
+#define MXVR_LADDR                     0xFFC02730 /* MXVR Logical Address Register */
+#define MXVR_GADDR                     0xFFC02734 /* MXVR Group Address Register */
+#define MXVR_AADDR                     0xFFC02738 /* MXVR Alternate Address Register */
+#define MXVR_ALLOC_0                   0xFFC0273C /* MXVR Allocation Table Register 0 */
+#define MXVR_ALLOC_1                   0xFFC02740 /* MXVR Allocation Table Register 1 */
+#define MXVR_ALLOC_2                   0xFFC02744 /* MXVR Allocation Table Register 2 */
+#define MXVR_ALLOC_3                   0xFFC02748 /* MXVR Allocation Table Register 3 */
+#define MXVR_ALLOC_4                   0xFFC0274C /* MXVR Allocation Table Register 4 */
+#define MXVR_ALLOC_5                   0xFFC02750 /* MXVR Allocation Table Register 5 */
+#define MXVR_ALLOC_6                   0xFFC02754 /* MXVR Allocation Table Register 6 */
+#define MXVR_ALLOC_7                   0xFFC02758 /* MXVR Allocation Table Register 7 */
+#define MXVR_ALLOC_8                   0xFFC0275C /* MXVR Allocation Table Register 8 */
+#define MXVR_ALLOC_9                   0xFFC02760 /* MXVR Allocation Table Register 9 */
+#define MXVR_ALLOC_10                  0xFFC02764 /* MXVR Allocation Table Register 10 */
+#define MXVR_ALLOC_11                  0xFFC02768 /* MXVR Allocation Table Register 11 */
+#define MXVR_ALLOC_12                  0xFFC0276C /* MXVR Allocation Table Register 12 */
+#define MXVR_ALLOC_13                  0xFFC02770 /* MXVR Allocation Table Register 13 */
+#define MXVR_ALLOC_14                  0xFFC02774 /* MXVR Allocation Table Register 14 */
+#define MXVR_SYNC_LCHAN_0              0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define MXVR_SYNC_LCHAN_1              0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define MXVR_SYNC_LCHAN_2              0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define MXVR_SYNC_LCHAN_3              0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define MXVR_SYNC_LCHAN_4              0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define MXVR_SYNC_LCHAN_5              0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define MXVR_SYNC_LCHAN_6              0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define MXVR_SYNC_LCHAN_7              0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
+#define MXVR_DMA0_CONFIG               0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
+#define MXVR_DMA0_START_ADDR           0xFFC0279C /* MXVR Sync Data DMA0 Start Address */
+#define MXVR_DMA0_COUNT                0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
+#define MXVR_DMA0_CURR_ADDR            0xFFC027A4 /* MXVR Sync Data DMA0 Current Address */
+#define MXVR_DMA0_CURR_COUNT           0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count */
+#define MXVR_DMA1_CONFIG               0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
+#define MXVR_DMA1_START_ADDR           0xFFC027B0 /* MXVR Sync Data DMA1 Start Address */
+#define MXVR_DMA1_COUNT                0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
+#define MXVR_DMA1_CURR_ADDR            0xFFC027B8 /* MXVR Sync Data DMA1 Current Address */
+#define MXVR_DMA1_CURR_COUNT           0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count */
+#define MXVR_DMA2_CONFIG               0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
+#define MXVR_DMA2_START_ADDR           0xFFC027C4 /* MXVR Sync Data DMA2 Start Address */
+#define MXVR_DMA2_COUNT                0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
+#define MXVR_DMA2_CURR_ADDR            0xFFC027CC /* MXVR Sync Data DMA2 Current Address */
+#define MXVR_DMA2_CURR_COUNT           0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count */
+#define MXVR_DMA3_CONFIG               0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
+#define MXVR_DMA3_START_ADDR           0xFFC027D8 /* MXVR Sync Data DMA3 Start Address */
+#define MXVR_DMA3_COUNT                0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
+#define MXVR_DMA3_CURR_ADDR            0xFFC027E0 /* MXVR Sync Data DMA3 Current Address */
+#define MXVR_DMA3_CURR_COUNT           0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count */
+#define MXVR_DMA4_CONFIG               0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
+#define MXVR_DMA4_START_ADDR           0xFFC027EC /* MXVR Sync Data DMA4 Start Address */
+#define MXVR_DMA4_COUNT                0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
+#define MXVR_DMA4_CURR_ADDR            0xFFC027F4 /* MXVR Sync Data DMA4 Current Address */
+#define MXVR_DMA4_CURR_COUNT           0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count */
+#define MXVR_DMA5_CONFIG               0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
+#define MXVR_DMA5_START_ADDR           0xFFC02800 /* MXVR Sync Data DMA5 Start Address */
+#define MXVR_DMA5_COUNT                0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
+#define MXVR_DMA5_CURR_ADDR            0xFFC02808 /* MXVR Sync Data DMA5 Current Address */
+#define MXVR_DMA5_CURR_COUNT           0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count */
+#define MXVR_DMA6_CONFIG               0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
+#define MXVR_DMA6_START_ADDR           0xFFC02814 /* MXVR Sync Data DMA6 Start Address */
+#define MXVR_DMA6_COUNT                0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
+#define MXVR_DMA6_CURR_ADDR            0xFFC0281C /* MXVR Sync Data DMA6 Current Address */
+#define MXVR_DMA6_CURR_COUNT           0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count */
+#define MXVR_DMA7_CONFIG               0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
+#define MXVR_DMA7_START_ADDR           0xFFC02828 /* MXVR Sync Data DMA7 Start Address */
+#define MXVR_DMA7_COUNT                0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
+#define MXVR_DMA7_CURR_ADDR            0xFFC02830 /* MXVR Sync Data DMA7 Current Address */
+#define MXVR_DMA7_CURR_COUNT           0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count */
+#define MXVR_AP_CTL                    0xFFC02838 /* MXVR Async Packet Control Register */
+#define MXVR_APRB_START_ADDR           0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
+#define MXVR_APRB_CURR_ADDR            0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
+#define MXVR_APTB_START_ADDR           0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
+#define MXVR_APTB_CURR_ADDR            0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
+#define MXVR_CM_CTL                    0xFFC0284C /* MXVR Control Message Control Register */
+#define MXVR_CMRB_START_ADDR           0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
+#define MXVR_CMRB_CURR_ADDR            0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
+#define MXVR_CMTB_START_ADDR           0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
+#define MXVR_CMTB_CURR_ADDR            0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
+#define MXVR_RRDB_START_ADDR           0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
+#define MXVR_RRDB_CURR_ADDR            0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
+#define MXVR_PAT_DATA_0                0xFFC02868 /* MXVR Pattern Data Register 0 */
+#define MXVR_PAT_EN_0                  0xFFC0286C /* MXVR Pattern Enable Register 0 */
+#define MXVR_PAT_DATA_1                0xFFC02870 /* MXVR Pattern Data Register 1 */
+#define MXVR_PAT_EN_1                  0xFFC02874 /* MXVR Pattern Enable Register 1 */
+#define MXVR_FRAME_CNT_0               0xFFC02878 /* MXVR Frame Counter 0 */
+#define MXVR_FRAME_CNT_1               0xFFC0287C /* MXVR Frame Counter 1 */
+#define MXVR_ROUTING_0                 0xFFC02880 /* MXVR Routing Table Register 0 */
+#define MXVR_ROUTING_1                 0xFFC02884 /* MXVR Routing Table Register 1 */
+#define MXVR_ROUTING_2                 0xFFC02888 /* MXVR Routing Table Register 2 */
+#define MXVR_ROUTING_3                 0xFFC0288C /* MXVR Routing Table Register 3 */
+#define MXVR_ROUTING_4                 0xFFC02890 /* MXVR Routing Table Register 4 */
+#define MXVR_ROUTING_5                 0xFFC02894 /* MXVR Routing Table Register 5 */
+#define MXVR_ROUTING_6                 0xFFC02898 /* MXVR Routing Table Register 6 */
+#define MXVR_ROUTING_7                 0xFFC0289C /* MXVR Routing Table Register 7 */
+#define MXVR_ROUTING_8                 0xFFC028A0 /* MXVR Routing Table Register 8 */
+#define MXVR_ROUTING_9                 0xFFC028A4 /* MXVR Routing Table Register 9 */
+#define MXVR_ROUTING_10                0xFFC028A8 /* MXVR Routing Table Register 10 */
+#define MXVR_ROUTING_11                0xFFC028AC /* MXVR Routing Table Register 11 */
+#define MXVR_ROUTING_12                0xFFC028B0 /* MXVR Routing Table Register 12 */
+#define MXVR_ROUTING_13                0xFFC028B4 /* MXVR Routing Table Register 13 */
+#define MXVR_ROUTING_14                0xFFC028B8 /* MXVR Routing Table Register 14 */
+#define MXVR_BLOCK_CNT                 0xFFC028C0 /* MXVR Block Counter */
+#define MXVR_CLK_CTL                   0xFFC028D0 /* MXVR Clock Control Register */
+#define MXVR_CDRPLL_CTL                0xFFC028D4 /* MXVR Clock/Data Recovery PLL Control Register */
+#define MXVR_FMPLL_CTL                 0xFFC028D8 /* MXVR Frequency Multiply PLL Control Register */
+#define MXVR_PIN_CTL                   0xFFC028DC /* MXVR Pin Control Register */
+#define MXVR_SCLK_CNT                  0xFFC028E0 /* MXVR System Clock Counter Register */
+#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
+#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
+#define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
+#define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
+#define SDH_COMMAND                    0xFFC0390C /* SDH Command */
+#define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
+#define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
+#define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
+#define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
+#define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
+#define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
+#define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
+#define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
+#define SDH_STATUS                     0xFFC03934 /* SDH Status */
+#define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
+#define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
+#define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
+#define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
+#define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
+#define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
+#define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
+#define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
+#define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
+#define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
+#define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
+#define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
+#define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
+#define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
+#define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
+#define ATAPI_CONTROL                  0xFFC03800 /* ATAPI Control Register */
+#define ATAPI_STATUS                   0xFFC03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR                 0xFFC03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF                0xFFC0380C /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF                0xFFC03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK                 0xFFC03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS               0xFFC03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN                 0xFFC0381C /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS              0xFFC03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE                 0xFFC03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE                0xFFC03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT               0xFFC0382C /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT               0xFFC03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT             0xFFC03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT           0xFFC03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0                0xFFC03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0                0xFFC03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1                0xFFC03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0              0xFFC03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1              0xFFC03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2              0xFFC03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0              0xFFC03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1              0xFFC03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2              0xFFC03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3              0xFFC0386C /* ATAPI Ultra-DMA Timing 3 Register */
+#define NFC_CTL                        0xFFC03B00 /* NAND Control Register */
+#define NFC_STAT                       0xFFC03B04 /* NAND Status Register */
+#define NFC_IRQSTAT                    0xFFC03B08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK                    0xFFC03B0C /* NAND Interrupt Mask Register */
+#define NFC_ECC0                       0xFFC03B10 /* NAND ECC Register 0 */
+#define NFC_ECC1                       0xFFC03B14 /* NAND ECC Register 1 */
+#define NFC_ECC2                       0xFFC03B18 /* NAND ECC Register 2 */
+#define NFC_ECC3                       0xFFC03B1C /* NAND ECC Register 3 */
+#define NFC_COUNT                      0xFFC03B20 /* NAND ECC Count Register */
+#define NFC_RST                        0xFFC03B24 /* NAND ECC Reset Register */
+#define NFC_PGCTL                      0xFFC03B28 /* NAND Page Control Register */
+#define NFC_READ                       0xFFC03B2C /* NAND Read Data Register */
+#define NFC_ADDR                       0xFFC03B40 /* NAND Address Register */
+#define NFC_CMD                        0xFFC03B44 /* NAND Command Register */
+#define NFC_DATA_WR                    0xFFC03B48 /* NAND Data Write Register */
+#define NFC_DATA_RD                    0xFFC03B4C /* NAND Data Read Register */
+#define EPPI0_STATUS                   0xFFC01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT                   0xFFC01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY                   0xFFC01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT                   0xFFC0100C /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY                   0xFFC01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                    0xFFC01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE                     0xFFC01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV                   0xFFC0101C /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL                  0xFFC01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL                 0xFFC01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL                0xFFC01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB                 0xFFC0102C /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF                0xFFC01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP                     0xFFC01034 /* EPPI0 Clipping Register */
+#define EPPI1_STATUS                   0xFFC01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT                   0xFFC01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY                   0xFFC01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT                   0xFFC0130C /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY                   0xFFC01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                    0xFFC01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE                     0xFFC01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV                   0xFFC0131C /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL                  0xFFC01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL                 0xFFC01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL                0xFFC01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB                 0xFFC0132C /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF                0xFFC01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP                     0xFFC01334 /* EPPI1 Clipping Register */
+#define EPPI2_STATUS                   0xFFC02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT                   0xFFC02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY                   0xFFC02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT                   0xFFC0290C /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY                   0xFFC02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                    0xFFC02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE                     0xFFC02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV                   0xFFC0291C /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL                  0xFFC02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL                 0xFFC02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL                0xFFC02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB                 0xFFC0292C /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF                0xFFC02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP                     0xFFC02934 /* EPPI2 Clipping Register */
+#define CAN0_MC1                       0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                       0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                      0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1                      0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1                       0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1                       0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                      0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1                      0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                    0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                    0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                     0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                      0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1                     0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN0_MC2                       0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                       0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                      0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2                      0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2                       0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2                       0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                      0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2                      0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                    0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                    0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                     0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                      0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2                     0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN0_CLOCK                     0xFFC02A80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING                    0xFFC02A84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG                     0xFFC02A88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS                    0xFFC02A8C /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC                       0xFFC02A90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS                       0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM                       0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF                       0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL                   0xFFC02AA0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR                      0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD                      0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR                       0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR                       0xFFC02AB4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT                     0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC                      0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF                     0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
+#define CAN0_AM00L                     0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H                     0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L                     0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H                     0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L                     0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H                     0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L                     0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H                     0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L                     0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H                     0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L                     0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H                     0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L                     0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H                     0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L                     0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H                     0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L                     0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H                     0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L                     0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H                     0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L                     0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H                     0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L                     0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H                     0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L                     0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H                     0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L                     0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H                     0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L                     0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H                     0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L                     0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H                     0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+#define CAN0_AM16L                     0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H                     0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L                     0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H                     0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L                     0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H                     0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L                     0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H                     0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L                     0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H                     0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L                     0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H                     0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L                     0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H                     0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L                     0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H                     0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L                     0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H                     0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L                     0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H                     0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L                     0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H                     0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L                     0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H                     0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L                     0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H                     0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L                     0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H                     0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L                     0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H                     0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L                     0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H                     0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+#define CAN0_MB00_DATA0                0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1                0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2                0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3                0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH               0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP            0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0                  0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1                  0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0                0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1                0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2                0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3                0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH               0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP            0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0                  0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1                  0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0                0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1                0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2                0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3                0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH               0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP            0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0                  0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1                  0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0                0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1                0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2                0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3                0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH               0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP            0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0                  0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1                  0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0                0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1                0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2                0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3                0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH               0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP            0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0                  0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1                  0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0                0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1                0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2                0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3                0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH               0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP            0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0                  0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1                  0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0                0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1                0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2                0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3                0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH               0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP            0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0                  0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1                  0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0                0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1                0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2                0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3                0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH               0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP            0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0                  0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1                  0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0                0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1                0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2                0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3                0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH               0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP            0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0                  0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1                  0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0                0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1                0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2                0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3                0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH               0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP            0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0                  0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1                  0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0                0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1                0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2                0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3                0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH               0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP            0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0                  0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1                  0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0                0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1                0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2                0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3                0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH               0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP            0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0                  0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1                  0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0                0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1                0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2                0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3                0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH               0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP            0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0                  0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1                  0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0                0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1                0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2                0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3                0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH               0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP            0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0                  0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1                  0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0                0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1                0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2                0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3                0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH               0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP            0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0                  0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1                  0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0                0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1                0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2                0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3                0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH               0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP            0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0                  0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1                  0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
+#define CAN0_MB16_DATA0                0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1                0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2                0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3                0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH               0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP            0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0                  0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1                  0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0                0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1                0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2                0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3                0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH               0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP            0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0                  0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1                  0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0                0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1                0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2                0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3                0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH               0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP            0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0                  0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1                  0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0                0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1                0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2                0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3                0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH               0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP            0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0                  0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1                  0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0                0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1                0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2                0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3                0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH               0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP            0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0                  0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1                  0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0                0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1                0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2                0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3                0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH               0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP            0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0                  0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1                  0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0                0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1                0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2                0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3                0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH               0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP            0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0                  0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1                  0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0                0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1                0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2                0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3                0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH               0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP            0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0                  0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1                  0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0                0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1                0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2                0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3                0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH               0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP            0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0                  0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1                  0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0                0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1                0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2                0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3                0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH               0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP            0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0                  0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1                  0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0                0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1                0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2                0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3                0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH               0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP            0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0                  0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1                  0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0                0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1                0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2                0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3                0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH               0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP            0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0                  0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1                  0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0                0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1                0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2                0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3                0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH               0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP            0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0                  0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1                  0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0                0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1                0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2                0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3                0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH               0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP            0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0                  0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1                  0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0                0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1                0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2                0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3                0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH               0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP            0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0                  0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1                  0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0                0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1                0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2                0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3                0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH               0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP            0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0                  0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1                  0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
+#define CAN1_MC1                       0xFFC03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1                       0xFFC03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1                      0xFFC03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1                      0xFFC0320C /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1                       0xFFC03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1                       0xFFC03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1                      0xFFC03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1                      0xFFC0321C /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1                    0xFFC03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1                    0xFFC03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1                     0xFFC03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1                      0xFFC0322C /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1                     0xFFC03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+#define CAN1_MC2                       0xFFC03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2                       0xFFC03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2                      0xFFC03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2                      0xFFC0324C /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2                       0xFFC03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2                       0xFFC03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2                      0xFFC03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2                      0xFFC0325C /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2                    0xFFC03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2                    0xFFC03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2                     0xFFC03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2                      0xFFC0326C /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2                     0xFFC03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+#define CAN1_CLOCK                     0xFFC03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING                    0xFFC03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG                     0xFFC03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS                    0xFFC0328C /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC                       0xFFC03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS                       0xFFC03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM                       0xFFC03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF                       0xFFC0329C /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL                   0xFFC032A0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR                      0xFFC032A4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD                      0xFFC032AC /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR                       0xFFC032B0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR                       0xFFC032B4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT                     0xFFC032C4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC                      0xFFC032C8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF                     0xFFC032CC /* CAN Controller 1 Universal Counter Configuration Register */
+#define CAN1_AM00L                     0xFFC03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H                     0xFFC03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L                     0xFFC03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H                     0xFFC0330C /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L                     0xFFC03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H                     0xFFC03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L                     0xFFC03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H                     0xFFC0331C /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L                     0xFFC03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H                     0xFFC03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L                     0xFFC03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H                     0xFFC0332C /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L                     0xFFC03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H                     0xFFC03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L                     0xFFC03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H                     0xFFC0333C /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L                     0xFFC03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H                     0xFFC03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L                     0xFFC03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H                     0xFFC0334C /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L                     0xFFC03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H                     0xFFC03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L                     0xFFC03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H                     0xFFC0335C /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L                     0xFFC03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H                     0xFFC03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L                     0xFFC03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H                     0xFFC0336C /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L                     0xFFC03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H                     0xFFC03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L                     0xFFC03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H                     0xFFC0337C /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+#define CAN1_AM16L                     0xFFC03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H                     0xFFC03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L                     0xFFC03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H                     0xFFC0338C /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L                     0xFFC03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H                     0xFFC03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L                     0xFFC03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H                     0xFFC0339C /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L                     0xFFC033A0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H                     0xFFC033A4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L                     0xFFC033A8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H                     0xFFC033AC /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L                     0xFFC033B0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H                     0xFFC033B4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L                     0xFFC033B8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H                     0xFFC033BC /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L                     0xFFC033C0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H                     0xFFC033C4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L                     0xFFC033C8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H                     0xFFC033CC /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L                     0xFFC033D0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H                     0xFFC033D4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L                     0xFFC033D8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H                     0xFFC033DC /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L                     0xFFC033E0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H                     0xFFC033E4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L                     0xFFC033E8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H                     0xFFC033EC /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L                     0xFFC033F0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H                     0xFFC033F4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L                     0xFFC033F8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H                     0xFFC033FC /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+#define CAN1_MB00_DATA0                0xFFC03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1                0xFFC03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2                0xFFC03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3                0xFFC0340C /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH               0xFFC03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP            0xFFC03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0                  0xFFC03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1                  0xFFC0341C /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0                0xFFC03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1                0xFFC03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2                0xFFC03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3                0xFFC0342C /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH               0xFFC03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP            0xFFC03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0                  0xFFC03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1                  0xFFC0343C /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0                0xFFC03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1                0xFFC03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2                0xFFC03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3                0xFFC0344C /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH               0xFFC03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP            0xFFC03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0                  0xFFC03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1                  0xFFC0345C /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0                0xFFC03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1                0xFFC03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2                0xFFC03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3                0xFFC0346C /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH               0xFFC03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP            0xFFC03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0                  0xFFC03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1                  0xFFC0347C /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0                0xFFC03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1                0xFFC03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2                0xFFC03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3                0xFFC0348C /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH               0xFFC03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP            0xFFC03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0                  0xFFC03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1                  0xFFC0349C /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0                0xFFC034A0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1                0xFFC034A4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2                0xFFC034A8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3                0xFFC034AC /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH               0xFFC034B0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP            0xFFC034B4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0                  0xFFC034B8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1                  0xFFC034BC /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0                0xFFC034C0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1                0xFFC034C4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2                0xFFC034C8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3                0xFFC034CC /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH               0xFFC034D0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP            0xFFC034D4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0                  0xFFC034D8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1                  0xFFC034DC /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0                0xFFC034E0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1                0xFFC034E4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2                0xFFC034E8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3                0xFFC034EC /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH               0xFFC034F0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP            0xFFC034F4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0                  0xFFC034F8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1                  0xFFC034FC /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0                0xFFC03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1                0xFFC03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2                0xFFC03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3                0xFFC0350C /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH               0xFFC03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP            0xFFC03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0                  0xFFC03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1                  0xFFC0351C /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0                0xFFC03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1                0xFFC03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2                0xFFC03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3                0xFFC0352C /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH               0xFFC03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP            0xFFC03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0                  0xFFC03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1                  0xFFC0353C /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0                0xFFC03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1                0xFFC03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2                0xFFC03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3                0xFFC0354C /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH               0xFFC03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP            0xFFC03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0                  0xFFC03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1                  0xFFC0355C /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0                0xFFC03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1                0xFFC03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2                0xFFC03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3                0xFFC0356C /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH               0xFFC03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP            0xFFC03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0                  0xFFC03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1                  0xFFC0357C /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0                0xFFC03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1                0xFFC03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2                0xFFC03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3                0xFFC0358C /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH               0xFFC03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP            0xFFC03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0                  0xFFC03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1                  0xFFC0359C /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0                0xFFC035A0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1                0xFFC035A4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2                0xFFC035A8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3                0xFFC035AC /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH               0xFFC035B0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP            0xFFC035B4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0                  0xFFC035B8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1                  0xFFC035BC /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0                0xFFC035C0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1                0xFFC035C4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2                0xFFC035C8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3                0xFFC035CC /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH               0xFFC035D0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP            0xFFC035D4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0                  0xFFC035D8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1                  0xFFC035DC /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0                0xFFC035E0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1                0xFFC035E4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2                0xFFC035E8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3                0xFFC035EC /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH               0xFFC035F0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP            0xFFC035F4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0                  0xFFC035F8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1                  0xFFC035FC /* CAN Controller 1 Mailbox 15 ID1 Register */
+#define CAN1_MB16_DATA0                0xFFC03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1                0xFFC03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2                0xFFC03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3                0xFFC0360C /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH               0xFFC03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP            0xFFC03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0                  0xFFC03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1                  0xFFC0361C /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0                0xFFC03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1                0xFFC03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2                0xFFC03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3                0xFFC0362C /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH               0xFFC03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP            0xFFC03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0                  0xFFC03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1                  0xFFC0363C /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0                0xFFC03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1                0xFFC03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2                0xFFC03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3                0xFFC0364C /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH               0xFFC03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP            0xFFC03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0                  0xFFC03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1                  0xFFC0365C /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0                0xFFC03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1                0xFFC03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2                0xFFC03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3                0xFFC0366C /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH               0xFFC03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP            0xFFC03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0                  0xFFC03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1                  0xFFC0367C /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0                0xFFC03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1                0xFFC03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2                0xFFC03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3                0xFFC0368C /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH               0xFFC03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP            0xFFC03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0                  0xFFC03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1                  0xFFC0369C /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0                0xFFC036A0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1                0xFFC036A4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2                0xFFC036A8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3                0xFFC036AC /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH               0xFFC036B0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP            0xFFC036B4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0                  0xFFC036B8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1                  0xFFC036BC /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0                0xFFC036C0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1                0xFFC036C4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2                0xFFC036C8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3                0xFFC036CC /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH               0xFFC036D0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP            0xFFC036D4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0                  0xFFC036D8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1                  0xFFC036DC /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0                0xFFC036E0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1                0xFFC036E4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2                0xFFC036E8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3                0xFFC036EC /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH               0xFFC036F0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP            0xFFC036F4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0                  0xFFC036F8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1                  0xFFC036FC /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0                0xFFC03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1                0xFFC03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2                0xFFC03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3                0xFFC0370C /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH               0xFFC03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP            0xFFC03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0                  0xFFC03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1                  0xFFC0371C /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0                0xFFC03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1                0xFFC03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2                0xFFC03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3                0xFFC0372C /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH               0xFFC03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP            0xFFC03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0                  0xFFC03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1                  0xFFC0373C /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0                0xFFC03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1                0xFFC03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2                0xFFC03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3                0xFFC0374C /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH               0xFFC03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP            0xFFC03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0                  0xFFC03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1                  0xFFC0375C /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0                0xFFC03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1                0xFFC03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2                0xFFC03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3                0xFFC0376C /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH               0xFFC03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP            0xFFC03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0                  0xFFC03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1                  0xFFC0377C /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0                0xFFC03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1                0xFFC03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2                0xFFC03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3                0xFFC0378C /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH               0xFFC03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP            0xFFC03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0                  0xFFC03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1                  0xFFC0379C /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0                0xFFC037A0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1                0xFFC037A4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2                0xFFC037A8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3                0xFFC037AC /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH               0xFFC037B0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP            0xFFC037B4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0                  0xFFC037B8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1                  0xFFC037BC /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0                0xFFC037C0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1                0xFFC037C4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2                0xFFC037C8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3                0xFFC037CC /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH               0xFFC037D0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP            0xFFC037D4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0                  0xFFC037D8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1                  0xFFC037DC /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0                0xFFC037E0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1                0xFFC037E4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2                0xFFC037E8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3                0xFFC037EC /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH               0xFFC037F0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP            0xFFC037F4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0                  0xFFC037F8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1                  0xFFC037FC /* CAN Controller 1 Mailbox 31 ID1 Register */
+#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag Register */
+#define SPI0_STAT                      0xFFC00508 /* SPI0 Status Register */
+#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW                    0xFFC00518 /* SPI0 Receive Data Buffer Shadow Register */
+#define SPI1_CTL                       0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG                       0xFFC02304 /* SPI1 Flag Register */
+#define SPI1_STAT                      0xFFC02308 /* SPI1 Status Register */
+#define SPI1_TDBR                      0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                      0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                      0xFFC02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW                    0xFFC02318 /* SPI1 Receive Data Buffer Shadow Register */
+#define SPI2_CTL                       0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG                       0xFFC02404 /* SPI2 Flag Register */
+#define SPI2_STAT                      0xFFC02408 /* SPI2 Status Register */
+#define SPI2_TDBR                      0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                      0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                      0xFFC02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW                    0xFFC02418 /* SPI2 Receive Data Buffer Shadow Register */
+#define TWI0_CLKDIV                    0xFFC00700 /* Clock Divider Register */
+#define TWI0_CONTROL                   0xFFC00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC0070C /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT               0xFFC00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC0071C /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC0072C /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16                0xFFC00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16                0xFFC0078C /* TWI FIFO Receive Data Double Byte Register */
+#define TWI1_CLKDIV                    0xFFC02200 /* Clock Divider Register */
+#define TWI1_CONTROL                   0xFFC02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC0220C /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT               0xFFC02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC0221C /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK                  0xFFC02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL                  0xFFC02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT                 0xFFC0222C /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8                 0xFFC02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16                0xFFC02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8                 0xFFC02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16                0xFFC0228C /* TWI FIFO Receive Data Double Byte Register */
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 Receive Data Register */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi channel Receive Select Register 3 */
+#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 Receive Data Register */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi channel Receive Select Register 3 */
+#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT2_TCR1                    0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                    0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV                 0xFFC02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV                  0xFFC0250C /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX                      0xFFC02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RCR1                    0xFFC02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2                    0xFFC02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV                 0xFFC02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV                  0xFFC0252C /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_RX                      0xFFC02518 /* SPORT2 Receive Data Register */
+#define SPORT2_STAT                    0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_MCMC1                   0xFFC02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2                   0xFFC0253C /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_CHNL                    0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MRCS0                   0xFFC02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1                   0xFFC02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2                   0xFFC02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3                   0xFFC0255C /* SPORT2 Multi channel Receive Select Register 3 */
+#define SPORT2_MTCS0                   0xFFC02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1                   0xFFC02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2                   0xFFC02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3                   0xFFC0254C /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT3_TCR1                    0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                    0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV                 0xFFC02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV                  0xFFC0260C /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX                      0xFFC02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RCR1                    0xFFC02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2                    0xFFC02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV                 0xFFC02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV                  0xFFC0262C /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_RX                      0xFFC02618 /* SPORT3 Receive Data Register */
+#define SPORT3_STAT                    0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_MCMC1                   0xFFC02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2                   0xFFC0263C /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_CHNL                    0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MRCS0                   0xFFC02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1                   0xFFC02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2                   0xFFC02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3                   0xFFC0265C /* SPORT3 Multi channel Receive Select Register 3 */
+#define SPORT3_MTCS0                   0xFFC02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1                   0xFFC02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2                   0xFFC02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3                   0xFFC0264C /* SPORT3 Multi channel Transmit Select Register 3 */
+#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
+#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
+#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
+#define UART0_LCR                      0xFFC0040C /* Line Control Register */
+#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
+#define UART0_LSR                      0xFFC00414 /* Line Status Register */
+#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
+#define UART0_SCR                      0xFFC0041C /* Scratch Register */
+#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
+#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
+#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
+#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
+#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
+#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
+#define UART1_LCR                      0xFFC0200C /* Line Control Register */
+#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
+#define UART1_LSR                      0xFFC02014 /* Line Status Register */
+#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
+#define UART1_SCR                      0xFFC0201C /* Scratch Register */
+#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
+#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
+#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
+#define UART2_DLL                      0xFFC02100 /* Divisor Latch Low Byte */
+#define UART2_DLH                      0xFFC02104 /* Divisor Latch High Byte */
+#define UART2_GCTL                     0xFFC02108 /* Global Control Register */
+#define UART2_LCR                      0xFFC0210C /* Line Control Register */
+#define UART2_MCR                      0xFFC02110 /* Modem Control Register */
+#define UART2_LSR                      0xFFC02114 /* Line Status Register */
+#define UART2_MSR                      0xFFC02118 /* Modem Status Register */
+#define UART2_SCR                      0xFFC0211C /* Scratch Register */
+#define UART2_IER_SET                  0xFFC02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR                0xFFC02124 /* Interrupt Enable Register Clear */
+#define UART2_THR                      0xFFC02128 /* Transmit Hold Register */
+#define UART2_RBR                      0xFFC0212C /* Receive Buffer Register */
+#define UART3_DLL                      0xFFC03100 /* Divisor Latch Low Byte */
+#define UART3_DLH                      0xFFC03104 /* Divisor Latch High Byte */
+#define UART3_GCTL                     0xFFC03108 /* Global Control Register */
+#define UART3_LCR                      0xFFC0310C /* Line Control Register */
+#define UART3_MCR                      0xFFC03110 /* Modem Control Register */
+#define UART3_LSR                      0xFFC03114 /* Line Status Register */
+#define UART3_MSR                      0xFFC03118 /* Modem Status Register */
+#define UART3_SCR                      0xFFC0311C /* Scratch Register */
+#define UART3_IER_SET                  0xFFC03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR                0xFFC03124 /* Interrupt Enable Register Clear */
+#define UART3_THR                      0xFFC03128 /* Transmit Hold Register */
+#define UART3_RBR                      0xFFC0312C /* Receive Buffer Register */
+#define USB_FADDR                      0xFFC03C00 /* Function address register */
+#define USB_POWER                      0xFFC03C04 /* Power management register */
+#define USB_INTRTX                     0xFFC03C08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX                     0xFFC03C0C /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE                    0xFFC03C10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE                    0xFFC03C14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB                    0xFFC03C18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE                   0xFFC03C1C /* Interrupt enable register for IntrUSB */
+#define USB_FRAME                      0xFFC03C20 /* USB frame number */
+#define USB_INDEX                      0xFFC03C24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE                   0xFFC03C28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR                   0xFFC03C2C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL                 0xFFC03C30 /* Global Clock Control for the core */
+#define USB_TX_MAX_PACKET              0xFFC03C40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0                       0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR                      0xFFC03C44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET              0xFFC03C48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR                      0xFFC03C4C /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0                     0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT                    0xFFC03C50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE                     0xFFC03C54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0                  0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL                 0xFFC03C58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE                     0xFFC03C5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL                 0xFFC03C60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT                    0xFFC03C68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+#define USB_EP0_FIFO                   0xFFC03C80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO                   0xFFC03C88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO                   0xFFC03C90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO                   0xFFC03C98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO                   0xFFC03CA0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO                   0xFFC03CA8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO                   0xFFC03CB0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO                   0xFFC03CB8 /* Endpoint 7 FIFO */
+#define USB_OTG_DEV_CTL                0xFFC03D00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ               0xFFC03D04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK              0xFFC03D08 /* VBUS Control Interrupt Enable */
+#define USB_LINKINFO                   0xFFC03D48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN                      0xFFC03D4C /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1                    0xFFC03D50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1                    0xFFC03D54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1                    0xFFC03D58 /* Time buffer for Low-Speed transactions */
+#define USB_APHY_CNTRL                 0xFFC03DE0 /* Register that increases visibility of Analog PHY */
+#define USB_APHY_CALIB                 0xFFC03DE4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2                0xFFC03DE8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+#define USB_PHY_TEST                   0xFFC03DEC /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL                0xFFC03DF0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV                 0xFFC03DF4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+#define USB_EP_NI0_TXMAXP              0xFFC03E00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR               0xFFC03E04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP              0xFFC03E08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR               0xFFC03E0C /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT             0xFFC03E10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE              0xFFC03E14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL          0xFFC03E18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE              0xFFC03E1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL          0xFFC03E20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT             0xFFC03E28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP              0xFFC03E40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR               0xFFC03E44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP              0xFFC03E48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR               0xFFC03E4C /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT             0xFFC03E50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE              0xFFC03E54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL          0xFFC03E58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE              0xFFC03E5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL          0xFFC03E60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT             0xFFC03E68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP              0xFFC03E80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR               0xFFC03E84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP              0xFFC03E88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR               0xFFC03E8C /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT             0xFFC03E90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE              0xFFC03E94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL          0xFFC03E98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE              0xFFC03E9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL          0xFFC03EA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT             0xFFC03EA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP              0xFFC03EC0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR               0xFFC03EC4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP              0xFFC03EC8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR               0xFFC03ECC /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT             0xFFC03ED0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE              0xFFC03ED4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL          0xFFC03ED8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE              0xFFC03EDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL          0xFFC03EE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT             0xFFC03EE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP              0xFFC03F00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR               0xFFC03F04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP              0xFFC03F08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR               0xFFC03F0C /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT             0xFFC03F10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE              0xFFC03F14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL          0xFFC03F18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE              0xFFC03F1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL          0xFFC03F20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT             0xFFC03F28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP              0xFFC03F40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR               0xFFC03F44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP              0xFFC03F48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR               0xFFC03F4C /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT             0xFFC03F50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE              0xFFC03F54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL          0xFFC03F58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE              0xFFC03F5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL          0xFFC03F60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT             0xFFC03F68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP              0xFFC03F80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR               0xFFC03F84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP              0xFFC03F88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR               0xFFC03F8C /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT             0xFFC03F90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE              0xFFC03F94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL          0xFFC03F98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE              0xFFC03F9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL          0xFFC03FA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT             0xFFC03FA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP              0xFFC03FC0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR               0xFFC03FC4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP              0xFFC03FC8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR               0xFFC03FCC /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT             0xFFC03FD0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE              0xFFC03FD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL          0xFFC03FD8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE              0xFFC03FDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL          0xFFC03FF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT             0xFFC03FF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT              0xFFC04000 /* Indicates pending interrupts for the DMA channels */
+#define USB_DMA0_CONTROL               0xFFC04004 /* DMA master channel 0 configuration */
+#define USB_DMA0_ADDRLOW               0xFFC04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_ADDRHIGH              0xFFC0400C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0_COUNTLOW              0xFFC04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0_COUNTHIGH             0xFFC04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA1_CONTROL               0xFFC04024 /* DMA master channel 1 configuration */
+#define USB_DMA1_ADDRLOW               0xFFC04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_ADDRHIGH              0xFFC0402C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1_COUNTLOW              0xFFC04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1_COUNTHIGH             0xFFC04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA2_CONTROL               0xFFC04044 /* DMA master channel 2 configuration */
+#define USB_DMA2_ADDRLOW               0xFFC04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_ADDRHIGH              0xFFC0404C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2_COUNTLOW              0xFFC04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2_COUNTHIGH             0xFFC04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA3_CONTROL               0xFFC04064 /* DMA master channel 3 configuration */
+#define USB_DMA3_ADDRLOW               0xFFC04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_ADDRHIGH              0xFFC0406C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3_COUNTLOW              0xFFC04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3_COUNTHIGH             0xFFC04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA4_CONTROL               0xFFC04084 /* DMA master channel 4 configuration */
+#define USB_DMA4_ADDRLOW               0xFFC04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_ADDRHIGH              0xFFC0408C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4_COUNTLOW              0xFFC04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4_COUNTHIGH             0xFFC04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA5_CONTROL               0xFFC040A4 /* DMA master channel 5 configuration */
+#define USB_DMA5_ADDRLOW               0xFFC040A8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_ADDRHIGH              0xFFC040AC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5_COUNTLOW              0xFFC040B0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5_COUNTHIGH             0xFFC040B4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA6_CONTROL               0xFFC040C4 /* DMA master channel 6 configuration */
+#define USB_DMA6_ADDRLOW               0xFFC040C8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_ADDRHIGH              0xFFC040CC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6_COUNTLOW              0xFFC040D0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6_COUNTHIGH             0xFFC040D4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA7_CONTROL               0xFFC040E4 /* DMA master channel 7 configuration */
+#define USB_DMA7_ADDRLOW               0xFFC040E8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_ADDRHIGH              0xFFC040EC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7_COUNTLOW              0xFFC040F0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7_COUNTHIGH             0xFFC040F4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+#endif /* __BFIN_DEF_ADSP_EDN_BF549_extended__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h
new file mode 100644
index 0000000..1b8c79b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF541_proc__
+#define __BFIN_CDEF_ADSP_BF541_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF542-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF541_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF541_def.h b/arch/blackfin/include/asm/mach-bf548/BF541_def.h
new file mode 100644
index 0000000..1469ac2
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF541_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF541_proc__
+#define __BFIN_DEF_ADSP_BF541_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF542-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF541_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
new file mode 100644
index 0000000..306b5f1
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF542_proc__
+#define __BFIN_CDEF_ADSP_BF542_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF542-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_def.h b/arch/blackfin/include/asm/mach-bf548/BF542_def.h
new file mode 100644
index 0000000..1324a13
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF542_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF542_proc__
+#define __BFIN_DEF_ADSP_BF542_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF542-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF542_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
new file mode 100644
index 0000000..47ef6e1
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF544_proc__
+#define __BFIN_CDEF_ADSP_BF544_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF544-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_def.h b/arch/blackfin/include/asm/mach-bf548/BF544_def.h
new file mode 100644
index 0000000..aef6e48
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF544_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF544_proc__
+#define __BFIN_DEF_ADSP_BF544_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF544-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF544_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
new file mode 100644
index 0000000..42d041a
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF547_proc__
+#define __BFIN_CDEF_ADSP_BF547_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF547-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_def.h b/arch/blackfin/include/asm/mach-bf548/BF547_def.h
new file mode 100644
index 0000000..ce7c880
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF547_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF547_proc__
+#define __BFIN_DEF_ADSP_BF547_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF547-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF547_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
new file mode 100644
index 0000000..cf02834
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF548_proc__
+#define __BFIN_CDEF_ADSP_BF548_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF548-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_def.h b/arch/blackfin/include/asm/mach-bf548/BF548_def.h
new file mode 100644
index 0000000..e02e843
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF548_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF548_proc__
+#define __BFIN_DEF_ADSP_BF548_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF548-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF548_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
new file mode 100644
index 0000000..3514cef
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
@@ -0,0 +1,323 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF549_proc__
+#define __BFIN_CDEF_ADSP_BF549_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "ADSP-EDN-BF549-extended_cdef.h"
+
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_def.h b/arch/blackfin/include/asm/mach-bf548/BF549_def.h
new file mode 100644
index 0000000..a16ff5a
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/BF549_def.h
@@ -0,0 +1,117 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF549_proc__
+#define __BFIN_DEF_ADSP_BF549_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "ADSP-EDN-BF549-extended_def.h"
+
+#define CHIPID                         0xFFC00014
+#define SWRST                          0xFFC00100 /* Software Reset Register */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
+#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+
+#endif /* __BFIN_DEF_ADSP_BF549_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h
new file mode 100644
index 0000000..192dd67
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h
@@ -0,0 +1,201 @@
+/*
+ * File: include/asm-blackfin/mach-bf548/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file should be up to date with:
+ *  - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
+/* External FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
+/* Host DMA Boot Modes Are Not Functional */
+#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value Is Not Initialized */
+#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
+/* USB Calibration Value to use */
+#define ANOMALY_05000346_value 0x5411
+/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
+#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
+/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
+#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
+/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
+#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* External Memory Read Access Hangs Core With PLL Bypass */
+#define ANOMALY_05000360 (1)
+/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
+#define ANOMALY_05000365 (1)
+/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
+#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
+/* Addressing Conflict between Boot ROM and Asynchronous Memory */
+#define ANOMALY_05000369 (1)
+/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
+#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
+/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
+#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
+/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
+#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
+/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
+#define ANOMALY_05000379 (1)
+/* 8-Bit NAND Flash Boot Mode Not Functional */
+#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
+/* Some ATAPI Modes Are Not Functional */
+#define ANOMALY_05000383 (1)
+/* Boot from OTP Memory Not Functional */
+#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
+/* bfrom_SysControl() Firmware Routine Not Functional */
+#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
+/* Programmable Preboot Settings Not Functional */
+#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
+/* CRC32 Checksum Support Not Functional */
+#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
+/* Reset Vector Must Not Be in SDRAM Memory Space */
+#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
+/* Changed Meaning of BCODE Field in SYSCR Register */
+#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
+/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
+#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
+/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
+/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
+#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
+/* Log Buffer Not Functional */
+#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
+/* Hook Routine Not Functional */
+#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
+/* Header Indirect Bit Not Functional */
+#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
+/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
+#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
+/* Lockbox SESR Disallows Certain User Interrupts */
+#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
+#define ANOMALY_05000405 (1)
+/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
+#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
+/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
+#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
+#define ANOMALY_05000408 (1)
+/* Lockbox firmware leaves MDMA0 channel enabled */
+#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
+#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
+#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
+/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
+#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
+#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
+/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
+#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+/* Software System Reset Corrupts PLL_LOCKCNT Register */
+#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
+/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
+#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
+/* OTP Write Accesses Not Supported */
+#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
+#define ANOMALY_05000446 (1)
+/* UART IrDA Receiver Fails on Extended Bit Pulses */
+#define ANOMALY_05000447 (1)
+/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
+#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
+/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
+#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
+/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000450 (1
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/def_local.h b/arch/blackfin/include/asm/mach-bf548/def_local.h
new file mode 100644
index 0000000..81eca83
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/def_local.h
@@ -0,0 +1,2 @@
+#include "mem_map.h"
+#include "ports.h"
diff --git a/arch/blackfin/include/asm/mach-bf548/mem_map.h b/arch/blackfin/include/asm/mach-bf548/mem_map.h
new file mode 100644
index 0000000..4f94397
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/mem_map.h
@@ -0,0 +1,21 @@
+/*
+ * Common Blackfin memory map
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BF54X_MEM_MAP_H__
+#define __BF54X_MEM_MAP_H__
+
+#define L1_DATA_A_SRAM      (0xFF800000)
+#define L1_DATA_A_SRAM_SIZE (0x4000)
+#define L1_DATA_A_SRAM_END  (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM      (0xFF900000)
+#define L1_DATA_B_SRAM_SIZE (0x4000)
+#define L1_DATA_B_SRAM_END  (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+#define L1_INST_SRAM        (0xFFA00000)
+#define L1_INST_SRAM_SIZE   (0xC000)
+#define L1_INST_SRAM_END    (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf548/ports.h b/arch/blackfin/include/asm/mach-bf548/ports.h
new file mode 100644
index 0000000..50054f3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf548/ports.h
@@ -0,0 +1,106 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x00000003
+#define PORT_x_MUX_1_MASK	0x0000000C
+#define PORT_x_MUX_2_MASK	0x00000030
+#define PORT_x_MUX_3_MASK	0x000000C0
+#define PORT_x_MUX_4_MASK	0x00000300
+#define PORT_x_MUX_5_MASK	0x00000C00
+#define PORT_x_MUX_6_MASK	0x00003000
+#define PORT_x_MUX_7_MASK	0x0000C000
+#define PORT_x_MUX_8_MASK	0x00030000
+#define PORT_x_MUX_9_MASK	0x000C0000
+#define PORT_x_MUX_10_MASK	0x00300000
+#define PORT_x_MUX_11_MASK	0x00C00000
+#define PORT_x_MUX_12_MASK	0x03000000
+#define PORT_x_MUX_13_MASK	0x0C000000
+#define PORT_x_MUX_14_MASK	0x30000000
+#define PORT_x_MUX_15_MASK	0xC0000000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
+
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+#include "../mach-common/bits/ports-h.h"
+#include "../mach-common/bits/ports-i.h"
+#include "../mach-common/bits/ports-j.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
new file mode 100644
index 0000000..e2c165a
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
@@ -0,0 +1,464 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF561_proc__
+#define __BFIN_CDEF_ADSP_BF561_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
+
+#define pSRAM_BASE_ADDR                ((uint32_t volatile *)SRAM_BASE_ADDR)
+#define bfin_read_SRAM_BASE_ADDR()     bfin_read32(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL)
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS)
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((uint32_t volatile *)DCPLB_ADDR0)
+#define bfin_read_DCPLB_ADDR0()        bfin_read32(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_write32(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((uint32_t volatile *)DCPLB_ADDR1)
+#define bfin_read_DCPLB_ADDR1()        bfin_read32(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_write32(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((uint32_t volatile *)DCPLB_ADDR2)
+#define bfin_read_DCPLB_ADDR2()        bfin_read32(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_write32(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((uint32_t volatile *)DCPLB_ADDR3)
+#define bfin_read_DCPLB_ADDR3()        bfin_read32(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_write32(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((uint32_t volatile *)DCPLB_ADDR4)
+#define bfin_read_DCPLB_ADDR4()        bfin_read32(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_write32(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((uint32_t volatile *)DCPLB_ADDR5)
+#define bfin_read_DCPLB_ADDR5()        bfin_read32(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_write32(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((uint32_t volatile *)DCPLB_ADDR6)
+#define bfin_read_DCPLB_ADDR6()        bfin_read32(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_write32(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((uint32_t volatile *)DCPLB_ADDR7)
+#define bfin_read_DCPLB_ADDR7()        bfin_read32(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_write32(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((uint32_t volatile *)DCPLB_ADDR8)
+#define bfin_read_DCPLB_ADDR8()        bfin_read32(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_write32(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((uint32_t volatile *)DCPLB_ADDR9)
+#define bfin_read_DCPLB_ADDR9()        bfin_read32(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_write32(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((uint32_t volatile *)DCPLB_ADDR10)
+#define bfin_read_DCPLB_ADDR10()       bfin_read32(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_write32(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((uint32_t volatile *)DCPLB_ADDR11)
+#define bfin_read_DCPLB_ADDR11()       bfin_read32(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_write32(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((uint32_t volatile *)DCPLB_ADDR12)
+#define bfin_read_DCPLB_ADDR12()       bfin_read32(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_write32(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((uint32_t volatile *)DCPLB_ADDR13)
+#define bfin_read_DCPLB_ADDR13()       bfin_read32(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_write32(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((uint32_t volatile *)DCPLB_ADDR14)
+#define bfin_read_DCPLB_ADDR14()       bfin_read32(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_write32(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((uint32_t volatile *)DCPLB_ADDR15)
+#define bfin_read_DCPLB_ADDR15()       bfin_read32(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_write32(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0)
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1)
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2)
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3)
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4)
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5)
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6)
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7)
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8)
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9)
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10)
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11)
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12)
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13)
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14)
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15)
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND)
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0)
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1)
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL)
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((uint32_t volatile *)ICPLB_FAULT_ADDR)
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((uint32_t volatile *)ICPLB_ADDR0)
+#define bfin_read_ICPLB_ADDR0()        bfin_read32(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_write32(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((uint32_t volatile *)ICPLB_ADDR1)
+#define bfin_read_ICPLB_ADDR1()        bfin_read32(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_write32(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((uint32_t volatile *)ICPLB_ADDR2)
+#define bfin_read_ICPLB_ADDR2()        bfin_read32(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_write32(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((uint32_t volatile *)ICPLB_ADDR3)
+#define bfin_read_ICPLB_ADDR3()        bfin_read32(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_write32(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((uint32_t volatile *)ICPLB_ADDR4)
+#define bfin_read_ICPLB_ADDR4()        bfin_read32(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_write32(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((uint32_t volatile *)ICPLB_ADDR5)
+#define bfin_read_ICPLB_ADDR5()        bfin_read32(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_write32(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((uint32_t volatile *)ICPLB_ADDR6)
+#define bfin_read_ICPLB_ADDR6()        bfin_read32(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_write32(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((uint32_t volatile *)ICPLB_ADDR7)
+#define bfin_read_ICPLB_ADDR7()        bfin_read32(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_write32(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((uint32_t volatile *)ICPLB_ADDR8)
+#define bfin_read_ICPLB_ADDR8()        bfin_read32(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_write32(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((uint32_t volatile *)ICPLB_ADDR9)
+#define bfin_read_ICPLB_ADDR9()        bfin_read32(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_write32(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((uint32_t volatile *)ICPLB_ADDR10)
+#define bfin_read_ICPLB_ADDR10()       bfin_read32(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_write32(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((uint32_t volatile *)ICPLB_ADDR11)
+#define bfin_read_ICPLB_ADDR11()       bfin_read32(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_write32(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((uint32_t volatile *)ICPLB_ADDR12)
+#define bfin_read_ICPLB_ADDR12()       bfin_read32(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_write32(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((uint32_t volatile *)ICPLB_ADDR13)
+#define bfin_read_ICPLB_ADDR13()       bfin_read32(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_write32(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((uint32_t volatile *)ICPLB_ADDR14)
+#define bfin_read_ICPLB_ADDR14()       bfin_read32(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_write32(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((uint32_t volatile *)ICPLB_ADDR15)
+#define bfin_read_ICPLB_ADDR15()       bfin_read32(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_write32(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0)
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1)
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2)
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3)
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4)
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5)
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6)
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7)
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8)
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9)
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10)
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11)
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12)
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13)
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14)
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15)
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND)
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0)
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
+#define pSICA_SYSCR                    ((uint16_t volatile *)SICA_SYSCR)
+#define bfin_read_SICA_SYSCR()         bfin_read16(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val)     bfin_write16(SICA_SYSCR, val)
+#define pSICA_RVECT                    ((uint16_t volatile *)SICA_RVECT)
+#define bfin_read_SICA_RVECT()         bfin_read16(SICA_RVECT)
+#define bfin_write_SICA_RVECT(val)     bfin_write16(SICA_RVECT, val)
+#define pSICA_IMASK0                   ((uint32_t volatile *)SICA_IMASK0)
+#define bfin_read_SICA_IMASK0()        bfin_read32(SICA_IMASK0)
+#define bfin_write_SICA_IMASK0(val)    bfin_write32(SICA_IMASK0, val)
+#define pSICA_IMASK1                   ((uint32_t volatile *)SICA_IMASK1)
+#define bfin_read_SICA_IMASK1()        bfin_read32(SICA_IMASK1)
+#define bfin_write_SICA_IMASK1(val)    bfin_write32(SICA_IMASK1, val)
+#define pSICA_ISR0                     ((uint32_t volatile *)SICA_ISR0)
+#define bfin_read_SICA_ISR0()          bfin_read32(SICA_ISR0)
+#define bfin_write_SICA_ISR0(val)      bfin_write32(SICA_ISR0, val)
+#define pSICA_ISR1                     ((uint32_t volatile *)SICA_ISR1)
+#define bfin_read_SICA_ISR1()          bfin_read32(SICA_ISR1)
+#define bfin_write_SICA_ISR1(val)      bfin_write32(SICA_ISR1, val)
+#define pSICA_IWR0                     ((uint32_t volatile *)SICA_IWR0)
+#define bfin_read_SICA_IWR0()          bfin_read32(SICA_IWR0)
+#define bfin_write_SICA_IWR0(val)      bfin_write32(SICA_IWR0, val)
+#define pSICA_IWR1                     ((uint32_t volatile *)SICA_IWR1)
+#define bfin_read_SICA_IWR1()          bfin_read32(SICA_IWR1)
+#define bfin_write_SICA_IWR1(val)      bfin_write32(SICA_IWR1, val)
+#define pSICA_IAR0                     ((uint32_t volatile *)SICA_IAR0)
+#define bfin_read_SICA_IAR0()          bfin_read32(SICA_IAR0)
+#define bfin_write_SICA_IAR0(val)      bfin_write32(SICA_IAR0, val)
+#define pSICA_IAR1                     ((uint32_t volatile *)SICA_IAR1)
+#define bfin_read_SICA_IAR1()          bfin_read32(SICA_IAR1)
+#define bfin_write_SICA_IAR1(val)      bfin_write32(SICA_IAR1, val)
+#define pSICA_IAR2                     ((uint32_t volatile *)SICA_IAR2)
+#define bfin_read_SICA_IAR2()          bfin_read32(SICA_IAR2)
+#define bfin_write_SICA_IAR2(val)      bfin_write32(SICA_IAR2, val)
+#define pSICA_IAR3                     ((uint32_t volatile *)SICA_IAR3)
+#define bfin_read_SICA_IAR3()          bfin_read32(SICA_IAR3)
+#define bfin_write_SICA_IAR3(val)      bfin_write32(SICA_IAR3, val)
+#define pSICA_IAR4                     ((uint32_t volatile *)SICA_IAR4)
+#define bfin_read_SICA_IAR4()          bfin_read32(SICA_IAR4)
+#define bfin_write_SICA_IAR4(val)      bfin_write32(SICA_IAR4, val)
+#define pSICA_IAR5                     ((uint32_t volatile *)SICA_IAR5)
+#define bfin_read_SICA_IAR5()          bfin_read32(SICA_IAR5)
+#define bfin_write_SICA_IAR5(val)      bfin_write32(SICA_IAR5, val)
+#define pSICA_IAR6                     ((uint32_t volatile *)SICA_IAR6)
+#define bfin_read_SICA_IAR6()          bfin_read32(SICA_IAR6)
+#define bfin_write_SICA_IAR6(val)      bfin_write32(SICA_IAR6, val)
+#define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
+#define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
+#define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
+#define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
+#define pSICB_SYSCR                    ((uint16_t volatile *)SICB_SYSCR)
+#define bfin_read_SICB_SYSCR()         bfin_read16(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val)     bfin_write16(SICB_SYSCR, val)
+#define pSICB_RVECT                    ((uint16_t volatile *)SICB_RVECT)
+#define bfin_read_SICB_RVECT()         bfin_read16(SICB_RVECT)
+#define bfin_write_SICB_RVECT(val)     bfin_write16(SICB_RVECT, val)
+#define pSICB_IMASK0                   ((uint32_t volatile *)SICB_IMASK0)
+#define bfin_read_SICB_IMASK0()        bfin_read32(SICB_IMASK0)
+#define bfin_write_SICB_IMASK0(val)    bfin_write32(SICB_IMASK0, val)
+#define pSICB_IMASK1                   ((uint32_t volatile *)SICB_IMASK1)
+#define bfin_read_SICB_IMASK1()        bfin_read32(SICB_IMASK1)
+#define bfin_write_SICB_IMASK1(val)    bfin_write32(SICB_IMASK1, val)
+#define pSICB_ISR0                     ((uint32_t volatile *)SICB_ISR0)
+#define bfin_read_SICB_ISR0()          bfin_read32(SICB_ISR0)
+#define bfin_write_SICB_ISR0(val)      bfin_write32(SICB_ISR0, val)
+#define pSICB_ISR1                     ((uint32_t volatile *)SICB_ISR1)
+#define bfin_read_SICB_ISR1()          bfin_read32(SICB_ISR1)
+#define bfin_write_SICB_ISR1(val)      bfin_write32(SICB_ISR1, val)
+#define pSICB_IWR0                     ((uint32_t volatile *)SICB_IWR0)
+#define bfin_read_SICB_IWR0()          bfin_read32(SICB_IWR0)
+#define bfin_write_SICB_IWR0(val)      bfin_write32(SICB_IWR0, val)
+#define pSICB_IWR1                     ((uint32_t volatile *)SICB_IWR1)
+#define bfin_read_SICB_IWR1()          bfin_read32(SICB_IWR1)
+#define bfin_write_SICB_IWR1(val)      bfin_write32(SICB_IWR1, val)
+#define pSICB_IAR0                     ((uint32_t volatile *)SICB_IAR0)
+#define bfin_read_SICB_IAR0()          bfin_read32(SICB_IAR0)
+#define bfin_write_SICB_IAR0(val)      bfin_write32(SICB_IAR0, val)
+#define pSICB_IAR1                     ((uint32_t volatile *)SICB_IAR1)
+#define bfin_read_SICB_IAR1()          bfin_read32(SICB_IAR1)
+#define bfin_write_SICB_IAR1(val)      bfin_write32(SICB_IAR1, val)
+#define pSICB_IAR2                     ((uint32_t volatile *)SICB_IAR2)
+#define bfin_read_SICB_IAR2()          bfin_read32(SICB_IAR2)
+#define bfin_write_SICB_IAR2(val)      bfin_write32(SICB_IAR2, val)
+#define pSICB_IAR3                     ((uint32_t volatile *)SICB_IAR3)
+#define bfin_read_SICB_IAR3()          bfin_read32(SICB_IAR3)
+#define bfin_write_SICB_IAR3(val)      bfin_write32(SICB_IAR3, val)
+#define pSICB_IAR4                     ((uint32_t volatile *)SICB_IAR4)
+#define bfin_read_SICB_IAR4()          bfin_read32(SICB_IAR4)
+#define bfin_write_SICB_IAR4(val)      bfin_write32(SICB_IAR4, val)
+#define pSICB_IAR5                     ((uint32_t volatile *)SICB_IAR5)
+#define bfin_read_SICB_IAR5()          bfin_read32(SICB_IAR5)
+#define bfin_write_SICB_IAR5(val)      bfin_write32(SICB_IAR5, val)
+#define pSICB_IAR6                     ((uint32_t volatile *)SICB_IAR6)
+#define bfin_read_SICB_IAR6()          bfin_read32(SICB_IAR6)
+#define bfin_write_SICB_IAR6(val)      bfin_write32(SICB_IAR6, val)
+#define pSICB_IAR7                     ((uint32_t volatile *)SICB_IAR7)
+#define bfin_read_SICB_IAR7()          bfin_read32(SICB_IAR7)
+#define bfin_write_SICB_IAR7(val)      bfin_write32(SICB_IAR7, val)
+#define pPPI0_CONTROL                  ((uint16_t volatile *)PPI0_CONTROL)
+#define bfin_read_PPI0_CONTROL()       bfin_read16(PPI0_CONTROL)
+#define bfin_write_PPI0_CONTROL(val)   bfin_write16(PPI0_CONTROL, val)
+#define pPPI0_STATUS                   ((uint16_t volatile *)PPI0_STATUS)
+#define bfin_read_PPI0_STATUS()        bfin_read16(PPI0_STATUS)
+#define bfin_write_PPI0_STATUS(val)    bfin_write16(PPI0_STATUS, val)
+#define pPPI0_DELAY                    ((uint16_t volatile *)PPI0_DELAY)
+#define bfin_read_PPI0_DELAY()         bfin_read16(PPI0_DELAY)
+#define bfin_write_PPI0_DELAY(val)     bfin_write16(PPI0_DELAY, val)
+#define pPPI0_COUNT                    ((uint16_t volatile *)PPI0_COUNT)
+#define bfin_read_PPI0_COUNT()         bfin_read16(PPI0_COUNT)
+#define bfin_write_PPI0_COUNT(val)     bfin_write16(PPI0_COUNT, val)
+#define pPPI0_FRAME                    ((uint16_t volatile *)PPI0_FRAME)
+#define bfin_read_PPI0_FRAME()         bfin_read16(PPI0_FRAME)
+#define bfin_write_PPI0_FRAME(val)     bfin_write16(PPI0_FRAME, val)
+#define pPPI1_CONTROL                  ((uint16_t volatile *)PPI1_CONTROL)
+#define bfin_read_PPI1_CONTROL()       bfin_read16(PPI1_CONTROL)
+#define bfin_write_PPI1_CONTROL(val)   bfin_write16(PPI1_CONTROL, val)
+#define pPPI1_STATUS                   ((uint16_t volatile *)PPI1_STATUS)
+#define bfin_read_PPI1_STATUS()        bfin_read16(PPI1_STATUS)
+#define bfin_write_PPI1_STATUS(val)    bfin_write16(PPI1_STATUS, val)
+#define pPPI1_DELAY                    ((uint16_t volatile *)PPI1_DELAY)
+#define bfin_read_PPI1_DELAY()         bfin_read16(PPI1_DELAY)
+#define bfin_write_PPI1_DELAY(val)     bfin_write16(PPI1_DELAY, val)
+#define pPPI1_COUNT                    ((uint16_t volatile *)PPI1_COUNT)
+#define bfin_read_PPI1_COUNT()         bfin_read16(PPI1_COUNT)
+#define bfin_write_PPI1_COUNT(val)     bfin_write16(PPI1_COUNT, val)
+#define pPPI1_FRAME                    ((uint16_t volatile *)PPI1_FRAME)
+#define bfin_read_PPI1_FRAME()         bfin_read16(PPI1_FRAME)
+#define bfin_write_PPI1_FRAME(val)     bfin_write16(PPI1_FRAME, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL)
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT)
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((uint32_t volatile *)TBUF)
+#define bfin_read_TBUF()               bfin_read32(TBUF)
+#define bfin_write_TBUF(val)           bfin_write32(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pSRAM_BASE_ADDR_CORE_A         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A)
+#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
+#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
+#define pSRAM_BASE_ADDR_CORE_B         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B)
+#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
+#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
+#define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
+#define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
+#define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
+#define pUART_THR                      ((uint16_t volatile *)UART_THR)
+#define bfin_read_UART_THR()           bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
+#define pUART_RBR                      ((uint16_t volatile *)UART_RBR)
+#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
+#define pUART_DLL                      ((uint16_t volatile *)UART_DLL)
+#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
+#define pUART_DLH                      ((uint16_t volatile *)UART_DLH)
+#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
+#define pUART_IER                      ((uint16_t volatile *)UART_IER)
+#define bfin_read_UART_IER()           bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
+#define pUART_IIR                      ((uint16_t volatile *)UART_IIR)
+#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
+#define pUART_LCR                      ((uint16_t volatile *)UART_LCR)
+#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
+#define pUART_MCR                      ((uint16_t volatile *)UART_MCR)
+#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
+#define pUART_LSR                      ((uint16_t volatile *)UART_LSR)
+#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
+#define pUART_MSR                      ((uint16_t volatile *)UART_MSR)
+#define bfin_read_UART_MSR()           bfin_read16(UART_MSR)
+#define bfin_write_UART_MSR(val)       bfin_write16(UART_MSR, val)
+#define pUART_SCR                      ((uint16_t volatile *)UART_SCR)
+#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
+#define pUART_GCTL                     ((uint16_t volatile *)UART_GCTL)
+#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
+#define pUART_GBL                      ((uint16_t volatile *)UART_GBL)
+#define bfin_read_UART_GBL()           bfin_read16(UART_GBL)
+#define bfin_write_UART_GBL(val)       bfin_write16(UART_GBL, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL)
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0)
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1)
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL)
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint32_t volatile *)EBIU_SDBCTL)
+#define bfin_read_EBIU_SDBCTL()        bfin_read32(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write32(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC)
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT)
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
new file mode 100644
index 0000000..8534962
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
@@ -0,0 +1,173 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF561_proc__
+#define __BFIN_DEF_ADSP_BF561_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
+
+#define SRAM_BASE_ADDR                 0xFFE00000
+#define DMEM_CONTROL                   0xFFE00004
+#define DCPLB_STATUS                   0xFFE00008
+#define DCPLB_FAULT_ADDR               0xFFE0000C
+#define DCPLB_ADDR0                    0xFFE00100
+#define DCPLB_ADDR1                    0xFFE00104
+#define DCPLB_ADDR2                    0xFFE00108
+#define DCPLB_ADDR3                    0xFFE0010C
+#define DCPLB_ADDR4                    0xFFE00110
+#define DCPLB_ADDR5                    0xFFE00114
+#define DCPLB_ADDR6                    0xFFE00118
+#define DCPLB_ADDR7                    0xFFE0011C
+#define DCPLB_ADDR8                    0xFFE00120
+#define DCPLB_ADDR9                    0xFFE00124
+#define DCPLB_ADDR10                   0xFFE00128
+#define DCPLB_ADDR11                   0xFFE0012C
+#define DCPLB_ADDR12                   0xFFE00130
+#define DCPLB_ADDR13                   0xFFE00134
+#define DCPLB_ADDR14                   0xFFE00138
+#define DCPLB_ADDR15                   0xFFE0013C
+#define DCPLB_DATA0                    0xFFE00200
+#define DCPLB_DATA1                    0xFFE00204
+#define DCPLB_DATA2                    0xFFE00208
+#define DCPLB_DATA3                    0xFFE0020C
+#define DCPLB_DATA4                    0xFFE00210
+#define DCPLB_DATA5                    0xFFE00214
+#define DCPLB_DATA6                    0xFFE00218
+#define DCPLB_DATA7                    0xFFE0021C
+#define DCPLB_DATA8                    0xFFE00220
+#define DCPLB_DATA9                    0xFFE00224
+#define DCPLB_DATA10                   0xFFE00228
+#define DCPLB_DATA11                   0xFFE0022C
+#define DCPLB_DATA12                   0xFFE00230
+#define DCPLB_DATA13                   0xFFE00234
+#define DCPLB_DATA14                   0xFFE00238
+#define DCPLB_DATA15                   0xFFE0023C
+#define DTEST_COMMAND                  0xFFE00300
+#define DTEST_DATA0                    0xFFE00400
+#define DTEST_DATA1                    0xFFE00404
+#define IMEM_CONTROL                   0xFFE01004
+#define ICPLB_STATUS                   0xFFE01008
+#define ICPLB_FAULT_ADDR               0xFFE0100C
+#define ICPLB_ADDR0                    0xFFE01100
+#define ICPLB_ADDR1                    0xFFE01104
+#define ICPLB_ADDR2                    0xFFE01108
+#define ICPLB_ADDR3                    0xFFE0110C
+#define ICPLB_ADDR4                    0xFFE01110
+#define ICPLB_ADDR5                    0xFFE01114
+#define ICPLB_ADDR6                    0xFFE01118
+#define ICPLB_ADDR7                    0xFFE0111C
+#define ICPLB_ADDR8                    0xFFE01120
+#define ICPLB_ADDR9                    0xFFE01124
+#define ICPLB_ADDR10                   0xFFE01128
+#define ICPLB_ADDR11                   0xFFE0112C
+#define ICPLB_ADDR12                   0xFFE01130
+#define ICPLB_ADDR13                   0xFFE01134
+#define ICPLB_ADDR14                   0xFFE01138
+#define ICPLB_ADDR15                   0xFFE0113C
+#define ICPLB_DATA0                    0xFFE01200
+#define ICPLB_DATA1                    0xFFE01204
+#define ICPLB_DATA2                    0xFFE01208
+#define ICPLB_DATA3                    0xFFE0120C
+#define ICPLB_DATA4                    0xFFE01210
+#define ICPLB_DATA5                    0xFFE01214
+#define ICPLB_DATA6                    0xFFE01218
+#define ICPLB_DATA7                    0xFFE0121C
+#define ICPLB_DATA8                    0xFFE01220
+#define ICPLB_DATA9                    0xFFE01224
+#define ICPLB_DATA10                   0xFFE01228
+#define ICPLB_DATA11                   0xFFE0122C
+#define ICPLB_DATA12                   0xFFE01230
+#define ICPLB_DATA13                   0xFFE01234
+#define ICPLB_DATA14                   0xFFE01238
+#define ICPLB_DATA15                   0xFFE0123C
+#define ITEST_COMMAND                  0xFFE01300
+#define ITEST_DATA0                    0xFFE01400
+#define ITEST_DATA1                    0xFFE01404
+#define SICA_SWRST                     0xFFC00100
+#define SICA_SYSCR                     0xFFC00104
+#define SICA_RVECT                     0xFFC00108
+#define SICA_IMASK0                    0xFFC0010C
+#define SICA_IMASK1                    0xFFC00110
+#define SICA_ISR0                      0xFFC00114
+#define SICA_ISR1                      0xFFC00118
+#define SICA_IWR0                      0xFFC0011C
+#define SICA_IWR1                      0xFFC00120
+#define SICA_IAR0                      0xFFC00124
+#define SICA_IAR1                      0xFFC00128
+#define SICA_IAR2                      0xFFC0012C
+#define SICA_IAR3                      0xFFC00130
+#define SICA_IAR4                      0xFFC00134
+#define SICA_IAR5                      0xFFC00138
+#define SICA_IAR6                      0xFFC0013C
+#define SICA_IAR7                      0xFFC00140
+#define SICB_SWRST                     0xFFC01100
+#define SICB_SYSCR                     0xFFC01104
+#define SICB_RVECT                     0xFFC01108
+#define SICB_IMASK0                    0xFFC0110C
+#define SICB_IMASK1                    0xFFC01110
+#define SICB_ISR0                      0xFFC01114
+#define SICB_ISR1                      0xFFC01118
+#define SICB_IWR0                      0xFFC0111C
+#define SICB_IWR1                      0xFFC01120
+#define SICB_IAR0                      0xFFC01124
+#define SICB_IAR1                      0xFFC01128
+#define SICB_IAR2                      0xFFC0112C
+#define SICB_IAR3                      0xFFC01130
+#define SICB_IAR4                      0xFFC01134
+#define SICB_IAR5                      0xFFC01138
+#define SICB_IAR6                      0xFFC0113C
+#define SICB_IAR7                      0xFFC01140
+#define PPI0_CONTROL                   0xFFC01000
+#define PPI0_STATUS                    0xFFC01004
+#define PPI0_DELAY                     0xFFC0100C
+#define PPI0_COUNT                     0xFFC01008
+#define PPI0_FRAME                     0xFFC01010
+#define PPI1_CONTROL                   0xFFC01300
+#define PPI1_STATUS                    0xFFC01304
+#define PPI1_DELAY                     0xFFC0130C
+#define PPI1_COUNT                     0xFFC01308
+#define PPI1_FRAME                     0xFFC01310
+#define TBUFCTL                        0xFFE06000
+#define TBUFSTAT                       0xFFE06004
+#define TBUF                           0xFFE06100
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define SRAM_BASE_ADDR_CORE_A          0xFFE00000
+#define SRAM_BASE_ADDR_CORE_B          0xFFE00000
+#define EVT_OVERRIDE                   0xFFE02100
+#define UART_THR                       0xFFC00400
+#define UART_RBR                       0xFFC00400
+#define UART_DLL                       0xFFC00400
+#define UART_DLH                       0xFFC00404
+#define UART_IER                       0xFFC00404
+#define UART_IIR                       0xFFC00408
+#define UART_LCR                       0xFFC0040C
+#define UART_MCR                       0xFFC00410
+#define UART_LSR                       0xFFC00414
+#define UART_MSR                       0xFFC00418
+#define UART_SCR                       0xFFC0041C
+#define UART_GCTL                      0xFFC00424
+#define UART_GBL                       0xFFC00424
+#define EBIU_AMGCTL                    0xFFC00A00
+#define EBIU_AMBCTL0                   0xFFC00A04
+#define EBIU_AMBCTL1                   0xFFC00A08
+#define EBIU_SDGCTL                    0xFFC00A10
+#define EBIU_SDBCTL                    0xFFC00A14
+#define EBIU_SDRRC                     0xFFC00A18
+#define EBIU_SDSTAT                    0xFFC00A1C
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h
new file mode 100644
index 0000000..e4aa20c
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h
@@ -0,0 +1,294 @@
+/*
+ * File: include/asm-blackfin/mach-bf561/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file should be up to date with:
+ *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
+#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
+# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
+#endif
+
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
+#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
+/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Testset instructions restricted to 32-bit aligned memory locations */
+#define ANOMALY_05000120 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Erroneous exception when enabling cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Signbits instruction not functional under certain conditions */
+#define ANOMALY_05000127 (1)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* IMDMA S1/D1 channel may stall */
+#define ANOMALY_05000149 (1)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
+#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT transmit data is not gated by external frame sync in certain conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
+#define ANOMALY_05000167 (1)
+/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
+/* DATA CPLB page miss can result in lost write-through cache data writes */
+#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
+/* Boot-ROM code modifies SICA_IWRx wakeup registers */
+#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
+/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
+/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* Disabling the PPI resets the PPI configuration registers */
+#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
+/* IMDMA does not operate to full speed for 600MHz and higher devices */
+#define ANOMALY_05000182 (1)
+/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
+/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
+/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
+#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
+/* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000187 (1)
+/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
+#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
+/* False Protection Exceptions */
+#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
+/* PPI not functional at core voltage < 1Volt */
+#define ANOMALY_05000190 (1)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
+/* Restarting SPORT in Specific Modes May Cause Data Corruption */
+#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
+/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
+/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
+#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
+/* Possible Infinite Stall with Specific Dual-DAG Situation */
+#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
+/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
+/* Specific sequence that can cause DMA error or DMA stopping */
+#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
+/* Recovery from "Brown-Out" Condition */
+#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
+/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
+#define ANOMALY_05000208 (1)
+/* Speed Path in Computational Unit Affects Certain Instructions */
+#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
+/* UART TX Interrupt Masked Erroneously */
+#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
+/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
+/* Incorrect Pulse-Width of UART Start Bit */
+#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
+/* Scratchpad Memory Bank Reads May Return Incorrect Data */
+#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
+/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
+#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
+/* UART STB Bit Incorrectly Affects Receiver Setting */
+#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
+/* SPORT data transmit lines are incorrectly driven in multichannel mode */
+#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
+/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
+/* TESTSET operation forces stall on the other core */
+#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
+/* Exception Not Generated for MMR Accesses in Reserved Region */
+#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+/* IMDMA destination IRQ status must be read prior to using IMDMA */
+#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
+/* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000267 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
+#define ANOMALY_05000269 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Data cache write back to external synchronous memory may be lost */
+#define ANOMALY_05000274 (1)
+/* PPI Timing and Sampling Information Updates */
+#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
+/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
+#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (1)
+/* A read will receive incorrect data under certain conditions */
+#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+#define ANOMALY_05000302 (1)
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (1)
+/* PF2 Output Remains Asserted After SPI Master Boot */
+#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
+/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
+#define ANOMALY_05000323 (1)
+/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
+#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
+/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
+#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
+/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
+#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
+/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
+#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
+#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
+/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
+#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Conflicting Column Address Widths Causes SDRAM Errors */
+#define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
+/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
+#define ANOMALY_05000412 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
+#define ANOMALY_05000425 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
+#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (1)
+#define ANOMALY_05000430 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf561/def_local.h b/arch/blackfin/include/asm/mach-bf561/def_local.h
new file mode 100644
index 0000000..597dcec
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/def_local.h
@@ -0,0 +1,12 @@
+#define SWRST SICA_SWRST
+#define SYSCR SICA_SYSCR
+#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
+#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
+
+#define WDOG_CNT WDOGA_CNT
+#define WDOG_CTL WDOGA_CTL
+#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
+#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
+#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
+
+#include "ports.h"
diff --git a/arch/blackfin/include/asm/mach-bf561/ports.h b/arch/blackfin/include/asm/mach-bf561/ports.h
new file mode 100644
index 0000000..194d4a3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf561/ports.h
@@ -0,0 +1,44 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-f.h"
+
+/* The non-standard PF16+ */
+#define PF16		(1 << 0)
+#define PF17		(1 << 1)
+#define PF18		(1 << 2)
+#define PF19		(1 << 3)
+#define PF20		(1 << 4)
+#define PF21		(1 << 5)
+#define PF22		(1 << 6)
+#define PF23		(1 << 7)
+#define PF24		(1 << 8)
+#define PF25		(1 << 9)
+#define PF26		(1 << 10)
+#define PF27		(1 << 11)
+#define PF28		(1 << 12)
+#define PF29		(1 << 13)
+#define PF30		(1 << 14)
+#define PF31		(1 << 15)
+#define PF32		(1 << 0)
+#define PF33		(1 << 1)
+#define PF34		(1 << 2)
+#define PF35		(1 << 3)
+#define PF36		(1 << 4)
+#define PF37		(1 << 5)
+#define PF38		(1 << 6)
+#define PF39		(1 << 7)
+#define PF40		(1 << 8)
+#define PF41		(1 << 9)
+#define PF42		(1 << 10)
+#define PF43		(1 << 11)
+#define PF44		(1 << 12)
+#define PF45		(1 << 13)
+#define PF46		(1 << 14)
+#define PF47		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
new file mode 100644
index 0000000..43f3850
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
@@ -0,0 +1,1988 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
+#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
+
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL)
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV)
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL)
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT)
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT)
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL)
+#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
+#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG)
+#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
+#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT)
+#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
+#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR)
+#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
+#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR)
+#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
+#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD)
+#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
+#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW)
+#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
+#define pWDOGA_CTL                     ((uint16_t volatile *)WDOGA_CTL)
+#define bfin_read_WDOGA_CTL()          bfin_read16(WDOGA_CTL)
+#define bfin_write_WDOGA_CTL(val)      bfin_write16(WDOGA_CTL, val)
+#define pWDOGA_CNT                     ((uint32_t volatile *)WDOGA_CNT)
+#define bfin_read_WDOGA_CNT()          bfin_read32(WDOGA_CNT)
+#define bfin_write_WDOGA_CNT(val)      bfin_write32(WDOGA_CNT, val)
+#define pWDOGA_STAT                    ((uint32_t volatile *)WDOGA_STAT)
+#define bfin_read_WDOGA_STAT()         bfin_read32(WDOGA_STAT)
+#define bfin_write_WDOGA_STAT(val)     bfin_write32(WDOGA_STAT, val)
+#define pWDOGB_CTL                     ((uint16_t volatile *)WDOGB_CTL)
+#define bfin_read_WDOGB_CTL()          bfin_read16(WDOGB_CTL)
+#define bfin_write_WDOGB_CTL(val)      bfin_write16(WDOGB_CTL, val)
+#define pWDOGB_CNT                     ((uint32_t volatile *)WDOGB_CNT)
+#define bfin_read_WDOGB_CNT()          bfin_read32(WDOGB_CNT)
+#define bfin_write_WDOGB_CNT(val)      bfin_write32(WDOGB_CNT, val)
+#define pWDOGB_STAT                    ((uint32_t volatile *)WDOGB_STAT)
+#define bfin_read_WDOGB_STAT()         bfin_read32(WDOGB_STAT)
+#define bfin_write_WDOGB_STAT(val)     bfin_write32(WDOGB_STAT, val)
+#define pDMA1_TC_PER                   ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */
+#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
+#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
+#define pDMA1_TC_CNT                   ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */
+#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
+#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
+#define pDMA1_0_CONFIG                 ((uint16_t volatile *)DMA1_0_CONFIG)
+#define bfin_read_DMA1_0_CONFIG()      bfin_read16(DMA1_0_CONFIG)
+#define bfin_write_DMA1_0_CONFIG(val)  bfin_write16(DMA1_0_CONFIG, val)
+#define pDMA1_0_NEXT_DESC_PTR          ((void * volatile *)DMA1_0_NEXT_DESC_PTR)
+#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
+#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
+#define pDMA1_0_START_ADDR             ((void * volatile *)DMA1_0_START_ADDR)
+#define bfin_read_DMA1_0_START_ADDR()  bfin_readPTR(DMA1_0_START_ADDR)
+#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
+#define pDMA1_0_X_COUNT                ((uint16_t volatile *)DMA1_0_X_COUNT)
+#define bfin_read_DMA1_0_X_COUNT()     bfin_read16(DMA1_0_X_COUNT)
+#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
+#define pDMA1_0_Y_COUNT                ((uint16_t volatile *)DMA1_0_Y_COUNT)
+#define bfin_read_DMA1_0_Y_COUNT()     bfin_read16(DMA1_0_Y_COUNT)
+#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
+#define pDMA1_0_X_MODIFY               ((uint16_t volatile *)DMA1_0_X_MODIFY)
+#define bfin_read_DMA1_0_X_MODIFY()    bfin_read16(DMA1_0_X_MODIFY)
+#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
+#define pDMA1_0_Y_MODIFY               ((uint16_t volatile *)DMA1_0_Y_MODIFY)
+#define bfin_read_DMA1_0_Y_MODIFY()    bfin_read16(DMA1_0_Y_MODIFY)
+#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
+#define pDMA1_0_CURR_DESC_PTR          ((void * volatile *)DMA1_0_CURR_DESC_PTR)
+#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
+#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
+#define pDMA1_0_CURR_ADDR              ((void * volatile *)DMA1_0_CURR_ADDR)
+#define bfin_read_DMA1_0_CURR_ADDR()   bfin_readPTR(DMA1_0_CURR_ADDR)
+#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
+#define pDMA1_0_CURR_X_COUNT           ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
+#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
+#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
+#define pDMA1_0_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)
+#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
+#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
+#define pDMA1_0_IRQ_STATUS             ((uint16_t volatile *)DMA1_0_IRQ_STATUS)
+#define bfin_read_DMA1_0_IRQ_STATUS()  bfin_read16(DMA1_0_IRQ_STATUS)
+#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
+#define pDMA1_0_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)
+#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
+#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
+#define pDMA1_1_CONFIG                 ((uint16_t volatile *)DMA1_1_CONFIG)
+#define bfin_read_DMA1_1_CONFIG()      bfin_read16(DMA1_1_CONFIG)
+#define bfin_write_DMA1_1_CONFIG(val)  bfin_write16(DMA1_1_CONFIG, val)
+#define pDMA1_1_NEXT_DESC_PTR          ((void * volatile *)DMA1_1_NEXT_DESC_PTR)
+#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
+#define pDMA1_1_START_ADDR             ((void * volatile *)DMA1_1_START_ADDR)
+#define bfin_read_DMA1_1_START_ADDR()  bfin_readPTR(DMA1_1_START_ADDR)
+#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
+#define pDMA1_1_X_COUNT                ((uint16_t volatile *)DMA1_1_X_COUNT)
+#define bfin_read_DMA1_1_X_COUNT()     bfin_read16(DMA1_1_X_COUNT)
+#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
+#define pDMA1_1_Y_COUNT                ((uint16_t volatile *)DMA1_1_Y_COUNT)
+#define bfin_read_DMA1_1_Y_COUNT()     bfin_read16(DMA1_1_Y_COUNT)
+#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
+#define pDMA1_1_X_MODIFY               ((uint16_t volatile *)DMA1_1_X_MODIFY)
+#define bfin_read_DMA1_1_X_MODIFY()    bfin_read16(DMA1_1_X_MODIFY)
+#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
+#define pDMA1_1_Y_MODIFY               ((uint16_t volatile *)DMA1_1_Y_MODIFY)
+#define bfin_read_DMA1_1_Y_MODIFY()    bfin_read16(DMA1_1_Y_MODIFY)
+#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
+#define pDMA1_1_CURR_DESC_PTR          ((void * volatile *)DMA1_1_CURR_DESC_PTR)
+#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
+#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
+#define pDMA1_1_CURR_ADDR              ((void * volatile *)DMA1_1_CURR_ADDR)
+#define bfin_read_DMA1_1_CURR_ADDR()   bfin_readPTR(DMA1_1_CURR_ADDR)
+#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
+#define pDMA1_1_CURR_X_COUNT           ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
+#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
+#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
+#define pDMA1_1_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)
+#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
+#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
+#define pDMA1_1_IRQ_STATUS             ((uint16_t volatile *)DMA1_1_IRQ_STATUS)
+#define bfin_read_DMA1_1_IRQ_STATUS()  bfin_read16(DMA1_1_IRQ_STATUS)
+#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
+#define pDMA1_1_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)
+#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
+#define pDMA1_2_CONFIG                 ((uint16_t volatile *)DMA1_2_CONFIG)
+#define bfin_read_DMA1_2_CONFIG()      bfin_read16(DMA1_2_CONFIG)
+#define bfin_write_DMA1_2_CONFIG(val)  bfin_write16(DMA1_2_CONFIG, val)
+#define pDMA1_2_NEXT_DESC_PTR          ((void * volatile *)DMA1_2_NEXT_DESC_PTR)
+#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
+#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
+#define pDMA1_2_START_ADDR             ((void * volatile *)DMA1_2_START_ADDR)
+#define bfin_read_DMA1_2_START_ADDR()  bfin_readPTR(DMA1_2_START_ADDR)
+#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
+#define pDMA1_2_X_COUNT                ((uint16_t volatile *)DMA1_2_X_COUNT)
+#define bfin_read_DMA1_2_X_COUNT()     bfin_read16(DMA1_2_X_COUNT)
+#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
+#define pDMA1_2_Y_COUNT                ((uint16_t volatile *)DMA1_2_Y_COUNT)
+#define bfin_read_DMA1_2_Y_COUNT()     bfin_read16(DMA1_2_Y_COUNT)
+#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
+#define pDMA1_2_X_MODIFY               ((uint16_t volatile *)DMA1_2_X_MODIFY)
+#define bfin_read_DMA1_2_X_MODIFY()    bfin_read16(DMA1_2_X_MODIFY)
+#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
+#define pDMA1_2_Y_MODIFY               ((uint16_t volatile *)DMA1_2_Y_MODIFY)
+#define bfin_read_DMA1_2_Y_MODIFY()    bfin_read16(DMA1_2_Y_MODIFY)
+#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
+#define pDMA1_2_CURR_DESC_PTR          ((void * volatile *)DMA1_2_CURR_DESC_PTR)
+#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
+#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
+#define pDMA1_2_CURR_ADDR              ((void * volatile *)DMA1_2_CURR_ADDR)
+#define bfin_read_DMA1_2_CURR_ADDR()   bfin_readPTR(DMA1_2_CURR_ADDR)
+#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
+#define pDMA1_2_CURR_X_COUNT           ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
+#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
+#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
+#define pDMA1_2_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)
+#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
+#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
+#define pDMA1_2_IRQ_STATUS             ((uint16_t volatile *)DMA1_2_IRQ_STATUS)
+#define bfin_read_DMA1_2_IRQ_STATUS()  bfin_read16(DMA1_2_IRQ_STATUS)
+#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
+#define pDMA1_2_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)
+#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
+#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
+#define pDMA1_3_CONFIG                 ((uint16_t volatile *)DMA1_3_CONFIG)
+#define bfin_read_DMA1_3_CONFIG()      bfin_read16(DMA1_3_CONFIG)
+#define bfin_write_DMA1_3_CONFIG(val)  bfin_write16(DMA1_3_CONFIG, val)
+#define pDMA1_3_NEXT_DESC_PTR          ((void * volatile *)DMA1_3_NEXT_DESC_PTR)
+#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
+#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
+#define pDMA1_3_START_ADDR             ((void * volatile *)DMA1_3_START_ADDR)
+#define bfin_read_DMA1_3_START_ADDR()  bfin_readPTR(DMA1_3_START_ADDR)
+#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
+#define pDMA1_3_X_COUNT                ((uint16_t volatile *)DMA1_3_X_COUNT)
+#define bfin_read_DMA1_3_X_COUNT()     bfin_read16(DMA1_3_X_COUNT)
+#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
+#define pDMA1_3_Y_COUNT                ((uint16_t volatile *)DMA1_3_Y_COUNT)
+#define bfin_read_DMA1_3_Y_COUNT()     bfin_read16(DMA1_3_Y_COUNT)
+#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
+#define pDMA1_3_X_MODIFY               ((uint16_t volatile *)DMA1_3_X_MODIFY)
+#define bfin_read_DMA1_3_X_MODIFY()    bfin_read16(DMA1_3_X_MODIFY)
+#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
+#define pDMA1_3_Y_MODIFY               ((uint16_t volatile *)DMA1_3_Y_MODIFY)
+#define bfin_read_DMA1_3_Y_MODIFY()    bfin_read16(DMA1_3_Y_MODIFY)
+#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
+#define pDMA1_3_CURR_DESC_PTR          ((void * volatile *)DMA1_3_CURR_DESC_PTR)
+#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
+#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
+#define pDMA1_3_CURR_ADDR              ((void * volatile *)DMA1_3_CURR_ADDR)
+#define bfin_read_DMA1_3_CURR_ADDR()   bfin_readPTR(DMA1_3_CURR_ADDR)
+#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
+#define pDMA1_3_CURR_X_COUNT           ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
+#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
+#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
+#define pDMA1_3_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)
+#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
+#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
+#define pDMA1_3_IRQ_STATUS             ((uint16_t volatile *)DMA1_3_IRQ_STATUS)
+#define bfin_read_DMA1_3_IRQ_STATUS()  bfin_read16(DMA1_3_IRQ_STATUS)
+#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
+#define pDMA1_3_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)
+#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
+#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
+#define pDMA1_4_CONFIG                 ((uint16_t volatile *)DMA1_4_CONFIG)
+#define bfin_read_DMA1_4_CONFIG()      bfin_read16(DMA1_4_CONFIG)
+#define bfin_write_DMA1_4_CONFIG(val)  bfin_write16(DMA1_4_CONFIG, val)
+#define pDMA1_4_NEXT_DESC_PTR          ((void * volatile *)DMA1_4_NEXT_DESC_PTR)
+#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
+#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
+#define pDMA1_4_START_ADDR             ((void * volatile *)DMA1_4_START_ADDR)
+#define bfin_read_DMA1_4_START_ADDR()  bfin_readPTR(DMA1_4_START_ADDR)
+#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
+#define pDMA1_4_X_COUNT                ((uint16_t volatile *)DMA1_4_X_COUNT)
+#define bfin_read_DMA1_4_X_COUNT()     bfin_read16(DMA1_4_X_COUNT)
+#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
+#define pDMA1_4_Y_COUNT                ((uint16_t volatile *)DMA1_4_Y_COUNT)
+#define bfin_read_DMA1_4_Y_COUNT()     bfin_read16(DMA1_4_Y_COUNT)
+#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
+#define pDMA1_4_X_MODIFY               ((uint16_t volatile *)DMA1_4_X_MODIFY)
+#define bfin_read_DMA1_4_X_MODIFY()    bfin_read16(DMA1_4_X_MODIFY)
+#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
+#define pDMA1_4_Y_MODIFY               ((uint16_t volatile *)DMA1_4_Y_MODIFY)
+#define bfin_read_DMA1_4_Y_MODIFY()    bfin_read16(DMA1_4_Y_MODIFY)
+#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
+#define pDMA1_4_CURR_DESC_PTR          ((void * volatile *)DMA1_4_CURR_DESC_PTR)
+#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
+#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
+#define pDMA1_4_CURR_ADDR              ((void * volatile *)DMA1_4_CURR_ADDR)
+#define bfin_read_DMA1_4_CURR_ADDR()   bfin_readPTR(DMA1_4_CURR_ADDR)
+#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
+#define pDMA1_4_CURR_X_COUNT           ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
+#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
+#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
+#define pDMA1_4_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)
+#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
+#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
+#define pDMA1_4_IRQ_STATUS             ((uint16_t volatile *)DMA1_4_IRQ_STATUS)
+#define bfin_read_DMA1_4_IRQ_STATUS()  bfin_read16(DMA1_4_IRQ_STATUS)
+#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
+#define pDMA1_4_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)
+#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
+#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
+#define pDMA1_5_CONFIG                 ((uint16_t volatile *)DMA1_5_CONFIG)
+#define bfin_read_DMA1_5_CONFIG()      bfin_read16(DMA1_5_CONFIG)
+#define bfin_write_DMA1_5_CONFIG(val)  bfin_write16(DMA1_5_CONFIG, val)
+#define pDMA1_5_NEXT_DESC_PTR          ((void * volatile *)DMA1_5_NEXT_DESC_PTR)
+#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
+#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
+#define pDMA1_5_START_ADDR             ((void * volatile *)DMA1_5_START_ADDR)
+#define bfin_read_DMA1_5_START_ADDR()  bfin_readPTR(DMA1_5_START_ADDR)
+#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
+#define pDMA1_5_X_COUNT                ((uint16_t volatile *)DMA1_5_X_COUNT)
+#define bfin_read_DMA1_5_X_COUNT()     bfin_read16(DMA1_5_X_COUNT)
+#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
+#define pDMA1_5_Y_COUNT                ((uint16_t volatile *)DMA1_5_Y_COUNT)
+#define bfin_read_DMA1_5_Y_COUNT()     bfin_read16(DMA1_5_Y_COUNT)
+#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
+#define pDMA1_5_X_MODIFY               ((uint16_t volatile *)DMA1_5_X_MODIFY)
+#define bfin_read_DMA1_5_X_MODIFY()    bfin_read16(DMA1_5_X_MODIFY)
+#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
+#define pDMA1_5_Y_MODIFY               ((uint16_t volatile *)DMA1_5_Y_MODIFY)
+#define bfin_read_DMA1_5_Y_MODIFY()    bfin_read16(DMA1_5_Y_MODIFY)
+#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
+#define pDMA1_5_CURR_DESC_PTR          ((void * volatile *)DMA1_5_CURR_DESC_PTR)
+#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
+#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
+#define pDMA1_5_CURR_ADDR              ((void * volatile *)DMA1_5_CURR_ADDR)
+#define bfin_read_DMA1_5_CURR_ADDR()   bfin_readPTR(DMA1_5_CURR_ADDR)
+#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
+#define pDMA1_5_CURR_X_COUNT           ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
+#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
+#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
+#define pDMA1_5_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)
+#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
+#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
+#define pDMA1_5_IRQ_STATUS             ((uint16_t volatile *)DMA1_5_IRQ_STATUS)
+#define bfin_read_DMA1_5_IRQ_STATUS()  bfin_read16(DMA1_5_IRQ_STATUS)
+#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
+#define pDMA1_5_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)
+#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
+#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
+#define pDMA1_6_CONFIG                 ((uint16_t volatile *)DMA1_6_CONFIG)
+#define bfin_read_DMA1_6_CONFIG()      bfin_read16(DMA1_6_CONFIG)
+#define bfin_write_DMA1_6_CONFIG(val)  bfin_write16(DMA1_6_CONFIG, val)
+#define pDMA1_6_NEXT_DESC_PTR          ((void * volatile *)DMA1_6_NEXT_DESC_PTR)
+#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
+#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
+#define pDMA1_6_START_ADDR             ((void * volatile *)DMA1_6_START_ADDR)
+#define bfin_read_DMA1_6_START_ADDR()  bfin_readPTR(DMA1_6_START_ADDR)
+#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
+#define pDMA1_6_X_COUNT                ((uint16_t volatile *)DMA1_6_X_COUNT)
+#define bfin_read_DMA1_6_X_COUNT()     bfin_read16(DMA1_6_X_COUNT)
+#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
+#define pDMA1_6_Y_COUNT                ((uint16_t volatile *)DMA1_6_Y_COUNT)
+#define bfin_read_DMA1_6_Y_COUNT()     bfin_read16(DMA1_6_Y_COUNT)
+#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
+#define pDMA1_6_X_MODIFY               ((uint16_t volatile *)DMA1_6_X_MODIFY)
+#define bfin_read_DMA1_6_X_MODIFY()    bfin_read16(DMA1_6_X_MODIFY)
+#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
+#define pDMA1_6_Y_MODIFY               ((uint16_t volatile *)DMA1_6_Y_MODIFY)
+#define bfin_read_DMA1_6_Y_MODIFY()    bfin_read16(DMA1_6_Y_MODIFY)
+#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
+#define pDMA1_6_CURR_DESC_PTR          ((void * volatile *)DMA1_6_CURR_DESC_PTR)
+#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
+#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
+#define pDMA1_6_CURR_ADDR              ((void * volatile *)DMA1_6_CURR_ADDR)
+#define bfin_read_DMA1_6_CURR_ADDR()   bfin_readPTR(DMA1_6_CURR_ADDR)
+#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
+#define pDMA1_6_CURR_X_COUNT           ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
+#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
+#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
+#define pDMA1_6_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)
+#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
+#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
+#define pDMA1_6_IRQ_STATUS             ((uint16_t volatile *)DMA1_6_IRQ_STATUS)
+#define bfin_read_DMA1_6_IRQ_STATUS()  bfin_read16(DMA1_6_IRQ_STATUS)
+#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
+#define pDMA1_6_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)
+#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
+#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
+#define pDMA1_7_CONFIG                 ((uint16_t volatile *)DMA1_7_CONFIG)
+#define bfin_read_DMA1_7_CONFIG()      bfin_read16(DMA1_7_CONFIG)
+#define bfin_write_DMA1_7_CONFIG(val)  bfin_write16(DMA1_7_CONFIG, val)
+#define pDMA1_7_NEXT_DESC_PTR          ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
+#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
+#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
+#define pDMA1_7_START_ADDR             ((void * volatile *)DMA1_7_START_ADDR)
+#define bfin_read_DMA1_7_START_ADDR()  bfin_readPTR(DMA1_7_START_ADDR)
+#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
+#define pDMA1_7_X_COUNT                ((uint16_t volatile *)DMA1_7_X_COUNT)
+#define bfin_read_DMA1_7_X_COUNT()     bfin_read16(DMA1_7_X_COUNT)
+#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
+#define pDMA1_7_Y_COUNT                ((uint16_t volatile *)DMA1_7_Y_COUNT)
+#define bfin_read_DMA1_7_Y_COUNT()     bfin_read16(DMA1_7_Y_COUNT)
+#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
+#define pDMA1_7_X_MODIFY               ((uint16_t volatile *)DMA1_7_X_MODIFY)
+#define bfin_read_DMA1_7_X_MODIFY()    bfin_read16(DMA1_7_X_MODIFY)
+#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
+#define pDMA1_7_Y_MODIFY               ((uint16_t volatile *)DMA1_7_Y_MODIFY)
+#define bfin_read_DMA1_7_Y_MODIFY()    bfin_read16(DMA1_7_Y_MODIFY)
+#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
+#define pDMA1_7_CURR_DESC_PTR          ((void * volatile *)DMA1_7_CURR_DESC_PTR)
+#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
+#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
+#define pDMA1_7_CURR_ADDR              ((void * volatile *)DMA1_7_CURR_ADDR)
+#define bfin_read_DMA1_7_CURR_ADDR()   bfin_readPTR(DMA1_7_CURR_ADDR)
+#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
+#define pDMA1_7_CURR_X_COUNT           ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
+#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
+#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
+#define pDMA1_7_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)
+#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
+#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
+#define pDMA1_7_IRQ_STATUS             ((uint16_t volatile *)DMA1_7_IRQ_STATUS)
+#define bfin_read_DMA1_7_IRQ_STATUS()  bfin_read16(DMA1_7_IRQ_STATUS)
+#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
+#define pDMA1_7_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)
+#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
+#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
+#define pDMA1_8_CONFIG                 ((uint16_t volatile *)DMA1_8_CONFIG)
+#define bfin_read_DMA1_8_CONFIG()      bfin_read16(DMA1_8_CONFIG)
+#define bfin_write_DMA1_8_CONFIG(val)  bfin_write16(DMA1_8_CONFIG, val)
+#define pDMA1_8_NEXT_DESC_PTR          ((void * volatile *)DMA1_8_NEXT_DESC_PTR)
+#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
+#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
+#define pDMA1_8_START_ADDR             ((void * volatile *)DMA1_8_START_ADDR)
+#define bfin_read_DMA1_8_START_ADDR()  bfin_readPTR(DMA1_8_START_ADDR)
+#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
+#define pDMA1_8_X_COUNT                ((uint16_t volatile *)DMA1_8_X_COUNT)
+#define bfin_read_DMA1_8_X_COUNT()     bfin_read16(DMA1_8_X_COUNT)
+#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
+#define pDMA1_8_Y_COUNT                ((uint16_t volatile *)DMA1_8_Y_COUNT)
+#define bfin_read_DMA1_8_Y_COUNT()     bfin_read16(DMA1_8_Y_COUNT)
+#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
+#define pDMA1_8_X_MODIFY               ((uint16_t volatile *)DMA1_8_X_MODIFY)
+#define bfin_read_DMA1_8_X_MODIFY()    bfin_read16(DMA1_8_X_MODIFY)
+#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
+#define pDMA1_8_Y_MODIFY               ((uint16_t volatile *)DMA1_8_Y_MODIFY)
+#define bfin_read_DMA1_8_Y_MODIFY()    bfin_read16(DMA1_8_Y_MODIFY)
+#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
+#define pDMA1_8_CURR_DESC_PTR          ((void * volatile *)DMA1_8_CURR_DESC_PTR)
+#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
+#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
+#define pDMA1_8_CURR_ADDR              ((void * volatile *)DMA1_8_CURR_ADDR)
+#define bfin_read_DMA1_8_CURR_ADDR()   bfin_readPTR(DMA1_8_CURR_ADDR)
+#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
+#define pDMA1_8_CURR_X_COUNT           ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
+#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
+#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
+#define pDMA1_8_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)
+#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
+#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
+#define pDMA1_8_IRQ_STATUS             ((uint16_t volatile *)DMA1_8_IRQ_STATUS)
+#define bfin_read_DMA1_8_IRQ_STATUS()  bfin_read16(DMA1_8_IRQ_STATUS)
+#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
+#define pDMA1_8_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)
+#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
+#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
+#define pDMA1_9_CONFIG                 ((uint16_t volatile *)DMA1_9_CONFIG)
+#define bfin_read_DMA1_9_CONFIG()      bfin_read16(DMA1_9_CONFIG)
+#define bfin_write_DMA1_9_CONFIG(val)  bfin_write16(DMA1_9_CONFIG, val)
+#define pDMA1_9_NEXT_DESC_PTR          ((void * volatile *)DMA1_9_NEXT_DESC_PTR)
+#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
+#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
+#define pDMA1_9_START_ADDR             ((void * volatile *)DMA1_9_START_ADDR)
+#define bfin_read_DMA1_9_START_ADDR()  bfin_readPTR(DMA1_9_START_ADDR)
+#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
+#define pDMA1_9_X_COUNT                ((uint16_t volatile *)DMA1_9_X_COUNT)
+#define bfin_read_DMA1_9_X_COUNT()     bfin_read16(DMA1_9_X_COUNT)
+#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
+#define pDMA1_9_Y_COUNT                ((uint16_t volatile *)DMA1_9_Y_COUNT)
+#define bfin_read_DMA1_9_Y_COUNT()     bfin_read16(DMA1_9_Y_COUNT)
+#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
+#define pDMA1_9_X_MODIFY               ((uint16_t volatile *)DMA1_9_X_MODIFY)
+#define bfin_read_DMA1_9_X_MODIFY()    bfin_read16(DMA1_9_X_MODIFY)
+#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
+#define pDMA1_9_Y_MODIFY               ((uint16_t volatile *)DMA1_9_Y_MODIFY)
+#define bfin_read_DMA1_9_Y_MODIFY()    bfin_read16(DMA1_9_Y_MODIFY)
+#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
+#define pDMA1_9_CURR_DESC_PTR          ((void * volatile *)DMA1_9_CURR_DESC_PTR)
+#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
+#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
+#define pDMA1_9_CURR_ADDR              ((void * volatile *)DMA1_9_CURR_ADDR)
+#define bfin_read_DMA1_9_CURR_ADDR()   bfin_readPTR(DMA1_9_CURR_ADDR)
+#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
+#define pDMA1_9_CURR_X_COUNT           ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
+#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
+#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
+#define pDMA1_9_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)
+#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
+#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
+#define pDMA1_9_IRQ_STATUS             ((uint16_t volatile *)DMA1_9_IRQ_STATUS)
+#define bfin_read_DMA1_9_IRQ_STATUS()  bfin_read16(DMA1_9_IRQ_STATUS)
+#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
+#define pDMA1_9_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)
+#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
+#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
+#define pDMA1_10_CONFIG                ((uint16_t volatile *)DMA1_10_CONFIG)
+#define bfin_read_DMA1_10_CONFIG()     bfin_read16(DMA1_10_CONFIG)
+#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
+#define pDMA1_10_NEXT_DESC_PTR         ((void * volatile *)DMA1_10_NEXT_DESC_PTR)
+#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
+#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
+#define pDMA1_10_START_ADDR            ((void * volatile *)DMA1_10_START_ADDR)
+#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
+#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
+#define pDMA1_10_X_COUNT               ((uint16_t volatile *)DMA1_10_X_COUNT)
+#define bfin_read_DMA1_10_X_COUNT()    bfin_read16(DMA1_10_X_COUNT)
+#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
+#define pDMA1_10_Y_COUNT               ((uint16_t volatile *)DMA1_10_Y_COUNT)
+#define bfin_read_DMA1_10_Y_COUNT()    bfin_read16(DMA1_10_Y_COUNT)
+#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
+#define pDMA1_10_X_MODIFY              ((uint16_t volatile *)DMA1_10_X_MODIFY)
+#define bfin_read_DMA1_10_X_MODIFY()   bfin_read16(DMA1_10_X_MODIFY)
+#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
+#define pDMA1_10_Y_MODIFY              ((uint16_t volatile *)DMA1_10_Y_MODIFY)
+#define bfin_read_DMA1_10_Y_MODIFY()   bfin_read16(DMA1_10_Y_MODIFY)
+#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
+#define pDMA1_10_CURR_DESC_PTR         ((void * volatile *)DMA1_10_CURR_DESC_PTR)
+#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
+#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
+#define pDMA1_10_CURR_ADDR             ((void * volatile *)DMA1_10_CURR_ADDR)
+#define bfin_read_DMA1_10_CURR_ADDR()  bfin_readPTR(DMA1_10_CURR_ADDR)
+#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
+#define pDMA1_10_CURR_X_COUNT          ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
+#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
+#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
+#define pDMA1_10_CURR_Y_COUNT          ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)
+#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
+#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
+#define pDMA1_10_IRQ_STATUS            ((uint16_t volatile *)DMA1_10_IRQ_STATUS)
+#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
+#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
+#define pDMA1_10_PERIPHERAL_MAP        ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)
+#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
+#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
+#define pDMA1_11_CONFIG                ((uint16_t volatile *)DMA1_11_CONFIG)
+#define bfin_read_DMA1_11_CONFIG()     bfin_read16(DMA1_11_CONFIG)
+#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
+#define pDMA1_11_NEXT_DESC_PTR         ((void * volatile *)DMA1_11_NEXT_DESC_PTR)
+#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
+#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
+#define pDMA1_11_START_ADDR            ((void * volatile *)DMA1_11_START_ADDR)
+#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
+#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
+#define pDMA1_11_X_COUNT               ((uint16_t volatile *)DMA1_11_X_COUNT)
+#define bfin_read_DMA1_11_X_COUNT()    bfin_read16(DMA1_11_X_COUNT)
+#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
+#define pDMA1_11_Y_COUNT               ((uint16_t volatile *)DMA1_11_Y_COUNT)
+#define bfin_read_DMA1_11_Y_COUNT()    bfin_read16(DMA1_11_Y_COUNT)
+#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
+#define pDMA1_11_X_MODIFY              ((uint16_t volatile *)DMA1_11_X_MODIFY)
+#define bfin_read_DMA1_11_X_MODIFY()   bfin_read16(DMA1_11_X_MODIFY)
+#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
+#define pDMA1_11_Y_MODIFY              ((uint16_t volatile *)DMA1_11_Y_MODIFY)
+#define bfin_read_DMA1_11_Y_MODIFY()   bfin_read16(DMA1_11_Y_MODIFY)
+#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
+#define pDMA1_11_CURR_DESC_PTR         ((void * volatile *)DMA1_11_CURR_DESC_PTR)
+#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
+#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
+#define pDMA1_11_CURR_ADDR             ((void * volatile *)DMA1_11_CURR_ADDR)
+#define bfin_read_DMA1_11_CURR_ADDR()  bfin_readPTR(DMA1_11_CURR_ADDR)
+#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
+#define pDMA1_11_CURR_X_COUNT          ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
+#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
+#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
+#define pDMA1_11_CURR_Y_COUNT          ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)
+#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
+#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
+#define pDMA1_11_IRQ_STATUS            ((uint16_t volatile *)DMA1_11_IRQ_STATUS)
+#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
+#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
+#define pDMA1_11_PERIPHERAL_MAP        ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)
+#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
+#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
+#define pDMA2_TC_PER                   ((uint16_t volatile *)DMA2_TC_PER)
+#define bfin_read_DMA2_TC_PER()        bfin_read16(DMA2_TC_PER)
+#define bfin_write_DMA2_TC_PER(val)    bfin_write16(DMA2_TC_PER, val)
+#define pDMA2_TC_CNT                   ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */
+#define bfin_read_DMA2_TC_CNT()        bfin_read16(DMA2_TC_CNT)
+#define bfin_write_DMA2_TC_CNT(val)    bfin_write16(DMA2_TC_CNT, val)
+#define pDMA2_0_CONFIG                 ((uint16_t volatile *)DMA2_0_CONFIG)
+#define bfin_read_DMA2_0_CONFIG()      bfin_read16(DMA2_0_CONFIG)
+#define bfin_write_DMA2_0_CONFIG(val)  bfin_write16(DMA2_0_CONFIG, val)
+#define pDMA2_0_NEXT_DESC_PTR          ((void * volatile *)DMA2_0_NEXT_DESC_PTR)
+#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
+#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
+#define pDMA2_0_START_ADDR             ((void * volatile *)DMA2_0_START_ADDR)
+#define bfin_read_DMA2_0_START_ADDR()  bfin_readPTR(DMA2_0_START_ADDR)
+#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
+#define pDMA2_0_X_COUNT                ((uint16_t volatile *)DMA2_0_X_COUNT)
+#define bfin_read_DMA2_0_X_COUNT()     bfin_read16(DMA2_0_X_COUNT)
+#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
+#define pDMA2_0_Y_COUNT                ((uint16_t volatile *)DMA2_0_Y_COUNT)
+#define bfin_read_DMA2_0_Y_COUNT()     bfin_read16(DMA2_0_Y_COUNT)
+#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
+#define pDMA2_0_X_MODIFY               ((uint16_t volatile *)DMA2_0_X_MODIFY)
+#define bfin_read_DMA2_0_X_MODIFY()    bfin_read16(DMA2_0_X_MODIFY)
+#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
+#define pDMA2_0_Y_MODIFY               ((uint16_t volatile *)DMA2_0_Y_MODIFY)
+#define bfin_read_DMA2_0_Y_MODIFY()    bfin_read16(DMA2_0_Y_MODIFY)
+#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
+#define pDMA2_0_CURR_DESC_PTR          ((void * volatile *)DMA2_0_CURR_DESC_PTR)
+#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
+#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
+#define pDMA2_0_CURR_ADDR              ((void * volatile *)DMA2_0_CURR_ADDR)
+#define bfin_read_DMA2_0_CURR_ADDR()   bfin_readPTR(DMA2_0_CURR_ADDR)
+#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
+#define pDMA2_0_CURR_X_COUNT           ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
+#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
+#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
+#define pDMA2_0_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)
+#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
+#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
+#define pDMA2_0_IRQ_STATUS             ((uint16_t volatile *)DMA2_0_IRQ_STATUS)
+#define bfin_read_DMA2_0_IRQ_STATUS()  bfin_read16(DMA2_0_IRQ_STATUS)
+#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
+#define pDMA2_0_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)
+#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
+#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
+#define pDMA2_1_CONFIG                 ((uint16_t volatile *)DMA2_1_CONFIG)
+#define bfin_read_DMA2_1_CONFIG()      bfin_read16(DMA2_1_CONFIG)
+#define bfin_write_DMA2_1_CONFIG(val)  bfin_write16(DMA2_1_CONFIG, val)
+#define pDMA2_1_NEXT_DESC_PTR          ((void * volatile *)DMA2_1_NEXT_DESC_PTR)
+#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
+#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
+#define pDMA2_1_START_ADDR             ((void * volatile *)DMA2_1_START_ADDR)
+#define bfin_read_DMA2_1_START_ADDR()  bfin_readPTR(DMA2_1_START_ADDR)
+#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
+#define pDMA2_1_X_COUNT                ((uint16_t volatile *)DMA2_1_X_COUNT)
+#define bfin_read_DMA2_1_X_COUNT()     bfin_read16(DMA2_1_X_COUNT)
+#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
+#define pDMA2_1_Y_COUNT                ((uint16_t volatile *)DMA2_1_Y_COUNT)
+#define bfin_read_DMA2_1_Y_COUNT()     bfin_read16(DMA2_1_Y_COUNT)
+#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
+#define pDMA2_1_X_MODIFY               ((uint16_t volatile *)DMA2_1_X_MODIFY)
+#define bfin_read_DMA2_1_X_MODIFY()    bfin_read16(DMA2_1_X_MODIFY)
+#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
+#define pDMA2_1_Y_MODIFY               ((uint16_t volatile *)DMA2_1_Y_MODIFY)
+#define bfin_read_DMA2_1_Y_MODIFY()    bfin_read16(DMA2_1_Y_MODIFY)
+#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
+#define pDMA2_1_CURR_DESC_PTR          ((void * volatile *)DMA2_1_CURR_DESC_PTR)
+#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
+#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
+#define pDMA2_1_CURR_ADDR              ((void * volatile *)DMA2_1_CURR_ADDR)
+#define bfin_read_DMA2_1_CURR_ADDR()   bfin_readPTR(DMA2_1_CURR_ADDR)
+#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
+#define pDMA2_1_CURR_X_COUNT           ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
+#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
+#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
+#define pDMA2_1_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)
+#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
+#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
+#define pDMA2_1_IRQ_STATUS             ((uint16_t volatile *)DMA2_1_IRQ_STATUS)
+#define bfin_read_DMA2_1_IRQ_STATUS()  bfin_read16(DMA2_1_IRQ_STATUS)
+#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
+#define pDMA2_1_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)
+#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
+#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
+#define pDMA2_2_CONFIG                 ((uint16_t volatile *)DMA2_2_CONFIG)
+#define bfin_read_DMA2_2_CONFIG()      bfin_read16(DMA2_2_CONFIG)
+#define bfin_write_DMA2_2_CONFIG(val)  bfin_write16(DMA2_2_CONFIG, val)
+#define pDMA2_2_NEXT_DESC_PTR          ((void * volatile *)DMA2_2_NEXT_DESC_PTR)
+#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
+#define pDMA2_2_START_ADDR             ((void * volatile *)DMA2_2_START_ADDR)
+#define bfin_read_DMA2_2_START_ADDR()  bfin_readPTR(DMA2_2_START_ADDR)
+#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
+#define pDMA2_2_X_COUNT                ((uint16_t volatile *)DMA2_2_X_COUNT)
+#define bfin_read_DMA2_2_X_COUNT()     bfin_read16(DMA2_2_X_COUNT)
+#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
+#define pDMA2_2_Y_COUNT                ((uint16_t volatile *)DMA2_2_Y_COUNT)
+#define bfin_read_DMA2_2_Y_COUNT()     bfin_read16(DMA2_2_Y_COUNT)
+#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
+#define pDMA2_2_X_MODIFY               ((uint16_t volatile *)DMA2_2_X_MODIFY)
+#define bfin_read_DMA2_2_X_MODIFY()    bfin_read16(DMA2_2_X_MODIFY)
+#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
+#define pDMA2_2_Y_MODIFY               ((uint16_t volatile *)DMA2_2_Y_MODIFY)
+#define bfin_read_DMA2_2_Y_MODIFY()    bfin_read16(DMA2_2_Y_MODIFY)
+#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
+#define pDMA2_2_CURR_DESC_PTR          ((void * volatile *)DMA2_2_CURR_DESC_PTR)
+#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
+#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
+#define pDMA2_2_CURR_ADDR              ((void * volatile *)DMA2_2_CURR_ADDR)
+#define bfin_read_DMA2_2_CURR_ADDR()   bfin_readPTR(DMA2_2_CURR_ADDR)
+#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
+#define pDMA2_2_CURR_X_COUNT           ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
+#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
+#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
+#define pDMA2_2_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)
+#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
+#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
+#define pDMA2_2_IRQ_STATUS             ((uint16_t volatile *)DMA2_2_IRQ_STATUS)
+#define bfin_read_DMA2_2_IRQ_STATUS()  bfin_read16(DMA2_2_IRQ_STATUS)
+#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
+#define pDMA2_2_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)
+#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
+#define pDMA2_3_CONFIG                 ((uint16_t volatile *)DMA2_3_CONFIG)
+#define bfin_read_DMA2_3_CONFIG()      bfin_read16(DMA2_3_CONFIG)
+#define bfin_write_DMA2_3_CONFIG(val)  bfin_write16(DMA2_3_CONFIG, val)
+#define pDMA2_3_NEXT_DESC_PTR          ((void * volatile *)DMA2_3_NEXT_DESC_PTR)
+#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
+#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
+#define pDMA2_3_START_ADDR             ((void * volatile *)DMA2_3_START_ADDR)
+#define bfin_read_DMA2_3_START_ADDR()  bfin_readPTR(DMA2_3_START_ADDR)
+#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
+#define pDMA2_3_X_COUNT                ((uint16_t volatile *)DMA2_3_X_COUNT)
+#define bfin_read_DMA2_3_X_COUNT()     bfin_read16(DMA2_3_X_COUNT)
+#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
+#define pDMA2_3_Y_COUNT                ((uint16_t volatile *)DMA2_3_Y_COUNT)
+#define bfin_read_DMA2_3_Y_COUNT()     bfin_read16(DMA2_3_Y_COUNT)
+#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
+#define pDMA2_3_X_MODIFY               ((uint16_t volatile *)DMA2_3_X_MODIFY)
+#define bfin_read_DMA2_3_X_MODIFY()    bfin_read16(DMA2_3_X_MODIFY)
+#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
+#define pDMA2_3_Y_MODIFY               ((uint16_t volatile *)DMA2_3_Y_MODIFY)
+#define bfin_read_DMA2_3_Y_MODIFY()    bfin_read16(DMA2_3_Y_MODIFY)
+#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
+#define pDMA2_3_CURR_DESC_PTR          ((void * volatile *)DMA2_3_CURR_DESC_PTR)
+#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
+#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
+#define pDMA2_3_CURR_ADDR              ((void * volatile *)DMA2_3_CURR_ADDR)
+#define bfin_read_DMA2_3_CURR_ADDR()   bfin_readPTR(DMA2_3_CURR_ADDR)
+#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
+#define pDMA2_3_CURR_X_COUNT           ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
+#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
+#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
+#define pDMA2_3_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)
+#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
+#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
+#define pDMA2_3_IRQ_STATUS             ((uint16_t volatile *)DMA2_3_IRQ_STATUS)
+#define bfin_read_DMA2_3_IRQ_STATUS()  bfin_read16(DMA2_3_IRQ_STATUS)
+#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
+#define pDMA2_3_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)
+#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
+#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
+#define pDMA2_4_CONFIG                 ((uint16_t volatile *)DMA2_4_CONFIG)
+#define bfin_read_DMA2_4_CONFIG()      bfin_read16(DMA2_4_CONFIG)
+#define bfin_write_DMA2_4_CONFIG(val)  bfin_write16(DMA2_4_CONFIG, val)
+#define pDMA2_4_NEXT_DESC_PTR          ((void * volatile *)DMA2_4_NEXT_DESC_PTR)
+#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
+#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
+#define pDMA2_4_START_ADDR             ((void * volatile *)DMA2_4_START_ADDR)
+#define bfin_read_DMA2_4_START_ADDR()  bfin_readPTR(DMA2_4_START_ADDR)
+#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
+#define pDMA2_4_X_COUNT                ((uint16_t volatile *)DMA2_4_X_COUNT)
+#define bfin_read_DMA2_4_X_COUNT()     bfin_read16(DMA2_4_X_COUNT)
+#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
+#define pDMA2_4_Y_COUNT                ((uint16_t volatile *)DMA2_4_Y_COUNT)
+#define bfin_read_DMA2_4_Y_COUNT()     bfin_read16(DMA2_4_Y_COUNT)
+#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
+#define pDMA2_4_X_MODIFY               ((uint16_t volatile *)DMA2_4_X_MODIFY)
+#define bfin_read_DMA2_4_X_MODIFY()    bfin_read16(DMA2_4_X_MODIFY)
+#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
+#define pDMA2_4_Y_MODIFY               ((uint16_t volatile *)DMA2_4_Y_MODIFY)
+#define bfin_read_DMA2_4_Y_MODIFY()    bfin_read16(DMA2_4_Y_MODIFY)
+#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
+#define pDMA2_4_CURR_DESC_PTR          ((void * volatile *)DMA2_4_CURR_DESC_PTR)
+#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
+#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
+#define pDMA2_4_CURR_ADDR              ((void * volatile *)DMA2_4_CURR_ADDR)
+#define bfin_read_DMA2_4_CURR_ADDR()   bfin_readPTR(DMA2_4_CURR_ADDR)
+#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
+#define pDMA2_4_CURR_X_COUNT           ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
+#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
+#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
+#define pDMA2_4_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)
+#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
+#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
+#define pDMA2_4_IRQ_STATUS             ((uint16_t volatile *)DMA2_4_IRQ_STATUS)
+#define bfin_read_DMA2_4_IRQ_STATUS()  bfin_read16(DMA2_4_IRQ_STATUS)
+#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
+#define pDMA2_4_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)
+#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
+#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
+#define pDMA2_5_CONFIG                 ((uint16_t volatile *)DMA2_5_CONFIG)
+#define bfin_read_DMA2_5_CONFIG()      bfin_read16(DMA2_5_CONFIG)
+#define bfin_write_DMA2_5_CONFIG(val)  bfin_write16(DMA2_5_CONFIG, val)
+#define pDMA2_5_NEXT_DESC_PTR          ((void * volatile *)DMA2_5_NEXT_DESC_PTR)
+#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
+#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
+#define pDMA2_5_START_ADDR             ((void * volatile *)DMA2_5_START_ADDR)
+#define bfin_read_DMA2_5_START_ADDR()  bfin_readPTR(DMA2_5_START_ADDR)
+#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
+#define pDMA2_5_X_COUNT                ((uint16_t volatile *)DMA2_5_X_COUNT)
+#define bfin_read_DMA2_5_X_COUNT()     bfin_read16(DMA2_5_X_COUNT)
+#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
+#define pDMA2_5_Y_COUNT                ((uint16_t volatile *)DMA2_5_Y_COUNT)
+#define bfin_read_DMA2_5_Y_COUNT()     bfin_read16(DMA2_5_Y_COUNT)
+#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
+#define pDMA2_5_X_MODIFY               ((uint16_t volatile *)DMA2_5_X_MODIFY)
+#define bfin_read_DMA2_5_X_MODIFY()    bfin_read16(DMA2_5_X_MODIFY)
+#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
+#define pDMA2_5_Y_MODIFY               ((uint16_t volatile *)DMA2_5_Y_MODIFY)
+#define bfin_read_DMA2_5_Y_MODIFY()    bfin_read16(DMA2_5_Y_MODIFY)
+#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
+#define pDMA2_5_CURR_DESC_PTR          ((void * volatile *)DMA2_5_CURR_DESC_PTR)
+#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
+#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
+#define pDMA2_5_CURR_ADDR              ((void * volatile *)DMA2_5_CURR_ADDR)
+#define bfin_read_DMA2_5_CURR_ADDR()   bfin_readPTR(DMA2_5_CURR_ADDR)
+#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
+#define pDMA2_5_CURR_X_COUNT           ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
+#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
+#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
+#define pDMA2_5_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)
+#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
+#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
+#define pDMA2_5_IRQ_STATUS             ((uint16_t volatile *)DMA2_5_IRQ_STATUS)
+#define bfin_read_DMA2_5_IRQ_STATUS()  bfin_read16(DMA2_5_IRQ_STATUS)
+#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
+#define pDMA2_5_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)
+#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
+#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
+#define pDMA2_6_CONFIG                 ((uint16_t volatile *)DMA2_6_CONFIG)
+#define bfin_read_DMA2_6_CONFIG()      bfin_read16(DMA2_6_CONFIG)
+#define bfin_write_DMA2_6_CONFIG(val)  bfin_write16(DMA2_6_CONFIG, val)
+#define pDMA2_6_NEXT_DESC_PTR          ((void * volatile *)DMA2_6_NEXT_DESC_PTR)
+#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
+#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
+#define pDMA2_6_START_ADDR             ((void * volatile *)DMA2_6_START_ADDR)
+#define bfin_read_DMA2_6_START_ADDR()  bfin_readPTR(DMA2_6_START_ADDR)
+#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
+#define pDMA2_6_X_COUNT                ((uint16_t volatile *)DMA2_6_X_COUNT)
+#define bfin_read_DMA2_6_X_COUNT()     bfin_read16(DMA2_6_X_COUNT)
+#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
+#define pDMA2_6_Y_COUNT                ((uint16_t volatile *)DMA2_6_Y_COUNT)
+#define bfin_read_DMA2_6_Y_COUNT()     bfin_read16(DMA2_6_Y_COUNT)
+#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
+#define pDMA2_6_X_MODIFY               ((uint16_t volatile *)DMA2_6_X_MODIFY)
+#define bfin_read_DMA2_6_X_MODIFY()    bfin_read16(DMA2_6_X_MODIFY)
+#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
+#define pDMA2_6_Y_MODIFY               ((uint16_t volatile *)DMA2_6_Y_MODIFY)
+#define bfin_read_DMA2_6_Y_MODIFY()    bfin_read16(DMA2_6_Y_MODIFY)
+#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
+#define pDMA2_6_CURR_DESC_PTR          ((void * volatile *)DMA2_6_CURR_DESC_PTR)
+#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
+#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
+#define pDMA2_6_CURR_ADDR              ((void * volatile *)DMA2_6_CURR_ADDR)
+#define bfin_read_DMA2_6_CURR_ADDR()   bfin_readPTR(DMA2_6_CURR_ADDR)
+#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
+#define pDMA2_6_CURR_X_COUNT           ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
+#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
+#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
+#define pDMA2_6_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)
+#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
+#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
+#define pDMA2_6_IRQ_STATUS             ((uint16_t volatile *)DMA2_6_IRQ_STATUS)
+#define bfin_read_DMA2_6_IRQ_STATUS()  bfin_read16(DMA2_6_IRQ_STATUS)
+#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
+#define pDMA2_6_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)
+#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
+#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
+#define pDMA2_7_CONFIG                 ((uint16_t volatile *)DMA2_7_CONFIG)
+#define bfin_read_DMA2_7_CONFIG()      bfin_read16(DMA2_7_CONFIG)
+#define bfin_write_DMA2_7_CONFIG(val)  bfin_write16(DMA2_7_CONFIG, val)
+#define pDMA2_7_NEXT_DESC_PTR          ((void * volatile *)DMA2_7_NEXT_DESC_PTR)
+#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
+#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
+#define pDMA2_7_START_ADDR             ((void * volatile *)DMA2_7_START_ADDR)
+#define bfin_read_DMA2_7_START_ADDR()  bfin_readPTR(DMA2_7_START_ADDR)
+#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
+#define pDMA2_7_X_COUNT                ((uint16_t volatile *)DMA2_7_X_COUNT)
+#define bfin_read_DMA2_7_X_COUNT()     bfin_read16(DMA2_7_X_COUNT)
+#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
+#define pDMA2_7_Y_COUNT                ((uint16_t volatile *)DMA2_7_Y_COUNT)
+#define bfin_read_DMA2_7_Y_COUNT()     bfin_read16(DMA2_7_Y_COUNT)
+#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
+#define pDMA2_7_X_MODIFY               ((uint16_t volatile *)DMA2_7_X_MODIFY)
+#define bfin_read_DMA2_7_X_MODIFY()    bfin_read16(DMA2_7_X_MODIFY)
+#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
+#define pDMA2_7_Y_MODIFY               ((uint16_t volatile *)DMA2_7_Y_MODIFY)
+#define bfin_read_DMA2_7_Y_MODIFY()    bfin_read16(DMA2_7_Y_MODIFY)
+#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
+#define pDMA2_7_CURR_DESC_PTR          ((void * volatile *)DMA2_7_CURR_DESC_PTR)
+#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
+#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
+#define pDMA2_7_CURR_ADDR              ((void * volatile *)DMA2_7_CURR_ADDR)
+#define bfin_read_DMA2_7_CURR_ADDR()   bfin_readPTR(DMA2_7_CURR_ADDR)
+#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
+#define pDMA2_7_CURR_X_COUNT           ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
+#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
+#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
+#define pDMA2_7_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)
+#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
+#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
+#define pDMA2_7_IRQ_STATUS             ((uint16_t volatile *)DMA2_7_IRQ_STATUS)
+#define bfin_read_DMA2_7_IRQ_STATUS()  bfin_read16(DMA2_7_IRQ_STATUS)
+#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
+#define pDMA2_7_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)
+#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
+#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
+#define pDMA2_8_CONFIG                 ((uint16_t volatile *)DMA2_8_CONFIG)
+#define bfin_read_DMA2_8_CONFIG()      bfin_read16(DMA2_8_CONFIG)
+#define bfin_write_DMA2_8_CONFIG(val)  bfin_write16(DMA2_8_CONFIG, val)
+#define pDMA2_8_NEXT_DESC_PTR          ((void * volatile *)DMA2_8_NEXT_DESC_PTR)
+#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
+#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
+#define pDMA2_8_START_ADDR             ((void * volatile *)DMA2_8_START_ADDR)
+#define bfin_read_DMA2_8_START_ADDR()  bfin_readPTR(DMA2_8_START_ADDR)
+#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
+#define pDMA2_8_X_COUNT                ((uint16_t volatile *)DMA2_8_X_COUNT)
+#define bfin_read_DMA2_8_X_COUNT()     bfin_read16(DMA2_8_X_COUNT)
+#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
+#define pDMA2_8_Y_COUNT                ((uint16_t volatile *)DMA2_8_Y_COUNT)
+#define bfin_read_DMA2_8_Y_COUNT()     bfin_read16(DMA2_8_Y_COUNT)
+#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
+#define pDMA2_8_X_MODIFY               ((uint16_t volatile *)DMA2_8_X_MODIFY)
+#define bfin_read_DMA2_8_X_MODIFY()    bfin_read16(DMA2_8_X_MODIFY)
+#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
+#define pDMA2_8_Y_MODIFY               ((uint16_t volatile *)DMA2_8_Y_MODIFY)
+#define bfin_read_DMA2_8_Y_MODIFY()    bfin_read16(DMA2_8_Y_MODIFY)
+#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
+#define pDMA2_8_CURR_DESC_PTR          ((void * volatile *)DMA2_8_CURR_DESC_PTR)
+#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
+#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
+#define pDMA2_8_CURR_ADDR              ((void * volatile *)DMA2_8_CURR_ADDR)
+#define bfin_read_DMA2_8_CURR_ADDR()   bfin_readPTR(DMA2_8_CURR_ADDR)
+#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
+#define pDMA2_8_CURR_X_COUNT           ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
+#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
+#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
+#define pDMA2_8_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)
+#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
+#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
+#define pDMA2_8_IRQ_STATUS             ((uint16_t volatile *)DMA2_8_IRQ_STATUS)
+#define bfin_read_DMA2_8_IRQ_STATUS()  bfin_read16(DMA2_8_IRQ_STATUS)
+#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
+#define pDMA2_8_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)
+#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
+#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
+#define pDMA2_9_CONFIG                 ((uint16_t volatile *)DMA2_9_CONFIG)
+#define bfin_read_DMA2_9_CONFIG()      bfin_read16(DMA2_9_CONFIG)
+#define bfin_write_DMA2_9_CONFIG(val)  bfin_write16(DMA2_9_CONFIG, val)
+#define pDMA2_9_NEXT_DESC_PTR          ((void * volatile *)DMA2_9_NEXT_DESC_PTR)
+#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
+#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
+#define pDMA2_9_START_ADDR             ((void * volatile *)DMA2_9_START_ADDR)
+#define bfin_read_DMA2_9_START_ADDR()  bfin_readPTR(DMA2_9_START_ADDR)
+#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
+#define pDMA2_9_X_COUNT                ((uint16_t volatile *)DMA2_9_X_COUNT)
+#define bfin_read_DMA2_9_X_COUNT()     bfin_read16(DMA2_9_X_COUNT)
+#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
+#define pDMA2_9_Y_COUNT                ((uint16_t volatile *)DMA2_9_Y_COUNT)
+#define bfin_read_DMA2_9_Y_COUNT()     bfin_read16(DMA2_9_Y_COUNT)
+#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
+#define pDMA2_9_X_MODIFY               ((uint16_t volatile *)DMA2_9_X_MODIFY)
+#define bfin_read_DMA2_9_X_MODIFY()    bfin_read16(DMA2_9_X_MODIFY)
+#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
+#define pDMA2_9_Y_MODIFY               ((uint16_t volatile *)DMA2_9_Y_MODIFY)
+#define bfin_read_DMA2_9_Y_MODIFY()    bfin_read16(DMA2_9_Y_MODIFY)
+#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
+#define pDMA2_9_CURR_DESC_PTR          ((void * volatile *)DMA2_9_CURR_DESC_PTR)
+#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
+#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
+#define pDMA2_9_CURR_ADDR              ((void * volatile *)DMA2_9_CURR_ADDR)
+#define bfin_read_DMA2_9_CURR_ADDR()   bfin_readPTR(DMA2_9_CURR_ADDR)
+#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
+#define pDMA2_9_CURR_X_COUNT           ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
+#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
+#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
+#define pDMA2_9_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)
+#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
+#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
+#define pDMA2_9_IRQ_STATUS             ((uint16_t volatile *)DMA2_9_IRQ_STATUS)
+#define bfin_read_DMA2_9_IRQ_STATUS()  bfin_read16(DMA2_9_IRQ_STATUS)
+#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
+#define pDMA2_9_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)
+#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
+#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
+#define pDMA2_10_CONFIG                ((uint16_t volatile *)DMA2_10_CONFIG)
+#define bfin_read_DMA2_10_CONFIG()     bfin_read16(DMA2_10_CONFIG)
+#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
+#define pDMA2_10_NEXT_DESC_PTR         ((void * volatile *)DMA2_10_NEXT_DESC_PTR)
+#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
+#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
+#define pDMA2_10_START_ADDR            ((void * volatile *)DMA2_10_START_ADDR)
+#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
+#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
+#define pDMA2_10_X_COUNT               ((uint16_t volatile *)DMA2_10_X_COUNT)
+#define bfin_read_DMA2_10_X_COUNT()    bfin_read16(DMA2_10_X_COUNT)
+#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
+#define pDMA2_10_Y_COUNT               ((uint16_t volatile *)DMA2_10_Y_COUNT)
+#define bfin_read_DMA2_10_Y_COUNT()    bfin_read16(DMA2_10_Y_COUNT)
+#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
+#define pDMA2_10_X_MODIFY              ((uint16_t volatile *)DMA2_10_X_MODIFY)
+#define bfin_read_DMA2_10_X_MODIFY()   bfin_read16(DMA2_10_X_MODIFY)
+#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
+#define pDMA2_10_Y_MODIFY              ((uint16_t volatile *)DMA2_10_Y_MODIFY)
+#define bfin_read_DMA2_10_Y_MODIFY()   bfin_read16(DMA2_10_Y_MODIFY)
+#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
+#define pDMA2_10_CURR_DESC_PTR         ((void * volatile *)DMA2_10_CURR_DESC_PTR)
+#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
+#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
+#define pDMA2_10_CURR_ADDR             ((void * volatile *)DMA2_10_CURR_ADDR)
+#define bfin_read_DMA2_10_CURR_ADDR()  bfin_readPTR(DMA2_10_CURR_ADDR)
+#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
+#define pDMA2_10_CURR_X_COUNT          ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
+#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
+#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
+#define pDMA2_10_CURR_Y_COUNT          ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)
+#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
+#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
+#define pDMA2_10_IRQ_STATUS            ((uint16_t volatile *)DMA2_10_IRQ_STATUS)
+#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
+#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
+#define pDMA2_10_PERIPHERAL_MAP        ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)
+#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
+#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
+#define pDMA2_11_CONFIG                ((uint16_t volatile *)DMA2_11_CONFIG)
+#define bfin_read_DMA2_11_CONFIG()     bfin_read16(DMA2_11_CONFIG)
+#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
+#define pDMA2_11_NEXT_DESC_PTR         ((void * volatile *)DMA2_11_NEXT_DESC_PTR)
+#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
+#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
+#define pDMA2_11_START_ADDR            ((void * volatile *)DMA2_11_START_ADDR)
+#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
+#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
+#define pDMA2_11_X_COUNT               ((uint16_t volatile *)DMA2_11_X_COUNT)
+#define bfin_read_DMA2_11_X_COUNT()    bfin_read16(DMA2_11_X_COUNT)
+#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
+#define pDMA2_11_Y_COUNT               ((uint16_t volatile *)DMA2_11_Y_COUNT)
+#define bfin_read_DMA2_11_Y_COUNT()    bfin_read16(DMA2_11_Y_COUNT)
+#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
+#define pDMA2_11_X_MODIFY              ((uint16_t volatile *)DMA2_11_X_MODIFY)
+#define bfin_read_DMA2_11_X_MODIFY()   bfin_read16(DMA2_11_X_MODIFY)
+#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
+#define pDMA2_11_Y_MODIFY              ((uint16_t volatile *)DMA2_11_Y_MODIFY)
+#define bfin_read_DMA2_11_Y_MODIFY()   bfin_read16(DMA2_11_Y_MODIFY)
+#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
+#define pDMA2_11_CURR_DESC_PTR         ((void * volatile *)DMA2_11_CURR_DESC_PTR)
+#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
+#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
+#define pDMA2_11_CURR_ADDR             ((void * volatile *)DMA2_11_CURR_ADDR)
+#define bfin_read_DMA2_11_CURR_ADDR()  bfin_readPTR(DMA2_11_CURR_ADDR)
+#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
+#define pDMA2_11_CURR_X_COUNT          ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
+#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
+#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
+#define pDMA2_11_CURR_Y_COUNT          ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)
+#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
+#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
+#define pDMA2_11_IRQ_STATUS            ((uint16_t volatile *)DMA2_11_IRQ_STATUS)
+#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
+#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
+#define pDMA2_11_PERIPHERAL_MAP        ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)
+#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
+#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
+#define pIMDMA_S0_CONFIG               ((uint16_t volatile *)IMDMA_S0_CONFIG)
+#define bfin_read_IMDMA_S0_CONFIG()    bfin_read16(IMDMA_S0_CONFIG)
+#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
+#define pIMDMA_S0_NEXT_DESC_PTR        ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)
+#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
+#define pIMDMA_S0_START_ADDR           ((void * volatile *)IMDMA_S0_START_ADDR)
+#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
+#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
+#define pIMDMA_S0_X_COUNT              ((uint16_t volatile *)IMDMA_S0_X_COUNT)
+#define bfin_read_IMDMA_S0_X_COUNT()   bfin_read16(IMDMA_S0_X_COUNT)
+#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
+#define pIMDMA_S0_Y_COUNT              ((uint16_t volatile *)IMDMA_S0_Y_COUNT)
+#define bfin_read_IMDMA_S0_Y_COUNT()   bfin_read16(IMDMA_S0_Y_COUNT)
+#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
+#define pIMDMA_S0_X_MODIFY             ((uint16_t volatile *)IMDMA_S0_X_MODIFY)
+#define bfin_read_IMDMA_S0_X_MODIFY()  bfin_read16(IMDMA_S0_X_MODIFY)
+#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
+#define pIMDMA_S0_Y_MODIFY             ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)
+#define bfin_read_IMDMA_S0_Y_MODIFY()  bfin_read16(IMDMA_S0_Y_MODIFY)
+#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
+#define pIMDMA_S0_CURR_DESC_PTR        ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)
+#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
+#define pIMDMA_S0_CURR_ADDR            ((void * volatile *)IMDMA_S0_CURR_ADDR)
+#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
+#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
+#define pIMDMA_S0_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
+#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
+#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
+#define pIMDMA_S0_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)
+#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
+#define pIMDMA_S0_IRQ_STATUS           ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)
+#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
+#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
+#define pIMDMA_D0_CONFIG               ((uint16_t volatile *)IMDMA_D0_CONFIG)
+#define bfin_read_IMDMA_D0_CONFIG()    bfin_read16(IMDMA_D0_CONFIG)
+#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
+#define pIMDMA_D0_NEXT_DESC_PTR        ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)
+#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
+#define pIMDMA_D0_START_ADDR           ((void * volatile *)IMDMA_D0_START_ADDR)
+#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
+#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
+#define pIMDMA_D0_X_COUNT              ((uint16_t volatile *)IMDMA_D0_X_COUNT)
+#define bfin_read_IMDMA_D0_X_COUNT()   bfin_read16(IMDMA_D0_X_COUNT)
+#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
+#define pIMDMA_D0_Y_COUNT              ((uint16_t volatile *)IMDMA_D0_Y_COUNT)
+#define bfin_read_IMDMA_D0_Y_COUNT()   bfin_read16(IMDMA_D0_Y_COUNT)
+#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
+#define pIMDMA_D0_X_MODIFY             ((uint16_t volatile *)IMDMA_D0_X_MODIFY)
+#define bfin_read_IMDMA_D0_X_MODIFY()  bfin_read16(IMDMA_D0_X_MODIFY)
+#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
+#define pIMDMA_D0_Y_MODIFY             ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)
+#define bfin_read_IMDMA_D0_Y_MODIFY()  bfin_read16(IMDMA_D0_Y_MODIFY)
+#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
+#define pIMDMA_D0_CURR_DESC_PTR        ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)
+#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
+#define pIMDMA_D0_CURR_ADDR            ((void * volatile *)IMDMA_D0_CURR_ADDR)
+#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
+#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
+#define pIMDMA_D0_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
+#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
+#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
+#define pIMDMA_D0_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)
+#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
+#define pIMDMA_D0_IRQ_STATUS           ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)
+#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
+#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
+#define pIMDMA_S1_CONFIG               ((uint16_t volatile *)IMDMA_S1_CONFIG)
+#define bfin_read_IMDMA_S1_CONFIG()    bfin_read16(IMDMA_S1_CONFIG)
+#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
+#define pIMDMA_S1_NEXT_DESC_PTR        ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)
+#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
+#define pIMDMA_S1_START_ADDR           ((void * volatile *)IMDMA_S1_START_ADDR)
+#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
+#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
+#define pIMDMA_S1_X_COUNT              ((uint16_t volatile *)IMDMA_S1_X_COUNT)
+#define bfin_read_IMDMA_S1_X_COUNT()   bfin_read16(IMDMA_S1_X_COUNT)
+#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
+#define pIMDMA_S1_Y_COUNT              ((uint16_t volatile *)IMDMA_S1_Y_COUNT)
+#define bfin_read_IMDMA_S1_Y_COUNT()   bfin_read16(IMDMA_S1_Y_COUNT)
+#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
+#define pIMDMA_S1_X_MODIFY             ((uint16_t volatile *)IMDMA_S1_X_MODIFY)
+#define bfin_read_IMDMA_S1_X_MODIFY()  bfin_read16(IMDMA_S1_X_MODIFY)
+#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
+#define pIMDMA_S1_Y_MODIFY             ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)
+#define bfin_read_IMDMA_S1_Y_MODIFY()  bfin_read16(IMDMA_S1_Y_MODIFY)
+#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
+#define pIMDMA_S1_CURR_DESC_PTR        ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)
+#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
+#define pIMDMA_S1_CURR_ADDR            ((void * volatile *)IMDMA_S1_CURR_ADDR)
+#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
+#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
+#define pIMDMA_S1_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
+#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
+#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
+#define pIMDMA_S1_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)
+#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
+#define pIMDMA_S1_IRQ_STATUS           ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)
+#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
+#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
+#define pIMDMA_D1_CONFIG               ((uint16_t volatile *)IMDMA_D1_CONFIG)
+#define bfin_read_IMDMA_D1_CONFIG()    bfin_read16(IMDMA_D1_CONFIG)
+#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
+#define pIMDMA_D1_NEXT_DESC_PTR        ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)
+#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
+#define pIMDMA_D1_START_ADDR           ((void * volatile *)IMDMA_D1_START_ADDR)
+#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
+#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
+#define pIMDMA_D1_X_COUNT              ((uint16_t volatile *)IMDMA_D1_X_COUNT)
+#define bfin_read_IMDMA_D1_X_COUNT()   bfin_read16(IMDMA_D1_X_COUNT)
+#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
+#define pIMDMA_D1_Y_COUNT              ((uint16_t volatile *)IMDMA_D1_Y_COUNT)
+#define bfin_read_IMDMA_D1_Y_COUNT()   bfin_read16(IMDMA_D1_Y_COUNT)
+#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
+#define pIMDMA_D1_X_MODIFY             ((uint16_t volatile *)IMDMA_D1_X_MODIFY)
+#define bfin_read_IMDMA_D1_X_MODIFY()  bfin_read16(IMDMA_D1_X_MODIFY)
+#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
+#define pIMDMA_D1_Y_MODIFY             ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)
+#define bfin_read_IMDMA_D1_Y_MODIFY()  bfin_read16(IMDMA_D1_Y_MODIFY)
+#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
+#define pIMDMA_D1_CURR_DESC_PTR        ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)
+#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
+#define pIMDMA_D1_CURR_ADDR            ((void * volatile *)IMDMA_D1_CURR_ADDR)
+#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
+#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
+#define pIMDMA_D1_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
+#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
+#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
+#define pIMDMA_D1_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)
+#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
+#define pIMDMA_D1_IRQ_STATUS           ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)
+#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
+#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
+#define pMDMA1_S0_CONFIG               ((uint16_t volatile *)MDMA1_S0_CONFIG)
+#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
+#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
+#define pMDMA1_S0_NEXT_DESC_PTR        ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
+#define pMDMA1_S0_START_ADDR           ((void * volatile *)MDMA1_S0_START_ADDR)
+#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
+#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
+#define pMDMA1_S0_X_COUNT              ((uint16_t volatile *)MDMA1_S0_X_COUNT)
+#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
+#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
+#define pMDMA1_S0_Y_COUNT              ((uint16_t volatile *)MDMA1_S0_Y_COUNT)
+#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
+#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
+#define pMDMA1_S0_X_MODIFY             ((uint16_t volatile *)MDMA1_S0_X_MODIFY)
+#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
+#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
+#define pMDMA1_S0_Y_MODIFY             ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)
+#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
+#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
+#define pMDMA1_S0_CURR_DESC_PTR        ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
+#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
+#define pMDMA1_S0_CURR_ADDR            ((void * volatile *)MDMA1_S0_CURR_ADDR)
+#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
+#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
+#define pMDMA1_S0_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
+#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
+#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
+#define pMDMA1_S0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)
+#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
+#define pMDMA1_S0_IRQ_STATUS           ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)
+#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
+#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
+#define pMDMA1_S0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
+#define pMDMA1_D0_CONFIG               ((uint16_t volatile *)MDMA1_D0_CONFIG)
+#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
+#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
+#define pMDMA1_D0_NEXT_DESC_PTR        ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
+#define pMDMA1_D0_START_ADDR           ((void * volatile *)MDMA1_D0_START_ADDR)
+#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
+#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
+#define pMDMA1_D0_X_COUNT              ((uint16_t volatile *)MDMA1_D0_X_COUNT)
+#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
+#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
+#define pMDMA1_D0_Y_COUNT              ((uint16_t volatile *)MDMA1_D0_Y_COUNT)
+#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
+#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
+#define pMDMA1_D0_X_MODIFY             ((uint16_t volatile *)MDMA1_D0_X_MODIFY)
+#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
+#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
+#define pMDMA1_D0_Y_MODIFY             ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)
+#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
+#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
+#define pMDMA1_D0_CURR_DESC_PTR        ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
+#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
+#define pMDMA1_D0_CURR_ADDR            ((void * volatile *)MDMA1_D0_CURR_ADDR)
+#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
+#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
+#define pMDMA1_D0_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
+#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
+#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
+#define pMDMA1_D0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)
+#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
+#define pMDMA1_D0_IRQ_STATUS           ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
+#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
+#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
+#define pMDMA1_D0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
+#define pMDMA1_S1_CONFIG               ((uint16_t volatile *)MDMA1_S1_CONFIG)
+#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
+#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
+#define pMDMA1_S1_NEXT_DESC_PTR        ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
+#define pMDMA1_S1_START_ADDR           ((void * volatile *)MDMA1_S1_START_ADDR)
+#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
+#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
+#define pMDMA1_S1_X_COUNT              ((uint16_t volatile *)MDMA1_S1_X_COUNT)
+#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
+#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
+#define pMDMA1_S1_Y_COUNT              ((uint16_t volatile *)MDMA1_S1_Y_COUNT)
+#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
+#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
+#define pMDMA1_S1_X_MODIFY             ((uint16_t volatile *)MDMA1_S1_X_MODIFY)
+#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
+#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
+#define pMDMA1_S1_Y_MODIFY             ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)
+#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
+#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
+#define pMDMA1_S1_CURR_DESC_PTR        ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
+#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
+#define pMDMA1_S1_CURR_ADDR            ((void * volatile *)MDMA1_S1_CURR_ADDR)
+#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
+#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
+#define pMDMA1_S1_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
+#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
+#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
+#define pMDMA1_S1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)
+#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
+#define pMDMA1_S1_IRQ_STATUS           ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)
+#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
+#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
+#define pMDMA1_S1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
+#define pMDMA1_D1_CONFIG               ((uint16_t volatile *)MDMA1_D1_CONFIG)
+#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
+#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
+#define pMDMA1_D1_NEXT_DESC_PTR        ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
+#define pMDMA1_D1_START_ADDR           ((void * volatile *)MDMA1_D1_START_ADDR)
+#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
+#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
+#define pMDMA1_D1_X_COUNT              ((uint16_t volatile *)MDMA1_D1_X_COUNT)
+#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
+#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
+#define pMDMA1_D1_Y_COUNT              ((uint16_t volatile *)MDMA1_D1_Y_COUNT)
+#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
+#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
+#define pMDMA1_D1_X_MODIFY             ((uint16_t volatile *)MDMA1_D1_X_MODIFY)
+#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
+#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
+#define pMDMA1_D1_Y_MODIFY             ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)
+#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
+#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
+#define pMDMA1_D1_CURR_DESC_PTR        ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
+#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
+#define pMDMA1_D1_CURR_ADDR            ((void * volatile *)MDMA1_D1_CURR_ADDR)
+#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
+#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
+#define pMDMA1_D1_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
+#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
+#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
+#define pMDMA1_D1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)
+#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
+#define pMDMA1_D1_IRQ_STATUS           ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)
+#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
+#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
+#define pMDMA1_D1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
+#define pMDMA2_S0_CONFIG               ((uint16_t volatile *)MDMA2_S0_CONFIG)
+#define bfin_read_MDMA2_S0_CONFIG()    bfin_read16(MDMA2_S0_CONFIG)
+#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
+#define pMDMA2_S0_NEXT_DESC_PTR        ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)
+#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
+#define pMDMA2_S0_START_ADDR           ((void * volatile *)MDMA2_S0_START_ADDR)
+#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
+#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
+#define pMDMA2_S0_X_COUNT              ((uint16_t volatile *)MDMA2_S0_X_COUNT)
+#define bfin_read_MDMA2_S0_X_COUNT()   bfin_read16(MDMA2_S0_X_COUNT)
+#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
+#define pMDMA2_S0_Y_COUNT              ((uint16_t volatile *)MDMA2_S0_Y_COUNT)
+#define bfin_read_MDMA2_S0_Y_COUNT()   bfin_read16(MDMA2_S0_Y_COUNT)
+#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
+#define pMDMA2_S0_X_MODIFY             ((uint16_t volatile *)MDMA2_S0_X_MODIFY)
+#define bfin_read_MDMA2_S0_X_MODIFY()  bfin_read16(MDMA2_S0_X_MODIFY)
+#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
+#define pMDMA2_S0_Y_MODIFY             ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)
+#define bfin_read_MDMA2_S0_Y_MODIFY()  bfin_read16(MDMA2_S0_Y_MODIFY)
+#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
+#define pMDMA2_S0_CURR_DESC_PTR        ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)
+#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
+#define pMDMA2_S0_CURR_ADDR            ((void * volatile *)MDMA2_S0_CURR_ADDR)
+#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
+#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
+#define pMDMA2_S0_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
+#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
+#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
+#define pMDMA2_S0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)
+#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
+#define pMDMA2_S0_IRQ_STATUS           ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)
+#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
+#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
+#define pMDMA2_S0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)
+#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
+#define pMDMA2_D0_CONFIG               ((uint16_t volatile *)MDMA2_D0_CONFIG)
+#define bfin_read_MDMA2_D0_CONFIG()    bfin_read16(MDMA2_D0_CONFIG)
+#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
+#define pMDMA2_D0_NEXT_DESC_PTR        ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)
+#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
+#define pMDMA2_D0_START_ADDR           ((void * volatile *)MDMA2_D0_START_ADDR)
+#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
+#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
+#define pMDMA2_D0_X_COUNT              ((uint16_t volatile *)MDMA2_D0_X_COUNT)
+#define bfin_read_MDMA2_D0_X_COUNT()   bfin_read16(MDMA2_D0_X_COUNT)
+#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
+#define pMDMA2_D0_Y_COUNT              ((uint16_t volatile *)MDMA2_D0_Y_COUNT)
+#define bfin_read_MDMA2_D0_Y_COUNT()   bfin_read16(MDMA2_D0_Y_COUNT)
+#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
+#define pMDMA2_D0_X_MODIFY             ((uint16_t volatile *)MDMA2_D0_X_MODIFY)
+#define bfin_read_MDMA2_D0_X_MODIFY()  bfin_read16(MDMA2_D0_X_MODIFY)
+#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
+#define pMDMA2_D0_Y_MODIFY             ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)
+#define bfin_read_MDMA2_D0_Y_MODIFY()  bfin_read16(MDMA2_D0_Y_MODIFY)
+#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
+#define pMDMA2_D0_CURR_DESC_PTR        ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)
+#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
+#define pMDMA2_D0_CURR_ADDR            ((void * volatile *)MDMA2_D0_CURR_ADDR)
+#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
+#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
+#define pMDMA2_D0_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
+#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
+#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
+#define pMDMA2_D0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)
+#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
+#define pMDMA2_D0_IRQ_STATUS           ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)
+#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
+#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
+#define pMDMA2_D0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)
+#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
+#define pMDMA2_S1_CONFIG               ((uint16_t volatile *)MDMA2_S1_CONFIG)
+#define bfin_read_MDMA2_S1_CONFIG()    bfin_read16(MDMA2_S1_CONFIG)
+#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
+#define pMDMA2_S1_NEXT_DESC_PTR        ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)
+#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
+#define pMDMA2_S1_START_ADDR           ((void * volatile *)MDMA2_S1_START_ADDR)
+#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
+#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
+#define pMDMA2_S1_X_COUNT              ((uint16_t volatile *)MDMA2_S1_X_COUNT)
+#define bfin_read_MDMA2_S1_X_COUNT()   bfin_read16(MDMA2_S1_X_COUNT)
+#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
+#define pMDMA2_S1_Y_COUNT              ((uint16_t volatile *)MDMA2_S1_Y_COUNT)
+#define bfin_read_MDMA2_S1_Y_COUNT()   bfin_read16(MDMA2_S1_Y_COUNT)
+#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
+#define pMDMA2_S1_X_MODIFY             ((uint16_t volatile *)MDMA2_S1_X_MODIFY)
+#define bfin_read_MDMA2_S1_X_MODIFY()  bfin_read16(MDMA2_S1_X_MODIFY)
+#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
+#define pMDMA2_S1_Y_MODIFY             ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)
+#define bfin_read_MDMA2_S1_Y_MODIFY()  bfin_read16(MDMA2_S1_Y_MODIFY)
+#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
+#define pMDMA2_S1_CURR_DESC_PTR        ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)
+#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
+#define pMDMA2_S1_CURR_ADDR            ((void * volatile *)MDMA2_S1_CURR_ADDR)
+#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
+#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
+#define pMDMA2_S1_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
+#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
+#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
+#define pMDMA2_S1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)
+#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
+#define pMDMA2_S1_IRQ_STATUS           ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)
+#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
+#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
+#define pMDMA2_S1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)
+#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
+#define pMDMA2_D1_CONFIG               ((uint16_t volatile *)MDMA2_D1_CONFIG)
+#define bfin_read_MDMA2_D1_CONFIG()    bfin_read16(MDMA2_D1_CONFIG)
+#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
+#define pMDMA2_D1_NEXT_DESC_PTR        ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)
+#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
+#define pMDMA2_D1_START_ADDR           ((void * volatile *)MDMA2_D1_START_ADDR)
+#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
+#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
+#define pMDMA2_D1_X_COUNT              ((uint16_t volatile *)MDMA2_D1_X_COUNT)
+#define bfin_read_MDMA2_D1_X_COUNT()   bfin_read16(MDMA2_D1_X_COUNT)
+#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
+#define pMDMA2_D1_Y_COUNT              ((uint16_t volatile *)MDMA2_D1_Y_COUNT)
+#define bfin_read_MDMA2_D1_Y_COUNT()   bfin_read16(MDMA2_D1_Y_COUNT)
+#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
+#define pMDMA2_D1_X_MODIFY             ((uint16_t volatile *)MDMA2_D1_X_MODIFY)
+#define bfin_read_MDMA2_D1_X_MODIFY()  bfin_read16(MDMA2_D1_X_MODIFY)
+#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
+#define pMDMA2_D1_Y_MODIFY             ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)
+#define bfin_read_MDMA2_D1_Y_MODIFY()  bfin_read16(MDMA2_D1_Y_MODIFY)
+#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
+#define pMDMA2_D1_CURR_DESC_PTR        ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)
+#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
+#define pMDMA2_D1_CURR_ADDR            ((void * volatile *)MDMA2_D1_CURR_ADDR)
+#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
+#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
+#define pMDMA2_D1_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
+#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
+#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
+#define pMDMA2_D1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)
+#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
+#define pMDMA2_D1_IRQ_STATUS           ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)
+#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
+#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
+#define pMDMA2_D1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)
+#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG)
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER)
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD)
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH)
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG)
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER)
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD)
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH)
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG)
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER)
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD)
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH)
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG)
+#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
+#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER)
+#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
+#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD)
+#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
+#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH)
+#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
+#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG)
+#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
+#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER)
+#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
+#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD)
+#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
+#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH)
+#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
+#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG)
+#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
+#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER)
+#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
+#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD)
+#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
+#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH)
+#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
+#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG)
+#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
+#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER)
+#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
+#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD)
+#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
+#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH)
+#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
+#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG)
+#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
+#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER)
+#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
+#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD)
+#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
+#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH)
+#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
+#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG)
+#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
+#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER)
+#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD)
+#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
+#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH)
+#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
+#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG)
+#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
+#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER)
+#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD)
+#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
+#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH)
+#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
+#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG)
+#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER)
+#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD)
+#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH)
+#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
+#define pTIMER11_CONFIG                ((uint16_t volatile *)TIMER11_CONFIG)
+#define bfin_read_TIMER11_CONFIG()     bfin_read16(TIMER11_CONFIG)
+#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
+#define pTIMER11_COUNTER               ((uint32_t volatile *)TIMER11_COUNTER)
+#define bfin_read_TIMER11_COUNTER()    bfin_read32(TIMER11_COUNTER)
+#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
+#define pTIMER11_PERIOD                ((uint32_t volatile *)TIMER11_PERIOD)
+#define bfin_read_TIMER11_PERIOD()     bfin_read32(TIMER11_PERIOD)
+#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
+#define pTIMER11_WIDTH                 ((uint32_t volatile *)TIMER11_WIDTH)
+#define bfin_read_TIMER11_WIDTH()      bfin_read32(TIMER11_WIDTH)
+#define bfin_write_TIMER11_WIDTH(val)  bfin_write32(TIMER11_WIDTH, val)
+#define pTMRS4_ENABLE                  ((uint32_t volatile *)TMRS4_ENABLE)
+#define bfin_read_TMRS4_ENABLE()       bfin_read32(TMRS4_ENABLE)
+#define bfin_write_TMRS4_ENABLE(val)   bfin_write32(TMRS4_ENABLE, val)
+#define pTMRS4_DISABLE                 ((uint32_t volatile *)TMRS4_DISABLE)
+#define bfin_read_TMRS4_DISABLE()      bfin_read32(TMRS4_DISABLE)
+#define bfin_write_TMRS4_DISABLE(val)  bfin_write32(TMRS4_DISABLE, val)
+#define pTMRS4_STATUS                  ((uint32_t volatile *)TMRS4_STATUS)
+#define bfin_read_TMRS4_STATUS()       bfin_read32(TMRS4_STATUS)
+#define bfin_write_TMRS4_STATUS(val)   bfin_write32(TMRS4_STATUS, val)
+#define pTMRS8_ENABLE                  ((uint32_t volatile *)TMRS8_ENABLE)
+#define bfin_read_TMRS8_ENABLE()       bfin_read32(TMRS8_ENABLE)
+#define bfin_write_TMRS8_ENABLE(val)   bfin_write32(TMRS8_ENABLE, val)
+#define pTMRS8_DISABLE                 ((uint32_t volatile *)TMRS8_DISABLE)
+#define bfin_read_TMRS8_DISABLE()      bfin_read32(TMRS8_DISABLE)
+#define bfin_write_TMRS8_DISABLE(val)  bfin_write32(TMRS8_DISABLE, val)
+#define pTMRS8_STATUS                  ((uint32_t volatile *)TMRS8_STATUS)
+#define bfin_read_TMRS8_STATUS()       bfin_read32(TMRS8_STATUS)
+#define bfin_write_TMRS8_STATUS(val)   bfin_write32(TMRS8_STATUS, val)
+#define pFIO0_FLAG_D                   ((uint16_t volatile *)FIO0_FLAG_D)
+#define bfin_read_FIO0_FLAG_D()        bfin_read16(FIO0_FLAG_D)
+#define bfin_write_FIO0_FLAG_D(val)    bfin_write16(FIO0_FLAG_D, val)
+#define pFIO0_FLAG_C                   ((uint16_t volatile *)FIO0_FLAG_C)
+#define bfin_read_FIO0_FLAG_C()        bfin_read16(FIO0_FLAG_C)
+#define bfin_write_FIO0_FLAG_C(val)    bfin_write16(FIO0_FLAG_C, val)
+#define pFIO0_FLAG_S                   ((uint16_t volatile *)FIO0_FLAG_S)
+#define bfin_read_FIO0_FLAG_S()        bfin_read16(FIO0_FLAG_S)
+#define bfin_write_FIO0_FLAG_S(val)    bfin_write16(FIO0_FLAG_S, val)
+#define pFIO0_FLAG_T                   ((uint16_t volatile *)FIO0_FLAG_T)
+#define bfin_read_FIO0_FLAG_T()        bfin_read16(FIO0_FLAG_T)
+#define bfin_write_FIO0_FLAG_T(val)    bfin_write16(FIO0_FLAG_T, val)
+#define pFIO0_MASKA_D                  ((uint16_t volatile *)FIO0_MASKA_D)
+#define bfin_read_FIO0_MASKA_D()       bfin_read16(FIO0_MASKA_D)
+#define bfin_write_FIO0_MASKA_D(val)   bfin_write16(FIO0_MASKA_D, val)
+#define pFIO0_MASKA_C                  ((uint16_t volatile *)FIO0_MASKA_C)
+#define bfin_read_FIO0_MASKA_C()       bfin_read16(FIO0_MASKA_C)
+#define bfin_write_FIO0_MASKA_C(val)   bfin_write16(FIO0_MASKA_C, val)
+#define pFIO0_MASKA_S                  ((uint16_t volatile *)FIO0_MASKA_S)
+#define bfin_read_FIO0_MASKA_S()       bfin_read16(FIO0_MASKA_S)
+#define bfin_write_FIO0_MASKA_S(val)   bfin_write16(FIO0_MASKA_S, val)
+#define pFIO0_MASKA_T                  ((uint16_t volatile *)FIO0_MASKA_T)
+#define bfin_read_FIO0_MASKA_T()       bfin_read16(FIO0_MASKA_T)
+#define bfin_write_FIO0_MASKA_T(val)   bfin_write16(FIO0_MASKA_T, val)
+#define pFIO0_MASKB_D                  ((uint16_t volatile *)FIO0_MASKB_D)
+#define bfin_read_FIO0_MASKB_D()       bfin_read16(FIO0_MASKB_D)
+#define bfin_write_FIO0_MASKB_D(val)   bfin_write16(FIO0_MASKB_D, val)
+#define pFIO0_MASKB_C                  ((uint16_t volatile *)FIO0_MASKB_C)
+#define bfin_read_FIO0_MASKB_C()       bfin_read16(FIO0_MASKB_C)
+#define bfin_write_FIO0_MASKB_C(val)   bfin_write16(FIO0_MASKB_C, val)
+#define pFIO0_MASKB_S                  ((uint16_t volatile *)FIO0_MASKB_S)
+#define bfin_read_FIO0_MASKB_S()       bfin_read16(FIO0_MASKB_S)
+#define bfin_write_FIO0_MASKB_S(val)   bfin_write16(FIO0_MASKB_S, val)
+#define pFIO0_MASKB_T                  ((uint16_t volatile *)FIO0_MASKB_T)
+#define bfin_read_FIO0_MASKB_T()       bfin_read16(FIO0_MASKB_T)
+#define bfin_write_FIO0_MASKB_T(val)   bfin_write16(FIO0_MASKB_T, val)
+#define pFIO0_DIR                      ((uint16_t volatile *)FIO0_DIR)
+#define bfin_read_FIO0_DIR()           bfin_read16(FIO0_DIR)
+#define bfin_write_FIO0_DIR(val)       bfin_write16(FIO0_DIR, val)
+#define pFIO0_POLAR                    ((uint16_t volatile *)FIO0_POLAR)
+#define bfin_read_FIO0_POLAR()         bfin_read16(FIO0_POLAR)
+#define bfin_write_FIO0_POLAR(val)     bfin_write16(FIO0_POLAR, val)
+#define pFIO0_EDGE                     ((uint16_t volatile *)FIO0_EDGE)
+#define bfin_read_FIO0_EDGE()          bfin_read16(FIO0_EDGE)
+#define bfin_write_FIO0_EDGE(val)      bfin_write16(FIO0_EDGE, val)
+#define pFIO0_BOTH                     ((uint16_t volatile *)FIO0_BOTH)
+#define bfin_read_FIO0_BOTH()          bfin_read16(FIO0_BOTH)
+#define bfin_write_FIO0_BOTH(val)      bfin_write16(FIO0_BOTH, val)
+#define pFIO0_INEN                     ((uint16_t volatile *)FIO0_INEN)
+#define bfin_read_FIO0_INEN()          bfin_read16(FIO0_INEN)
+#define bfin_write_FIO0_INEN(val)      bfin_write16(FIO0_INEN, val)
+#define pFIO1_FLAG_D                   ((uint16_t volatile *)FIO1_FLAG_D)
+#define bfin_read_FIO1_FLAG_D()        bfin_read16(FIO1_FLAG_D)
+#define bfin_write_FIO1_FLAG_D(val)    bfin_write16(FIO1_FLAG_D, val)
+#define pFIO1_FLAG_C                   ((uint16_t volatile *)FIO1_FLAG_C)
+#define bfin_read_FIO1_FLAG_C()        bfin_read16(FIO1_FLAG_C)
+#define bfin_write_FIO1_FLAG_C(val)    bfin_write16(FIO1_FLAG_C, val)
+#define pFIO1_FLAG_S                   ((uint16_t volatile *)FIO1_FLAG_S)
+#define bfin_read_FIO1_FLAG_S()        bfin_read16(FIO1_FLAG_S)
+#define bfin_write_FIO1_FLAG_S(val)    bfin_write16(FIO1_FLAG_S, val)
+#define pFIO1_FLAG_T                   ((uint16_t volatile *)FIO1_FLAG_T)
+#define bfin_read_FIO1_FLAG_T()        bfin_read16(FIO1_FLAG_T)
+#define bfin_write_FIO1_FLAG_T(val)    bfin_write16(FIO1_FLAG_T, val)
+#define pFIO1_MASKA_D                  ((uint16_t volatile *)FIO1_MASKA_D)
+#define bfin_read_FIO1_MASKA_D()       bfin_read16(FIO1_MASKA_D)
+#define bfin_write_FIO1_MASKA_D(val)   bfin_write16(FIO1_MASKA_D, val)
+#define pFIO1_MASKA_C                  ((uint16_t volatile *)FIO1_MASKA_C)
+#define bfin_read_FIO1_MASKA_C()       bfin_read16(FIO1_MASKA_C)
+#define bfin_write_FIO1_MASKA_C(val)   bfin_write16(FIO1_MASKA_C, val)
+#define pFIO1_MASKA_S                  ((uint16_t volatile *)FIO1_MASKA_S)
+#define bfin_read_FIO1_MASKA_S()       bfin_read16(FIO1_MASKA_S)
+#define bfin_write_FIO1_MASKA_S(val)   bfin_write16(FIO1_MASKA_S, val)
+#define pFIO1_MASKA_T                  ((uint16_t volatile *)FIO1_MASKA_T)
+#define bfin_read_FIO1_MASKA_T()       bfin_read16(FIO1_MASKA_T)
+#define bfin_write_FIO1_MASKA_T(val)   bfin_write16(FIO1_MASKA_T, val)
+#define pFIO1_MASKB_D                  ((uint16_t volatile *)FIO1_MASKB_D)
+#define bfin_read_FIO1_MASKB_D()       bfin_read16(FIO1_MASKB_D)
+#define bfin_write_FIO1_MASKB_D(val)   bfin_write16(FIO1_MASKB_D, val)
+#define pFIO1_MASKB_C                  ((uint16_t volatile *)FIO1_MASKB_C)
+#define bfin_read_FIO1_MASKB_C()       bfin_read16(FIO1_MASKB_C)
+#define bfin_write_FIO1_MASKB_C(val)   bfin_write16(FIO1_MASKB_C, val)
+#define pFIO1_MASKB_S                  ((uint16_t volatile *)FIO1_MASKB_S)
+#define bfin_read_FIO1_MASKB_S()       bfin_read16(FIO1_MASKB_S)
+#define bfin_write_FIO1_MASKB_S(val)   bfin_write16(FIO1_MASKB_S, val)
+#define pFIO1_MASKB_T                  ((uint16_t volatile *)FIO1_MASKB_T)
+#define bfin_read_FIO1_MASKB_T()       bfin_read16(FIO1_MASKB_T)
+#define bfin_write_FIO1_MASKB_T(val)   bfin_write16(FIO1_MASKB_T, val)
+#define pFIO1_DIR                      ((uint16_t volatile *)FIO1_DIR)
+#define bfin_read_FIO1_DIR()           bfin_read16(FIO1_DIR)
+#define bfin_write_FIO1_DIR(val)       bfin_write16(FIO1_DIR, val)
+#define pFIO1_POLAR                    ((uint16_t volatile *)FIO1_POLAR)
+#define bfin_read_FIO1_POLAR()         bfin_read16(FIO1_POLAR)
+#define bfin_write_FIO1_POLAR(val)     bfin_write16(FIO1_POLAR, val)
+#define pFIO1_EDGE                     ((uint16_t volatile *)FIO1_EDGE)
+#define bfin_read_FIO1_EDGE()          bfin_read16(FIO1_EDGE)
+#define bfin_write_FIO1_EDGE(val)      bfin_write16(FIO1_EDGE, val)
+#define pFIO1_BOTH                     ((uint16_t volatile *)FIO1_BOTH)
+#define bfin_read_FIO1_BOTH()          bfin_read16(FIO1_BOTH)
+#define bfin_write_FIO1_BOTH(val)      bfin_write16(FIO1_BOTH, val)
+#define pFIO1_INEN                     ((uint16_t volatile *)FIO1_INEN)
+#define bfin_read_FIO1_INEN()          bfin_read16(FIO1_INEN)
+#define bfin_write_FIO1_INEN(val)      bfin_write16(FIO1_INEN, val)
+#define pFIO2_FLAG_D                   ((uint16_t volatile *)FIO2_FLAG_D)
+#define bfin_read_FIO2_FLAG_D()        bfin_read16(FIO2_FLAG_D)
+#define bfin_write_FIO2_FLAG_D(val)    bfin_write16(FIO2_FLAG_D, val)
+#define pFIO2_FLAG_C                   ((uint16_t volatile *)FIO2_FLAG_C)
+#define bfin_read_FIO2_FLAG_C()        bfin_read16(FIO2_FLAG_C)
+#define bfin_write_FIO2_FLAG_C(val)    bfin_write16(FIO2_FLAG_C, val)
+#define pFIO2_FLAG_S                   ((uint16_t volatile *)FIO2_FLAG_S)
+#define bfin_read_FIO2_FLAG_S()        bfin_read16(FIO2_FLAG_S)
+#define bfin_write_FIO2_FLAG_S(val)    bfin_write16(FIO2_FLAG_S, val)
+#define pFIO2_FLAG_T                   ((uint16_t volatile *)FIO2_FLAG_T)
+#define bfin_read_FIO2_FLAG_T()        bfin_read16(FIO2_FLAG_T)
+#define bfin_write_FIO2_FLAG_T(val)    bfin_write16(FIO2_FLAG_T, val)
+#define pFIO2_MASKA_D                  ((uint16_t volatile *)FIO2_MASKA_D)
+#define bfin_read_FIO2_MASKA_D()       bfin_read16(FIO2_MASKA_D)
+#define bfin_write_FIO2_MASKA_D(val)   bfin_write16(FIO2_MASKA_D, val)
+#define pFIO2_MASKA_C                  ((uint16_t volatile *)FIO2_MASKA_C)
+#define bfin_read_FIO2_MASKA_C()       bfin_read16(FIO2_MASKA_C)
+#define bfin_write_FIO2_MASKA_C(val)   bfin_write16(FIO2_MASKA_C, val)
+#define pFIO2_MASKA_S                  ((uint16_t volatile *)FIO2_MASKA_S)
+#define bfin_read_FIO2_MASKA_S()       bfin_read16(FIO2_MASKA_S)
+#define bfin_write_FIO2_MASKA_S(val)   bfin_write16(FIO2_MASKA_S, val)
+#define pFIO2_MASKA_T                  ((uint16_t volatile *)FIO2_MASKA_T)
+#define bfin_read_FIO2_MASKA_T()       bfin_read16(FIO2_MASKA_T)
+#define bfin_write_FIO2_MASKA_T(val)   bfin_write16(FIO2_MASKA_T, val)
+#define pFIO2_MASKB_D                  ((uint16_t volatile *)FIO2_MASKB_D)
+#define bfin_read_FIO2_MASKB_D()       bfin_read16(FIO2_MASKB_D)
+#define bfin_write_FIO2_MASKB_D(val)   bfin_write16(FIO2_MASKB_D, val)
+#define pFIO2_MASKB_C                  ((uint16_t volatile *)FIO2_MASKB_C)
+#define bfin_read_FIO2_MASKB_C()       bfin_read16(FIO2_MASKB_C)
+#define bfin_write_FIO2_MASKB_C(val)   bfin_write16(FIO2_MASKB_C, val)
+#define pFIO2_MASKB_S                  ((uint16_t volatile *)FIO2_MASKB_S)
+#define bfin_read_FIO2_MASKB_S()       bfin_read16(FIO2_MASKB_S)
+#define bfin_write_FIO2_MASKB_S(val)   bfin_write16(FIO2_MASKB_S, val)
+#define pFIO2_MASKB_T                  ((uint16_t volatile *)FIO2_MASKB_T)
+#define bfin_read_FIO2_MASKB_T()       bfin_read16(FIO2_MASKB_T)
+#define bfin_write_FIO2_MASKB_T(val)   bfin_write16(FIO2_MASKB_T, val)
+#define pFIO2_DIR                      ((uint16_t volatile *)FIO2_DIR)
+#define bfin_read_FIO2_DIR()           bfin_read16(FIO2_DIR)
+#define bfin_write_FIO2_DIR(val)       bfin_write16(FIO2_DIR, val)
+#define pFIO2_POLAR                    ((uint16_t volatile *)FIO2_POLAR)
+#define bfin_read_FIO2_POLAR()         bfin_read16(FIO2_POLAR)
+#define bfin_write_FIO2_POLAR(val)     bfin_write16(FIO2_POLAR, val)
+#define pFIO2_EDGE                     ((uint16_t volatile *)FIO2_EDGE)
+#define bfin_read_FIO2_EDGE()          bfin_read16(FIO2_EDGE)
+#define bfin_write_FIO2_EDGE(val)      bfin_write16(FIO2_EDGE, val)
+#define pFIO2_BOTH                     ((uint16_t volatile *)FIO2_BOTH)
+#define bfin_read_FIO2_BOTH()          bfin_read16(FIO2_BOTH)
+#define bfin_write_FIO2_BOTH(val)      bfin_write16(FIO2_BOTH, val)
+#define pFIO2_INEN                     ((uint16_t volatile *)FIO2_INEN)
+#define bfin_read_FIO2_INEN()          bfin_read16(FIO2_INEN)
+#define bfin_write_FIO2_INEN(val)      bfin_write16(FIO2_INEN, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1)
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2)
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV)
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV)
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX)
+#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1)
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2)
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV)
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV)
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT)
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL)
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1)
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2)
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0)
+#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
+#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1)
+#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
+#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2)
+#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
+#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3)
+#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
+#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0)
+#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
+#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1)
+#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
+#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2)
+#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
+#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3)
+#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1)
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2)
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV)
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV)
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX)
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1)
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2)
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV)
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV)
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT)
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL)
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1)
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2)
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0)
+#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
+#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1)
+#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
+#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2)
+#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
+#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3)
+#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
+#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0)
+#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
+#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1)
+#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
+#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2)
+#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
+#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3)
+#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
+#define pEVT0                          ((void * volatile *)EVT0)
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1)
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2)
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3)
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4)
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5)
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6)
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7)
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8)
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9)
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10)
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11)
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12)
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13)
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14)
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15)
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL)
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD)
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE)
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT)
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h
new file mode 100644
index 0000000..b4857c3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h
@@ -0,0 +1,670 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__
+#define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__
+
+#define PLL_CTL                        0xFFC00000
+#define PLL_DIV                        0xFFC00004
+#define VR_CTL                         0xFFC00008
+#define PLL_STAT                       0xFFC0000C
+#define PLL_LOCKCNT                    0xFFC00010
+#define CHIPID                         0xFFC00014
+#define SPI_CTL                        0xFFC00500
+#define SPI_FLG                        0xFFC00504
+#define SPI_STAT                       0xFFC00508
+#define SPI_TDBR                       0xFFC0050C
+#define SPI_RDBR                       0xFFC00510
+#define SPI_BAUD                       0xFFC00514
+#define SPI_SHADOW                     0xFFC00518
+#define WDOGA_CTL                      0xFFC00200
+#define WDOGA_CNT                      0xFFC00204
+#define WDOGA_STAT                     0xFFC00208
+#define WDOGB_CTL                      0xFFC01200
+#define WDOGB_CNT                      0xFFC01204
+#define WDOGB_STAT                     0xFFC01208
+#define DMA1_TC_PER                    0xFFC01B0C /* Traffic Control Periods */
+#define DMA1_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */
+#define DMA1_0_CONFIG                  0xFFC01C08
+#define DMA1_0_NEXT_DESC_PTR           0xFFC01C00
+#define DMA1_0_START_ADDR              0xFFC01C04
+#define DMA1_0_X_COUNT                 0xFFC01C10
+#define DMA1_0_Y_COUNT                 0xFFC01C18
+#define DMA1_0_X_MODIFY                0xFFC01C14
+#define DMA1_0_Y_MODIFY                0xFFC01C1C
+#define DMA1_0_CURR_DESC_PTR           0xFFC01C20
+#define DMA1_0_CURR_ADDR               0xFFC01C24
+#define DMA1_0_CURR_X_COUNT            0xFFC01C30
+#define DMA1_0_CURR_Y_COUNT            0xFFC01C38
+#define DMA1_0_IRQ_STATUS              0xFFC01C28
+#define DMA1_0_PERIPHERAL_MAP          0xFFC01C2C
+#define DMA1_1_CONFIG                  0xFFC01C48
+#define DMA1_1_NEXT_DESC_PTR           0xFFC01C40
+#define DMA1_1_START_ADDR              0xFFC01C44
+#define DMA1_1_X_COUNT                 0xFFC01C50
+#define DMA1_1_Y_COUNT                 0xFFC01C58
+#define DMA1_1_X_MODIFY                0xFFC01C54
+#define DMA1_1_Y_MODIFY                0xFFC01C5C
+#define DMA1_1_CURR_DESC_PTR           0xFFC01C60
+#define DMA1_1_CURR_ADDR               0xFFC01C64
+#define DMA1_1_CURR_X_COUNT            0xFFC01C70
+#define DMA1_1_CURR_Y_COUNT            0xFFC01C78
+#define DMA1_1_IRQ_STATUS              0xFFC01C68
+#define DMA1_1_PERIPHERAL_MAP          0xFFC01C6C
+#define DMA1_2_CONFIG                  0xFFC01C88
+#define DMA1_2_NEXT_DESC_PTR           0xFFC01C80
+#define DMA1_2_START_ADDR              0xFFC01C84
+#define DMA1_2_X_COUNT                 0xFFC01C90
+#define DMA1_2_Y_COUNT                 0xFFC01C98
+#define DMA1_2_X_MODIFY                0xFFC01C94
+#define DMA1_2_Y_MODIFY                0xFFC01C9C
+#define DMA1_2_CURR_DESC_PTR           0xFFC01CA0
+#define DMA1_2_CURR_ADDR               0xFFC01CA4
+#define DMA1_2_CURR_X_COUNT            0xFFC01CB0
+#define DMA1_2_CURR_Y_COUNT            0xFFC01CB8
+#define DMA1_2_IRQ_STATUS              0xFFC01CA8
+#define DMA1_2_PERIPHERAL_MAP          0xFFC01CAC
+#define DMA1_3_CONFIG                  0xFFC01CC8
+#define DMA1_3_NEXT_DESC_PTR           0xFFC01CC0
+#define DMA1_3_START_ADDR              0xFFC01CC4
+#define DMA1_3_X_COUNT                 0xFFC01CD0
+#define DMA1_3_Y_COUNT                 0xFFC01CD8
+#define DMA1_3_X_MODIFY                0xFFC01CD4
+#define DMA1_3_Y_MODIFY                0xFFC01CDC
+#define DMA1_3_CURR_DESC_PTR           0xFFC01CE0
+#define DMA1_3_CURR_ADDR               0xFFC01CE4
+#define DMA1_3_CURR_X_COUNT            0xFFC01CF0
+#define DMA1_3_CURR_Y_COUNT            0xFFC01CF8
+#define DMA1_3_IRQ_STATUS              0xFFC01CE8
+#define DMA1_3_PERIPHERAL_MAP          0xFFC01CEC
+#define DMA1_4_CONFIG                  0xFFC01D08
+#define DMA1_4_NEXT_DESC_PTR           0xFFC01D00
+#define DMA1_4_START_ADDR              0xFFC01D04
+#define DMA1_4_X_COUNT                 0xFFC01D10
+#define DMA1_4_Y_COUNT                 0xFFC01D18
+#define DMA1_4_X_MODIFY                0xFFC01D14
+#define DMA1_4_Y_MODIFY                0xFFC01D1C
+#define DMA1_4_CURR_DESC_PTR           0xFFC01D20
+#define DMA1_4_CURR_ADDR               0xFFC01D24
+#define DMA1_4_CURR_X_COUNT            0xFFC01D30
+#define DMA1_4_CURR_Y_COUNT            0xFFC01D38
+#define DMA1_4_IRQ_STATUS              0xFFC01D28
+#define DMA1_4_PERIPHERAL_MAP          0xFFC01D2C
+#define DMA1_5_CONFIG                  0xFFC01D48
+#define DMA1_5_NEXT_DESC_PTR           0xFFC01D40
+#define DMA1_5_START_ADDR              0xFFC01D44
+#define DMA1_5_X_COUNT                 0xFFC01D50
+#define DMA1_5_Y_COUNT                 0xFFC01D58
+#define DMA1_5_X_MODIFY                0xFFC01D54
+#define DMA1_5_Y_MODIFY                0xFFC01D5C
+#define DMA1_5_CURR_DESC_PTR           0xFFC01D60
+#define DMA1_5_CURR_ADDR               0xFFC01D64
+#define DMA1_5_CURR_X_COUNT            0xFFC01D70
+#define DMA1_5_CURR_Y_COUNT            0xFFC01D78
+#define DMA1_5_IRQ_STATUS              0xFFC01D68
+#define DMA1_5_PERIPHERAL_MAP          0xFFC01D6C
+#define DMA1_6_CONFIG                  0xFFC01D88
+#define DMA1_6_NEXT_DESC_PTR           0xFFC01D80
+#define DMA1_6_START_ADDR              0xFFC01D84
+#define DMA1_6_X_COUNT                 0xFFC01D90
+#define DMA1_6_Y_COUNT                 0xFFC01D98
+#define DMA1_6_X_MODIFY                0xFFC01D94
+#define DMA1_6_Y_MODIFY                0xFFC01D9C
+#define DMA1_6_CURR_DESC_PTR           0xFFC01DA0
+#define DMA1_6_CURR_ADDR               0xFFC01DA4
+#define DMA1_6_CURR_X_COUNT            0xFFC01DB0
+#define DMA1_6_CURR_Y_COUNT            0xFFC01DB8
+#define DMA1_6_IRQ_STATUS              0xFFC01DA8
+#define DMA1_6_PERIPHERAL_MAP          0xFFC01DAC
+#define DMA1_7_CONFIG                  0xFFC01DC8
+#define DMA1_7_NEXT_DESC_PTR           0xFFC01DC0
+#define DMA1_7_START_ADDR              0xFFC01DC4
+#define DMA1_7_X_COUNT                 0xFFC01DD0
+#define DMA1_7_Y_COUNT                 0xFFC01DD8
+#define DMA1_7_X_MODIFY                0xFFC01DD4
+#define DMA1_7_Y_MODIFY                0xFFC01DDC
+#define DMA1_7_CURR_DESC_PTR           0xFFC01DE0
+#define DMA1_7_CURR_ADDR               0xFFC01DE4
+#define DMA1_7_CURR_X_COUNT            0xFFC01DF0
+#define DMA1_7_CURR_Y_COUNT            0xFFC01DF8
+#define DMA1_7_IRQ_STATUS              0xFFC01DE8
+#define DMA1_7_PERIPHERAL_MAP          0xFFC01DEC
+#define DMA1_8_CONFIG                  0xFFC01E08
+#define DMA1_8_NEXT_DESC_PTR           0xFFC01E00
+#define DMA1_8_START_ADDR              0xFFC01E04
+#define DMA1_8_X_COUNT                 0xFFC01E10
+#define DMA1_8_Y_COUNT                 0xFFC01E18
+#define DMA1_8_X_MODIFY                0xFFC01E14
+#define DMA1_8_Y_MODIFY                0xFFC01E1C
+#define DMA1_8_CURR_DESC_PTR           0xFFC01E20
+#define DMA1_8_CURR_ADDR               0xFFC01E24
+#define DMA1_8_CURR_X_COUNT            0xFFC01E30
+#define DMA1_8_CURR_Y_COUNT            0xFFC01E38
+#define DMA1_8_IRQ_STATUS              0xFFC01E28
+#define DMA1_8_PERIPHERAL_MAP          0xFFC01E2C
+#define DMA1_9_CONFIG                  0xFFC01E48
+#define DMA1_9_NEXT_DESC_PTR           0xFFC01E40
+#define DMA1_9_START_ADDR              0xFFC01E44
+#define DMA1_9_X_COUNT                 0xFFC01E50
+#define DMA1_9_Y_COUNT                 0xFFC01E58
+#define DMA1_9_X_MODIFY                0xFFC01E54
+#define DMA1_9_Y_MODIFY                0xFFC01E5C
+#define DMA1_9_CURR_DESC_PTR           0xFFC01E60
+#define DMA1_9_CURR_ADDR               0xFFC01E64
+#define DMA1_9_CURR_X_COUNT            0xFFC01E70
+#define DMA1_9_CURR_Y_COUNT            0xFFC01E78
+#define DMA1_9_IRQ_STATUS              0xFFC01E68
+#define DMA1_9_PERIPHERAL_MAP          0xFFC01E6C
+#define DMA1_10_CONFIG                 0xFFC01E88
+#define DMA1_10_NEXT_DESC_PTR          0xFFC01E80
+#define DMA1_10_START_ADDR             0xFFC01E84
+#define DMA1_10_X_COUNT                0xFFC01E90
+#define DMA1_10_Y_COUNT                0xFFC01E98
+#define DMA1_10_X_MODIFY               0xFFC01E94
+#define DMA1_10_Y_MODIFY               0xFFC01E9C
+#define DMA1_10_CURR_DESC_PTR          0xFFC01EA0
+#define DMA1_10_CURR_ADDR              0xFFC01EA4
+#define DMA1_10_CURR_X_COUNT           0xFFC01EB0
+#define DMA1_10_CURR_Y_COUNT           0xFFC01EB8
+#define DMA1_10_IRQ_STATUS             0xFFC01EA8
+#define DMA1_10_PERIPHERAL_MAP         0xFFC01EAC
+#define DMA1_11_CONFIG                 0xFFC01EC8
+#define DMA1_11_NEXT_DESC_PTR          0xFFC01EC0
+#define DMA1_11_START_ADDR             0xFFC01EC4
+#define DMA1_11_X_COUNT                0xFFC01ED0
+#define DMA1_11_Y_COUNT                0xFFC01ED8
+#define DMA1_11_X_MODIFY               0xFFC01ED4
+#define DMA1_11_Y_MODIFY               0xFFC01EDC
+#define DMA1_11_CURR_DESC_PTR          0xFFC01EE0
+#define DMA1_11_CURR_ADDR              0xFFC01EE4
+#define DMA1_11_CURR_X_COUNT           0xFFC01EF0
+#define DMA1_11_CURR_Y_COUNT           0xFFC01EF8
+#define DMA1_11_IRQ_STATUS             0xFFC01EE8
+#define DMA1_11_PERIPHERAL_MAP         0xFFC01EEC
+#define DMA2_TC_PER                    0xFFC00B0C
+#define DMA2_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */
+#define DMA2_0_CONFIG                  0xFFC00C08
+#define DMA2_0_NEXT_DESC_PTR           0xFFC00C00
+#define DMA2_0_START_ADDR              0xFFC00C04
+#define DMA2_0_X_COUNT                 0xFFC00C10
+#define DMA2_0_Y_COUNT                 0xFFC00C18
+#define DMA2_0_X_MODIFY                0xFFC00C14
+#define DMA2_0_Y_MODIFY                0xFFC00C1C
+#define DMA2_0_CURR_DESC_PTR           0xFFC00C20
+#define DMA2_0_CURR_ADDR               0xFFC00C24
+#define DMA2_0_CURR_X_COUNT            0xFFC00C30
+#define DMA2_0_CURR_Y_COUNT            0xFFC00C38
+#define DMA2_0_IRQ_STATUS              0xFFC00C28
+#define DMA2_0_PERIPHERAL_MAP          0xFFC00C2C
+#define DMA2_1_CONFIG                  0xFFC00C48
+#define DMA2_1_NEXT_DESC_PTR           0xFFC00C40
+#define DMA2_1_START_ADDR              0xFFC00C44
+#define DMA2_1_X_COUNT                 0xFFC00C50
+#define DMA2_1_Y_COUNT                 0xFFC00C58
+#define DMA2_1_X_MODIFY                0xFFC00C54
+#define DMA2_1_Y_MODIFY                0xFFC00C5C
+#define DMA2_1_CURR_DESC_PTR           0xFFC00C60
+#define DMA2_1_CURR_ADDR               0xFFC00C64
+#define DMA2_1_CURR_X_COUNT            0xFFC00C70
+#define DMA2_1_CURR_Y_COUNT            0xFFC00C78
+#define DMA2_1_IRQ_STATUS              0xFFC00C68
+#define DMA2_1_PERIPHERAL_MAP          0xFFC00C6C
+#define DMA2_2_CONFIG                  0xFFC00C88
+#define DMA2_2_NEXT_DESC_PTR           0xFFC00C80
+#define DMA2_2_START_ADDR              0xFFC00C84
+#define DMA2_2_X_COUNT                 0xFFC00C90
+#define DMA2_2_Y_COUNT                 0xFFC00C98
+#define DMA2_2_X_MODIFY                0xFFC00C94
+#define DMA2_2_Y_MODIFY                0xFFC00C9C
+#define DMA2_2_CURR_DESC_PTR           0xFFC00CA0
+#define DMA2_2_CURR_ADDR               0xFFC00CA4
+#define DMA2_2_CURR_X_COUNT            0xFFC00CB0
+#define DMA2_2_CURR_Y_COUNT            0xFFC00CB8
+#define DMA2_2_IRQ_STATUS              0xFFC00CA8
+#define DMA2_2_PERIPHERAL_MAP          0xFFC00CAC
+#define DMA2_3_CONFIG                  0xFFC00CC8
+#define DMA2_3_NEXT_DESC_PTR           0xFFC00CC0
+#define DMA2_3_START_ADDR              0xFFC00CC4
+#define DMA2_3_X_COUNT                 0xFFC00CD0
+#define DMA2_3_Y_COUNT                 0xFFC00CD8
+#define DMA2_3_X_MODIFY                0xFFC00CD4
+#define DMA2_3_Y_MODIFY                0xFFC00CDC
+#define DMA2_3_CURR_DESC_PTR           0xFFC00CE0
+#define DMA2_3_CURR_ADDR               0xFFC00CE4
+#define DMA2_3_CURR_X_COUNT            0xFFC00CF0
+#define DMA2_3_CURR_Y_COUNT            0xFFC00CF8
+#define DMA2_3_IRQ_STATUS              0xFFC00CE8
+#define DMA2_3_PERIPHERAL_MAP          0xFFC00CEC
+#define DMA2_4_CONFIG                  0xFFC00D08
+#define DMA2_4_NEXT_DESC_PTR           0xFFC00D00
+#define DMA2_4_START_ADDR              0xFFC00D04
+#define DMA2_4_X_COUNT                 0xFFC00D10
+#define DMA2_4_Y_COUNT                 0xFFC00D18
+#define DMA2_4_X_MODIFY                0xFFC00D14
+#define DMA2_4_Y_MODIFY                0xFFC00D1C
+#define DMA2_4_CURR_DESC_PTR           0xFFC00D20
+#define DMA2_4_CURR_ADDR               0xFFC00D24
+#define DMA2_4_CURR_X_COUNT            0xFFC00D30
+#define DMA2_4_CURR_Y_COUNT            0xFFC00D38
+#define DMA2_4_IRQ_STATUS              0xFFC00D28
+#define DMA2_4_PERIPHERAL_MAP          0xFFC00D2C
+#define DMA2_5_CONFIG                  0xFFC00D48
+#define DMA2_5_NEXT_DESC_PTR           0xFFC00D40
+#define DMA2_5_START_ADDR              0xFFC00D44
+#define DMA2_5_X_COUNT                 0xFFC00D50
+#define DMA2_5_Y_COUNT                 0xFFC00D58
+#define DMA2_5_X_MODIFY                0xFFC00D54
+#define DMA2_5_Y_MODIFY                0xFFC00D5C
+#define DMA2_5_CURR_DESC_PTR           0xFFC00D60
+#define DMA2_5_CURR_ADDR               0xFFC00D64
+#define DMA2_5_CURR_X_COUNT            0xFFC00D70
+#define DMA2_5_CURR_Y_COUNT            0xFFC00D78
+#define DMA2_5_IRQ_STATUS              0xFFC00D68
+#define DMA2_5_PERIPHERAL_MAP          0xFFC00D6C
+#define DMA2_6_CONFIG                  0xFFC00D88
+#define DMA2_6_NEXT_DESC_PTR           0xFFC00D80
+#define DMA2_6_START_ADDR              0xFFC00D84
+#define DMA2_6_X_COUNT                 0xFFC00D90
+#define DMA2_6_Y_COUNT                 0xFFC00D98
+#define DMA2_6_X_MODIFY                0xFFC00D94
+#define DMA2_6_Y_MODIFY                0xFFC00D9C
+#define DMA2_6_CURR_DESC_PTR           0xFFC00DA0
+#define DMA2_6_CURR_ADDR               0xFFC00DA4
+#define DMA2_6_CURR_X_COUNT            0xFFC00DB0
+#define DMA2_6_CURR_Y_COUNT            0xFFC00DB8
+#define DMA2_6_IRQ_STATUS              0xFFC00DA8
+#define DMA2_6_PERIPHERAL_MAP          0xFFC00DAC
+#define DMA2_7_CONFIG                  0xFFC00DC8
+#define DMA2_7_NEXT_DESC_PTR           0xFFC00DC0
+#define DMA2_7_START_ADDR              0xFFC00DC4
+#define DMA2_7_X_COUNT                 0xFFC00DD0
+#define DMA2_7_Y_COUNT                 0xFFC00DD8
+#define DMA2_7_X_MODIFY                0xFFC00DD4
+#define DMA2_7_Y_MODIFY                0xFFC00DDC
+#define DMA2_7_CURR_DESC_PTR           0xFFC00DE0
+#define DMA2_7_CURR_ADDR               0xFFC00DE4
+#define DMA2_7_CURR_X_COUNT            0xFFC00DF0
+#define DMA2_7_CURR_Y_COUNT            0xFFC00DF8
+#define DMA2_7_IRQ_STATUS              0xFFC00DE8
+#define DMA2_7_PERIPHERAL_MAP          0xFFC00DEC
+#define DMA2_8_CONFIG                  0xFFC00E08
+#define DMA2_8_NEXT_DESC_PTR           0xFFC00E00
+#define DMA2_8_START_ADDR              0xFFC00E04
+#define DMA2_8_X_COUNT                 0xFFC00E10
+#define DMA2_8_Y_COUNT                 0xFFC00E18
+#define DMA2_8_X_MODIFY                0xFFC00E14
+#define DMA2_8_Y_MODIFY                0xFFC00E1C
+#define DMA2_8_CURR_DESC_PTR           0xFFC00E20
+#define DMA2_8_CURR_ADDR               0xFFC00E24
+#define DMA2_8_CURR_X_COUNT            0xFFC00E30
+#define DMA2_8_CURR_Y_COUNT            0xFFC00E38
+#define DMA2_8_IRQ_STATUS              0xFFC00E28
+#define DMA2_8_PERIPHERAL_MAP          0xFFC00E2C
+#define DMA2_9_CONFIG                  0xFFC00E48
+#define DMA2_9_NEXT_DESC_PTR           0xFFC00E40
+#define DMA2_9_START_ADDR              0xFFC00E44
+#define DMA2_9_X_COUNT                 0xFFC00E50
+#define DMA2_9_Y_COUNT                 0xFFC00E58
+#define DMA2_9_X_MODIFY                0xFFC00E54
+#define DMA2_9_Y_MODIFY                0xFFC00E5C
+#define DMA2_9_CURR_DESC_PTR           0xFFC00E60
+#define DMA2_9_CURR_ADDR               0xFFC00E64
+#define DMA2_9_CURR_X_COUNT            0xFFC00E70
+#define DMA2_9_CURR_Y_COUNT            0xFFC00E78
+#define DMA2_9_IRQ_STATUS              0xFFC00E68
+#define DMA2_9_PERIPHERAL_MAP          0xFFC00E6C
+#define DMA2_10_CONFIG                 0xFFC00E88
+#define DMA2_10_NEXT_DESC_PTR          0xFFC00E80
+#define DMA2_10_START_ADDR             0xFFC00E84
+#define DMA2_10_X_COUNT                0xFFC00E90
+#define DMA2_10_Y_COUNT                0xFFC00E98
+#define DMA2_10_X_MODIFY               0xFFC00E94
+#define DMA2_10_Y_MODIFY               0xFFC00E9C
+#define DMA2_10_CURR_DESC_PTR          0xFFC00EA0
+#define DMA2_10_CURR_ADDR              0xFFC00EA4
+#define DMA2_10_CURR_X_COUNT           0xFFC00EB0
+#define DMA2_10_CURR_Y_COUNT           0xFFC00EB8
+#define DMA2_10_IRQ_STATUS             0xFFC00EA8
+#define DMA2_10_PERIPHERAL_MAP         0xFFC00EAC
+#define DMA2_11_CONFIG                 0xFFC00EC8
+#define DMA2_11_NEXT_DESC_PTR          0xFFC00EC0
+#define DMA2_11_START_ADDR             0xFFC00EC4
+#define DMA2_11_X_COUNT                0xFFC00ED0
+#define DMA2_11_Y_COUNT                0xFFC00ED8
+#define DMA2_11_X_MODIFY               0xFFC00ED4
+#define DMA2_11_Y_MODIFY               0xFFC00EDC
+#define DMA2_11_CURR_DESC_PTR          0xFFC00EE0
+#define DMA2_11_CURR_ADDR              0xFFC00EE4
+#define DMA2_11_CURR_X_COUNT           0xFFC00EF0
+#define DMA2_11_CURR_Y_COUNT           0xFFC00EF8
+#define DMA2_11_IRQ_STATUS             0xFFC00EE8
+#define DMA2_11_PERIPHERAL_MAP         0xFFC00EEC
+#define IMDMA_S0_CONFIG                0xFFC01848
+#define IMDMA_S0_NEXT_DESC_PTR         0xFFC01840
+#define IMDMA_S0_START_ADDR            0xFFC01844
+#define IMDMA_S0_X_COUNT               0xFFC01850
+#define IMDMA_S0_Y_COUNT               0xFFC01858
+#define IMDMA_S0_X_MODIFY              0xFFC01854
+#define IMDMA_S0_Y_MODIFY              0xFFC0185C
+#define IMDMA_S0_CURR_DESC_PTR         0xFFC01860
+#define IMDMA_S0_CURR_ADDR             0xFFC01864
+#define IMDMA_S0_CURR_X_COUNT          0xFFC01870
+#define IMDMA_S0_CURR_Y_COUNT          0xFFC01878
+#define IMDMA_S0_IRQ_STATUS            0xFFC01868
+#define IMDMA_D0_CONFIG                0xFFC01808
+#define IMDMA_D0_NEXT_DESC_PTR         0xFFC01800
+#define IMDMA_D0_START_ADDR            0xFFC01804
+#define IMDMA_D0_X_COUNT               0xFFC01810
+#define IMDMA_D0_Y_COUNT               0xFFC01818
+#define IMDMA_D0_X_MODIFY              0xFFC01814
+#define IMDMA_D0_Y_MODIFY              0xFFC0181C
+#define IMDMA_D0_CURR_DESC_PTR         0xFFC01820
+#define IMDMA_D0_CURR_ADDR             0xFFC01824
+#define IMDMA_D0_CURR_X_COUNT          0xFFC01830
+#define IMDMA_D0_CURR_Y_COUNT          0xFFC01838
+#define IMDMA_D0_IRQ_STATUS            0xFFC01828
+#define IMDMA_S1_CONFIG                0xFFC018C8
+#define IMDMA_S1_NEXT_DESC_PTR         0xFFC018C0
+#define IMDMA_S1_START_ADDR            0xFFC018C4
+#define IMDMA_S1_X_COUNT               0xFFC018D0
+#define IMDMA_S1_Y_COUNT               0xFFC018D8
+#define IMDMA_S1_X_MODIFY              0xFFC018D4
+#define IMDMA_S1_Y_MODIFY              0xFFC018DC
+#define IMDMA_S1_CURR_DESC_PTR         0xFFC018E0
+#define IMDMA_S1_CURR_ADDR             0xFFC018E4
+#define IMDMA_S1_CURR_X_COUNT          0xFFC018F0
+#define IMDMA_S1_CURR_Y_COUNT          0xFFC018F8
+#define IMDMA_S1_IRQ_STATUS            0xFFC018E8
+#define IMDMA_D1_CONFIG                0xFFC01888
+#define IMDMA_D1_NEXT_DESC_PTR         0xFFC01880
+#define IMDMA_D1_START_ADDR            0xFFC01884
+#define IMDMA_D1_X_COUNT               0xFFC01890
+#define IMDMA_D1_Y_COUNT               0xFFC01898
+#define IMDMA_D1_X_MODIFY              0xFFC01894
+#define IMDMA_D1_Y_MODIFY              0xFFC0189C
+#define IMDMA_D1_CURR_DESC_PTR         0xFFC018A0
+#define IMDMA_D1_CURR_ADDR             0xFFC018A4
+#define IMDMA_D1_CURR_X_COUNT          0xFFC018B0
+#define IMDMA_D1_CURR_Y_COUNT          0xFFC018B8
+#define IMDMA_D1_IRQ_STATUS            0xFFC018A8
+#define MDMA1_S0_CONFIG                0xFFC01F48
+#define MDMA1_S0_NEXT_DESC_PTR         0xFFC01F40
+#define MDMA1_S0_START_ADDR            0xFFC01F44
+#define MDMA1_S0_X_COUNT               0xFFC01F50
+#define MDMA1_S0_Y_COUNT               0xFFC01F58
+#define MDMA1_S0_X_MODIFY              0xFFC01F54
+#define MDMA1_S0_Y_MODIFY              0xFFC01F5C
+#define MDMA1_S0_CURR_DESC_PTR         0xFFC01F60
+#define MDMA1_S0_CURR_ADDR             0xFFC01F64
+#define MDMA1_S0_CURR_X_COUNT          0xFFC01F70
+#define MDMA1_S0_CURR_Y_COUNT          0xFFC01F78
+#define MDMA1_S0_IRQ_STATUS            0xFFC01F68
+#define MDMA1_S0_PERIPHERAL_MAP        0xFFC01F6C
+#define MDMA1_D0_CONFIG                0xFFC01F08
+#define MDMA1_D0_NEXT_DESC_PTR         0xFFC01F00
+#define MDMA1_D0_START_ADDR            0xFFC01F04
+#define MDMA1_D0_X_COUNT               0xFFC01F10
+#define MDMA1_D0_Y_COUNT               0xFFC01F18
+#define MDMA1_D0_X_MODIFY              0xFFC01F14
+#define MDMA1_D0_Y_MODIFY              0xFFC01F1C
+#define MDMA1_D0_CURR_DESC_PTR         0xFFC01F20
+#define MDMA1_D0_CURR_ADDR             0xFFC01F24
+#define MDMA1_D0_CURR_X_COUNT          0xFFC01F30
+#define MDMA1_D0_CURR_Y_COUNT          0xFFC01F38
+#define MDMA1_D0_IRQ_STATUS            0xFFC01F28
+#define MDMA1_D0_PERIPHERAL_MAP        0xFFC01F2C
+#define MDMA1_S1_CONFIG                0xFFC01FC8
+#define MDMA1_S1_NEXT_DESC_PTR         0xFFC01FC0
+#define MDMA1_S1_START_ADDR            0xFFC01FC4
+#define MDMA1_S1_X_COUNT               0xFFC01FD0
+#define MDMA1_S1_Y_COUNT               0xFFC01FD8
+#define MDMA1_S1_X_MODIFY              0xFFC01FD4
+#define MDMA1_S1_Y_MODIFY              0xFFC01FDC
+#define MDMA1_S1_CURR_DESC_PTR         0xFFC01FE0
+#define MDMA1_S1_CURR_ADDR             0xFFC01FE4
+#define MDMA1_S1_CURR_X_COUNT          0xFFC01FF0
+#define MDMA1_S1_CURR_Y_COUNT          0xFFC01FF8
+#define MDMA1_S1_IRQ_STATUS            0xFFC01FE8
+#define MDMA1_S1_PERIPHERAL_MAP        0xFFC01FEC
+#define MDMA1_D1_CONFIG                0xFFC01F88
+#define MDMA1_D1_NEXT_DESC_PTR         0xFFC01F80
+#define MDMA1_D1_START_ADDR            0xFFC01F84
+#define MDMA1_D1_X_COUNT               0xFFC01F90
+#define MDMA1_D1_Y_COUNT               0xFFC01F98
+#define MDMA1_D1_X_MODIFY              0xFFC01F94
+#define MDMA1_D1_Y_MODIFY              0xFFC01F9C
+#define MDMA1_D1_CURR_DESC_PTR         0xFFC01FA0
+#define MDMA1_D1_CURR_ADDR             0xFFC01FA4
+#define MDMA1_D1_CURR_X_COUNT          0xFFC01FB0
+#define MDMA1_D1_CURR_Y_COUNT          0xFFC01FB8
+#define MDMA1_D1_IRQ_STATUS            0xFFC01FA8
+#define MDMA1_D1_PERIPHERAL_MAP        0xFFC01FAC
+#define MDMA2_S0_CONFIG                0xFFC00F48
+#define MDMA2_S0_NEXT_DESC_PTR         0xFFC00F40
+#define MDMA2_S0_START_ADDR            0xFFC00F44
+#define MDMA2_S0_X_COUNT               0xFFC00F50
+#define MDMA2_S0_Y_COUNT               0xFFC00F58
+#define MDMA2_S0_X_MODIFY              0xFFC00F54
+#define MDMA2_S0_Y_MODIFY              0xFFC00F5C
+#define MDMA2_S0_CURR_DESC_PTR         0xFFC00F60
+#define MDMA2_S0_CURR_ADDR             0xFFC00F64
+#define MDMA2_S0_CURR_X_COUNT          0xFFC00F70
+#define MDMA2_S0_CURR_Y_COUNT          0xFFC00F78
+#define MDMA2_S0_IRQ_STATUS            0xFFC00F68
+#define MDMA2_S0_PERIPHERAL_MAP        0xFFC00F6C
+#define MDMA2_D0_CONFIG                0xFFC00F08
+#define MDMA2_D0_NEXT_DESC_PTR         0xFFC00F00
+#define MDMA2_D0_START_ADDR            0xFFC00F04
+#define MDMA2_D0_X_COUNT               0xFFC00F10
+#define MDMA2_D0_Y_COUNT               0xFFC00F18
+#define MDMA2_D0_X_MODIFY              0xFFC00F14
+#define MDMA2_D0_Y_MODIFY              0xFFC00F1C
+#define MDMA2_D0_CURR_DESC_PTR         0xFFC00F20
+#define MDMA2_D0_CURR_ADDR             0xFFC00F24
+#define MDMA2_D0_CURR_X_COUNT          0xFFC00F30
+#define MDMA2_D0_CURR_Y_COUNT          0xFFC00F38
+#define MDMA2_D0_IRQ_STATUS            0xFFC00F28
+#define MDMA2_D0_PERIPHERAL_MAP        0xFFC00F2C
+#define MDMA2_S1_CONFIG                0xFFC00FC8
+#define MDMA2_S1_NEXT_DESC_PTR         0xFFC00FC0
+#define MDMA2_S1_START_ADDR            0xFFC00FC4
+#define MDMA2_S1_X_COUNT               0xFFC00FD0
+#define MDMA2_S1_Y_COUNT               0xFFC00FD8
+#define MDMA2_S1_X_MODIFY              0xFFC00FD4
+#define MDMA2_S1_Y_MODIFY              0xFFC00FDC
+#define MDMA2_S1_CURR_DESC_PTR         0xFFC00FE0
+#define MDMA2_S1_CURR_ADDR             0xFFC00FE4
+#define MDMA2_S1_CURR_X_COUNT          0xFFC00FF0
+#define MDMA2_S1_CURR_Y_COUNT          0xFFC00FF8
+#define MDMA2_S1_IRQ_STATUS            0xFFC00FE8
+#define MDMA2_S1_PERIPHERAL_MAP        0xFFC00FEC
+#define MDMA2_D1_CONFIG                0xFFC00F88
+#define MDMA2_D1_NEXT_DESC_PTR         0xFFC00F80
+#define MDMA2_D1_START_ADDR            0xFFC00F84
+#define MDMA2_D1_X_COUNT               0xFFC00F90
+#define MDMA2_D1_Y_COUNT               0xFFC00F98
+#define MDMA2_D1_X_MODIFY              0xFFC00F94
+#define MDMA2_D1_Y_MODIFY              0xFFC00F9C
+#define MDMA2_D1_CURR_DESC_PTR         0xFFC00FA0
+#define MDMA2_D1_CURR_ADDR             0xFFC00FA4
+#define MDMA2_D1_CURR_X_COUNT          0xFFC00FB0
+#define MDMA2_D1_CURR_Y_COUNT          0xFFC00FB8
+#define MDMA2_D1_IRQ_STATUS            0xFFC00FA8
+#define MDMA2_D1_PERIPHERAL_MAP        0xFFC00FAC
+#define TIMER0_CONFIG                  0xFFC00600
+#define TIMER0_COUNTER                 0xFFC00604
+#define TIMER0_PERIOD                  0xFFC00608
+#define TIMER0_WIDTH                   0xFFC0060C
+#define TIMER1_CONFIG                  0xFFC00610
+#define TIMER1_COUNTER                 0xFFC00614
+#define TIMER1_PERIOD                  0xFFC00618
+#define TIMER1_WIDTH                   0xFFC0061C
+#define TIMER2_CONFIG                  0xFFC00620
+#define TIMER2_COUNTER                 0xFFC00624
+#define TIMER2_PERIOD                  0xFFC00628
+#define TIMER2_WIDTH                   0xFFC0062C
+#define TIMER3_CONFIG                  0xFFC00630
+#define TIMER3_COUNTER                 0xFFC00634
+#define TIMER3_PERIOD                  0xFFC00638
+#define TIMER3_WIDTH                   0xFFC0063C
+#define TIMER4_CONFIG                  0xFFC00640
+#define TIMER4_COUNTER                 0xFFC00644
+#define TIMER4_PERIOD                  0xFFC00648
+#define TIMER4_WIDTH                   0xFFC0064C
+#define TIMER5_CONFIG                  0xFFC00650
+#define TIMER5_COUNTER                 0xFFC00654
+#define TIMER5_PERIOD                  0xFFC00658
+#define TIMER5_WIDTH                   0xFFC0065C
+#define TIMER6_CONFIG                  0xFFC00660
+#define TIMER6_COUNTER                 0xFFC00664
+#define TIMER6_PERIOD                  0xFFC00668
+#define TIMER6_WIDTH                   0xFFC0066C
+#define TIMER7_CONFIG                  0xFFC00670
+#define TIMER7_COUNTER                 0xFFC00674
+#define TIMER7_PERIOD                  0xFFC00678
+#define TIMER7_WIDTH                   0xFFC0067C
+#define TIMER8_CONFIG                  0xFFC01600
+#define TIMER8_COUNTER                 0xFFC01604
+#define TIMER8_PERIOD                  0xFFC01608
+#define TIMER8_WIDTH                   0xFFC0160C
+#define TIMER9_CONFIG                  0xFFC01610
+#define TIMER9_COUNTER                 0xFFC01614
+#define TIMER9_PERIOD                  0xFFC01618
+#define TIMER9_WIDTH                   0xFFC0161C
+#define TIMER10_CONFIG                 0xFFC01620
+#define TIMER10_COUNTER                0xFFC01624
+#define TIMER10_PERIOD                 0xFFC01628
+#define TIMER10_WIDTH                  0xFFC0162C
+#define TIMER11_CONFIG                 0xFFC01630
+#define TIMER11_COUNTER                0xFFC01634
+#define TIMER11_PERIOD                 0xFFC01638
+#define TIMER11_WIDTH                  0xFFC0163C
+#define TMRS4_ENABLE                   0xFFC01640
+#define TMRS4_DISABLE                  0xFFC01644
+#define TMRS4_STATUS                   0xFFC01648
+#define TMRS8_ENABLE                   0xFFC00680
+#define TMRS8_DISABLE                  0xFFC00684
+#define TMRS8_STATUS                   0xFFC00688
+#define FIO0_FLAG_D                    0xFFC00700
+#define FIO0_FLAG_C                    0xFFC00704
+#define FIO0_FLAG_S                    0xFFC00708
+#define FIO0_FLAG_T                    0xFFC0070C
+#define FIO0_MASKA_D                   0xFFC00710
+#define FIO0_MASKA_C                   0xFFC00714
+#define FIO0_MASKA_S                   0xFFC00718
+#define FIO0_MASKA_T                   0xFFC0071C
+#define FIO0_MASKB_D                   0xFFC00720
+#define FIO0_MASKB_C                   0xFFC00724
+#define FIO0_MASKB_S                   0xFFC00728
+#define FIO0_MASKB_T                   0xFFC0072C
+#define FIO0_DIR                       0xFFC00730
+#define FIO0_POLAR                     0xFFC00734
+#define FIO0_EDGE                      0xFFC00738
+#define FIO0_BOTH                      0xFFC0073C
+#define FIO0_INEN                      0xFFC00740
+#define FIO1_FLAG_D                    0xFFC01500
+#define FIO1_FLAG_C                    0xFFC01504
+#define FIO1_FLAG_S                    0xFFC01508
+#define FIO1_FLAG_T                    0xFFC0150C
+#define FIO1_MASKA_D                   0xFFC01510
+#define FIO1_MASKA_C                   0xFFC01514
+#define FIO1_MASKA_S                   0xFFC01518
+#define FIO1_MASKA_T                   0xFFC0151C
+#define FIO1_MASKB_D                   0xFFC01520
+#define FIO1_MASKB_C                   0xFFC01524
+#define FIO1_MASKB_S                   0xFFC01528
+#define FIO1_MASKB_T                   0xFFC0152C
+#define FIO1_DIR                       0xFFC01530
+#define FIO1_POLAR                     0xFFC01534
+#define FIO1_EDGE                      0xFFC01538
+#define FIO1_BOTH                      0xFFC0153C
+#define FIO1_INEN                      0xFFC01540
+#define FIO2_FLAG_D                    0xFFC01700
+#define FIO2_FLAG_C                    0xFFC01704
+#define FIO2_FLAG_S                    0xFFC01708
+#define FIO2_FLAG_T                    0xFFC0170C
+#define FIO2_MASKA_D                   0xFFC01710
+#define FIO2_MASKA_C                   0xFFC01714
+#define FIO2_MASKA_S                   0xFFC01718
+#define FIO2_MASKA_T                   0xFFC0171C
+#define FIO2_MASKB_D                   0xFFC01720
+#define FIO2_MASKB_C                   0xFFC01724
+#define FIO2_MASKB_S                   0xFFC01728
+#define FIO2_MASKB_T                   0xFFC0172C
+#define FIO2_DIR                       0xFFC01730
+#define FIO2_POLAR                     0xFFC01734
+#define FIO2_EDGE                      0xFFC01738
+#define FIO2_BOTH                      0xFFC0173C
+#define FIO2_INEN                      0xFFC01740
+#define SPORT0_TCR1                    0xFFC00800
+#define SPORT0_TCR2                    0xFFC00804
+#define SPORT0_TCLKDIV                 0xFFC00808
+#define SPORT0_TFSDIV                  0xFFC0080C
+#define SPORT0_TX                      0xFFC00810
+#define SPORT0_RX                      0xFFC00818
+#define SPORT0_RCR1                    0xFFC00820
+#define SPORT0_RCR2                    0xFFC00824
+#define SPORT0_RCLKDIV                 0xFFC00828
+#define SPORT0_RFSDIV                  0xFFC0082C
+#define SPORT0_STAT                    0xFFC00830
+#define SPORT0_CHNL                    0xFFC00834
+#define SPORT0_MCMC1                   0xFFC00838
+#define SPORT0_MCMC2                   0xFFC0083C
+#define SPORT0_MTCS0                   0xFFC00840
+#define SPORT0_MTCS1                   0xFFC00844
+#define SPORT0_MTCS2                   0xFFC00848
+#define SPORT0_MTCS3                   0xFFC0084C
+#define SPORT0_MRCS0                   0xFFC00850
+#define SPORT0_MRCS1                   0xFFC00854
+#define SPORT0_MRCS2                   0xFFC00858
+#define SPORT0_MRCS3                   0xFFC0085C
+#define SPORT1_TCR1                    0xFFC00900
+#define SPORT1_TCR2                    0xFFC00904
+#define SPORT1_TCLKDIV                 0xFFC00908
+#define SPORT1_TFSDIV                  0xFFC0090C
+#define SPORT1_TX                      0xFFC00910
+#define SPORT1_RX                      0xFFC00918
+#define SPORT1_RCR1                    0xFFC00920
+#define SPORT1_RCR2                    0xFFC00924
+#define SPORT1_RCLKDIV                 0xFFC00928
+#define SPORT1_RFSDIV                  0xFFC0092C
+#define SPORT1_STAT                    0xFFC00930
+#define SPORT1_CHNL                    0xFFC00934
+#define SPORT1_MCMC1                   0xFFC00938
+#define SPORT1_MCMC2                   0xFFC0093C
+#define SPORT1_MTCS0                   0xFFC00940
+#define SPORT1_MTCS1                   0xFFC00944
+#define SPORT1_MTCS2                   0xFFC00948
+#define SPORT1_MTCS3                   0xFFC0094C
+#define SPORT1_MRCS0                   0xFFC00950
+#define SPORT1_MRCS1                   0xFFC00954
+#define SPORT1_MRCS2                   0xFFC00958
+#define SPORT1_MRCS3                   0xFFC0095C
+#define EVT0                           0xFFE02000
+#define EVT1                           0xFFE02004
+#define EVT2                           0xFFE02008
+#define EVT3                           0xFFE0200C
+#define EVT4                           0xFFE02010
+#define EVT5                           0xFFE02014
+#define EVT6                           0xFFE02018
+#define EVT7                           0xFFE0201C
+#define EVT8                           0xFFE02020
+#define EVT9                           0xFFE02024
+#define EVT10                          0xFFE02028
+#define EVT11                          0xFFE0202C
+#define EVT12                          0xFFE02030
+#define EVT13                          0xFFE02034
+#define EVT14                          0xFFE02038
+#define EVT15                          0xFFE0203C
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000
+#define TPERIOD                        0xFFE03004
+#define TSCALE                         0xFFE03008
+#define TCOUNT                         0xFFE0300C
+
+#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
new file mode 100644
index 0000000..af17813
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
@@ -0,0 +1,73 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_core__
+#define __BFIN_CDEF_ADSP_EDN_core__
+
+#define pWPIACTL                       ((uint32_t volatile *)WPIACTL)
+#define bfin_read_WPIACTL()            bfin_read32(WPIACTL)
+#define bfin_write_WPIACTL(val)        bfin_write32(WPIACTL, val)
+#define pWPIA0                         ((void * volatile *)WPIA0)
+#define bfin_read_WPIA0()              bfin_readPTR(WPIA0)
+#define bfin_write_WPIA0(val)          bfin_writePTR(WPIA0, val)
+#define pWPIA1                         ((void * volatile *)WPIA1)
+#define bfin_read_WPIA1()              bfin_readPTR(WPIA1)
+#define bfin_write_WPIA1(val)          bfin_writePTR(WPIA1, val)
+#define pWPIA2                         ((void * volatile *)WPIA2)
+#define bfin_read_WPIA2()              bfin_readPTR(WPIA2)
+#define bfin_write_WPIA2(val)          bfin_writePTR(WPIA2, val)
+#define pWPIA3                         ((void * volatile *)WPIA3)
+#define bfin_read_WPIA3()              bfin_readPTR(WPIA3)
+#define bfin_write_WPIA3(val)          bfin_writePTR(WPIA3, val)
+#define pWPIA4                         ((void * volatile *)WPIA4)
+#define bfin_read_WPIA4()              bfin_readPTR(WPIA4)
+#define bfin_write_WPIA4(val)          bfin_writePTR(WPIA4, val)
+#define pWPIA5                         ((void * volatile *)WPIA5)
+#define bfin_read_WPIA5()              bfin_readPTR(WPIA5)
+#define bfin_write_WPIA5(val)          bfin_writePTR(WPIA5, val)
+#define pWPIACNT0                      ((uint32_t volatile *)WPIACNT0)
+#define bfin_read_WPIACNT0()           bfin_read32(WPIACNT0)
+#define bfin_write_WPIACNT0(val)       bfin_write32(WPIACNT0, val)
+#define pWPIACNT1                      ((uint32_t volatile *)WPIACNT1)
+#define bfin_read_WPIACNT1()           bfin_read32(WPIACNT1)
+#define bfin_write_WPIACNT1(val)       bfin_write32(WPIACNT1, val)
+#define pWPIACNT2                      ((uint32_t volatile *)WPIACNT2)
+#define bfin_read_WPIACNT2()           bfin_read32(WPIACNT2)
+#define bfin_write_WPIACNT2(val)       bfin_write32(WPIACNT2, val)
+#define pWPIACNT3                      ((uint32_t volatile *)WPIACNT3)
+#define bfin_read_WPIACNT3()           bfin_read32(WPIACNT3)
+#define bfin_write_WPIACNT3(val)       bfin_write32(WPIACNT3, val)
+#define pWPIACNT4                      ((uint32_t volatile *)WPIACNT4)
+#define bfin_read_WPIACNT4()           bfin_read32(WPIACNT4)
+#define bfin_write_WPIACNT4(val)       bfin_write32(WPIACNT4, val)
+#define pWPIACNT5                      ((uint32_t volatile *)WPIACNT5)
+#define bfin_read_WPIACNT5()           bfin_read32(WPIACNT5)
+#define bfin_write_WPIACNT5(val)       bfin_write32(WPIACNT5, val)
+#define pWPDACTL                       ((uint32_t volatile *)WPDACTL)
+#define bfin_read_WPDACTL()            bfin_read32(WPDACTL)
+#define bfin_write_WPDACTL(val)        bfin_write32(WPDACTL, val)
+#define pWPDA0                         ((void * volatile *)WPDA0)
+#define bfin_read_WPDA0()              bfin_readPTR(WPDA0)
+#define bfin_write_WPDA0(val)          bfin_writePTR(WPDA0, val)
+#define pWPDA1                         ((void * volatile *)WPDA1)
+#define bfin_read_WPDA1()              bfin_readPTR(WPDA1)
+#define bfin_write_WPDA1(val)          bfin_writePTR(WPDA1, val)
+#define pWPDACNT0                      ((uint32_t volatile *)WPDACNT0)
+#define bfin_read_WPDACNT0()           bfin_read32(WPDACNT0)
+#define bfin_write_WPDACNT0(val)       bfin_write32(WPDACNT0, val)
+#define pWPDACNT1                      ((uint32_t volatile *)WPDACNT1)
+#define bfin_read_WPDACNT1()           bfin_read32(WPDACNT1)
+#define bfin_write_WPDACNT1(val)       bfin_write32(WPDACNT1, val)
+#define pWPSTAT                        ((uint32_t volatile *)WPSTAT)
+#define bfin_read_WPSTAT()             bfin_read32(WPSTAT)
+#define bfin_write_WPSTAT(val)         bfin_write32(WPSTAT, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
+#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
new file mode 100644
index 0000000..74f5d30
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h
@@ -0,0 +1,31 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_core__
+#define __BFIN_DEF_ADSP_EDN_core__
+
+#define WPIACTL                        0xFFE07000
+#define WPIA0                          0xFFE07040
+#define WPIA1                          0xFFE07044
+#define WPIA2                          0xFFE07048
+#define WPIA3                          0xFFE0704C
+#define WPIA4                          0xFFE07050
+#define WPIA5                          0xFFE07054
+#define WPIACNT0                       0xFFE07080
+#define WPIACNT1                       0xFFE07084
+#define WPIACNT2                       0xFFE07088
+#define WPIACNT3                       0xFFE0708C
+#define WPIACNT4                       0xFFE07090
+#define WPIACNT5                       0xFFE07094
+#define WPDACTL                        0xFFE07100
+#define WPDA0                          0xFFE07140
+#define WPDA1                          0xFFE07144
+#define WPDACNT0                       0xFFE07180
+#define WPDACNT1                       0xFFE07184
+#define WPSTAT                         0xFFE07200
+#define DSPID                          0xFFE05000
+#define DBGSTAT                        0xFFE05008
+
+#endif /* __BFIN_DEF_ADSP_EDN_core__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
new file mode 100644
index 0000000..2e61b5f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
@@ -0,0 +1,1607 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_EDN_extended__
+#define __BFIN_CDEF_ADSP_EDN_extended__
+
+#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
+#define bfin_read_ILAT()               bfin_read32(ILAT)
+#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
+#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
+#define bfin_read_IMASK()              bfin_read32(IMASK)
+#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
+#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
+#define bfin_read_IPEND()              bfin_read32(IPEND)
+#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
+#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
+#define bfin_read_IPRIO()              bfin_read32(IPRIO)
+#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
+#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
+#define bfin_read_TCNTL()              bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
+#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
+#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
+#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
+#define bfin_read_TSCALE()             bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
+#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
+#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
+#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
+#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_FAULT_STATUS            ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */
+#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
+#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((uint32_t volatile *)DCPLB_FAULT_ADDR)
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_read32(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
+#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
+#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
+#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
+#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
+#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
+#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
+#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
+#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
+#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
+#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
+#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
+#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
+#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
+#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
+#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
+#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
+#define bfin_read_EVT0()               bfin_readPTR(EVT0)
+#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
+#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
+#define bfin_read_EVT1()               bfin_readPTR(EVT1)
+#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
+#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
+#define bfin_read_EVT2()               bfin_readPTR(EVT2)
+#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
+#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
+#define bfin_read_EVT3()               bfin_readPTR(EVT3)
+#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
+#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
+#define bfin_read_EVT4()               bfin_readPTR(EVT4)
+#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
+#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
+#define bfin_read_EVT5()               bfin_readPTR(EVT5)
+#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
+#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
+#define bfin_read_EVT6()               bfin_readPTR(EVT6)
+#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
+#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
+#define bfin_read_EVT7()               bfin_readPTR(EVT7)
+#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
+#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
+#define bfin_read_EVT8()               bfin_readPTR(EVT8)
+#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
+#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
+#define bfin_read_EVT9()               bfin_readPTR(EVT9)
+#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
+#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
+#define bfin_read_EVT10()              bfin_readPTR(EVT10)
+#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
+#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
+#define bfin_read_EVT11()              bfin_readPTR(EVT11)
+#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
+#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
+#define bfin_read_EVT12()              bfin_readPTR(EVT12)
+#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
+#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
+#define bfin_read_EVT13()              bfin_readPTR(EVT13)
+#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
+#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
+#define bfin_read_EVT14()              bfin_readPTR(EVT14)
+#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
+#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
+#define bfin_read_EVT15()              bfin_readPTR(EVT15)
+#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_FAULT_STATUS            ((uint32_t volatile *)ICPLB_FAULT_STATUS)
+#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS)
+#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((uint32_t volatile *)ICPLB_FAULT_ADDR)
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pMDMAFLX0_DMACNFG_D            ((uint16_t volatile *)MDMAFLX0_DMACNFG_D)
+#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
+#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
+#define pMDMAFLX0_XCOUNT_D             ((uint16_t volatile *)MDMAFLX0_XCOUNT_D)
+#define bfin_read_MDMAFLX0_XCOUNT_D()  bfin_read16(MDMAFLX0_XCOUNT_D)
+#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
+#define pMDMAFLX0_XMODIFY_D            ((uint16_t volatile *)MDMAFLX0_XMODIFY_D)
+#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
+#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
+#define pMDMAFLX0_YCOUNT_D             ((uint16_t volatile *)MDMAFLX0_YCOUNT_D)
+#define bfin_read_MDMAFLX0_YCOUNT_D()  bfin_read16(MDMAFLX0_YCOUNT_D)
+#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
+#define pMDMAFLX0_YMODIFY_D            ((uint16_t volatile *)MDMAFLX0_YMODIFY_D)
+#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
+#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
+#define pMDMAFLX0_IRQSTAT_D            ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D)
+#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
+#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
+#define pMDMAFLX0_PMAP_D               ((uint16_t volatile *)MDMAFLX0_PMAP_D)
+#define bfin_read_MDMAFLX0_PMAP_D()    bfin_read16(MDMAFLX0_PMAP_D)
+#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
+#define pMDMAFLX0_CURXCOUNT_D          ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D)
+#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
+#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
+#define pMDMAFLX0_CURYCOUNT_D          ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D)
+#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
+#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
+#define pMDMAFLX0_DMACNFG_S            ((uint16_t volatile *)MDMAFLX0_DMACNFG_S)
+#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
+#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
+#define pMDMAFLX0_XCOUNT_S             ((uint16_t volatile *)MDMAFLX0_XCOUNT_S)
+#define bfin_read_MDMAFLX0_XCOUNT_S()  bfin_read16(MDMAFLX0_XCOUNT_S)
+#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
+#define pMDMAFLX0_XMODIFY_S            ((uint16_t volatile *)MDMAFLX0_XMODIFY_S)
+#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
+#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
+#define pMDMAFLX0_YCOUNT_S             ((uint16_t volatile *)MDMAFLX0_YCOUNT_S)
+#define bfin_read_MDMAFLX0_YCOUNT_S()  bfin_read16(MDMAFLX0_YCOUNT_S)
+#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
+#define pMDMAFLX0_YMODIFY_S            ((uint16_t volatile *)MDMAFLX0_YMODIFY_S)
+#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
+#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
+#define pMDMAFLX0_IRQSTAT_S            ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S)
+#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
+#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
+#define pMDMAFLX0_PMAP_S               ((uint16_t volatile *)MDMAFLX0_PMAP_S)
+#define bfin_read_MDMAFLX0_PMAP_S()    bfin_read16(MDMAFLX0_PMAP_S)
+#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
+#define pMDMAFLX0_CURXCOUNT_S          ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S)
+#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
+#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
+#define pMDMAFLX0_CURYCOUNT_S          ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S)
+#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
+#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
+#define pMDMAFLX1_DMACNFG_D            ((uint16_t volatile *)MDMAFLX1_DMACNFG_D)
+#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
+#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
+#define pMDMAFLX1_XCOUNT_D             ((uint16_t volatile *)MDMAFLX1_XCOUNT_D)
+#define bfin_read_MDMAFLX1_XCOUNT_D()  bfin_read16(MDMAFLX1_XCOUNT_D)
+#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
+#define pMDMAFLX1_XMODIFY_D            ((uint16_t volatile *)MDMAFLX1_XMODIFY_D)
+#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
+#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
+#define pMDMAFLX1_YCOUNT_D             ((uint16_t volatile *)MDMAFLX1_YCOUNT_D)
+#define bfin_read_MDMAFLX1_YCOUNT_D()  bfin_read16(MDMAFLX1_YCOUNT_D)
+#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
+#define pMDMAFLX1_YMODIFY_D            ((uint16_t volatile *)MDMAFLX1_YMODIFY_D)
+#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
+#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
+#define pMDMAFLX1_IRQSTAT_D            ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D)
+#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
+#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
+#define pMDMAFLX1_PMAP_D               ((uint16_t volatile *)MDMAFLX1_PMAP_D)
+#define bfin_read_MDMAFLX1_PMAP_D()    bfin_read16(MDMAFLX1_PMAP_D)
+#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
+#define pMDMAFLX1_CURXCOUNT_D          ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D)
+#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
+#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
+#define pMDMAFLX1_CURYCOUNT_D          ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D)
+#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
+#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
+#define pMDMAFLX1_DMACNFG_S            ((uint16_t volatile *)MDMAFLX1_DMACNFG_S)
+#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
+#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
+#define pMDMAFLX1_XCOUNT_S             ((uint16_t volatile *)MDMAFLX1_XCOUNT_S)
+#define bfin_read_MDMAFLX1_XCOUNT_S()  bfin_read16(MDMAFLX1_XCOUNT_S)
+#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
+#define pMDMAFLX1_XMODIFY_S            ((uint16_t volatile *)MDMAFLX1_XMODIFY_S)
+#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
+#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
+#define pMDMAFLX1_YCOUNT_S             ((uint16_t volatile *)MDMAFLX1_YCOUNT_S)
+#define bfin_read_MDMAFLX1_YCOUNT_S()  bfin_read16(MDMAFLX1_YCOUNT_S)
+#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
+#define pMDMAFLX1_YMODIFY_S            ((uint16_t volatile *)MDMAFLX1_YMODIFY_S)
+#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
+#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
+#define pMDMAFLX1_IRQSTAT_S            ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S)
+#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
+#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
+#define pMDMAFLX1_PMAP_S               ((uint16_t volatile *)MDMAFLX1_PMAP_S)
+#define bfin_read_MDMAFLX1_PMAP_S()    bfin_read16(MDMAFLX1_PMAP_S)
+#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
+#define pMDMAFLX1_CURXCOUNT_S          ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S)
+#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
+#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
+#define pMDMAFLX1_CURYCOUNT_S          ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S)
+#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
+#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
+#define pDMAFLX0_DMACNFG               ((uint16_t volatile *)DMAFLX0_DMACNFG)
+#define bfin_read_DMAFLX0_DMACNFG()    bfin_read16(DMAFLX0_DMACNFG)
+#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
+#define pDMAFLX0_XCOUNT                ((uint16_t volatile *)DMAFLX0_XCOUNT)
+#define bfin_read_DMAFLX0_XCOUNT()     bfin_read16(DMAFLX0_XCOUNT)
+#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
+#define pDMAFLX0_XMODIFY               ((uint16_t volatile *)DMAFLX0_XMODIFY)
+#define bfin_read_DMAFLX0_XMODIFY()    bfin_read16(DMAFLX0_XMODIFY)
+#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
+#define pDMAFLX0_YCOUNT                ((uint16_t volatile *)DMAFLX0_YCOUNT)
+#define bfin_read_DMAFLX0_YCOUNT()     bfin_read16(DMAFLX0_YCOUNT)
+#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
+#define pDMAFLX0_YMODIFY               ((uint16_t volatile *)DMAFLX0_YMODIFY)
+#define bfin_read_DMAFLX0_YMODIFY()    bfin_read16(DMAFLX0_YMODIFY)
+#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
+#define pDMAFLX0_IRQSTAT               ((uint16_t volatile *)DMAFLX0_IRQSTAT)
+#define bfin_read_DMAFLX0_IRQSTAT()    bfin_read16(DMAFLX0_IRQSTAT)
+#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
+#define pDMAFLX0_PMAP                  ((uint16_t volatile *)DMAFLX0_PMAP)
+#define bfin_read_DMAFLX0_PMAP()       bfin_read16(DMAFLX0_PMAP)
+#define bfin_write_DMAFLX0_PMAP(val)   bfin_write16(DMAFLX0_PMAP, val)
+#define pDMAFLX0_CURXCOUNT             ((uint16_t volatile *)DMAFLX0_CURXCOUNT)
+#define bfin_read_DMAFLX0_CURXCOUNT()  bfin_read16(DMAFLX0_CURXCOUNT)
+#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
+#define pDMAFLX0_CURYCOUNT             ((uint16_t volatile *)DMAFLX0_CURYCOUNT)
+#define bfin_read_DMAFLX0_CURYCOUNT()  bfin_read16(DMAFLX0_CURYCOUNT)
+#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
+#define pDMAFLX1_DMACNFG               ((uint16_t volatile *)DMAFLX1_DMACNFG)
+#define bfin_read_DMAFLX1_DMACNFG()    bfin_read16(DMAFLX1_DMACNFG)
+#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
+#define pDMAFLX1_XCOUNT                ((uint16_t volatile *)DMAFLX1_XCOUNT)
+#define bfin_read_DMAFLX1_XCOUNT()     bfin_read16(DMAFLX1_XCOUNT)
+#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
+#define pDMAFLX1_XMODIFY               ((uint16_t volatile *)DMAFLX1_XMODIFY)
+#define bfin_read_DMAFLX1_XMODIFY()    bfin_read16(DMAFLX1_XMODIFY)
+#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
+#define pDMAFLX1_YCOUNT                ((uint16_t volatile *)DMAFLX1_YCOUNT)
+#define bfin_read_DMAFLX1_YCOUNT()     bfin_read16(DMAFLX1_YCOUNT)
+#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
+#define pDMAFLX1_YMODIFY               ((uint16_t volatile *)DMAFLX1_YMODIFY)
+#define bfin_read_DMAFLX1_YMODIFY()    bfin_read16(DMAFLX1_YMODIFY)
+#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
+#define pDMAFLX1_IRQSTAT               ((uint16_t volatile *)DMAFLX1_IRQSTAT)
+#define bfin_read_DMAFLX1_IRQSTAT()    bfin_read16(DMAFLX1_IRQSTAT)
+#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
+#define pDMAFLX1_PMAP                  ((uint16_t volatile *)DMAFLX1_PMAP)
+#define bfin_read_DMAFLX1_PMAP()       bfin_read16(DMAFLX1_PMAP)
+#define bfin_write_DMAFLX1_PMAP(val)   bfin_write16(DMAFLX1_PMAP, val)
+#define pDMAFLX1_CURXCOUNT             ((uint16_t volatile *)DMAFLX1_CURXCOUNT)
+#define bfin_read_DMAFLX1_CURXCOUNT()  bfin_read16(DMAFLX1_CURXCOUNT)
+#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
+#define pDMAFLX1_CURYCOUNT             ((uint16_t volatile *)DMAFLX1_CURYCOUNT)
+#define bfin_read_DMAFLX1_CURYCOUNT()  bfin_read16(DMAFLX1_CURYCOUNT)
+#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
+#define pDMAFLX2_DMACNFG               ((uint16_t volatile *)DMAFLX2_DMACNFG)
+#define bfin_read_DMAFLX2_DMACNFG()    bfin_read16(DMAFLX2_DMACNFG)
+#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
+#define pDMAFLX2_XCOUNT                ((uint16_t volatile *)DMAFLX2_XCOUNT)
+#define bfin_read_DMAFLX2_XCOUNT()     bfin_read16(DMAFLX2_XCOUNT)
+#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
+#define pDMAFLX2_XMODIFY               ((uint16_t volatile *)DMAFLX2_XMODIFY)
+#define bfin_read_DMAFLX2_XMODIFY()    bfin_read16(DMAFLX2_XMODIFY)
+#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
+#define pDMAFLX2_YCOUNT                ((uint16_t volatile *)DMAFLX2_YCOUNT)
+#define bfin_read_DMAFLX2_YCOUNT()     bfin_read16(DMAFLX2_YCOUNT)
+#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
+#define pDMAFLX2_YMODIFY               ((uint16_t volatile *)DMAFLX2_YMODIFY)
+#define bfin_read_DMAFLX2_YMODIFY()    bfin_read16(DMAFLX2_YMODIFY)
+#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
+#define pDMAFLX2_IRQSTAT               ((uint16_t volatile *)DMAFLX2_IRQSTAT)
+#define bfin_read_DMAFLX2_IRQSTAT()    bfin_read16(DMAFLX2_IRQSTAT)
+#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
+#define pDMAFLX2_PMAP                  ((uint16_t volatile *)DMAFLX2_PMAP)
+#define bfin_read_DMAFLX2_PMAP()       bfin_read16(DMAFLX2_PMAP)
+#define bfin_write_DMAFLX2_PMAP(val)   bfin_write16(DMAFLX2_PMAP, val)
+#define pDMAFLX2_CURXCOUNT             ((uint16_t volatile *)DMAFLX2_CURXCOUNT)
+#define bfin_read_DMAFLX2_CURXCOUNT()  bfin_read16(DMAFLX2_CURXCOUNT)
+#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
+#define pDMAFLX2_CURYCOUNT             ((uint16_t volatile *)DMAFLX2_CURYCOUNT)
+#define bfin_read_DMAFLX2_CURYCOUNT()  bfin_read16(DMAFLX2_CURYCOUNT)
+#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
+#define pDMAFLX3_DMACNFG               ((uint16_t volatile *)DMAFLX3_DMACNFG)
+#define bfin_read_DMAFLX3_DMACNFG()    bfin_read16(DMAFLX3_DMACNFG)
+#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
+#define pDMAFLX3_XCOUNT                ((uint16_t volatile *)DMAFLX3_XCOUNT)
+#define bfin_read_DMAFLX3_XCOUNT()     bfin_read16(DMAFLX3_XCOUNT)
+#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
+#define pDMAFLX3_XMODIFY               ((uint16_t volatile *)DMAFLX3_XMODIFY)
+#define bfin_read_DMAFLX3_XMODIFY()    bfin_read16(DMAFLX3_XMODIFY)
+#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
+#define pDMAFLX3_YCOUNT                ((uint16_t volatile *)DMAFLX3_YCOUNT)
+#define bfin_read_DMAFLX3_YCOUNT()     bfin_read16(DMAFLX3_YCOUNT)
+#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
+#define pDMAFLX3_YMODIFY               ((uint16_t volatile *)DMAFLX3_YMODIFY)
+#define bfin_read_DMAFLX3_YMODIFY()    bfin_read16(DMAFLX3_YMODIFY)
+#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
+#define pDMAFLX3_IRQSTAT               ((uint16_t volatile *)DMAFLX3_IRQSTAT)
+#define bfin_read_DMAFLX3_IRQSTAT()    bfin_read16(DMAFLX3_IRQSTAT)
+#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
+#define pDMAFLX3_PMAP                  ((uint16_t volatile *)DMAFLX3_PMAP)
+#define bfin_read_DMAFLX3_PMAP()       bfin_read16(DMAFLX3_PMAP)
+#define bfin_write_DMAFLX3_PMAP(val)   bfin_write16(DMAFLX3_PMAP, val)
+#define pDMAFLX3_CURXCOUNT             ((uint16_t volatile *)DMAFLX3_CURXCOUNT)
+#define bfin_read_DMAFLX3_CURXCOUNT()  bfin_read16(DMAFLX3_CURXCOUNT)
+#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
+#define pDMAFLX3_CURYCOUNT             ((uint16_t volatile *)DMAFLX3_CURYCOUNT)
+#define bfin_read_DMAFLX3_CURYCOUNT()  bfin_read16(DMAFLX3_CURYCOUNT)
+#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
+#define pDMAFLX4_DMACNFG               ((uint16_t volatile *)DMAFLX4_DMACNFG)
+#define bfin_read_DMAFLX4_DMACNFG()    bfin_read16(DMAFLX4_DMACNFG)
+#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
+#define pDMAFLX4_XCOUNT                ((uint16_t volatile *)DMAFLX4_XCOUNT)
+#define bfin_read_DMAFLX4_XCOUNT()     bfin_read16(DMAFLX4_XCOUNT)
+#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
+#define pDMAFLX4_XMODIFY               ((uint16_t volatile *)DMAFLX4_XMODIFY)
+#define bfin_read_DMAFLX4_XMODIFY()    bfin_read16(DMAFLX4_XMODIFY)
+#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
+#define pDMAFLX4_YCOUNT                ((uint16_t volatile *)DMAFLX4_YCOUNT)
+#define bfin_read_DMAFLX4_YCOUNT()     bfin_read16(DMAFLX4_YCOUNT)
+#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
+#define pDMAFLX4_YMODIFY               ((uint16_t volatile *)DMAFLX4_YMODIFY)
+#define bfin_read_DMAFLX4_YMODIFY()    bfin_read16(DMAFLX4_YMODIFY)
+#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
+#define pDMAFLX4_IRQSTAT               ((uint16_t volatile *)DMAFLX4_IRQSTAT)
+#define bfin_read_DMAFLX4_IRQSTAT()    bfin_read16(DMAFLX4_IRQSTAT)
+#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
+#define pDMAFLX4_PMAP                  ((uint16_t volatile *)DMAFLX4_PMAP)
+#define bfin_read_DMAFLX4_PMAP()       bfin_read16(DMAFLX4_PMAP)
+#define bfin_write_DMAFLX4_PMAP(val)   bfin_write16(DMAFLX4_PMAP, val)
+#define pDMAFLX4_CURXCOUNT             ((uint16_t volatile *)DMAFLX4_CURXCOUNT)
+#define bfin_read_DMAFLX4_CURXCOUNT()  bfin_read16(DMAFLX4_CURXCOUNT)
+#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
+#define pDMAFLX4_CURYCOUNT             ((uint16_t volatile *)DMAFLX4_CURYCOUNT)
+#define bfin_read_DMAFLX4_CURYCOUNT()  bfin_read16(DMAFLX4_CURYCOUNT)
+#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
+#define pDMAFLX5_DMACNFG               ((uint16_t volatile *)DMAFLX5_DMACNFG)
+#define bfin_read_DMAFLX5_DMACNFG()    bfin_read16(DMAFLX5_DMACNFG)
+#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
+#define pDMAFLX5_XCOUNT                ((uint16_t volatile *)DMAFLX5_XCOUNT)
+#define bfin_read_DMAFLX5_XCOUNT()     bfin_read16(DMAFLX5_XCOUNT)
+#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
+#define pDMAFLX5_XMODIFY               ((uint16_t volatile *)DMAFLX5_XMODIFY)
+#define bfin_read_DMAFLX5_XMODIFY()    bfin_read16(DMAFLX5_XMODIFY)
+#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
+#define pDMAFLX5_YCOUNT                ((uint16_t volatile *)DMAFLX5_YCOUNT)
+#define bfin_read_DMAFLX5_YCOUNT()     bfin_read16(DMAFLX5_YCOUNT)
+#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
+#define pDMAFLX5_YMODIFY               ((uint16_t volatile *)DMAFLX5_YMODIFY)
+#define bfin_read_DMAFLX5_YMODIFY()    bfin_read16(DMAFLX5_YMODIFY)
+#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
+#define pDMAFLX5_IRQSTAT               ((uint16_t volatile *)DMAFLX5_IRQSTAT)
+#define bfin_read_DMAFLX5_IRQSTAT()    bfin_read16(DMAFLX5_IRQSTAT)
+#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
+#define pDMAFLX5_PMAP                  ((uint16_t volatile *)DMAFLX5_PMAP)
+#define bfin_read_DMAFLX5_PMAP()       bfin_read16(DMAFLX5_PMAP)
+#define bfin_write_DMAFLX5_PMAP(val)   bfin_write16(DMAFLX5_PMAP, val)
+#define pDMAFLX5_CURXCOUNT             ((uint16_t volatile *)DMAFLX5_CURXCOUNT)
+#define bfin_read_DMAFLX5_CURXCOUNT()  bfin_read16(DMAFLX5_CURXCOUNT)
+#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
+#define pDMAFLX5_CURYCOUNT             ((uint16_t volatile *)DMAFLX5_CURYCOUNT)
+#define bfin_read_DMAFLX5_CURYCOUNT()  bfin_read16(DMAFLX5_CURYCOUNT)
+#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
+#define pDMAFLX6_DMACNFG               ((uint16_t volatile *)DMAFLX6_DMACNFG)
+#define bfin_read_DMAFLX6_DMACNFG()    bfin_read16(DMAFLX6_DMACNFG)
+#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
+#define pDMAFLX6_XCOUNT                ((uint16_t volatile *)DMAFLX6_XCOUNT)
+#define bfin_read_DMAFLX6_XCOUNT()     bfin_read16(DMAFLX6_XCOUNT)
+#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
+#define pDMAFLX6_XMODIFY               ((uint16_t volatile *)DMAFLX6_XMODIFY)
+#define bfin_read_DMAFLX6_XMODIFY()    bfin_read16(DMAFLX6_XMODIFY)
+#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
+#define pDMAFLX6_YCOUNT                ((uint16_t volatile *)DMAFLX6_YCOUNT)
+#define bfin_read_DMAFLX6_YCOUNT()     bfin_read16(DMAFLX6_YCOUNT)
+#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
+#define pDMAFLX6_YMODIFY               ((uint16_t volatile *)DMAFLX6_YMODIFY)
+#define bfin_read_DMAFLX6_YMODIFY()    bfin_read16(DMAFLX6_YMODIFY)
+#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
+#define pDMAFLX6_IRQSTAT               ((uint16_t volatile *)DMAFLX6_IRQSTAT)
+#define bfin_read_DMAFLX6_IRQSTAT()    bfin_read16(DMAFLX6_IRQSTAT)
+#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
+#define pDMAFLX6_PMAP                  ((uint16_t volatile *)DMAFLX6_PMAP)
+#define bfin_read_DMAFLX6_PMAP()       bfin_read16(DMAFLX6_PMAP)
+#define bfin_write_DMAFLX6_PMAP(val)   bfin_write16(DMAFLX6_PMAP, val)
+#define pDMAFLX6_CURXCOUNT             ((uint16_t volatile *)DMAFLX6_CURXCOUNT)
+#define bfin_read_DMAFLX6_CURXCOUNT()  bfin_read16(DMAFLX6_CURXCOUNT)
+#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
+#define pDMAFLX6_CURYCOUNT             ((uint16_t volatile *)DMAFLX6_CURYCOUNT)
+#define bfin_read_DMAFLX6_CURYCOUNT()  bfin_read16(DMAFLX6_CURYCOUNT)
+#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
+#define pDMAFLX7_DMACNFG               ((uint16_t volatile *)DMAFLX7_DMACNFG)
+#define bfin_read_DMAFLX7_DMACNFG()    bfin_read16(DMAFLX7_DMACNFG)
+#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
+#define pDMAFLX7_XCOUNT                ((uint16_t volatile *)DMAFLX7_XCOUNT)
+#define bfin_read_DMAFLX7_XCOUNT()     bfin_read16(DMAFLX7_XCOUNT)
+#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
+#define pDMAFLX7_XMODIFY               ((uint16_t volatile *)DMAFLX7_XMODIFY)
+#define bfin_read_DMAFLX7_XMODIFY()    bfin_read16(DMAFLX7_XMODIFY)
+#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
+#define pDMAFLX7_YCOUNT                ((uint16_t volatile *)DMAFLX7_YCOUNT)
+#define bfin_read_DMAFLX7_YCOUNT()     bfin_read16(DMAFLX7_YCOUNT)
+#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
+#define pDMAFLX7_YMODIFY               ((uint16_t volatile *)DMAFLX7_YMODIFY)
+#define bfin_read_DMAFLX7_YMODIFY()    bfin_read16(DMAFLX7_YMODIFY)
+#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
+#define pDMAFLX7_IRQSTAT               ((uint16_t volatile *)DMAFLX7_IRQSTAT)
+#define bfin_read_DMAFLX7_IRQSTAT()    bfin_read16(DMAFLX7_IRQSTAT)
+#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
+#define pDMAFLX7_PMAP                  ((uint16_t volatile *)DMAFLX7_PMAP)
+#define bfin_read_DMAFLX7_PMAP()       bfin_read16(DMAFLX7_PMAP)
+#define bfin_write_DMAFLX7_PMAP(val)   bfin_write16(DMAFLX7_PMAP, val)
+#define pDMAFLX7_CURXCOUNT             ((uint16_t volatile *)DMAFLX7_CURXCOUNT)
+#define bfin_read_DMAFLX7_CURXCOUNT()  bfin_read16(DMAFLX7_CURXCOUNT)
+#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
+#define pDMAFLX7_CURYCOUNT             ((uint16_t volatile *)DMAFLX7_CURYCOUNT)
+#define bfin_read_DMAFLX7_CURYCOUNT()  bfin_read16(DMAFLX7_CURYCOUNT)
+#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
+#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG)
+#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
+#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER)
+#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
+#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD)
+#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
+#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH)
+#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
+#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG)
+#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
+#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER)
+#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
+#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD)
+#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
+#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH)
+#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
+#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG)
+#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
+#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER)
+#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
+#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD)
+#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
+#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH)
+#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
+#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE)
+#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
+#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE)
+#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
+#define pTIMER_STATUS                  ((uint16_t volatile *)TIMER_STATUS)
+#define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
+#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
+#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
+#define pSIC_IMASK                     ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
+#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
+#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
+#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
+#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
+#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
+#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
+#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
+#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
+#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
+#define pSIC_ISR                       ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
+#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
+#define pSIC_IWR                       ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
+#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
+#define pUART_THR                      ((uint16_t volatile *)UART_THR) /* Transmit Holding */
+#define bfin_read_UART_THR()           bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
+#define pUART_DLL                      ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */
+#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
+#define pUART_DLH                      ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */
+#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
+#define pUART_IER                      ((uint16_t volatile *)UART_IER)
+#define bfin_read_UART_IER()           bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
+#define pUART_IIR                      ((uint16_t volatile *)UART_IIR)
+#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
+#define pUART_LCR                      ((uint16_t volatile *)UART_LCR)
+#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
+#define pUART_MCR                      ((uint16_t volatile *)UART_MCR)
+#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
+#define pUART_LSR                      ((uint16_t volatile *)UART_LSR)
+#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
+#define pUART_SCR                      ((uint16_t volatile *)UART_SCR)
+#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
+#define pUART_RBR                      ((uint16_t volatile *)UART_RBR) /* Receive Buffer */
+#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
+#define pUART_GCTL                     ((uint16_t volatile *)UART_GCTL)
+#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
+#define pSPT0_TX_CONFIG0               ((uint16_t volatile *)SPT0_TX_CONFIG0)
+#define bfin_read_SPT0_TX_CONFIG0()    bfin_read16(SPT0_TX_CONFIG0)
+#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
+#define pSPT0_TX_CONFIG1               ((uint16_t volatile *)SPT0_TX_CONFIG1)
+#define bfin_read_SPT0_TX_CONFIG1()    bfin_read16(SPT0_TX_CONFIG1)
+#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
+#define pSPT0_RX_CONFIG0               ((uint16_t volatile *)SPT0_RX_CONFIG0)
+#define bfin_read_SPT0_RX_CONFIG0()    bfin_read16(SPT0_RX_CONFIG0)
+#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
+#define pSPT0_RX_CONFIG1               ((uint16_t volatile *)SPT0_RX_CONFIG1)
+#define bfin_read_SPT0_RX_CONFIG1()    bfin_read16(SPT0_RX_CONFIG1)
+#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
+#define pSPT0_TX                       ((uint32_t volatile *)SPT0_TX)
+#define bfin_read_SPT0_TX()            bfin_read32(SPT0_TX)
+#define bfin_write_SPT0_TX(val)        bfin_write32(SPT0_TX, val)
+#define pSPT0_RX                       ((uint32_t volatile *)SPT0_RX)
+#define bfin_read_SPT0_RX()            bfin_read32(SPT0_RX)
+#define bfin_write_SPT0_RX(val)        bfin_write32(SPT0_RX, val)
+#define pSPT0_TSCLKDIV                 ((uint16_t volatile *)SPT0_TSCLKDIV)
+#define bfin_read_SPT0_TSCLKDIV()      bfin_read16(SPT0_TSCLKDIV)
+#define bfin_write_SPT0_TSCLKDIV(val)  bfin_write16(SPT0_TSCLKDIV, val)
+#define pSPT0_RSCLKDIV                 ((uint16_t volatile *)SPT0_RSCLKDIV)
+#define bfin_read_SPT0_RSCLKDIV()      bfin_read16(SPT0_RSCLKDIV)
+#define bfin_write_SPT0_RSCLKDIV(val)  bfin_write16(SPT0_RSCLKDIV, val)
+#define pSPT0_TFSDIV                   ((uint16_t volatile *)SPT0_TFSDIV)
+#define bfin_read_SPT0_TFSDIV()        bfin_read16(SPT0_TFSDIV)
+#define bfin_write_SPT0_TFSDIV(val)    bfin_write16(SPT0_TFSDIV, val)
+#define pSPT0_RFSDIV                   ((uint16_t volatile *)SPT0_RFSDIV)
+#define bfin_read_SPT0_RFSDIV()        bfin_read16(SPT0_RFSDIV)
+#define bfin_write_SPT0_RFSDIV(val)    bfin_write16(SPT0_RFSDIV, val)
+#define pSPT0_STAT                     ((uint16_t volatile *)SPT0_STAT)
+#define bfin_read_SPT0_STAT()          bfin_read16(SPT0_STAT)
+#define bfin_write_SPT0_STAT(val)      bfin_write16(SPT0_STAT, val)
+#define pSPT0_MTCS0                    ((uint32_t volatile *)SPT0_MTCS0)
+#define bfin_read_SPT0_MTCS0()         bfin_read32(SPT0_MTCS0)
+#define bfin_write_SPT0_MTCS0(val)     bfin_write32(SPT0_MTCS0, val)
+#define pSPT0_MTCS1                    ((uint32_t volatile *)SPT0_MTCS1)
+#define bfin_read_SPT0_MTCS1()         bfin_read32(SPT0_MTCS1)
+#define bfin_write_SPT0_MTCS1(val)     bfin_write32(SPT0_MTCS1, val)
+#define pSPT0_MTCS2                    ((uint32_t volatile *)SPT0_MTCS2)
+#define bfin_read_SPT0_MTCS2()         bfin_read32(SPT0_MTCS2)
+#define bfin_write_SPT0_MTCS2(val)     bfin_write32(SPT0_MTCS2, val)
+#define pSPT0_MTCS3                    ((uint32_t volatile *)SPT0_MTCS3)
+#define bfin_read_SPT0_MTCS3()         bfin_read32(SPT0_MTCS3)
+#define bfin_write_SPT0_MTCS3(val)     bfin_write32(SPT0_MTCS3, val)
+#define pSPT0_MRCS0                    ((uint32_t volatile *)SPT0_MRCS0)
+#define bfin_read_SPT0_MRCS0()         bfin_read32(SPT0_MRCS0)
+#define bfin_write_SPT0_MRCS0(val)     bfin_write32(SPT0_MRCS0, val)
+#define pSPT0_MRCS1                    ((uint32_t volatile *)SPT0_MRCS1)
+#define bfin_read_SPT0_MRCS1()         bfin_read32(SPT0_MRCS1)
+#define bfin_write_SPT0_MRCS1(val)     bfin_write32(SPT0_MRCS1, val)
+#define pSPT0_MRCS2                    ((uint32_t volatile *)SPT0_MRCS2)
+#define bfin_read_SPT0_MRCS2()         bfin_read32(SPT0_MRCS2)
+#define bfin_write_SPT0_MRCS2(val)     bfin_write32(SPT0_MRCS2, val)
+#define pSPT0_MRCS3                    ((uint32_t volatile *)SPT0_MRCS3)
+#define bfin_read_SPT0_MRCS3()         bfin_read32(SPT0_MRCS3)
+#define bfin_write_SPT0_MRCS3(val)     bfin_write32(SPT0_MRCS3, val)
+#define pSPT0_MCMC1                    ((uint16_t volatile *)SPT0_MCMC1)
+#define bfin_read_SPT0_MCMC1()         bfin_read16(SPT0_MCMC1)
+#define bfin_write_SPT0_MCMC1(val)     bfin_write16(SPT0_MCMC1, val)
+#define pSPT0_MCMC2                    ((uint16_t volatile *)SPT0_MCMC2)
+#define bfin_read_SPT0_MCMC2()         bfin_read16(SPT0_MCMC2)
+#define bfin_write_SPT0_MCMC2(val)     bfin_write16(SPT0_MCMC2, val)
+#define pSPT0_CHNL                     ((uint16_t volatile *)SPT0_CHNL)
+#define bfin_read_SPT0_CHNL()          bfin_read16(SPT0_CHNL)
+#define bfin_write_SPT0_CHNL(val)      bfin_write16(SPT0_CHNL, val)
+#define pSPT1_TX_CONFIG0               ((uint16_t volatile *)SPT1_TX_CONFIG0)
+#define bfin_read_SPT1_TX_CONFIG0()    bfin_read16(SPT1_TX_CONFIG0)
+#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
+#define pSPT1_TX_CONFIG1               ((uint16_t volatile *)SPT1_TX_CONFIG1)
+#define bfin_read_SPT1_TX_CONFIG1()    bfin_read16(SPT1_TX_CONFIG1)
+#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
+#define pSPT1_RX_CONFIG0               ((uint16_t volatile *)SPT1_RX_CONFIG0)
+#define bfin_read_SPT1_RX_CONFIG0()    bfin_read16(SPT1_RX_CONFIG0)
+#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
+#define pSPT1_RX_CONFIG1               ((uint16_t volatile *)SPT1_RX_CONFIG1)
+#define bfin_read_SPT1_RX_CONFIG1()    bfin_read16(SPT1_RX_CONFIG1)
+#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
+#define pSPT1_TX                       ((uint16_t volatile *)SPT1_TX)
+#define bfin_read_SPT1_TX()            bfin_read16(SPT1_TX)
+#define bfin_write_SPT1_TX(val)        bfin_write16(SPT1_TX, val)
+#define pSPT1_RX                       ((uint16_t volatile *)SPT1_RX)
+#define bfin_read_SPT1_RX()            bfin_read16(SPT1_RX)
+#define bfin_write_SPT1_RX(val)        bfin_write16(SPT1_RX, val)
+#define pSPT1_TSCLKDIV                 ((uint16_t volatile *)SPT1_TSCLKDIV)
+#define bfin_read_SPT1_TSCLKDIV()      bfin_read16(SPT1_TSCLKDIV)
+#define bfin_write_SPT1_TSCLKDIV(val)  bfin_write16(SPT1_TSCLKDIV, val)
+#define pSPT1_RSCLKDIV                 ((uint16_t volatile *)SPT1_RSCLKDIV)
+#define bfin_read_SPT1_RSCLKDIV()      bfin_read16(SPT1_RSCLKDIV)
+#define bfin_write_SPT1_RSCLKDIV(val)  bfin_write16(SPT1_RSCLKDIV, val)
+#define pSPT1_TFSDIV                   ((uint16_t volatile *)SPT1_TFSDIV)
+#define bfin_read_SPT1_TFSDIV()        bfin_read16(SPT1_TFSDIV)
+#define bfin_write_SPT1_TFSDIV(val)    bfin_write16(SPT1_TFSDIV, val)
+#define pSPT1_RFSDIV                   ((uint16_t volatile *)SPT1_RFSDIV)
+#define bfin_read_SPT1_RFSDIV()        bfin_read16(SPT1_RFSDIV)
+#define bfin_write_SPT1_RFSDIV(val)    bfin_write16(SPT1_RFSDIV, val)
+#define pSPT1_STAT                     ((uint16_t volatile *)SPT1_STAT)
+#define bfin_read_SPT1_STAT()          bfin_read16(SPT1_STAT)
+#define bfin_write_SPT1_STAT(val)      bfin_write16(SPT1_STAT, val)
+#define pSPT1_MTCS0                    ((uint32_t volatile *)SPT1_MTCS0)
+#define bfin_read_SPT1_MTCS0()         bfin_read32(SPT1_MTCS0)
+#define bfin_write_SPT1_MTCS0(val)     bfin_write32(SPT1_MTCS0, val)
+#define pSPT1_MTCS1                    ((uint32_t volatile *)SPT1_MTCS1)
+#define bfin_read_SPT1_MTCS1()         bfin_read32(SPT1_MTCS1)
+#define bfin_write_SPT1_MTCS1(val)     bfin_write32(SPT1_MTCS1, val)
+#define pSPT1_MTCS2                    ((uint32_t volatile *)SPT1_MTCS2)
+#define bfin_read_SPT1_MTCS2()         bfin_read32(SPT1_MTCS2)
+#define bfin_write_SPT1_MTCS2(val)     bfin_write32(SPT1_MTCS2, val)
+#define pSPT1_MTCS3                    ((uint32_t volatile *)SPT1_MTCS3)
+#define bfin_read_SPT1_MTCS3()         bfin_read32(SPT1_MTCS3)
+#define bfin_write_SPT1_MTCS3(val)     bfin_write32(SPT1_MTCS3, val)
+#define pSPT1_MRCS0                    ((uint32_t volatile *)SPT1_MRCS0)
+#define bfin_read_SPT1_MRCS0()         bfin_read32(SPT1_MRCS0)
+#define bfin_write_SPT1_MRCS0(val)     bfin_write32(SPT1_MRCS0, val)
+#define pSPT1_MRCS1                    ((uint32_t volatile *)SPT1_MRCS1)
+#define bfin_read_SPT1_MRCS1()         bfin_read32(SPT1_MRCS1)
+#define bfin_write_SPT1_MRCS1(val)     bfin_write32(SPT1_MRCS1, val)
+#define pSPT1_MRCS2                    ((uint32_t volatile *)SPT1_MRCS2)
+#define bfin_read_SPT1_MRCS2()         bfin_read32(SPT1_MRCS2)
+#define bfin_write_SPT1_MRCS2(val)     bfin_write32(SPT1_MRCS2, val)
+#define pSPT1_MRCS3                    ((uint32_t volatile *)SPT1_MRCS3)
+#define bfin_read_SPT1_MRCS3()         bfin_read32(SPT1_MRCS3)
+#define bfin_write_SPT1_MRCS3(val)     bfin_write32(SPT1_MRCS3, val)
+#define pSPT1_MCMC1                    ((uint16_t volatile *)SPT1_MCMC1)
+#define bfin_read_SPT1_MCMC1()         bfin_read16(SPT1_MCMC1)
+#define bfin_write_SPT1_MCMC1(val)     bfin_write16(SPT1_MCMC1, val)
+#define pSPT1_MCMC2                    ((uint16_t volatile *)SPT1_MCMC2)
+#define bfin_read_SPT1_MCMC2()         bfin_read16(SPT1_MCMC2)
+#define bfin_write_SPT1_MCMC2(val)     bfin_write16(SPT1_MCMC2, val)
+#define pSPT1_CHNL                     ((uint16_t volatile *)SPT1_CHNL)
+#define bfin_read_SPT1_CHNL()          bfin_read16(SPT1_CHNL)
+#define bfin_write_SPT1_CHNL(val)      bfin_write16(SPT1_CHNL, val)
+#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL)
+#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
+#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS)
+#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
+#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY)
+#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
+#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT)
+#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
+#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME)
+#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
+#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */
+#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
+#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */
+#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
+#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */
+#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
+#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
+#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */
+#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
+#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
+#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
+#define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
+#define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
+#define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
+#define pCHIPID                        ((uint32_t volatile *)CHIPID)
+#define bfin_read_CHIPID()             bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
+#define bfin_read_TBUF()               bfin_readPTR(TBUF)
+#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
+#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
+#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
+#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
+#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
+#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
+#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT)
+#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
+#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL)
+#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
+#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT)
+#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
+#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT)
+#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
+#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM)
+#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
+#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN)
+#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
+#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL)
+#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
+#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG)
+#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
+#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT)
+#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
+#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR)
+#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
+#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR)
+#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
+#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD)
+#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
+#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW)
+#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
+#define pFIO_FLAG_D                    ((uint16_t volatile *)FIO_FLAG_D)
+#define bfin_read_FIO_FLAG_D()         bfin_read16(FIO_FLAG_D)
+#define bfin_write_FIO_FLAG_D(val)     bfin_write16(FIO_FLAG_D, val)
+#define pFIO_FLAG_C                    ((uint16_t volatile *)FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_C()         bfin_read16(FIO_FLAG_C)
+#define bfin_write_FIO_FLAG_C(val)     bfin_write16(FIO_FLAG_C, val)
+#define pFIO_FLAG_S                    ((uint16_t volatile *)FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_S()         bfin_read16(FIO_FLAG_S)
+#define bfin_write_FIO_FLAG_S(val)     bfin_write16(FIO_FLAG_S, val)
+#define pFIO_FLAG_T                    ((uint16_t volatile *)FIO_FLAG_T)
+#define bfin_read_FIO_FLAG_T()         bfin_read16(FIO_FLAG_T)
+#define bfin_write_FIO_FLAG_T(val)     bfin_write16(FIO_FLAG_T, val)
+#define pFIO_MASKA_D                   ((uint16_t volatile *)FIO_MASKA_D)
+#define bfin_read_FIO_MASKA_D()        bfin_read16(FIO_MASKA_D)
+#define bfin_write_FIO_MASKA_D(val)    bfin_write16(FIO_MASKA_D, val)
+#define pFIO_MASKA_C                   ((uint16_t volatile *)FIO_MASKA_C)
+#define bfin_read_FIO_MASKA_C()        bfin_read16(FIO_MASKA_C)
+#define bfin_write_FIO_MASKA_C(val)    bfin_write16(FIO_MASKA_C, val)
+#define pFIO_MASKA_S                   ((uint16_t volatile *)FIO_MASKA_S)
+#define bfin_read_FIO_MASKA_S()        bfin_read16(FIO_MASKA_S)
+#define bfin_write_FIO_MASKA_S(val)    bfin_write16(FIO_MASKA_S, val)
+#define pFIO_MASKA_T                   ((uint16_t volatile *)FIO_MASKA_T)
+#define bfin_read_FIO_MASKA_T()        bfin_read16(FIO_MASKA_T)
+#define bfin_write_FIO_MASKA_T(val)    bfin_write16(FIO_MASKA_T, val)
+#define pFIO_MASKB_D                   ((uint16_t volatile *)FIO_MASKB_D)
+#define bfin_read_FIO_MASKB_D()        bfin_read16(FIO_MASKB_D)
+#define bfin_write_FIO_MASKB_D(val)    bfin_write16(FIO_MASKB_D, val)
+#define pFIO_MASKB_C                   ((uint16_t volatile *)FIO_MASKB_C)
+#define bfin_read_FIO_MASKB_C()        bfin_read16(FIO_MASKB_C)
+#define bfin_write_FIO_MASKB_C(val)    bfin_write16(FIO_MASKB_C, val)
+#define pFIO_MASKB_S                   ((uint16_t volatile *)FIO_MASKB_S)
+#define bfin_read_FIO_MASKB_S()        bfin_read16(FIO_MASKB_S)
+#define bfin_write_FIO_MASKB_S(val)    bfin_write16(FIO_MASKB_S, val)
+#define pFIO_MASKB_T                   ((uint16_t volatile *)FIO_MASKB_T)
+#define bfin_read_FIO_MASKB_T()        bfin_read16(FIO_MASKB_T)
+#define bfin_write_FIO_MASKB_T(val)    bfin_write16(FIO_MASKB_T, val)
+#define pFIO_DIR                       ((uint16_t volatile *)FIO_DIR)
+#define bfin_read_FIO_DIR()            bfin_read16(FIO_DIR)
+#define bfin_write_FIO_DIR(val)        bfin_write16(FIO_DIR, val)
+#define pFIO_POLAR                     ((uint16_t volatile *)FIO_POLAR)
+#define bfin_read_FIO_POLAR()          bfin_read16(FIO_POLAR)
+#define bfin_write_FIO_POLAR(val)      bfin_write16(FIO_POLAR, val)
+#define pFIO_EDGE                      ((uint16_t volatile *)FIO_EDGE)
+#define bfin_read_FIO_EDGE()           bfin_read16(FIO_EDGE)
+#define bfin_write_FIO_EDGE(val)       bfin_write16(FIO_EDGE, val)
+#define pFIO_BOTH                      ((uint16_t volatile *)FIO_BOTH)
+#define bfin_read_FIO_BOTH()           bfin_read16(FIO_BOTH)
+#define bfin_write_FIO_BOTH(val)       bfin_write16(FIO_BOTH, val)
+#define pFIO_INEN                      ((uint16_t volatile *)FIO_INEN)
+#define bfin_read_FIO_INEN()           bfin_read16(FIO_INEN)
+#define bfin_write_FIO_INEN(val)       bfin_write16(FIO_INEN, val)
+#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
+#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
+#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
+#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
+#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
+#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
+#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
+#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
+#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
+#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
+#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
+#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
+#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
+#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
+#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
+#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
+#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
+#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
+#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
+#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
+#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
+#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
+#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
+#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
+#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
+#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
+#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
+#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
+#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
+#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
+#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
+#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
+#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
+#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
+#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
+#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
+#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
+#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
+#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
+#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
+#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
+#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
+#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
+#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
+#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
+#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
+#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
+#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
+#define pDMA0_NEXT_DESC_PTR            ((uint32_t volatile *)DMA0_NEXT_DESC_PTR)
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define pDMA0_START_ADDR               ((uint32_t volatile *)DMA0_START_ADDR)
+#define bfin_read_DMA0_START_ADDR()    bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
+#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
+#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
+#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT)
+#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
+#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY)
+#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
+#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT)
+#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
+#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY)
+#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
+#define pDMA0_CURR_DESC_PTR            ((uint32_t volatile *)DMA0_CURR_DESC_PTR)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define pDMA0_CURR_ADDR                ((uint32_t volatile *)DMA0_CURR_ADDR)
+#define bfin_read_DMA0_CURR_ADDR()     bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
+#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS)
+#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
+#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP)
+#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
+#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT)
+#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
+#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT)
+#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define pDMA1_NEXT_DESC_PTR            ((uint32_t volatile *)DMA1_NEXT_DESC_PTR)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define pDMA1_START_ADDR               ((uint32_t volatile *)DMA1_START_ADDR)
+#define bfin_read_DMA1_START_ADDR()    bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
+#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
+#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
+#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT)
+#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
+#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY)
+#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
+#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT)
+#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
+#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY)
+#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
+#define pDMA1_CURR_DESC_PTR            ((uint32_t volatile *)DMA1_CURR_DESC_PTR)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define pDMA1_CURR_ADDR                ((uint32_t volatile *)DMA1_CURR_ADDR)
+#define bfin_read_DMA1_CURR_ADDR()     bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
+#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS)
+#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
+#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP)
+#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
+#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT)
+#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
+#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT)
+#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define pDMA2_NEXT_DESC_PTR            ((uint32_t volatile *)DMA2_NEXT_DESC_PTR)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define pDMA2_START_ADDR               ((uint32_t volatile *)DMA2_START_ADDR)
+#define bfin_read_DMA2_START_ADDR()    bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
+#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
+#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
+#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT)
+#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
+#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY)
+#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
+#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT)
+#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
+#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY)
+#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
+#define pDMA2_CURR_DESC_PTR            ((uint32_t volatile *)DMA2_CURR_DESC_PTR)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define pDMA2_CURR_ADDR                ((uint32_t volatile *)DMA2_CURR_ADDR)
+#define bfin_read_DMA2_CURR_ADDR()     bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
+#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS)
+#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
+#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP)
+#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
+#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT)
+#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
+#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT)
+#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define pDMA3_NEXT_DESC_PTR            ((uint32_t volatile *)DMA3_NEXT_DESC_PTR)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define pDMA3_START_ADDR               ((uint32_t volatile *)DMA3_START_ADDR)
+#define bfin_read_DMA3_START_ADDR()    bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
+#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
+#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
+#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT)
+#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
+#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY)
+#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
+#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT)
+#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
+#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY)
+#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
+#define pDMA3_CURR_DESC_PTR            ((uint32_t volatile *)DMA3_CURR_DESC_PTR)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define pDMA3_CURR_ADDR                ((uint32_t volatile *)DMA3_CURR_ADDR)
+#define bfin_read_DMA3_CURR_ADDR()     bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
+#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS)
+#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
+#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP)
+#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
+#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT)
+#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
+#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT)
+#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define pDMA4_NEXT_DESC_PTR            ((uint32_t volatile *)DMA4_NEXT_DESC_PTR)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define pDMA4_START_ADDR               ((uint32_t volatile *)DMA4_START_ADDR)
+#define bfin_read_DMA4_START_ADDR()    bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
+#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
+#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
+#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT)
+#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
+#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY)
+#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
+#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT)
+#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
+#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY)
+#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
+#define pDMA4_CURR_DESC_PTR            ((uint32_t volatile *)DMA4_CURR_DESC_PTR)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define pDMA4_CURR_ADDR                ((uint32_t volatile *)DMA4_CURR_ADDR)
+#define bfin_read_DMA4_CURR_ADDR()     bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
+#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS)
+#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
+#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP)
+#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
+#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT)
+#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
+#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT)
+#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define pDMA5_NEXT_DESC_PTR            ((uint32_t volatile *)DMA5_NEXT_DESC_PTR)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define pDMA5_START_ADDR               ((uint32_t volatile *)DMA5_START_ADDR)
+#define bfin_read_DMA5_START_ADDR()    bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
+#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
+#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
+#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT)
+#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
+#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY)
+#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
+#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT)
+#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
+#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY)
+#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
+#define pDMA5_CURR_DESC_PTR            ((uint32_t volatile *)DMA5_CURR_DESC_PTR)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define pDMA5_CURR_ADDR                ((uint32_t volatile *)DMA5_CURR_ADDR)
+#define bfin_read_DMA5_CURR_ADDR()     bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
+#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS)
+#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
+#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP)
+#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
+#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT)
+#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
+#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT)
+#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define pDMA6_START_ADDR               ((uint32_t volatile *)DMA6_START_ADDR)
+#define bfin_read_DMA6_START_ADDR()    bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
+#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
+#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
+#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT)
+#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
+#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY)
+#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
+#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT)
+#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
+#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY)
+#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
+#define pDMA6_CURR_DESC_PTR            ((uint32_t volatile *)DMA6_CURR_DESC_PTR)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define pDMA6_CURR_ADDR                ((uint32_t volatile *)DMA6_CURR_ADDR)
+#define bfin_read_DMA6_CURR_ADDR()     bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
+#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS)
+#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
+#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP)
+#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
+#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT)
+#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
+#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT)
+#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define pDMA7_NEXT_DESC_PTR            ((uint32_t volatile *)DMA7_NEXT_DESC_PTR)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define pDMA7_START_ADDR               ((uint32_t volatile *)DMA7_START_ADDR)
+#define bfin_read_DMA7_START_ADDR()    bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
+#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
+#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
+#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT)
+#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
+#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY)
+#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
+#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT)
+#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
+#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY)
+#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
+#define pDMA7_CURR_DESC_PTR            ((uint32_t volatile *)DMA7_CURR_DESC_PTR)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define pDMA7_CURR_ADDR                ((uint32_t volatile *)DMA7_CURR_ADDR)
+#define bfin_read_DMA7_CURR_ADDR()     bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
+#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS)
+#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
+#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP)
+#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
+#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT)
+#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
+#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT)
+#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define pMDMA_D0_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define pMDMA_D0_START_ADDR            ((uint32_t volatile *)MDMA_D0_START_ADDR)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
+#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG)
+#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT)
+#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY)
+#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT)
+#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY)
+#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define pMDMA_D0_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define pMDMA_D0_CURR_ADDR             ((uint32_t volatile *)MDMA_D0_CURR_ADDR)
+#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define pMDMA_S0_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define pMDMA_S0_START_ADDR            ((uint32_t volatile *)MDMA_S0_START_ADDR)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
+#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG)
+#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT)
+#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY)
+#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT)
+#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY)
+#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define pMDMA_S0_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define pMDMA_S0_CURR_ADDR             ((uint32_t volatile *)MDMA_S0_CURR_ADDR)
+#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define pMDMA_D1_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define pMDMA_D1_START_ADDR            ((uint32_t volatile *)MDMA_D1_START_ADDR)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
+#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
+#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT)
+#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY)
+#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT)
+#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY)
+#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define pMDMA_D1_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define pMDMA_D1_CURR_ADDR             ((uint32_t volatile *)MDMA_D1_CURR_ADDR)
+#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define pMDMA_S1_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define pMDMA_S1_START_ADDR            ((uint32_t volatile *)MDMA_S1_START_ADDR)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
+#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG)
+#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT)
+#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY)
+#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT)
+#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY)
+#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define pMDMA_S1_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define pMDMA_S1_CURR_ADDR             ((uint32_t volatile *)MDMA_S1_CURR_ADDR)
+#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL)
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0)
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1)
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL)
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL)
+#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC)
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT)
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
+#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
+#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
+#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
+
+#endif /* __BFIN_CDEF_ADSP_EDN_extended__ */
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h
new file mode 100644
index 0000000..24b56b3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h
@@ -0,0 +1,543 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_EDN_extended__
+#define __BFIN_DEF_ADSP_EDN_extended__
+
+#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
+#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
+#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
+#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
+#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
+#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
+#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
+#define DCPLB_FAULT_STATUS             0xFFE00008 /* L1 Data Memory Controller Register */
+#define DCPLB_FAULT_ADDR               0xFFE0000C
+#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
+#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
+#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_FAULT_STATUS             0xFFE01008
+#define ICPLB_FAULT_ADDR               0xFFE0100C
+#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
+#define MDMAFLX0_DMACNFG_D             0xFFC00E08
+#define MDMAFLX0_XCOUNT_D              0xFFC00E10
+#define MDMAFLX0_XMODIFY_D             0xFFC00E14
+#define MDMAFLX0_YCOUNT_D              0xFFC00E18
+#define MDMAFLX0_YMODIFY_D             0xFFC00E1C
+#define MDMAFLX0_IRQSTAT_D             0xFFC00E28
+#define MDMAFLX0_PMAP_D                0xFFC00E2C
+#define MDMAFLX0_CURXCOUNT_D           0xFFC00E30
+#define MDMAFLX0_CURYCOUNT_D           0xFFC00E38
+#define MDMAFLX0_DMACNFG_S             0xFFC00E48
+#define MDMAFLX0_XCOUNT_S              0xFFC00E50
+#define MDMAFLX0_XMODIFY_S             0xFFC00E54
+#define MDMAFLX0_YCOUNT_S              0xFFC00E58
+#define MDMAFLX0_YMODIFY_S             0xFFC00E5C
+#define MDMAFLX0_IRQSTAT_S             0xFFC00E68
+#define MDMAFLX0_PMAP_S                0xFFC00E6C
+#define MDMAFLX0_CURXCOUNT_S           0xFFC00E70
+#define MDMAFLX0_CURYCOUNT_S           0xFFC00E78
+#define MDMAFLX1_DMACNFG_D             0xFFC00E88
+#define MDMAFLX1_XCOUNT_D              0xFFC00E90
+#define MDMAFLX1_XMODIFY_D             0xFFC00E94
+#define MDMAFLX1_YCOUNT_D              0xFFC00E98
+#define MDMAFLX1_YMODIFY_D             0xFFC00E9C
+#define MDMAFLX1_IRQSTAT_D             0xFFC00EA8
+#define MDMAFLX1_PMAP_D                0xFFC00EAC
+#define MDMAFLX1_CURXCOUNT_D           0xFFC00EB0
+#define MDMAFLX1_CURYCOUNT_D           0xFFC00EB8
+#define MDMAFLX1_DMACNFG_S             0xFFC00EC8
+#define MDMAFLX1_XCOUNT_S              0xFFC00ED0
+#define MDMAFLX1_XMODIFY_S             0xFFC00ED4
+#define MDMAFLX1_YCOUNT_S              0xFFC00ED8
+#define MDMAFLX1_YMODIFY_S             0xFFC00EDC
+#define MDMAFLX1_IRQSTAT_S             0xFFC00EE8
+#define MDMAFLX1_PMAP_S                0xFFC00EEC
+#define MDMAFLX1_CURXCOUNT_S           0xFFC00EF0
+#define MDMAFLX1_CURYCOUNT_S           0xFFC00EF8
+#define DMAFLX0_DMACNFG                0xFFC00C08
+#define DMAFLX0_XCOUNT                 0xFFC00C10
+#define DMAFLX0_XMODIFY                0xFFC00C14
+#define DMAFLX0_YCOUNT                 0xFFC00C18
+#define DMAFLX0_YMODIFY                0xFFC00C1C
+#define DMAFLX0_IRQSTAT                0xFFC00C28
+#define DMAFLX0_PMAP                   0xFFC00C2C
+#define DMAFLX0_CURXCOUNT              0xFFC00C30
+#define DMAFLX0_CURYCOUNT              0xFFC00C38
+#define DMAFLX1_DMACNFG                0xFFC00C48
+#define DMAFLX1_XCOUNT                 0xFFC00C50
+#define DMAFLX1_XMODIFY                0xFFC00C54
+#define DMAFLX1_YCOUNT                 0xFFC00C58
+#define DMAFLX1_YMODIFY                0xFFC00C5C
+#define DMAFLX1_IRQSTAT                0xFFC00C68
+#define DMAFLX1_PMAP                   0xFFC00C6C
+#define DMAFLX1_CURXCOUNT              0xFFC00C70
+#define DMAFLX1_CURYCOUNT              0xFFC00C78
+#define DMAFLX2_DMACNFG                0xFFC00C88
+#define DMAFLX2_XCOUNT                 0xFFC00C90
+#define DMAFLX2_XMODIFY                0xFFC00C94
+#define DMAFLX2_YCOUNT                 0xFFC00C98
+#define DMAFLX2_YMODIFY                0xFFC00C9C
+#define DMAFLX2_IRQSTAT                0xFFC00CA8
+#define DMAFLX2_PMAP                   0xFFC00CAC
+#define DMAFLX2_CURXCOUNT              0xFFC00CB0
+#define DMAFLX2_CURYCOUNT              0xFFC00CB8
+#define DMAFLX3_DMACNFG                0xFFC00CC8
+#define DMAFLX3_XCOUNT                 0xFFC00CD0
+#define DMAFLX3_XMODIFY                0xFFC00CD4
+#define DMAFLX3_YCOUNT                 0xFFC00CD8
+#define DMAFLX3_YMODIFY                0xFFC00CDC
+#define DMAFLX3_IRQSTAT                0xFFC00CE8
+#define DMAFLX3_PMAP                   0xFFC00CEC
+#define DMAFLX3_CURXCOUNT              0xFFC00CF0
+#define DMAFLX3_CURYCOUNT              0xFFC00CF8
+#define DMAFLX4_DMACNFG                0xFFC00D08
+#define DMAFLX4_XCOUNT                 0xFFC00D10
+#define DMAFLX4_XMODIFY                0xFFC00D14
+#define DMAFLX4_YCOUNT                 0xFFC00D18
+#define DMAFLX4_YMODIFY                0xFFC00D1C
+#define DMAFLX4_IRQSTAT                0xFFC00D28
+#define DMAFLX4_PMAP                   0xFFC00D2C
+#define DMAFLX4_CURXCOUNT              0xFFC00D30
+#define DMAFLX4_CURYCOUNT              0xFFC00D38
+#define DMAFLX5_DMACNFG                0xFFC00D48
+#define DMAFLX5_XCOUNT                 0xFFC00D50
+#define DMAFLX5_XMODIFY                0xFFC00D54
+#define DMAFLX5_YCOUNT                 0xFFC00D58
+#define DMAFLX5_YMODIFY                0xFFC00D5C
+#define DMAFLX5_IRQSTAT                0xFFC00D68
+#define DMAFLX5_PMAP                   0xFFC00D6C
+#define DMAFLX5_CURXCOUNT              0xFFC00D70
+#define DMAFLX5_CURYCOUNT              0xFFC00D78
+#define DMAFLX6_DMACNFG                0xFFC00D88
+#define DMAFLX6_XCOUNT                 0xFFC00D90
+#define DMAFLX6_XMODIFY                0xFFC00D94
+#define DMAFLX6_YCOUNT                 0xFFC00D98
+#define DMAFLX6_YMODIFY                0xFFC00D9C
+#define DMAFLX6_IRQSTAT                0xFFC00DA8
+#define DMAFLX6_PMAP                   0xFFC00DAC
+#define DMAFLX6_CURXCOUNT              0xFFC00DB0
+#define DMAFLX6_CURYCOUNT              0xFFC00DB8
+#define DMAFLX7_DMACNFG                0xFFC00DC8
+#define DMAFLX7_XCOUNT                 0xFFC00DD0
+#define DMAFLX7_XMODIFY                0xFFC00DD4
+#define DMAFLX7_YCOUNT                 0xFFC00DD8
+#define DMAFLX7_YMODIFY                0xFFC00DDC
+#define DMAFLX7_IRQSTAT                0xFFC00DE8
+#define DMAFLX7_PMAP                   0xFFC00DEC
+#define DMAFLX7_CURXCOUNT              0xFFC00DF0
+#define DMAFLX7_CURYCOUNT              0xFFC00DF8
+#define TIMER0_CONFIG                  0xFFC00600
+#define TIMER0_COUNTER                 0xFFC00604
+#define TIMER0_PERIOD                  0xFFC00608
+#define TIMER0_WIDTH                   0xFFC0060C
+#define TIMER1_CONFIG                  0xFFC00610
+#define TIMER1_COUNTER                 0xFFC00614
+#define TIMER1_PERIOD                  0xFFC00618
+#define TIMER1_WIDTH                   0xFFC0061C
+#define TIMER2_CONFIG                  0xFFC00620
+#define TIMER2_COUNTER                 0xFFC00624
+#define TIMER2_PERIOD                  0xFFC00628
+#define TIMER2_WIDTH                   0xFFC0062C
+#define TIMER_ENABLE                   0xFFC00640
+#define TIMER_DISABLE                  0xFFC00644
+#define TIMER_STATUS                   0xFFC00648
+#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
+#define UART_THR                       0xFFC00400 /* Transmit Holding */
+#define UART_DLL                       0xFFC00400 /* Divisor Latch Low Byte */
+#define UART_DLH                       0xFFC00404 /* Divisor Latch High Byte */
+#define UART_IER                       0xFFC00404
+#define UART_IIR                       0xFFC00408
+#define UART_LCR                       0xFFC0040C
+#define UART_MCR                       0xFFC00410
+#define UART_LSR                       0xFFC00414
+#define UART_SCR                       0xFFC0041C
+#define UART_RBR                       0xFFC00400 /* Receive Buffer */
+#define UART_GCTL                      0xFFC00424
+#define SPT0_TX_CONFIG0                0xFFC00800
+#define SPT0_TX_CONFIG1                0xFFC00804
+#define SPT0_RX_CONFIG0                0xFFC00820
+#define SPT0_RX_CONFIG1                0xFFC00824
+#define SPT0_TX                        0xFFC00810
+#define SPT0_RX                        0xFFC00818
+#define SPT0_TSCLKDIV                  0xFFC00808
+#define SPT0_RSCLKDIV                  0xFFC00828
+#define SPT0_TFSDIV                    0xFFC0080C
+#define SPT0_RFSDIV                    0xFFC0082C
+#define SPT0_STAT                      0xFFC00830
+#define SPT0_MTCS0                     0xFFC00840
+#define SPT0_MTCS1                     0xFFC00844
+#define SPT0_MTCS2                     0xFFC00848
+#define SPT0_MTCS3                     0xFFC0084C
+#define SPT0_MRCS0                     0xFFC00850
+#define SPT0_MRCS1                     0xFFC00854
+#define SPT0_MRCS2                     0xFFC00858
+#define SPT0_MRCS3                     0xFFC0085C
+#define SPT0_MCMC1                     0xFFC00838
+#define SPT0_MCMC2                     0xFFC0083C
+#define SPT0_CHNL                      0xFFC00834
+#define SPT1_TX_CONFIG0                0xFFC00900
+#define SPT1_TX_CONFIG1                0xFFC00904
+#define SPT1_RX_CONFIG0                0xFFC00920
+#define SPT1_RX_CONFIG1                0xFFC00924
+#define SPT1_TX                        0xFFC00910
+#define SPT1_RX                        0xFFC00918
+#define SPT1_TSCLKDIV                  0xFFC00908
+#define SPT1_RSCLKDIV                  0xFFC00928
+#define SPT1_TFSDIV                    0xFFC0090C
+#define SPT1_RFSDIV                    0xFFC0092C
+#define SPT1_STAT                      0xFFC00930
+#define SPT1_MTCS0                     0xFFC00940
+#define SPT1_MTCS1                     0xFFC00944
+#define SPT1_MTCS2                     0xFFC00948
+#define SPT1_MTCS3                     0xFFC0094C
+#define SPT1_MRCS0                     0xFFC00950
+#define SPT1_MRCS1                     0xFFC00954
+#define SPT1_MRCS2                     0xFFC00958
+#define SPT1_MRCS3                     0xFFC0095C
+#define SPT1_MCMC1                     0xFFC00938
+#define SPT1_MCMC2                     0xFFC0093C
+#define SPT1_CHNL                      0xFFC00934
+#define PPI_CONTROL                    0xFFC01000
+#define PPI_STATUS                     0xFFC01004
+#define PPI_DELAY                      0xFFC0100C
+#define PPI_COUNT                      0xFFC01008
+#define PPI_FRAME                      0xFFC01010
+#define PLL_CTL                        0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV                        0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT                       0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define SWRST                          0xFFC00100 /* Software Reset Register (16-bit) */
+#define SYSCR                          0xFFC00104 /* System Configuration register */
+#define EVT_OVERRIDE                   0xFFE02100
+#define CHIPID                         0xFFC00014
+#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF                           0xFFE06100 /* Trace Buffer */
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
+#define RTC_STAT                       0xFFC00300
+#define RTC_ICTL                       0xFFC00304
+#define RTC_ISTAT                      0xFFC00308
+#define RTC_SWCNT                      0xFFC0030C
+#define RTC_ALARM                      0xFFC00310
+#define RTC_PREN                       0xFFC00314
+#define SPI_CTL                        0xFFC00500
+#define SPI_FLG                        0xFFC00504
+#define SPI_STAT                       0xFFC00508
+#define SPI_TDBR                       0xFFC0050C
+#define SPI_RDBR                       0xFFC00510
+#define SPI_BAUD                       0xFFC00514
+#define SPI_SHADOW                     0xFFC00518
+#define FIO_FLAG_D                     0xFFC00700
+#define FIO_FLAG_C                     0xFFC00704
+#define FIO_FLAG_S                     0xFFC00708
+#define FIO_FLAG_T                     0xFFC0070C
+#define FIO_MASKA_D                    0xFFC00710
+#define FIO_MASKA_C                    0xFFC00714
+#define FIO_MASKA_S                    0xFFC00718
+#define FIO_MASKA_T                    0xFFC0071C
+#define FIO_MASKB_D                    0xFFC00720
+#define FIO_MASKB_C                    0xFFC00724
+#define FIO_MASKB_S                    0xFFC00728
+#define FIO_MASKB_T                    0xFFC0072C
+#define FIO_DIR                        0xFFC00730
+#define FIO_POLAR                      0xFFC00734
+#define FIO_EDGE                       0xFFC00738
+#define FIO_BOTH                       0xFFC0073C
+#define FIO_INEN                       0xFFC00740
+#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define DMA0_NEXT_DESC_PTR             0xFFC00C00
+#define DMA0_START_ADDR                0xFFC00C04
+#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                   0xFFC00C10
+#define DMA0_X_MODIFY                  0xFFC00C14
+#define DMA0_Y_COUNT                   0xFFC00C18
+#define DMA0_Y_MODIFY                  0xFFC00C1C
+#define DMA0_CURR_DESC_PTR             0xFFC00C20
+#define DMA0_CURR_ADDR                 0xFFC00C24
+#define DMA0_IRQ_STATUS                0xFFC00C28
+#define DMA0_PERIPHERAL_MAP            0xFFC00C2C
+#define DMA0_CURR_X_COUNT              0xFFC00C30
+#define DMA0_CURR_Y_COUNT              0xFFC00C38
+#define DMA1_NEXT_DESC_PTR             0xFFC00C40
+#define DMA1_START_ADDR                0xFFC00C44
+#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC00C50
+#define DMA1_X_MODIFY                  0xFFC00C54
+#define DMA1_Y_COUNT                   0xFFC00C58
+#define DMA1_Y_MODIFY                  0xFFC00C5C
+#define DMA1_CURR_DESC_PTR             0xFFC00C60
+#define DMA1_CURR_ADDR                 0xFFC00C64
+#define DMA1_IRQ_STATUS                0xFFC00C68
+#define DMA1_PERIPHERAL_MAP            0xFFC00C6C
+#define DMA1_CURR_X_COUNT              0xFFC00C70
+#define DMA1_CURR_Y_COUNT              0xFFC00C78
+#define DMA2_NEXT_DESC_PTR             0xFFC00C80
+#define DMA2_START_ADDR                0xFFC00C84
+#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC00C90
+#define DMA2_X_MODIFY                  0xFFC00C94
+#define DMA2_Y_COUNT                   0xFFC00C98
+#define DMA2_Y_MODIFY                  0xFFC00C9C
+#define DMA2_CURR_DESC_PTR             0xFFC00CA0
+#define DMA2_CURR_ADDR                 0xFFC00CA4
+#define DMA2_IRQ_STATUS                0xFFC00CA8
+#define DMA2_PERIPHERAL_MAP            0xFFC00CAC
+#define DMA2_CURR_X_COUNT              0xFFC00CB0
+#define DMA2_CURR_Y_COUNT              0xFFC00CB8
+#define DMA3_NEXT_DESC_PTR             0xFFC00CC0
+#define DMA3_START_ADDR                0xFFC00CC4
+#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC00CD0
+#define DMA3_X_MODIFY                  0xFFC00CD4
+#define DMA3_Y_COUNT                   0xFFC00CD8
+#define DMA3_Y_MODIFY                  0xFFC00CDC
+#define DMA3_CURR_DESC_PTR             0xFFC00CE0
+#define DMA3_CURR_ADDR                 0xFFC00CE4
+#define DMA3_IRQ_STATUS                0xFFC00CE8
+#define DMA3_PERIPHERAL_MAP            0xFFC00CEC
+#define DMA3_CURR_X_COUNT              0xFFC00CF0
+#define DMA3_CURR_Y_COUNT              0xFFC00CF8
+#define DMA4_NEXT_DESC_PTR             0xFFC00D00
+#define DMA4_START_ADDR                0xFFC00D04
+#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC00D10
+#define DMA4_X_MODIFY                  0xFFC00D14
+#define DMA4_Y_COUNT                   0xFFC00D18
+#define DMA4_Y_MODIFY                  0xFFC00D1C
+#define DMA4_CURR_DESC_PTR             0xFFC00D20
+#define DMA4_CURR_ADDR                 0xFFC00D24
+#define DMA4_IRQ_STATUS                0xFFC00D28
+#define DMA4_PERIPHERAL_MAP            0xFFC00D2C
+#define DMA4_CURR_X_COUNT              0xFFC00D30
+#define DMA4_CURR_Y_COUNT              0xFFC00D38
+#define DMA5_NEXT_DESC_PTR             0xFFC00D40
+#define DMA5_START_ADDR                0xFFC00D44
+#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC00D50
+#define DMA5_X_MODIFY                  0xFFC00D54
+#define DMA5_Y_COUNT                   0xFFC00D58
+#define DMA5_Y_MODIFY                  0xFFC00D5C
+#define DMA5_CURR_DESC_PTR             0xFFC00D60
+#define DMA5_CURR_ADDR                 0xFFC00D64
+#define DMA5_IRQ_STATUS                0xFFC00D68
+#define DMA5_PERIPHERAL_MAP            0xFFC00D6C
+#define DMA5_CURR_X_COUNT              0xFFC00D70
+#define DMA5_CURR_Y_COUNT              0xFFC00D78
+#define DMA6_NEXT_DESC_PTR             0xFFC00D80
+#define DMA6_START_ADDR                0xFFC00D84
+#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC00D90
+#define DMA6_X_MODIFY                  0xFFC00D94
+#define DMA6_Y_COUNT                   0xFFC00D98
+#define DMA6_Y_MODIFY                  0xFFC00D9C
+#define DMA6_CURR_DESC_PTR             0xFFC00DA0
+#define DMA6_CURR_ADDR                 0xFFC00DA4
+#define DMA6_IRQ_STATUS                0xFFC00DA8
+#define DMA6_PERIPHERAL_MAP            0xFFC00DAC
+#define DMA6_CURR_X_COUNT              0xFFC00DB0
+#define DMA6_CURR_Y_COUNT              0xFFC00DB8
+#define DMA7_NEXT_DESC_PTR             0xFFC00DC0
+#define DMA7_START_ADDR                0xFFC00DC4
+#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC00DD0
+#define DMA7_X_MODIFY                  0xFFC00DD4
+#define DMA7_Y_COUNT                   0xFFC00DD8
+#define DMA7_Y_MODIFY                  0xFFC00DDC
+#define DMA7_CURR_DESC_PTR             0xFFC00DE0
+#define DMA7_CURR_ADDR                 0xFFC00DE4
+#define DMA7_IRQ_STATUS                0xFFC00DE8
+#define DMA7_PERIPHERAL_MAP            0xFFC00DEC
+#define DMA7_CURR_X_COUNT              0xFFC00DF0
+#define DMA7_CURR_Y_COUNT              0xFFC00DF8
+#define MDMA_D0_NEXT_DESC_PTR          0xFFC00E00
+#define MDMA_D0_START_ADDR             0xFFC00E04
+#define MDMA_D0_CONFIG                 0xFFC00E08
+#define MDMA_D0_X_COUNT                0xFFC00E10
+#define MDMA_D0_X_MODIFY               0xFFC00E14
+#define MDMA_D0_Y_COUNT                0xFFC00E18
+#define MDMA_D0_Y_MODIFY               0xFFC00E1C
+#define MDMA_D0_CURR_DESC_PTR          0xFFC00E20
+#define MDMA_D0_CURR_ADDR              0xFFC00E24
+#define MDMA_D0_IRQ_STATUS             0xFFC00E28
+#define MDMA_D0_PERIPHERAL_MAP         0xFFC00E2C
+#define MDMA_D0_CURR_X_COUNT           0xFFC00E30
+#define MDMA_D0_CURR_Y_COUNT           0xFFC00E38
+#define MDMA_S0_NEXT_DESC_PTR          0xFFC00E40
+#define MDMA_S0_START_ADDR             0xFFC00E44
+#define MDMA_S0_CONFIG                 0xFFC00E48
+#define MDMA_S0_X_COUNT                0xFFC00E50
+#define MDMA_S0_X_MODIFY               0xFFC00E54
+#define MDMA_S0_Y_COUNT                0xFFC00E58
+#define MDMA_S0_Y_MODIFY               0xFFC00E5C
+#define MDMA_S0_CURR_DESC_PTR          0xFFC00E60
+#define MDMA_S0_CURR_ADDR              0xFFC00E64
+#define MDMA_S0_IRQ_STATUS             0xFFC00E68
+#define MDMA_S0_PERIPHERAL_MAP         0xFFC00E6C
+#define MDMA_S0_CURR_X_COUNT           0xFFC00E70
+#define MDMA_S0_CURR_Y_COUNT           0xFFC00E78
+#define MDMA_D1_NEXT_DESC_PTR          0xFFC00E80
+#define MDMA_D1_START_ADDR             0xFFC00E84
+#define MDMA_D1_CONFIG                 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT                0xFFC00E90
+#define MDMA_D1_X_MODIFY               0xFFC00E94
+#define MDMA_D1_Y_COUNT                0xFFC00E98
+#define MDMA_D1_Y_MODIFY               0xFFC00E9C
+#define MDMA_D1_CURR_DESC_PTR          0xFFC00EA0
+#define MDMA_D1_CURR_ADDR              0xFFC00EA4
+#define MDMA_D1_IRQ_STATUS             0xFFC00EA8
+#define MDMA_D1_PERIPHERAL_MAP         0xFFC00EAC
+#define MDMA_D1_CURR_X_COUNT           0xFFC00EB0
+#define MDMA_D1_CURR_Y_COUNT           0xFFC00EB8
+#define MDMA_S1_NEXT_DESC_PTR          0xFFC00EC0
+#define MDMA_S1_START_ADDR             0xFFC00EC4
+#define MDMA_S1_CONFIG                 0xFFC00EC8
+#define MDMA_S1_X_COUNT                0xFFC00ED0
+#define MDMA_S1_X_MODIFY               0xFFC00ED4
+#define MDMA_S1_Y_COUNT                0xFFC00ED8
+#define MDMA_S1_Y_MODIFY               0xFFC00EDC
+#define MDMA_S1_CURR_DESC_PTR          0xFFC00EE0
+#define MDMA_S1_CURR_ADDR              0xFFC00EE4
+#define MDMA_S1_IRQ_STATUS             0xFFC00EE8
+#define MDMA_S1_PERIPHERAL_MAP         0xFFC00EEC
+#define MDMA_S1_CURR_X_COUNT           0xFFC00EF0
+#define MDMA_S1_CURR_Y_COUNT           0xFFC00EF8
+#define EBIU_AMGCTL                    0xFFC00A00
+#define EBIU_AMBCTL0                   0xFFC00A04
+#define EBIU_AMBCTL1                   0xFFC00A08
+#define EBIU_SDGCTL                    0xFFC00A10
+#define EBIU_SDBCTL                    0xFFC00A14
+#define EBIU_SDRRC                     0xFFC00A18
+#define EBIU_SDSTAT                    0xFFC00A1C
+#define DMA_TC_CNT                     0xFFC00B0C
+#define DMA_TC_PER                     0xFFC00B10
+
+#endif /* __BFIN_DEF_ADSP_EDN_extended__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/bootrom.h b/arch/blackfin/include/asm/mach-common/bits/bootrom.h
new file mode 100644
index 0000000..f537e93
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/bootrom.h
@@ -0,0 +1,261 @@
+/*
+ * Boot ROM Entry Points and such
+ */
+
+/* These Blackfins all have a Boot ROM that is not reusable (at all):
+ *  BF531 / BF532 / BF533
+ *  BF538 / BF539
+ *  BF561
+ * So there is nothing for us to export ;(
+ *
+ * These Blackfins started to roll with the idea that the Boot ROM can
+ * provide useful functions, but still only a few (and not really useful):
+ *  BF534 / BF536 / BF537
+ *
+ * Looking forward, Boot ROM's on newer Blackfins have quite a few
+ * nice entry points that are usable at runtime and beyond.  We'll
+ * only define known legacy parts (listed above) and otherwise just
+ * assume it's a newer part.
+ *
+ * These entry points are accomplished by placing a small jump table at
+ * the start of the Boot ROM.  This way the addresses are fixed forever.
+ */
+
+#ifndef __BFIN_PERIPHERAL_BOOTROM__
+#define __BFIN_PERIPHERAL_BOOTROM__
+
+/* All Blackfin's have the Boot ROM entry point at the same address */
+#define _BOOTROM_RESET 0xEF000000
+
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
+    defined(__ADSPBF538__) || defined(__ADSPBF539__) || \
+    defined(__ADSPBF561__)
+
+	/* Nothing to export */
+
+#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
+
+	/* The BF537 family */
+
+#define _BOOTROM_FINAL_INIT            0xEF000002
+/*       reserved                      0xEF000004 */
+#define _BOOTROM_DO_MEMORY_DMA         0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH        0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI          0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI          0xEF00000C
+/*       reserved                      0xEF00000E */
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI   0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI   0xEF000014
+/*       reserved                      0xEF000016 */
+/*       reserved                      0xEF000018 */
+
+	/* Glue to newer Boot ROMs */
+#define _BOOTROM_MDMA                  _BOOTROM_DO_MEMORY_DMA
+#define _BOOTROM_MEMBOOT               _BOOTROM_BOOT_DXE_FLASH
+#define _BOOTROM_SPIBOOT               _BOOTROM_BOOT_DXE_FLASH
+#define _BOOTROM_TWIBOOT               _BOOTROM_BOOT_DXE_TWI
+
+#else
+
+	/* All the newer Boot ROMs */
+
+#define _BOOTROM_FINAL_INIT            0xEF000002
+#define _BOOTROM_PDMA                  0xEF000004
+#define _BOOTROM_MDMA                  0xEF000006
+#define _BOOTROM_MEMBOOT               0xEF000008
+#define _BOOTROM_SPIBOOT               0xEF00000A
+#define _BOOTROM_TWIBOOT               0xEF00000C
+/*       reserved                      0xEF00000E */
+/*       reserved                      0xEF000010 */
+/*       reserved                      0xEF000012 */
+/*       reserved                      0xEF000014 */
+/*       reserved                      0xEF000016 */
+#define _BOOTROM_OTP_COMMAND           0xEF000018
+#define _BOOTROM_OTP_READ              0xEF00001A
+#define _BOOTROM_OTP_WRITE             0xEF00001C
+#define _BOOTROM_ECC_TABLE             0xEF00001E
+#define _BOOTROM_BOOTKERNEL            0xEF000020
+#define _BOOTROM_GETPORT               0xEF000022
+#define _BOOTROM_NMI                   0xEF000024
+#define _BOOTROM_HWERROR               0xEF000026
+#define _BOOTROM_EXCEPTION             0xEF000028
+#define _BOOTROM_CRC32                 0xEF000030
+#define _BOOTROM_CRC32POLY             0xEF000032
+#define _BOOTROM_CRC32CALLBACK         0xEF000034
+#define _BOOTROM_CRC32INITCODE         0xEF000036
+#define _BOOTROM_SYSCONTROL            0xEF000038
+#define _BOOTROM_REV                   0xEF000040
+#define _BOOTROM_SESR                  0xEF001000
+
+#define BOOTROM_FOLLOWS_C_ABI 1
+
+#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1
+
+#endif
+
+#ifndef BOOTROM_FOLLOWS_C_ABI
+#define BOOTROM_FOLLOWS_C_ABI 0
+#endif
+#ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS
+#define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0
+#endif
+
+/* Possible syscontrol action flags */
+#define SYSCTRL_READ        0x00000000    /* read registers */
+#define SYSCTRL_WRITE       0x00000001    /* write registers */
+#define SYSCTRL_SYSRESET    0x00000002    /* perform system reset */
+#define SYSCTRL_CORERESET   0x00000004    /* perform core reset */
+#define SYSCTRL_SOFTRESET   0x00000006    /* perform core and system reset */
+#define SYSCTRL_VRCTL       0x00000010    /* read/write VR_CTL register */
+#define SYSCTRL_EXTVOLTAGE  0x00000020    /* VDDINT supplied externally */
+#define SYSCTRL_INTVOLTAGE  0x00000000    /* VDDINT generated by on-chip regulator */
+#define SYSCTRL_OTPVOLTAGE  0x00000040    /* For Factory Purposes Only */
+#define SYSCTRL_PLLCTL      0x00000100    /* read/write PLL_CTL register */
+#define SYSCTRL_PLLDIV      0x00000200    /* read/write PLL_DIV register */
+#define SYSCTRL_LOCKCNT     0x00000400    /* read/write PLL_LOCKCNT register */
+#define SYSCTRL_PLLSTAT     0x00000800    /* read/write PLL_STAT register */
+
+#ifndef __ASSEMBLY__
+
+#if BOOTROM_FOLLOWS_C_ABI
+# define BOOTROM_CALLED_FUNC_ATTR
+#else
+# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall))
+#endif
+
+/* Structures for the syscontrol() function */
+typedef struct ADI_SYSCTRL_VALUES {
+	uint16_t uwVrCtl;
+	uint16_t uwPllCtl;
+	uint16_t uwPllDiv;
+	uint16_t uwPllLockCnt;
+	uint16_t uwPllStat;
+} ADI_SYSCTRL_VALUES;
+
+#ifndef _BOOTROM_SYSCONTROL
+#define _BOOTROM_SYSCONTROL 0
+#endif
+static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL;
+
+/* We need a dedicated function since we need to screw with the stack pointer
+ * when resetting.  The on-chip ROM will save/restore registers on the stack
+ * when doing a system reset, so the stack cannot be outside of the chip.
+ */
+__attribute__((__noreturn__))
+static inline void bfrom_SoftReset(void *new_stack)
+{
+	while (1)
+		__asm__ __volatile__(
+			"sp = %[stack];"
+			"jump (%[bfrom_syscontrol]);"
+			: : [bfrom_syscontrol] "p"(bfrom_SysControl),
+				"q0"(SYSCTRL_SOFTRESET),
+				"q1"(0),
+				"q2"(NULL),
+				[stack] "p"(new_stack)
+		);
+}
+
+/* Structures for working with LDRs and boot rom callbacks */
+typedef struct ADI_BOOT_HEADER {
+	int32_t dBlockCode;
+	void    *pTargetAddress;
+	int32_t dByteCount;
+	int32_t dArgument;
+} ADI_BOOT_HEADER;
+
+typedef struct ADI_BOOT_BUFFER {
+	void    *pSource;
+	int32_t dByteCount;
+} ADI_BOOT_BUFFER;
+
+typedef struct ADI_BOOT_DATA {
+	void    *pSource;
+	void    *pDestination;
+	int16_t *pControlRegister;
+	int16_t *pDmaControlRegister;
+	int32_t dControlValue;
+	int32_t dByteCount;
+	int32_t dFlags;
+	int16_t uwDataWidth;
+	int16_t uwSrcModifyMult;
+	int16_t uwDstModifyMult;
+	int16_t uwHwait;
+	int16_t uwSsel;
+	int16_t uwUserShort;
+	int32_t dUserLong;
+	int32_t dReserved2;
+	void    *pErrorFunction;
+	void    *pLoadFunction;
+	void    *pCallBackFunction;
+	ADI_BOOT_HEADER *pHeader;
+	void    *pTempBuffer;
+	void    *pTempCurrent;
+	int32_t dTempByteCount;
+	int32_t dBlockCount;
+	int32_t dClock;
+	void    *pLogBuffer;
+	void    *pLogCurrent;
+	int32_t dLogByteCount;
+} ADI_BOOT_DATA;
+
+typedef void ADI_BOOT_HOOK_FUNC (ADI_BOOT_DATA *);
+
+#ifndef _BOOTROM_MEMBOOT
+#define _BOOTROM_MEMBOOT 0
+#endif
+static uint32_t (* const bfrom_MemBoot)(void *pBootStream, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_MEMBOOT;
+
+#ifndef _BOOTROM_TWIBOOT
+#define _BOOTROM_TWIBOOT 0
+#endif
+static uint32_t (* const bfrom_TwiBoot)(int32_t dTwiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_TWIBOOT;
+
+#ifndef _BOOTROM_SPIBOOT
+#define _BOOTROM_SPIBOOT 0
+#endif
+static uint32_t (* const bfrom_SpiBoot)(int32_t dSpiAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_SPIBOOT;
+
+#ifndef _BOOTROM_OTPBOOT
+#define _BOOTROM_OTPBOOT 0
+#endif
+static uint32_t (* const bfrom_OtpBoot)(int32_t dOtpAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_OTPBOOT;
+
+#ifndef _BOOTROM_NANDBOOT
+#define _BOOTROM_NANDBOOT 0
+#endif
+static uint32_t (* const bfrom_NandBoot)(int32_t dNandAddress, int32_t dFlags, int32_t dBlockCount, ADI_BOOT_HOOK_FUNC *pCallHook) = (void *)_BOOTROM_NANDBOOT;
+
+#endif /* __ASSEMBLY__ */
+
+/* Bit defines for ADI_BOOT_DATA->dFlags */
+#define BFLAG_DMACODE_MASK 0x0000000F
+#define BFLAG_SAFE         0x00000010
+#define BFLAG_AUX          0x00000020
+#define BFLAG_FILL         0x00000100
+#define BFLAG_QUICKBOOT    0x00000200
+#define BFLAG_CALLBACK     0x00000400
+#define BFLAG_INIT         0x00000800
+#define BFLAG_IGNORE       0x00001000
+#define BFLAG_INDIRECT     0x00002000
+#define BFLAG_FIRST        0x00004000
+#define BFLAG_FINAL        0x00008000
+#define BFLAG_HOOK         0x00400000
+#define BFLAG_HDRINDIRECT  0x00800000
+#define BFLAG_TYPE_MASK    0x00300000
+#define BFLAG_TYPE_1       0x00000000
+#define BFLAG_TYPE_2       0x00100000
+#define BFLAG_TYPE_3       0x00200000
+#define BFLAG_TYPE_4       0x00300000
+#define BFLAG_FASTREAD     0x00400000
+#define BFLAG_NOAUTO       0x01000000
+#define BFLAG_PERIPHERAL   0x02000000
+#define BFLAG_SLAVE        0x04000000
+#define BFLAG_WAKEUP       0x08000000
+#define BFLAG_NEXTDXE      0x10000000
+#define BFLAG_RETURN       0x20000000
+#define BFLAG_RESET        0x40000000
+#define BFLAG_NONRESTORE   0x80000000
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/core.h b/arch/blackfin/include/asm/mach-common/bits/core.h
new file mode 100644
index 0000000..6db4f81
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/core.h
@@ -0,0 +1,112 @@
+/*
+ * Misc Core Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_CORE__
+#define __BFIN_PERIPHERAL_CORE__
+
+/*
+ * EVT registers (ILAT, IMASK, and IPEND).
+ */
+
+#define EVT_EMU_P		0	/* Emulator interrupt bit position */
+#define EVT_RST_P		1	/* Reset interrupt bit position */
+#define EVT_NMI_P		2	/* Non Maskable interrupt bit position */
+#define EVT_EVX_P		3	/* Exception bit position */
+#define EVT_IRPTEN_P		4	/* Global interrupt enable bit position */
+#define EVT_IVHW_P		5	/* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P		6	/* Timer interrupt bit position */
+#define EVT_IVG7_P		7	/* IVG7 interrupt bit position */
+#define EVT_IVG8_P		8	/* IVG8 interrupt bit position */
+#define EVT_IVG9_P		9	/* IVG9 interrupt bit position */
+#define EVT_IVG10_P		10	/* IVG10 interrupt bit position */
+#define EVT_IVG11_P		11	/* IVG11 interrupt bit position */
+#define EVT_IVG12_P		12	/* IVG12 interrupt bit position */
+#define EVT_IVG13_P		13	/* IVG13 interrupt bit position */
+#define EVT_IVG14_P		14	/* IVG14 interrupt bit position */
+#define EVT_IVG15_P		15	/* IVG15 interrupt bit position */
+
+#define EVT_EMU			MK_BMSK_(EVT_EMU_P   )	/* Emulator interrupt mask */
+#define EVT_RST			MK_BMSK_(EVT_RST_P   )	/* Reset interrupt mask */
+#define EVT_NMI			MK_BMSK_(EVT_NMI_P   )	/* Non Maskable interrupt mask */
+#define EVT_EVX			MK_BMSK_(EVT_EVX_P   )	/* Exception mask */
+#define EVT_IRPTEN		MK_BMSK_(EVT_IRPTEN_P)	/* Global interrupt enable mask */
+#define EVT_IVHW		MK_BMSK_(EVT_IVHW_P  )	/* Hardware Error interrupt mask */
+#define EVT_IVTMR		MK_BMSK_(EVT_IVTMR_P )	/* Timer interrupt mask */
+#define EVT_IVG7		MK_BMSK_(EVT_IVG7_P  )	/* IVG7 interrupt mask */
+#define EVT_IVG8		MK_BMSK_(EVT_IVG8_P  )	/* IVG8 interrupt mask */
+#define EVT_IVG9		MK_BMSK_(EVT_IVG9_P  )	/* IVG9 interrupt mask */
+#define EVT_IVG10		MK_BMSK_(EVT_IVG10_P )	/* IVG10 interrupt mask */
+#define EVT_IVG11		MK_BMSK_(EVT_IVG11_P )	/* IVG11 interrupt mask */
+#define EVT_IVG12		MK_BMSK_(EVT_IVG12_P )	/* IVG12 interrupt mask */
+#define EVT_IVG13		MK_BMSK_(EVT_IVG13_P )	/* IVG13 interrupt mask */
+#define EVT_IVG14		MK_BMSK_(EVT_IVG14_P )	/* IVG14 interrupt mask */
+#define EVT_IVG15		MK_BMSK_(EVT_IVG15_P )	/* IVG15 interrupt mask */
+
+/*
+ * SEQSTAT register
+ */
+
+#define EXCAUSE_P	0	/* Last exception cause bit positions */
+#define EXCAUSE0_P	0	/* Last exception cause bit 0 */
+#define EXCAUSE1_P	1	/* Last exception cause bit 1 */
+#define EXCAUSE2_P	2	/* Last exception cause bit 2 */
+#define EXCAUSE3_P	3	/* Last exception cause bit 3 */
+#define EXCAUSE4_P	4	/* Last exception cause bit 4 */
+#define EXCAUSE5_P	5	/* Last exception cause bit 5 */
+#define IDLE_REQ_P	12	/* Pending idle mode request, set by IDLE instruction */
+#define SFTRESET_P	13	/* Indicates whether the last reset was a software reset (=1) */
+#define HWERRCAUSE_P	14	/* Last hw error cause bit positions */
+#define HWERRCAUSE0_P	14	/* Last hw error cause bit 0 */
+#define HWERRCAUSE1_P	15	/* Last hw error cause bit 1 */
+#define HWERRCAUSE2_P	16	/* Last hw error cause bit 2 */
+#define HWERRCAUSE3_P	17	/* Last hw error cause bit 3 */
+#define HWERRCAUSE4_P	18	/* Last hw error cause bit 4 */
+#define HWERRCAUSE5_P	19	/* Last hw error cause bit 5 */
+#define HWERRCAUSE6_P	20	/* Last hw error cause bit 6 */
+#define HWERRCAUSE7_P	21	/* Last hw error cause bit 7 */
+
+#define EXCAUSE \
+	( MK_BMSK_(EXCAUSE0_P) | \
+	  MK_BMSK_(EXCAUSE1_P) | \
+	  MK_BMSK_(EXCAUSE2_P) | \
+	  MK_BMSK_(EXCAUSE3_P) | \
+	  MK_BMSK_(EXCAUSE4_P) | \
+	  MK_BMSK_(EXCAUSE5_P) )
+#define SFTRESET \
+	( MK_BMSK_(SFTRESET_P) )
+#define HWERRCAUSE \
+	( MK_BMSK_(HWERRCAUSE0_P) | \
+	  MK_BMSK_(HWERRCAUSE1_P) | \
+	  MK_BMSK_(HWERRCAUSE2_P) | \
+	  MK_BMSK_(HWERRCAUSE3_P) | \
+	  MK_BMSK_(HWERRCAUSE4_P) )
+
+/* SWRST Masks */
+#define SYSTEM_RESET		0x0007		/* Initiates A System Software Reset */
+#ifdef __ADSPBF561__
+# define DOUBLE_FAULT_A		0x0008
+# define DOUBLE_FAULT_B		0x0010
+# define DOUBLE_FAULT		0x0018		/* Core [A|B] Double Fault Causes Reset */
+# define RESET_DOUBLE_A		0x0800
+# define RESET_DOUBLE_B		0x1000
+# define RESET_DOUBLE		0x1800		/* SW Reset Generated By Core [A|B] Double-Fault */
+# define RESET_WDOG_B		0x2000
+# define RESET_WDOG_A		0x4000
+# define RESET_WDOG		0x6000		/* SW Reset Generated By Watchdog [A|B] Timer */
+#else
+# define DOUBLE_FAULT		0x0008		/* Core Double Fault Causes Reset */
+# define RESET_DOUBLE		0x2000		/* SW Reset Generated By Core Double-Fault */
+# define RESET_WDOG		0x4000		/* SW Reset Generated By Watchdog Timer */
+#endif
+#define RESET_SOFTWARE		0x8000		/* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCFG Masks */
+#define SSSTEP			0x00000001	/* Supervisor Single Step */
+#define CCEN			0x00000002	/* Cycle Counter Enable */
+#define SNEN			0x00000004	/* Self-Nesting Interrupt Enable */
+#define SYSCFG_SSSTEP_P	0
+#define SYSCFG_CCEN_P	1
+#define SYSCFG_SCEN_P	2
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dma.h b/arch/blackfin/include/asm/mach-common/bits/dma.h
new file mode 100644
index 0000000..136313e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/dma.h
@@ -0,0 +1,58 @@
+/*
+ * DMA Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_DMA__
+#define __BFIN_PERIPHERAL_DMA__
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN			0x0001	/* DMA Channel Enable */
+#define WNR			0x0002	/* Channel Direction (W/R*) */
+#define WDSIZE_8		0x0000	/* Transfer Word Size = 8 */
+#define WDSIZE_16		0x0004	/* Transfer Word Size = 16 */
+#define WDSIZE_32		0x0008	/* Transfer Word Size = 32 */
+#define DMA2D			0x0010	/* DMA Mode (2D/1D*) */
+#define RESTART			0x0020	/* DMA Buffer Clear */
+#define DI_SEL			0x0040	/* Data Interrupt Timing Select */
+#define DI_EN			0x0080	/* Data Interrupt Enable */
+#define NDSIZE			0x0F00	/* Next Descriptor bitmask */
+#define NDSIZE_0		0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1		0x0100	/* Next Descriptor Size = 1 */
+#define NDSIZE_2		0x0200	/* Next Descriptor Size = 2 */
+#define NDSIZE_3		0x0300	/* Next Descriptor Size = 3 */
+#define NDSIZE_4		0x0400	/* Next Descriptor Size = 4 */
+#define NDSIZE_5		0x0500	/* Next Descriptor Size = 5 */
+#define NDSIZE_6		0x0600	/* Next Descriptor Size = 6 */
+#define NDSIZE_7		0x0700	/* Next Descriptor Size = 7 */
+#define NDSIZE_8		0x0800	/* Next Descriptor Size = 8 */
+#define NDSIZE_9		0x0900	/* Next Descriptor Size = 9 */
+#define FLOW_STOP		0x0000	/* Stop Mode */
+#define FLOW_AUTO		0x1000	/* Autobuffer Mode */
+#define FLOW_ARRAY		0x4000	/* Descriptor Array Mode */
+#define FLOW_SMALL		0x6000	/* Small Model Descriptor List Mode */
+#define FLOW_LARGE		0x7000	/* Large Model Descriptor List Mode */
+
+#define DMAEN_P			0	/* Channel Enable */
+#define WNR_P			1	/* Channel Direction (W/R*) */
+#define DMA2D_P			4	/* 2D/1D* Mode */
+#define RESTART_P		5	/* Restart */
+#define DI_SEL_P		6	/* Data Interrupt Select */
+#define DI_EN_P			7	/* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status */
+#define DMA_ERR			0x0002	/* DMA Error Interrupt Status */
+#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator */
+#define DMA_RUN			0x0008	/* DMA Channel Running Indicator */
+
+#define DMA_DONE_P		0	/* DMA Done Indicator */
+#define DMA_ERR_P		1	/* DMA Error Indicator */
+#define DFETCH_P		2	/* Descriptor Fetch Indicator */
+#define DMA_RUN_P		3	/* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define CTYPE_P			6	/* DMA Channel Type Indicator BIT POSITION */
+#define PMAP			0xF000	/* Peripheral Mapped To This Channel */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ebiu.h b/arch/blackfin/include/asm/mach-common/bits/ebiu.h
new file mode 100644
index 0000000..7c0c569
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ebiu.h
@@ -0,0 +1,440 @@
+/*
+ * EBIU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_EBIU__
+#define __BFIN_PERIPHERAL_EBIU__
+
+/* EBIU_AMGCTL Masks */
+#define AMCKEN		0x0001		/* Enable CLKOUT */
+#define AMBEN_NONE	0x0000		/* All Banks Disabled */
+#define AMBEN_B0	0x0002		/* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1	0x0004		/* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2	0x0006		/* Enable Asynchronous Memory Banks 0,/ 1, and 2 */
+#define AMBEN_ALL	0x0008		/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define B0_PEN		0x0010		/* Enable 16-bit packing Bank 0 */
+#define B1_PEN		0x0020		/* Enable 16-bit packing Bank 1 */
+#define B2_PEN		0x0040		/* Enable 16-bit packing Bank 2 */
+#define B3_PEN		0x0080		/* Enable 16-bit packing Bank 3 */
+#define CDPRIO		0x0100		/* Core has priority over DMA for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P	0x00000000	/* Enable CLKOUT */
+#define AMBEN_P0	0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1	0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2	0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+#define B0_PEN_P	0x00000004	/* Enable 16-bit packing Bank 0 */
+#define B1_PEN_P	0x00000005	/* Enable 16-bit packing Bank 1 */
+#define B2_PEN_P	0x00000006	/* Enable 16-bit packing Bank 2 */
+#define B3_PEN_P	0x00000007	/* Enable 16-bit packing Bank 3 */
+#define CDPRIO_P	0x00000008	/* Core has priority over DMA for external accesses */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN		0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL	0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1		0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2		0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3		0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4		0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1		0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2		0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3		0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4		0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1		0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2		0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3		0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0		0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1		0x00000100	/* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2		0x00000200	/* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3		0x00000300	/* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4		0x00000400	/* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5		0x00000500	/* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6		0x00000600	/* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7		0x00000700	/* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8		0x00000800	/* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9		0x00000900	/* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10	0x00000A00	/* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11	0x00000B00	/* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12	0x00000C00	/* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13	0x00000D00	/* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14	0x00000E00	/* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15	0x00000F00	/* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1		0x00001000	/* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2		0x00002000	/* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3		0x00003000	/* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4		0x00004000	/* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5		0x00005000	/* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6		0x00006000	/* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7		0x00007000	/* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8		0x00008000	/* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9		0x00009000	/* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10	0x0000A000	/* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11	0x0000B000	/* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12	0x0000C000	/* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13	0x0000D000	/* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14	0x0000E000	/* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15	0x0000F000	/* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN		0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL	0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1		0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2		0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3		0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4		0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1		0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2		0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3		0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4		0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1		0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2		0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3		0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0		0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1		0x01000000	/* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2		0x02000000	/* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3		0x03000000	/* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4		0x04000000	/* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5		0x05000000	/* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6		0x06000000	/* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7		0x07000000	/* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8		0x08000000	/* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9		0x09000000	/* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10	0x0A000000	/* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11	0x0B000000	/* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12	0x0C000000	/* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13	0x0D000000	/* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14	0x0E000000	/* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15	0x0F000000	/* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1		0x10000000	/* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2		0x20000000	/* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3		0x30000000	/* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4		0x40000000	/* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5		0x50000000	/* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6		0x60000000	/* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7		0x70000000	/* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8		0x80000000	/* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9		0x90000000	/* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10	0xA0000000	/* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11	0xB0000000	/* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12	0xC0000000	/* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13	0xD0000000	/* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14	0xE0000000	/* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15	0xF0000000	/* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN		0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL	0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1		0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2		0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3		0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4		0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1		0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2		0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3		0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4		0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1		0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2		0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3		0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0		0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1		0x00000100	/* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2		0x00000200	/* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3		0x00000300	/* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4		0x00000400	/* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5		0x00000500	/* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6		0x00000600	/* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7		0x00000700	/* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8		0x00000800	/* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9		0x00000900	/* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10	0x00000A00	/* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11	0x00000B00	/* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12	0x00000C00	/* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13	0x00000D00	/* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14	0x00000E00	/* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15	0x00000F00	/* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1		0x00001000	/* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2		0x00002000	/* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3		0x00003000	/* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4		0x00004000	/* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5		0x00005000	/* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6		0x00006000	/* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7		0x00007000	/* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8		0x00008000	/* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9		0x00009000	/* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10	0x0000A000	/* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11	0x0000B000	/* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12	0x0000C000	/* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13	0x0000D000	/* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14	0x0000E000	/* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15	0x0000F000	/* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN		0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL	0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1		0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2		0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3		0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4		0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1		0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2		0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3		0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4		0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1		0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2		0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3		0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0		0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1		0x01000000	/* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2		0x02000000	/* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3		0x03000000	/* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4		0x04000000	/* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5		0x05000000	/* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6		0x06000000	/* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7		0x07000000	/* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8		0x08000000	/* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9		0x09000000	/* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10	0x0A000000	/* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11	0x0B000000	/* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12	0x0C000000	/* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13	0x0D000000	/* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14	0x0E000000	/* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15	0x0F000000	/* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1		0x10000000	/* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2		0x20000000	/* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3		0x30000000	/* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4		0x40000000	/* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5		0x50000000	/* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6		0x60000000	/* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7		0x70000000	/* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8		0x80000000	/* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9		0x90000000	/* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10	0xA0000000	/* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11	0xB0000000	/* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12	0xC0000000	/* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13	0xD0000000	/* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14	0xE0000000	/* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15	0xF0000000	/* Bank 3 Write Access Time = 15 cycles */
+
+/* Only available on newer parts */
+#ifdef EBIU_MODE
+
+/* EBIU_MBSCTL Bit Positions */
+#define AMSB0CTL_P	0
+#define AMSB1CTL_P	2
+#define AMSB2CTL_P	4
+#define AMSB3CTL_P	6
+
+/* EBIU_MBSCTL Masks */
+#define AMSB0CTL_MASK	(0x3 << AMSB0CTL_P)	/* Async Memory Bank 0 Control Modes */
+#define AMSB0CTL_NONE	(0x0 << AMSB0CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB0CTL_ARE	(0x1 << AMSB0CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB0CTL_AOE	(0x2 << AMSB0CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB0CTL_AWE	(0x3 << AMSB0CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB1CTL_MASK	(0x3 << AMSB1CTL_P)	/* Async Memory Bank 1 Control Modes */
+#define AMSB1CTL_NONE	(0x0 << AMSB1CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB1CTL_ARE	(0x1 << AMSB1CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB1CTL_AOE	(0x2 << AMSB1CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB1CTL_AWE	(0x3 << AMSB1CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB2CTL_MASK	(0x3 << AMSB2CTL_P)	/* Async Memory Bank 2 Control Modes */
+#define AMSB2CTL_NONE	(0x0 << AMSB2CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB2CTL_ARE	(0x1 << AMSB2CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB2CTL_AOE	(0x2 << AMSB2CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB2CTL_AWE	(0x3 << AMSB2CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+#define AMSB3CTL_MASK	(0x3 << AMSB3CTL_P)	/* Async Memory Bank 3 Control Modes */
+#define AMSB3CTL_NONE	(0x0 << AMSB3CTL_P)	/* Control Mode - 00 - No logic */
+#define AMSB3CTL_ARE	(0x1 << AMSB3CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */
+#define AMSB3CTL_AOE	(0x2 << AMSB3CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */
+#define AMSB3CTL_AWE	(0x3 << AMSB3CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */
+
+/* EBIU_MODE Bit Positions */
+#define B0MODE_P	0
+#define B1MODE_P	2
+#define B2MODE_P	4
+#define B3MODE_P	6
+
+/* EBIU_MODE Masks */
+#define B0MODE_MASK	(0x3 << B0MODE_P)	/* Async Memory Bank 0 Access Mode */
+#define B0MODE_ASYNC	(0x0 << B0MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B0MODE_FLASH	(0x1 << B0MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B0MODE_PAGE	(0x2 << B0MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B0MODE_BURST	(0x3 << B0MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B1MODE_MASK	(0x3 << B1MODE_P)	/* Async Memory Bank 1 Access Mode */
+#define B1MODE_ASYNC	(0x0 << B1MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B1MODE_FLASH	(0x1 << B1MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B1MODE_PAGE	(0x2 << B1MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B1MODE_BURST	(0x3 << B1MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B2MODE_MASK	(0x3 << B2MODE_P)	/* Async Memory Bank 2 Access Mode */
+#define B2MODE_ASYNC	(0x0 << B2MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B2MODE_FLASH	(0x1 << B2MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B2MODE_PAGE	(0x2 << B2MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B2MODE_BURST	(0x3 << B2MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+#define B3MODE_MASK	(0x3 << B3MODE_P)	/* Async Memory Bank 3 Access Mode */
+#define B3MODE_ASYNC	(0x0 << B3MODE_P)	/* Access Mode - 00 - Asynchronous Mode */
+#define B3MODE_FLASH	(0x1 << B3MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */
+#define B3MODE_PAGE	(0x2 << B3MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */
+#define B3MODE_BURST	(0x3 << B3MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* EBIU_FCTL Bit Positions */
+#define TESTSETLOCK_P	0
+#define BCLK_P		1
+#define PGWS_P		3
+#define PGSZ_P		6
+#define RDDL_P		7
+
+/* EBIU_FCTL Masks */
+#define TESTSETLOCK	(0x1 << TESTSETLOCK_P)	/* Test set lock */
+#define BCLK_MASK	(0x3 << BCLK_P)		/* Burst clock frequency */
+#define BCLK_2		(0x1 << BCLK_P)		/* Burst clock frequency - SCLK/2 */
+#define BCLK_3		(0x2 << BCLK_P)		/* Burst clock frequency - SCLK/3 */
+#define BCLK_4		(0x3 << BCLK_P)		/* Burst clock frequency - SCLK/4 */
+#define PGWS_MASK	(0x7 << PGWS_P)		/* Page wait states */
+#define PGWS_0		(0x0 << PGWS_P)		/* Page wait states - 0 cycles */
+#define PGWS_1		(0x1 << PGWS_P)		/* Page wait states - 1 cycles */
+#define PGWS_2		(0x2 << PGWS_P)		/* Page wait states - 2 cycles */
+#define PGWS_3		(0x3 << PGWS_P)		/* Page wait states - 3 cycles */
+#define PGWS_4		(0x4 << PGWS_P)		/* Page wait states - 4 cycles */
+#define PGSZ		(0x1 << PGSZ_P)		/* Page size */
+#define PGSZ_4		(0x0 << PGSZ_P)		/* Page size - 4 words */
+#define PGSZ_8		(0x1 << PGSZ_P)		/* Page size - 8 words */
+#define RDDL		(0x38 << RDDL_P)	/* Read data delay */
+
+/* EBIU_ARBSTAT Masks */
+#define ARBSTAT		0x00000001	/* Arbitration status */
+#define BGSTAT		0x00000002	/* External Bus grant status */
+
+#endif /* EBIU_MODE */
+
+/* Only available on SDRAM based-parts */
+#ifdef EBIU_SDGCTL
+
+/* EBIU_SDGCTL Masks */
+#define SCTLE		0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define SCK1E		0x00000002	/* Enable CLKOUT, /SCLK1 */
+#define CL_2		0x00000008	/* SDRAM CAS latency = 2 cycles */
+#define CL_3		0x0000000C	/* SDRAM CAS latency = 3 cycles */
+#define PASR_ALL	0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1	0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0		0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1		0x00000040	/* SDRAM tRAS = 1 cycle */
+#define TRAS_2		0x00000080	/* SDRAM tRAS = 2 cycles */
+#define TRAS_3		0x000000C0	/* SDRAM tRAS = 3 cycles */
+#define TRAS_4		0x00000100	/* SDRAM tRAS = 4 cycles */
+#define TRAS_5		0x00000140	/* SDRAM tRAS = 5 cycles */
+#define TRAS_6		0x00000180	/* SDRAM tRAS = 6 cycles */
+#define TRAS_7		0x000001C0	/* SDRAM tRAS = 7 cycles */
+#define TRAS_8		0x00000200	/* SDRAM tRAS = 8 cycles */
+#define TRAS_9		0x00000240	/* SDRAM tRAS = 9 cycles */
+#define TRAS_10		0x00000280	/* SDRAM tRAS = 10 cycles */
+#define TRAS_11		0x000002C0	/* SDRAM tRAS = 11 cycles */
+#define TRAS_12		0x00000300	/* SDRAM tRAS = 12 cycles */
+#define TRAS_13		0x00000340	/* SDRAM tRAS = 13 cycles */
+#define TRAS_14		0x00000380	/* SDRAM tRAS = 14 cycles */
+#define TRAS_15		0x000003C0	/* SDRAM tRAS = 15 cycles */
+#define TRP_1		0x00000800	/* SDRAM tRP = 1 cycle */
+#define TRP_2		0x00001000	/* SDRAM tRP = 2 cycles */
+#define TRP_3		0x00001800	/* SDRAM tRP = 3 cycles */
+#define TRP_4		0x00002000	/* SDRAM tRP = 4 cycles */
+#define TRP_5		0x00002800	/* SDRAM tRP = 5 cycles */
+#define TRP_6		0x00003000	/* SDRAM tRP = 6 cycles */
+#define TRP_7		0x00003800	/* SDRAM tRP = 7 cycles */
+#define TRCD_1		0x00008000	/* SDRAM tRCD = 1 cycle */
+#define TRCD_2		0x00010000	/* SDRAM tRCD = 2 cycles */
+#define TRCD_3		0x00018000	/* SDRAM tRCD = 3 cycles */
+#define TRCD_4		0x00020000	/* SDRAM tRCD = 4 cycles */
+#define TRCD_5		0x00028000	/* SDRAM tRCD = 5 cycles */
+#define TRCD_6		0x00030000	/* SDRAM tRCD = 6 cycles */
+#define TRCD_7		0x00038000	/* SDRAM tRCD = 7 cycles */
+#define TWR_1		0x00080000	/* SDRAM tWR = 1 cycle */
+#define TWR_2		0x00100000	/* SDRAM tWR = 2 cycles */
+#define TWR_3		0x00180000	/* SDRAM tWR = 3 cycles */
+#define PUPSD		0x00200000	/* Power-up start delay */
+#define PSM		0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS		0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS		0x01000000	/* Start SDRAM self-refresh mode */
+#define EBUFE		0x02000000	/* Enable external buffering timing */
+#define FBBRW		0x04000000	/* Fast back-to-back read write enable */
+#define EMREN		0x10000000	/* Extended mode register enable */
+#define TCSR		0x20000000	/* Temp compensated self refresh value 85 deg C */
+#define CDDBG		0x40000000	/* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE		0x0001		/* Enable SDRAM External Bank */
+#define EBSZ_16		0x0000		/* SDRAM External Bank Size = 16MB */
+#define EBSZ_32		0x0002		/* SDRAM External Bank Size = 32MB */
+#define EBSZ_64		0x0004		/* SDRAM External Bank Size = 64MB */
+#define EBSZ_128	0x0006		/* SDRAM External Bank Size = 128MB */
+#define EBSZ_256	0x0008		/* SDRAM External Bank Size = 256MB */
+#define EBSZ_512	0x000A		/* SDRAM External Bank Size = 512MB */
+#define EBCAW_8		0x0000		/* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9		0x0010		/* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10	0x0020		/* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11	0x0030		/* SDRAM External Bank Column Address Width = 11 Bits */
+
+#ifdef __ADSPBF561__
+
+#define EB0E		(EBE<<0)	/* Enable SDRAM external bank 0 */
+#define EB0SZ_16	(EBSZ_16<<0)	/* SDRAM external bank size = 16MB */
+#define EB0SZ_32	(EBSZ_32<<0)	/* SDRAM external bank size = 32MB */
+#define EB0SZ_64	(EBSZ_64<<0)	/* SDRAM external bank size = 64MB */
+#define EB0SZ_128	(EBSZ_128<<0)	/* SDRAM external bank size = 128MB */
+#define EB0CAW_8	(EBCAW_8<<0)	/* SDRAM external bank column address width = 8 bits */
+#define EB0CAW_9	(EBCAW_9<<0)	/* SDRAM external bank column address width = 9 bits */
+#define EB0CAW_10	(EBCAW_10<<0)	/* SDRAM external bank column address width = 9 bits */
+#define EB0CAW_11	(EBCAW_11<<0)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB1E		(EBE<<8)	/* Enable SDRAM external bank 0 */
+#define EB1SZ_16	(EBSZ_16<<8)	/* SDRAM external bank size = 16MB */
+#define EB1SZ_32	(EBSZ_32<<8)	/* SDRAM external bank size = 32MB */
+#define EB1SZ_64	(EBSZ_64<<8)	/* SDRAM external bank size = 64MB */
+#define EB1SZ_128	(EBSZ_128<<8)	/* SDRAM external bank size = 128MB */
+#define EB1CAW_8	(EBCAW_8<<8)	/* SDRAM external bank column address width = 8 bits */
+#define EB1CAW_9	(EBCAW_9<<8)	/* SDRAM external bank column address width = 9 bits */
+#define EB1CAW_10	(EBCAW_10<<8)	/* SDRAM external bank column address width = 9 bits */
+#define EB1CAW_11	(EBCAW_11<<8)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB2E		(EBE<<16)	/* Enable SDRAM external bank 0 */
+#define EB2SZ_16	(EBSZ_16<<16)	/* SDRAM external bank size = 16MB */
+#define EB2SZ_32	(EBSZ_32<<16)	/* SDRAM external bank size = 32MB */
+#define EB2SZ_64	(EBSZ_64<<16)	/* SDRAM external bank size = 64MB */
+#define EB2SZ_128	(EBSZ_128<<16)	/* SDRAM external bank size = 128MB */
+#define EB2CAW_8	(EBCAW_8<<16)	/* SDRAM external bank column address width = 8 bits */
+#define EB2CAW_9	(EBCAW_9<<16)	/* SDRAM external bank column address width = 9 bits */
+#define EB2CAW_10	(EBCAW_10<<16)	/* SDRAM external bank column address width = 9 bits */
+#define EB2CAW_11	(EBCAW_11<<16)	/* SDRAM external bank column address width = 9 bits */
+
+#define EB3E		(EBE<<24)	/* Enable SDRAM external bank 0 */
+#define EB3SZ_16	(EBSZ_16<<24)	/* SDRAM external bank size = 16MB */
+#define EB3SZ_32	(EBSZ_32<<24)	/* SDRAM external bank size = 32MB */
+#define EB3SZ_64	(EBSZ_64<<24)	/* SDRAM external bank size = 64MB */
+#define EB3SZ_128	(EBSZ_128<<24)	/* SDRAM external bank size = 128MB */
+#define EB3CAW_8	(EBCAW_8<<24)	/* SDRAM external bank column address width = 8 bits */
+#define EB3CAW_9	(EBCAW_9<<24)	/* SDRAM external bank column address width = 9 bits */
+#define EB3CAW_10	(EBCAW_10<<24)	/* SDRAM external bank column address width = 9 bits */
+#define EB3CAW_11	(EBCAW_11<<24)	/* SDRAM external bank column address width = 9 bits */
+
+#endif /* BF561 */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI		0x0001		/* SDRAM controller is idle */
+#define SDSRA		0x0002		/* SDRAM self refresh is active */
+#define SDPUA		0x0004		/* SDRAM power up active */
+#define SDRS		0x0008		/* SDRAM is in reset state */
+#define SDEASE		0x0010		/* SDRAM EAB sticky error status - W1C */
+#define BGSTAT		0x0020		/* Bus granted */
+
+/* Only available on DDR based-parts */
+#else
+
+/* EBIU_ERRMST Masks */
+#define DEB0_ERROR	0x0001		/* DEB0 access on reserved memory */
+#define DEB1_ERROR	0x0002		/* DEB1 access on reserved memory */
+#define DEB2_ERROR	0x0004		/* DEB2 (USB) access on reserved memory */
+#define CORE_ERROR	0x0008		/* Core access on reserved memory */
+#define DEB0_MERROR	0x0010		/* DEB0 access on reserved memory and DEB0_ERROR is set */
+#define DEB1_MERROR	0x0020		/* DEB1 access on reserved memory and DEB1_ERROR is set */
+#define DEB2_MERROR	0x0040		/* DEB2 access on reserved memory and DEB2_ERROR is set */
+#define CORE_MERROR	0x0080		/* Core access on reserved memory and CORE_ERROR is set */
+
+/* EBIU_RSTCTL Masks */
+#define DDR_SRESET	0x0001		/* Reset Control to DDR Controller */
+#define SRREQ		0x0008		/* Self Refresh Request */
+#define SRACK		0x0010		/* Self Refresh Request Acknowledgement */
+#define MDDRENABLE	0x0020		/* Mobile DDR Enable */
+
+#endif /* EBIU_SDGCTL */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h
new file mode 100644
index 0000000..7a43bbb
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/emac.h
@@ -0,0 +1,220 @@
+/*
+ * Ethernet MAC Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_EMAC__
+#define __BFIN_PERIPHERAL_EMAC__
+
+/* EMAC_OPMODE Masks */
+#define	RE		0x00000001	/* Receiver Enable */
+#define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames */
+#define	HU		0x00000010	/* Hash Filter Unicast Address */
+#define	HM		0x00000020	/* Hash Filter Multicast Address */
+#define	PAM		0x00000040	/* Pass-All-Multicast Mode Enable */
+#define	PR		0x00000080	/* Promiscuous Mode Enable */
+#define	IFE		0x00000100	/* Inverse Filtering Enable */
+#define	DBF		0x00000200	/* Disable Broadcast Frame Reception */
+#define	PBF		0x00000400	/* Pass Bad Frames Enable */
+#define	PSF		0x00000800	/* Pass Short Frames Enable */
+#define	RAF		0x00001000	/* Receive-All Mode */
+#define	TE		0x00010000	/* Transmitter Enable */
+#define	DTXPAD		0x00020000	/* Disable Automatic TX Padding */
+#define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation */
+#define	DC		0x00080000	/* Deferral Check */
+#define	BOLMT		0x00300000	/* Back-Off Limit */
+#define	BOLMT_10	0x00000000	/* 10-bit range */
+#define	BOLMT_8		0x00100000	/* 8-bit range */
+#define	BOLMT_4		0x00200000	/* 4-bit range */
+#define	BOLMT_1		0x00300000	/* 1-bit range */
+#define	DRTY		0x00400000	/* Disable TX Retry On Collision */
+#define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision */
+#define	RMII		0x01000000	/* RMII/MII* Mode */
+#define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*) */
+#define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*) */
+#define	LB		0x08000000	/* Internal Loopback Enable */
+#define	DRO		0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+#define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*) */
+#define	STADISPRE	0x00000004	/* Disable Preamble Generation */
+#define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable */
+#define	REGAD		0x000007C0	/* STA Register Address */
+#define	PHYAD		0x0000F800	/* PHY Device Address */
+
+#define	SET_REGAD(x)	(((x) & 0x1F) <<  6)	/* Set STA Register Address */
+#define	SET_PHYAD(x)	(((x) & 0x1F) << 11)	/* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+#define	STADATA		0x0000FFFF	/* Station Management Data */
+
+/* EMAC_FLC Masks */
+#define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define	FLCE		0x00000002	/* Flow Control Enable */
+#define	PCF		0x00000004	/* Pass Control Frames */
+#define	BKPRSEN		0x00000008	/* Enable Backpressure */
+#define	FLCPAUSE	0xFFFF0000	/* Pause Time */
+
+#define	SET_FLCPAUSE(x)	(((x) & 0xFFFF) << 16)	/* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+#define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames */
+#define	MPKE		0x00000002	/* Magic Packet Enable */
+#define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable */
+#define	GUWKE		0x00000008	/* Global Unicast Wake Enable */
+#define	MPKS		0x00000020	/* Magic Packet Received Status */
+#define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+#define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0 */
+#define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1 */
+#define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2 */
+#define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3 */
+#define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+#define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset */
+#define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset */
+#define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset */
+#define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset */
+
+#define	SET_WF0_OFF(x)	(((x) & 0xFF) <<  0)	/* Set Wake-Up Filter 0 Byte Offset */
+#define	SET_WF1_OFF(x)	(((x) & 0xFF) <<  8)	/* Set Wake-Up Filter 1 Byte Offset */
+#define	SET_WF2_OFF(x)	(((x) & 0xFF) << 16)	/* Set Wake-Up Filter 2 Byte Offset */
+#define	SET_WF3_OFF(x)	(((x) & 0xFF) << 24)	/* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define	SET_WF_OFFS(x0,x1,x2,x3)	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+#define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC */
+#define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC */
+
+#define	SET_WF0_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 0 Target CRC */
+#define	SET_WF1_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+#define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC */
+#define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC */
+
+#define	SET_WF2_CRC(x)	(((x) & 0xFFFF) << 0)	/* Set Wake-Up Filter 2 Target CRC */
+#define	SET_WF3_CRC(x)	(((x) & 0xFFFF) << 16)	/* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable */
+#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation */
+#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define	SET_MDCDIV(x)	(((x) & 0x3F) << 8)	/* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+#define	PHYINT		0x00000001	/* PHY_INT Interrupt Status */
+#define	MMCINT		0x00000002	/* MMC Counter Interrupt Status */
+#define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status */
+#define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status */
+#define	WAKEDET		0x00000010	/* Wake-Up Detected Status */
+#define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status */
+#define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status */
+#define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+#define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes */
+#define	RX_COMP		0x00001000	/* RX Frame Complete */
+#define	RX_OK		0x00002000	/* RX Frame Received With No Errors */
+#define	RX_LONG		0x00004000	/* RX Frame Too Long Error */
+#define	RX_ALIGN	0x00008000	/* RX Frame Alignment Error */
+#define	RX_CRC		0x00010000	/* RX Frame CRC Error */
+#define	RX_LEN		0x00020000	/* RX Frame Length Error */
+#define	RX_FRAG		0x00040000	/* RX Frame Fragment Error */
+#define	RX_ADDR		0x00080000	/* RX Frame Address Filter Failed Error */
+#define	RX_DMAO		0x00100000	/* RX Frame DMA Overrun Error */
+#define	RX_PHY		0x00200000	/* RX Frame PHY Error */
+#define	RX_LATE		0x00400000	/* RX Frame Late Collision Error */
+#define	RX_RANGE	0x00800000	/* RX Frame Length Field Out of Range Error */
+#define	RX_MULTI	0x01000000	/* RX Multicast Frame Indicator */
+#define	RX_BROAD	0x02000000	/* RX Broadcast Frame Indicator */
+#define	RX_CTL		0x04000000	/* RX Control Frame Indicator */
+#define	RX_UCTL		0x08000000	/* Unsupported RX Control Frame Indicator */
+#define	RX_TYPE		0x10000000	/* RX Typed Frame Indicator */
+#define	RX_VLAN1	0x20000000	/* RX VLAN1 Frame Indicator */
+#define	RX_VLAN2	0x40000000	/* RX VLAN2 Frame Indicator */
+#define	RX_ACCEPT	0x80000000	/* RX Frame Accepted Indicator */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+#define	TX_COMP		0x00000001	/* TX Frame Complete */
+#define	TX_OK		0x00000002	/* TX Frame Sent With No Errors */
+#define	TX_ECOLL	0x00000004	/* TX Frame Excessive Collision Error */
+#define	TX_LATE		0x00000008	/* TX Frame Late Collision Error */
+#define	TX_DMAU		0x00000010	/* TX Frame DMA Underrun Error (STAT) */
+#define	TX_MACE		0x00000010	/* Internal MAC Error Detected (STKY and IRQE) */
+#define	TX_EDEFER	0x00000020	/* TX Frame Excessive Deferral Error */
+#define	TX_BROAD	0x00000040	/* TX Broadcast Frame Indicator */
+#define	TX_MULTI	0x00000080	/* TX Multicast Frame Indicator */
+#define	TX_CCNT		0x00000F00	/* TX Frame Collision Count */
+#define	TX_DEFER	0x00001000	/* TX Frame Deferred Indicator */
+#define	TX_CRS		0x00002000	/* TX Frame Carrier Sense Not Asserted Error */
+#define	TX_LOSS		0x00004000	/* TX Frame Carrier Lost During TX Error */
+#define	TX_RETRY	0x00008000	/* TX Frame Successful After Retry */
+#define	TX_FRLEN	0x07FF0000	/* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define	RSTC		0x00000001	/* Reset All Counters */
+#define	CROLL		0x00000002	/* Counter Roll-Over Enable */
+#define	CCOR		0x00000004	/* Counter Clear-On-Read Mode Enable */
+#define	MMCE		0x00000008	/* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define	RX_OK_CNT	0x00000001	/* RX Frames Received With No Errors */
+#define	RX_FCS_CNT	0x00000002	/* RX Frames W/Frame Check Sequence Errors */
+#define	RX_ALIGN_CNT	0x00000004	/* RX Frames With Alignment Errors */
+#define	RX_OCTET_CNT	0x00000008	/* RX Octets Received OK */
+#define	RX_LOST_CNT	0x00000010	/* RX Frames Lost Due To Internal MAC RX Error */
+#define	RX_UNI_CNT	0x00000020	/* Unicast RX Frames Received OK */
+#define	RX_MULTI_CNT	0x00000040	/* Multicast RX Frames Received OK */
+#define	RX_BROAD_CNT	0x00000080	/* Broadcast RX Frames Received OK */
+#define	RX_IRL_CNT	0x00000100	/* RX Frames With In-Range Length Errors */
+#define	RX_ORL_CNT	0x00000200	/* RX Frames With Out-Of-Range Length Errors */
+#define	RX_LONG_CNT	0x00000400	/* RX Frames With Frame Too Long Errors */
+#define	RX_MACCTL_CNT	0x00000800	/* MAC Control RX Frames Received */
+#define	RX_OPCODE_CTL	0x00001000	/* Unsupported Op-Code RX Frames Received */
+#define	RX_PAUSE_CNT	0x00002000	/* PAUSEMAC Control RX Frames Received */
+#define	RX_ALLF_CNT	0x00004000	/* All RX Frames Received */
+#define	RX_ALLO_CNT	0x00008000	/* All RX Octets Received */
+#define	RX_TYPED_CNT	0x00010000	/* Typed RX Frames Received */
+#define	RX_SHORT_CNT	0x00020000	/* RX Frame Fragments (< 64 Bytes) Received */
+#define	RX_EQ64_CNT	0x00040000	/* 64-Byte RX Frames Received */
+#define	RX_LT128_CNT	0x00080000	/* 65-127-Byte RX Frames Received */
+#define	RX_LT256_CNT	0x00100000	/* 128-255-Byte RX Frames Received */
+#define	RX_LT512_CNT	0x00200000	/* 256-511-Byte RX Frames Received */
+#define	RX_LT1024_CNT	0x00400000	/* 512-1023-Byte RX Frames Received */
+#define	RX_GE1024_CNT	0x00800000	/* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+#define	TX_OK_CNT	0x00000001	/* TX Frames Sent OK */
+#define	TX_SCOLL_CNT	0x00000002	/* TX Frames With Single Collisions */
+#define	TX_MCOLL_CNT	0x00000004	/* TX Frames With Multiple Collisions */
+#define	TX_OCTET_CNT	0x00000008	/* TX Octets Sent OK */
+#define	TX_DEFER_CNT	0x00000010	/* TX Frames With Deferred Transmission */
+#define	TX_LATE_CNT	0x00000020	/* TX Frames With Late Collisions */
+#define	TX_ABORTC_CNT	0x00000040	/* TX Frames Aborted Due To Excess Collisions */
+#define	TX_LOST_CNT	0x00000080	/* TX Frames Lost Due To Internal MAC TX Error */
+#define	TX_CRS_CNT	0x00000100	/* TX Frames With Carrier Sense Errors */
+#define	TX_UNI_CNT	0x00000200	/* Unicast TX Frames Sent */
+#define	TX_MULTI_CNT	0x00000400	/* Multicast TX Frames Sent */
+#define	TX_BROAD_CNT	0x00000800	/* Broadcast TX Frames Sent */
+#define	TX_EXDEF_CTL	0x00001000	/* TX Frames With Excessive Deferral */
+#define	TX_MACCTL_CNT	0x00002000	/* MAC Control TX Frames Sent */
+#define	TX_ALLF_CNT	0x00004000	/* All TX Frames Sent */
+#define	TX_ALLO_CNT	0x00008000	/* All TX Octets Sent */
+#define	TX_EQ64_CNT	0x00010000	/* 64-Byte TX Frames Sent */
+#define	TX_LT128_CNT	0x00020000	/* 65-127-Byte TX Frames Sent */
+#define	TX_LT256_CNT	0x00040000	/* 128-255-Byte TX Frames Sent */
+#define	TX_LT512_CNT	0x00080000	/* 256-511-Byte TX Frames Sent */
+#define	TX_LT1024_CNT	0x00100000	/* 512-1023-Byte TX Frames Sent */
+#define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent */
+#define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/eppi.h b/arch/blackfin/include/asm/mach-common/bits/eppi.h
new file mode 100644
index 0000000..fb1456f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/eppi.h
@@ -0,0 +1,70 @@
+/*
+ * Enhanced PPI (EPPI)
+ */
+
+#ifndef __BFIN_PERIPHERAL_EPPI__
+#define __BFIN_PERIPHERAL_EPPI__
+
+/* Bit masks for EPPIx_STATUS */
+#define CFIFO_ERR              0x0001        /* Chroma FIFO Error */
+#define YFIFO_ERR              0x0002        /* Luma FIFO Error */
+#define LTERR_OVR              0x0004        /* Line Track Overflow */
+#define LTERR_UNDR             0x0008        /* Line Track Underflow */
+#define FTERR_OVR              0x0010        /* Frame Track Overflow */
+#define FTERR_UNDR             0x0020        /* Frame Track Underflow */
+#define ERR_NCOR               0x0040        /* Preamble Error Not Corrected */
+#define DMA1URQ                0x0080        /* DMA1 Urgent Request */
+#define DMA0URQ                0x0100        /* DMA0 Urgent Request */
+#define ERR_DET                0x4000        /* Preamble Error Detected */
+#define FLD                    0x8000        /* Field */
+
+/* Bit masks for EPPIx_CONTROL */
+#define EPPI_EN                0x00000001    /* Enable */
+#define EPPI_DIR               0x00000002    /* Direction */
+#define XFR_TYPE               0x0000000c    /* Operating Mode */
+#define FS_CFG                 0x00000030    /* Frame Sync Configuration */
+#define FLD_SEL                0x00000040    /* Field Select/Trigger */
+#define ITU_TYPE               0x00000080    /* ITU Interlaced or Progressive */
+#define BLANKGEN               0x00000100    /* ITU Output Mode with Internal Blanking Generation */
+#define ICLKGEN                0x00000200    /* Internal Clock Generation */
+#define IFSGEN                 0x00000400    /* Internal Frame Sync Generation */
+#define POLC                   0x00001800    /* Frame Sync and Data Driving/Sampling Edges */
+#define POLS                   0x00006000    /* Frame Sync Polarity */
+#define DLENGTH                0x00038000    /* Data Length */
+#define SKIP_EN                0x00040000    /* Skip Enable */
+#define SKIP_EO                0x00080000    /* Skip Even or Odd */
+#define PACKEN                 0x00100000    /* Packing/Unpacking Enable */
+#define SWAPEN                 0x00200000    /* Swap Enable */
+#define SIGN_EXT               0x00400000    /* Sign Extension or Zero-filled / Data Split Format */
+#define SPLT_EVEN_ODD          0x00800000    /* Split Even and Odd Data Samples */
+#define SUBSPLT_ODD            0x01000000    /* Sub-split Odd Samples */
+#define DMACFG                 0x02000000    /* One or Two DMA Channels Mode */
+#define RGB_FMT_EN             0x04000000    /* RGB Formatting Enable */
+#define FIFO_RWM               0x18000000    /* FIFO Regular Watermarks */
+#define FIFO_UWM               0x60000000    /* FIFO Urgent Watermarks */
+
+#define DLEN_8                 (0 << 15)     /* 000 - 8 bits */
+#define DLEN_10                (1 << 15)     /* 001 - 10 bits */
+#define DLEN_12                (2 << 15)     /* 010 - 12 bits */
+#define DLEN_14                (3 << 15)     /* 011 - 14 bits */
+#define DLEN_16                (4 << 15)     /* 100 - 16 bits */
+#define DLEN_18                (5 << 15)     /* 101 - 18 bits */
+#define DLEN_24                (6 << 15)     /* 110 - 24 bits */
+
+/* Bit masks for EPPIx_FS2W_LVB */
+#define F1VB_BD                0x000000ff    /* Vertical Blanking before Field 1 Active Data */
+#define F1VB_AD                0x0000ff00    /* Vertical Blanking after Field 1 Active Data */
+#define F2VB_BD                0x00ff0000    /* Vertical Blanking before Field 2 Active Data */
+#define F2VB_AD                0xff000000    /* Vertical Blanking after Field 2 Active Data */
+
+/* Bit masks for EPPIx_FS2W_LAVF */
+#define F1_ACT                 0x0000ffff    /* Number of Lines of Active Data in Field 1 */
+#define F2_ACT                 0xffff0000    /* Number of Lines of Active Data in Field 2 */
+
+/* Bit masks for EPPIx_CLIP */
+#define LOW_ODD                0x000000ff    /* Lower Limit for Odd Bytes (Chroma) */
+#define HIGH_ODD               0x0000ff00    /* Upper Limit for Odd Bytes (Chroma) */
+#define LOW_EVEN               0x00ff0000    /* Lower Limit for Even Bytes (Luma) */
+#define HIGH_EVEN              0xff000000    /* Upper Limit for Even Bytes (Luma) */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/lockbox.h b/arch/blackfin/include/asm/mach-common/bits/lockbox.h
new file mode 100644
index 0000000..77f849e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/lockbox.h
@@ -0,0 +1,62 @@
+/*
+ * Lockbox/Security Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_LOCKBOX__
+#define __BFIN_PERIPHERAL_LOCKBOX__
+
+#ifndef __ASSEMBLY__
+
+#include "bootrom.h"
+
+/* SESR argument structure. Expected to reside at 0xFF900018. */
+typedef struct SESR_args {
+	unsigned short  usFlags;            /* security firmware flags            */
+	unsigned short  usIRQMask;          /* interrupt mask                     */
+	unsigned long   ulMessageSize;      /* message length in bytes            */
+	unsigned long   ulSFEntryPoint;     /* entry point of secure function     */
+	unsigned long   ulMessagePtr;       /* pointer to the buffer containing
+	                                       the digital signature and message  */
+	unsigned long   ulReserved1;        /* reserved                           */
+	unsigned long   ulReserved2;        /* reserved                           */
+} tSESR_args;
+
+/* Secure Entry Service Routine */
+static void (* const sesr)(void) = (void *)_BOOTROM_SESR;
+
+#endif
+
+/* SESR flags argument bitfields */
+#define SESR_FLAGS_STAY_AT_NMI              0x0000
+#define SESR_FLAGS_DROP_BELOW_NMI           0x0001
+#define SESR_FLAGS_NO_SF_DMA                0x0000
+#define SESR_FLAGS_DMA_SF_TO_RUN_DEST       0x0002
+#define SESR_FLAGS_USE_ADI_PUB_KEY          0x0000
+#define SESR_FLAGS_USE_CUST_PUB_KEY         0x0100
+
+/* Bit masks for SECURE_SYSSWT */
+#define EMUDABL                0x00000001    /* Emulation Disable */
+#define RSTDABL                0x00000002    /* Reset Disable */
+#define L1IDABL                0x0000001c    /* L1 Instruction Memory Disable */
+#define L1DADABL               0x000000e0    /* L1 Data Bank A Memory Disable */
+#define L1DBDABL               0x00000700    /* L1 Data Bank B Memory Disable */
+#define DMA0OVR                0x00000800    /* DMA0 Memory Access Override */
+#define DMA1OVR                0x00001000    /* DMA1 Memory Access Override */
+#define EMUOVR                 0x00004000    /* Emulation Override */
+#define OTPSEN                 0x00008000    /* OTP Secrets Enable */
+#define L2DABL                 0x00070000    /* L2 Memory Disable */
+
+/* Bit masks for SECURE_CONTROL */
+#define SECURE0                0x0001        /* SECURE 0 */
+#define SECURE1                0x0002        /* SECURE 1 */
+#define SECURE2                0x0004        /* SECURE 2 */
+#define SECURE3                0x0008        /* SECURE 3 */
+
+/* Bit masks for SECURE_STATUS */
+#define SECMODE                0x0003        /* Secured Mode Control State */
+#define NMI                    0x0004        /* Non Maskable Interrupt */
+#define AFVALID                0x0008        /* Authentication Firmware Valid */
+#define AFEXIT                 0x0010        /* Authentication Firmware Exit */
+#define SECSTAT                0x00e0        /* Secure Status */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
new file mode 100644
index 0000000..39998f8
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h
@@ -0,0 +1,116 @@
+/*
+ * MPU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_MPU__
+#define __BFIN_PERIPHERAL_MPU__
+
+/*
+ * DMEM_CONTROL Register
+ */
+
+/* ** Bit Positions */
+#define ENDM_P			0x00	/* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P		ENDM_P	/* "" (older define) */
+#define ENDCPLB_P		0x01	/* Enable DCPLBS */
+#define DMCTL_ENDCPLB_P		ENDCPLB_P	/* "" (older define) */
+#define DMC0_P			0x02	/* L1 Data Memory Configure bit 0 */
+#define DMCTL_DMC0_P		DMC0_P	/* "" (older define) */
+#define DMC1_P			0x03	/* L1 Data Memory Configure bit 1 */
+#define DMCTL_DMC1_P		DMC1_P	/* "" (older define) */
+#define DCBS_P			0x04	/* L1 Data Cache Bank Select */
+#define PORT_PREF0_P		0x12	/* DAG0 Port Preference */
+#define PORT_PREF1_P		0x13	/* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM			0x00000001	/* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB			0x00000002	/* Enable DCPLB */
+#define ASRAM_BSRAM		0x00000000
+#define ACACHE_BSRAM		0x00000008
+#define ACACHE_BCACHE		0x0000000C
+#define DCBS			0x00000010	/*  L1 Data Cache Bank Select */
+#define PORT_PREF0		0x00001000	/* DAG0 Port Preference */
+#define PORT_PREF1		0x00002000	/* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P			0x00	/* Enable L1 Code Memory */
+#define IMCTL_ENIM_P		0x00	/* "" (older define) */
+#define ENICPLB_P		0x01	/* Enable ICPLB */
+#define IMCTL_ENICPLB_P		0x01	/* "" (older define) */
+#define IMC_P			0x02	/* Enable */
+#define IMCTL_IMC_P		0x02	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P			0x03	/* Lock Way 0 */
+#define ILOC1_P			0x04	/* Lock Way 1 */
+#define ILOC2_P			0x05	/* Lock Way 2 */
+#define ILOC3_P			0x06	/* Lock Way 3 */
+#define LRUPRIORST_P		0x0D	/* Least Recently Used Replacement Priority */
+
+/* ** Masks */
+#define ENIM			0x00000001	/* Enable L1 Code Memory */
+#define ENICPLB			0x00000002	/* Enable ICPLB */
+#define IMC			0x00000004	/* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0			0x00000008	/* Lock Way 0 */
+#define ILOC1			0x00000010	/* Lock Way 1 */
+#define ILOC2			0x00000020	/* Lock Way 2 */
+#define ILOC3			0x00000040	/* Lock Way 3 */
+#define LRUPRIORST		0x00002000	/* Least Recently Used Replacement Priority */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* ** Bit Positions */
+#define CPLB_VALID_P		0x00000000	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P		0x00000001	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P		0x00000002	/* 0=no read access, 1=read access allowed (user mode) */
+
+/* ** Masks */
+#define CPLB_VALID		0x00000001	/* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK		0x00000002	/* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD		0x00000004	/* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB		0x00000000	/* 1 KB page size */
+#define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
+#define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
+#define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
+#define PAGE_SIZE_MASK		0x00030000	/* the bits for the page_size field */
+#define PAGE_SIZE_SHIFT		16
+#define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL		0x00001000	/* 0=non-cacheable in L1, 1=cacheable in L1 */
+
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO		0x00000100	/* 0=can be replaced by any line, 1=priority for non-replacement */
+
+/* DCPLB_DATA only */
+#define CPLB_USER_WR		0x00000008	/* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR		0x00000010	/* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY		0x00000080	/* 1=dirty, 0=clean */
+#define CPLB_L1_AOW		0x00008000	/* 0=do not allocate cache lines on write-through writes, */
+						/* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT			0x00004000	/* 0=write-back, 1=write-through */
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* ** Masks */
+#define TEST_READ		0x00000000	/* Read Access */
+#define TEST_WRITE		0x00000002	/* Write Access */
+#define TEST_TAG		0x00000000	/* Access TAG */
+#define TEST_DATA		0x00000004	/* Access DATA */
+#define TEST_DW0		0x00000000	/* Select Double Word 0 */
+#define TEST_DW1		0x00000008	/* Select Double Word 1 */
+#define TEST_DW2		0x00000010	/* Select Double Word 2 */
+#define TEST_DW3		0x00000018	/* Select Double Word 3 */
+#define TEST_MB0		0x00000000	/* Select Mini-Bank 0 */
+#define TEST_MB1		0x00010000	/* Select Mini-Bank 1 */
+#define TEST_MB2		0x00020000	/* Select Mini-Bank 2 */
+#define TEST_MB3		0x00030000	/* Select Mini-Bank 3 */
+#define TEST_SET(x)		((x << 5) & 0x03E0)	/* Set Index 0->31 */
+#define TEST_WAY0		0x00000000	/* Access Way0 */
+#define TEST_WAY1		0x04000000	/* Access Way1 */
+
+/* ** ITEST_COMMAND only */
+#define TEST_WAY2		0x08000000	/* Access Way2 */
+#define TEST_WAY3		0x0C000000	/* Access Way3 */
+
+/* ** DTEST_COMMAND only */
+#define TEST_BNKSELA		0x00000000	/* Access SuperBank A */
+#define TEST_BNKSELB		0x00800000	/* Access SuperBank B */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/otp.h b/arch/blackfin/include/asm/mach-common/bits/otp.h
new file mode 100644
index 0000000..4e3f1af
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/otp.h
@@ -0,0 +1,71 @@
+/*
+ * OTP Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_OTP__
+#define __BFIN_PERIPHERAL_OTP__
+
+#ifndef __ASSEMBLY__
+
+#include "bootrom.h"
+
+static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND;
+static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ;
+static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE;
+
+#endif
+
+/* otp_command(): defines for "command" */
+#define OTP_INIT                 0x00000001
+#define OTP_CLOSE                0x00000002
+
+/* otp_{read,write}(): defines for "flags" */
+#define OTP_LOWER_HALF           0x00000000 /* select upper/lower 64-bit half (bit 0) */
+#define OTP_UPPER_HALF           0x00000001
+#define OTP_NO_ECC               0x00000010 /* do not use ECC */
+#define OTP_LOCK                 0x00000020 /* sets page protection bit for page */
+#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
+
+/* Return values for all functions */
+#define OTP_SUCCESS          0x00000000
+#define OTP_MASTER_ERROR     0x001
+#define OTP_WRITE_ERROR      0x003
+#define OTP_READ_ERROR       0x005
+#define OTP_ACC_VIO_ERROR    0x009
+#define OTP_DATA_MULT_ERROR  0x011
+#define OTP_ECC_MULT_ERROR   0x021
+#define OTP_PREV_WR_ERROR    0x041
+#define OTP_DATA_SB_WARN     0x100
+#define OTP_ECC_SB_WARN      0x200
+
+/* Predefined otp pages: Factory Programmed Settings */
+#define FPS00                0x0004
+#define FPS01                0x0005
+#define FPS02                0x0006
+#define FPS03                0x0007
+#define FPS04                0x0008
+#define FPS05                0x0009
+#define FPS06                0x000A
+#define FPS07                0x000B
+#define FPS08                0x000C
+#define FPS09                0x000D
+#define FPS10                0x000E
+#define FPS11                0x000F
+
+/* Predefined otp pages: Customer Programmed Settings */
+#define CPS00                0x0010
+#define CPS01                0x0011
+#define CPS02                0x0012
+#define CPS03                0x0013
+#define CPS04                0x0014
+#define CPS05                0x0015
+#define CPS06                0x0016
+#define CPS07                0x0017
+
+/* Predefined otp pages: Pre-Boot Settings */
+#define PBS00                0x0018
+#define PBS01                0x0019
+#define PBS02                0x001A
+#define PBS03                0x001B
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/pata.h b/arch/blackfin/include/asm/mach-common/bits/pata.h
new file mode 100644
index 0000000..9b61824
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/pata.h
@@ -0,0 +1,220 @@
+/*
+ * ATAPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PATA__
+#define __BFIN_PERIPHERAL_PATA__
+
+/* Bit masks for ATAPI_CONTROL */
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+
+/* Bit masks for ATAPI_INT_STATUS */
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+
+/* Bit masks for ATAPI_LINE_STATUS */
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_SM_STATE */
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+/* Bit masks for ATAPI_CONTROL */
+#define                 PIO_START  0x1        /* Start PIO/Reg Op */
+#define               MULTI_START  0x2        /* Start Multi-DMA Op */
+#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
+#define                  XFER_DIR  0x8        /* Transfer Direction */
+#define                  IORDY_EN  0x10       /* IORDY Enable */
+#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
+#define                  SOFT_RST  0x40       /* Soft Reset */
+#define                   DEV_RST  0x80       /* Device Reset */
+#define                TFRCNT_RST  0x100      /* Trans Count Reset */
+#define               END_ON_TERM  0x200      /* End/Terminate Select */
+#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
+#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
+#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
+#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
+#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+#define                  DEV_ADDR  0x1f       /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
+#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
+#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
+#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
+#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
+#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
+#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
+#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
+
+/* Bit masks for ATAPI_INT_STATUS */
+#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
+#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
+#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
+#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
+#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
+#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
+#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
+#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
+
+/* Bit masks for ATAPI_LINE_STATUS */
+#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
+#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
+#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
+#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
+#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
+#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
+#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
+#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
+#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
+#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_SM_STATE */
+#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
+#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
+#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
+#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
+#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
+#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
+#define                    T4_REG  0xf000     /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
+#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
+#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+#define                        TH  0xff       /* Selects DIOW data hold */
+#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+#define                      TACK  0xff       /* Selects setup and hold times for TACK */
+#define                      TENV  0xff00     /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+#define                      TDVS  0xff       /* Selects data valid setup time */
+#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define                      TMLI  0xff00     /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+#define                      TZAH  0xff       /* Selects minimum delay required for output */
+#define               READY_PAUSE  0xff00     /* Selects ready to pause */
+
+#endif /* __BFIN_PERIPHERAL_PATA__ */
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
new file mode 100644
index 0000000..9009f26
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/pll.h
@@ -0,0 +1,96 @@
+/*
+ * PLL Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PLL__
+#define __BFIN_PERIPHERAL_PLL__
+
+/* PLL_CTL Masks */
+#define DF			0x0001		/* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF			0x0002		/* PLL Not Powered */
+#define STOPCK			0x0008		/* Core Clock Off */
+#define PDWN			0x0020		/* Enter Deep Sleep Mode */
+#define IN_DELAY		0x0040		/* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY		0x0080		/* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS			0x0100		/* Bypass the PLL */
+#define MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
+#define SPORT_HYST		0x8000		/* Enable Additional Hysteresis on SPORT Input Pins */
+
+/* PLL_DIV Masks */
+#define SSEL			0x000F		/* System Select */
+#define CSEL			0x0030		/* Core Select */
+#define CSEL_DIV1		0x0000		/* CCLK = VCO / 1 */
+#define CSEL_DIV2		0x0010		/* CCLK = VCO / 2 */
+#define CSEL_DIV4		0x0020		/* CCLK = VCO / 4 */
+#define CSEL_DIV8		0x0030		/* CCLK = VCO / 8 */
+
+#define CCLK_DIV1		CSEL_DIV1
+#define CCLK_DIV2		CSEL_DIV2
+#define CCLK_DIV4		CSEL_DIV4
+#define CCLK_DIV8		CSEL_DIV8
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
+#define FULL_ON			0x0002		/* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED	0x0004		/* Processor In Active Mode With PLL Disabled */
+#define DEEP_SLEEP		0x0008		/* Processor In Deep Sleep Mode */
+#define SLEEP			0x0010		/* Processor In Sleep Mode */
+#define PLL_LOCKED		0x0020		/* PLL_LOCKCNT Has Been Reached */
+#define CORE_IDLE		0x0040		/* Processor In IDLE Mode */
+#define VSTAT			0x0080		/* Voltage Regulator Has Reached Programmed Voltage */
+
+/* VR_CTL Masks */
+#ifdef __ADSPBF52x__
+#define FREQ_MASK		0x3000		/* Switching Oscillator Frequency For Regulator */
+#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
+#define FREQ_1000		0x3000		/* Switching Frequency Is 1 MHz */
+#else
+#define FREQ_MASK		0x0003		/* Switching Oscillator Frequency For Regulator */
+#define FREQ_HIBERNATE		0x0000		/* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333		0x0001		/* Switching Frequency Is 333 kHz */
+#define FREQ_667		0x0002		/* Switching Frequency Is 667 kHz */
+#define FREQ_1000		0x0003		/* Switching Frequency Is 1 MHz */
+#endif
+
+#define GAIN_MASK		0x000C		/* Voltage Level Gain */
+#define GAIN_5			0x0000		/* GAIN = 5 */
+#define GAIN_10			0x0004		/* GAIN = 10 */
+#define GAIN_20			0x0008		/* GAIN = 20 */
+#define GAIN_50			0x000C		/* GAIN = 50 */
+
+#ifdef __ADSPBF52x__
+#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
+#define VLEV_085		0x0040		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090		0x0050		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095		0x0060		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100		0x0070		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105		0x0080		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110		0x0090		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115		0x00A0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120		0x00B0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#else
+#define VLEV_MASK		0x00F0		/* Internal Voltage Level */
+#define VLEV_085		0x0060		/* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090		0x0070		/* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095		0x0080		/* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100		0x0090		/* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105		0x00A0		/* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110		0x00B0		/* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115		0x00C0		/* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120		0x00D0		/* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125		0x00E0		/* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130		0x00F0		/* VLEV = 1.30 V (-5% - +10% Accuracy) */
+#endif
+
+#define WAKE			0x0100		/* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE			0x0200		/* Enable CAN Wakeup From Hibernate */
+#define PHYWE			0x0400		/* Enable PHY Wakeup From Hibernate */
+#define GPWE			0x0400		/* General-purpose Wakeup From Hibernate */
+#define MXVRWE			0x0400		/* MXVR Wakeup From Hibernate */
+#define USBWE			0x0800		/* USB Wakeup From Hibernate */
+#define KPADWE			0x1000		/* Keypad Wakeup From Hibernate */
+#define ROTWE			0x2000		/* Rotary Counter Wakeup From Hibernate */
+#define CLKBUFOE		0x4000		/* CLKIN Buffer Output Enable */
+#define CKELOW			0x8000		/* Enable Drive CKE Low During Reset */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-a.h b/arch/blackfin/include/asm/mach-common/bits/ports-a.h
new file mode 100644
index 0000000..9f78a76
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-a.h
@@ -0,0 +1,25 @@
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0		(1 << 0)
+#define PA1		(1 << 1)
+#define PA2		(1 << 2)
+#define PA3		(1 << 3)
+#define PA4		(1 << 4)
+#define PA5		(1 << 5)
+#define PA6		(1 << 6)
+#define PA7		(1 << 7)
+#define PA8		(1 << 8)
+#define PA9		(1 << 9)
+#define PA10		(1 << 10)
+#define PA11		(1 << 11)
+#define PA12		(1 << 12)
+#define PA13		(1 << 13)
+#define PA14		(1 << 14)
+#define PA15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-b.h b/arch/blackfin/include/asm/mach-common/bits/ports-b.h
new file mode 100644
index 0000000..b81702f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-b.h
@@ -0,0 +1,25 @@
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0		(1 << 0)
+#define PB1		(1 << 1)
+#define PB2		(1 << 2)
+#define PB3		(1 << 3)
+#define PB4		(1 << 4)
+#define PB5		(1 << 5)
+#define PB6		(1 << 6)
+#define PB7		(1 << 7)
+#define PB8		(1 << 8)
+#define PB9		(1 << 9)
+#define PB10		(1 << 10)
+#define PB11		(1 << 11)
+#define PB12		(1 << 12)
+#define PB13		(1 << 13)
+#define PB14		(1 << 14)
+#define PB15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-c.h b/arch/blackfin/include/asm/mach-common/bits/ports-c.h
new file mode 100644
index 0000000..3cc665e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-c.h
@@ -0,0 +1,25 @@
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0		(1 << 0)
+#define PC1		(1 << 1)
+#define PC2		(1 << 2)
+#define PC3		(1 << 3)
+#define PC4		(1 << 4)
+#define PC5		(1 << 5)
+#define PC6		(1 << 6)
+#define PC7		(1 << 7)
+#define PC8		(1 << 8)
+#define PC9		(1 << 9)
+#define PC10		(1 << 10)
+#define PC11		(1 << 11)
+#define PC12		(1 << 12)
+#define PC13		(1 << 13)
+#define PC14		(1 << 14)
+#define PC15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-d.h b/arch/blackfin/include/asm/mach-common/bits/ports-d.h
new file mode 100644
index 0000000..868c6a0
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-d.h
@@ -0,0 +1,25 @@
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0		(1 << 0)
+#define PD1		(1 << 1)
+#define PD2		(1 << 2)
+#define PD3		(1 << 3)
+#define PD4		(1 << 4)
+#define PD5		(1 << 5)
+#define PD6		(1 << 6)
+#define PD7		(1 << 7)
+#define PD8		(1 << 8)
+#define PD9		(1 << 9)
+#define PD10		(1 << 10)
+#define PD11		(1 << 11)
+#define PD12		(1 << 12)
+#define PD13		(1 << 13)
+#define PD14		(1 << 14)
+#define PD15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-e.h b/arch/blackfin/include/asm/mach-common/bits/ports-e.h
new file mode 100644
index 0000000..c88b0d0
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-e.h
@@ -0,0 +1,25 @@
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0		(1 << 0)
+#define PE1		(1 << 1)
+#define PE2		(1 << 2)
+#define PE3		(1 << 3)
+#define PE4		(1 << 4)
+#define PE5		(1 << 5)
+#define PE6		(1 << 6)
+#define PE7		(1 << 7)
+#define PE8		(1 << 8)
+#define PE9		(1 << 9)
+#define PE10		(1 << 10)
+#define PE11		(1 << 11)
+#define PE12		(1 << 12)
+#define PE13		(1 << 13)
+#define PE14		(1 << 14)
+#define PE15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-f.h b/arch/blackfin/include/asm/mach-common/bits/ports-f.h
new file mode 100644
index 0000000..d6af206
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-f.h
@@ -0,0 +1,25 @@
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0		(1 << 0)
+#define PF1		(1 << 1)
+#define PF2		(1 << 2)
+#define PF3		(1 << 3)
+#define PF4		(1 << 4)
+#define PF5		(1 << 5)
+#define PF6		(1 << 6)
+#define PF7		(1 << 7)
+#define PF8		(1 << 8)
+#define PF9		(1 << 9)
+#define PF10		(1 << 10)
+#define PF11		(1 << 11)
+#define PF12		(1 << 12)
+#define PF13		(1 << 13)
+#define PF14		(1 << 14)
+#define PF15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-g.h b/arch/blackfin/include/asm/mach-common/bits/ports-g.h
new file mode 100644
index 0000000..09355d3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-g.h
@@ -0,0 +1,25 @@
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0		(1 << 0)
+#define PG1		(1 << 1)
+#define PG2		(1 << 2)
+#define PG3		(1 << 3)
+#define PG4		(1 << 4)
+#define PG5		(1 << 5)
+#define PG6		(1 << 6)
+#define PG7		(1 << 7)
+#define PG8		(1 << 8)
+#define PG9		(1 << 9)
+#define PG10		(1 << 10)
+#define PG11		(1 << 11)
+#define PG12		(1 << 12)
+#define PG13		(1 << 13)
+#define PG14		(1 << 14)
+#define PG15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-h.h b/arch/blackfin/include/asm/mach-common/bits/ports-h.h
new file mode 100644
index 0000000..fa3910c
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-h.h
@@ -0,0 +1,25 @@
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0		(1 << 0)
+#define PH1		(1 << 1)
+#define PH2		(1 << 2)
+#define PH3		(1 << 3)
+#define PH4		(1 << 4)
+#define PH5		(1 << 5)
+#define PH6		(1 << 6)
+#define PH7		(1 << 7)
+#define PH8		(1 << 8)
+#define PH9		(1 << 9)
+#define PH10		(1 << 10)
+#define PH11		(1 << 11)
+#define PH12		(1 << 12)
+#define PH13		(1 << 13)
+#define PH14		(1 << 14)
+#define PH15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-i.h b/arch/blackfin/include/asm/mach-common/bits/ports-i.h
new file mode 100644
index 0000000..f176f08
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-i.h
@@ -0,0 +1,25 @@
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0		(1 << 0)
+#define PI1		(1 << 1)
+#define PI2		(1 << 2)
+#define PI3		(1 << 3)
+#define PI4		(1 << 4)
+#define PI5		(1 << 5)
+#define PI6		(1 << 6)
+#define PI7		(1 << 7)
+#define PI8		(1 << 8)
+#define PI9		(1 << 9)
+#define PI10		(1 << 10)
+#define PI11		(1 << 11)
+#define PI12		(1 << 12)
+#define PI13		(1 << 13)
+#define PI14		(1 << 14)
+#define PI15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ports-j.h b/arch/blackfin/include/asm/mach-common/bits/ports-j.h
new file mode 100644
index 0000000..924123e
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ports-j.h
@@ -0,0 +1,25 @@
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0		(1 << 0)
+#define PJ1		(1 << 1)
+#define PJ2		(1 << 2)
+#define PJ3		(1 << 3)
+#define PJ4		(1 << 4)
+#define PJ5		(1 << 5)
+#define PJ6		(1 << 6)
+#define PJ7		(1 << 7)
+#define PJ8		(1 << 8)
+#define PJ9		(1 << 9)
+#define PJ10		(1 << 10)
+#define PJ11		(1 << 11)
+#define PJ12		(1 << 12)
+#define PJ13		(1 << 13)
+#define PJ14		(1 << 14)
+#define PJ15		(1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/ppi.h b/arch/blackfin/include/asm/mach-common/bits/ppi.h
new file mode 100644
index 0000000..523f238
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/ppi.h
@@ -0,0 +1,38 @@
+/*
+ * PPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PPI__
+#define __BFIN_PERIPHERAL_PPI__
+
+/* PPI_CONTROL Masks */
+#define PORT_EN			0x0001	/* PPI Port Enable */
+#define PORT_DIR		0x0002	/* PPI Port Direction */
+#define XFR_TYPE		0x000C	/* PPI Transfer Type */
+#define PORT_CFG		0x0030	/* PPI Port Configuration */
+#define FLD_SEL			0x0040	/* PPI Active Field Select */
+#define PACK_EN			0x0080	/* PPI Packing Mode */
+#define DMA32			0x0100	/* PPI 32-bit DMA Enable */
+#define SKIP_EN			0x0200	/* PPI Skip Element Enable */
+#define SKIP_EO			0x0400	/* PPI Skip Even/Odd Elements */
+#define DLENGTH			0x3800	/* PPI Data Length */
+#define DLEN_8			0x0000	/* Data Length = 8 Bits */
+#define DLEN_10			0x0800	/* Data Length = 10 Bits */
+#define DLEN_11			0x1000	/* Data Length = 11 Bits */
+#define DLEN_12			0x1800	/* Data Length = 12 Bits */
+#define DLEN_13			0x2000	/* Data Length = 13 Bits */
+#define DLEN_14			0x2800	/* Data Length = 14 Bits */
+#define DLEN_15			0x3000	/* Data Length = 15 Bits */
+#define DLEN_16			0x3800	/* Data Length = 16 Bits */
+#define POLC			0x4000	/* PPI Clock Polarity */
+#define POLS			0x8000	/* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define FLD			0x0400	/* Field Indicator */
+#define FT_ERR			0x0800	/* Frame Track Error */
+#define OVR			0x1000	/* FIFO Overflow Error */
+#define UNDR			0x2000	/* FIFO Underrun Error */
+#define ERR_DET			0x4000	/* Error Detected Indicator */
+#define ERR_NCOR		0x8000	/* Error Not Corrected Indicator */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/rtc.h b/arch/blackfin/include/asm/mach-common/bits/rtc.h
new file mode 100644
index 0000000..f5a0cdb
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/rtc.h
@@ -0,0 +1,42 @@
+/*
+ * RTC Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_RTC__
+#define __BFIN_PERIPHERAL_RTC__
+
+/* RTC_STAT and RTC_ALARM Masks */
+#define	RTC_SEC			0x0000003F	/* Real-Time Clock Seconds */
+#define	RTC_MIN			0x00000FC0	/* Real-Time Clock Minutes */
+#define	RTC_HR			0x0001F000	/* Real-Time Clock Hours */
+#define	RTC_DAY			0xFFFE0000	/* Real-Time Clock Days */
+
+#define RTC_SEC_P		0
+#define RTC_MIN_P		6
+#define RTC_HR_P		12
+#define RTC_DAY_P		17
+
+/*
+ * RTC_ALARM Macro
+ */
+#define SET_ALARM(day, hr, min, sec) \
+	( (((day) << RTC_DAY_P) & RTC_DAY) | \
+	  (((hr)  << RTC_HR_P ) & RTC_HR ) | \
+	  (((min) << RTC_MIN_P) & RTC_MIN) | \
+	  (((sec) << RTC_SEC_P) & RTC_SEC) )
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define	STOPWATCH		0x0001	/* Stopwatch Interrupt Enable */
+#define	ALARM			0x0002	/* Alarm Interrupt Enable */
+#define	SECOND			0x0004	/* Seconds (1 Hz) Interrupt Enable */
+#define	MINUTE			0x0008	/* Minutes Interrupt Enable */
+#define	HOUR			0x0010	/* Hours Interrupt Enable */
+#define	DAY			0x0020	/* 24 Hours (Days) Interrupt Enable */
+#define	DAY_ALARM		0x0040	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define	WRITE_PENDING		0x4000	/* Write Pending Status */
+#define	WRITE_COMPLETE		0x8000	/* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN			0x0001	/* Enable Prescaler, RTC Runs @1 Hz */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sdh.h b/arch/blackfin/include/asm/mach-common/bits/sdh.h
new file mode 100644
index 0000000..8c5dd33
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/sdh.h
@@ -0,0 +1,122 @@
+/*
+ * SDH Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SDH__
+#define __BFIN_PERIPHERAL_SDH__
+
+/* Bit masks for SDH_COMMAND */
+#define                   CMD_IDX  0x3f       /* Command Index */
+#define                   CMD_RSP  0x40       /* Response */
+#define                 CMD_L_RSP  0x80       /* Long Response */
+#define                 CMD_INT_E  0x100      /* Command Interrupt */
+#define                CMD_PEND_E  0x200      /* Command Pending */
+#define                     CMD_E  0x400      /* Command Enable */
+
+/* Bit masks for SDH_PWR_CTL */
+#define                    PWR_ON  0x3        /* Power On */
+#define                 SD_CMD_OD  0x40       /* Open Drain Output */
+#define                   ROD_CTL  0x80       /* Rod Control */
+
+/* Bit masks for SDH_CLK_CTL */
+#define                    CLKDIV  0xff       /* MC_CLK Divisor */
+#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
+#define                  PWR_SV_E  0x200      /* Power Save Enable */
+#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
+#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
+
+/* Bit masks for SDH_RESP_CMD */
+#define                  RESP_CMD  0x3f       /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+#define                     DTX_E  0x1        /* Data Transfer Enable */
+#define                   DTX_DIR  0x2        /* Data Transfer Direction */
+#define                  DTX_MODE  0x4        /* Data Transfer Mode */
+#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
+#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
+#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
+#define              CMD_TIME_OUT  0x4        /* CMD Time Out */
+#define              DAT_TIME_OUT  0x8        /* Data Time Out */
+#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
+#define                RX_OVERRUN  0x20       /* Receive Overrun */
+#define              CMD_RESP_END  0x40       /* CMD Response End */
+#define                  CMD_SENT  0x80       /* CMD Sent */
+#define                   DAT_END  0x100      /* Data End */
+#define             START_BIT_ERR  0x200      /* Start Bit Error */
+#define               DAT_BLK_END  0x400      /* Data Block End */
+#define                   CMD_ACT  0x800      /* CMD Active */
+#define                    TX_ACT  0x1000     /* Transmit Active */
+#define                    RX_ACT  0x2000     /* Receive Active */
+#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
+#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
+#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
+#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
+#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
+#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
+#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
+#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
+
+/* Bit masks for SDH_STATUS_CLR */
+#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
+#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
+#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
+#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
+#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
+#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
+#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
+#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
+#define              DAT_END_STAT  0x100      /* Data End Status */
+#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
+#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
+
+/* Bit masks for SDH_MASK0 */
+#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
+#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
+#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
+#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
+#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
+#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
+#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
+#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
+#define              DAT_END_MASK  0x100      /* Data End Mask */
+#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
+#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
+#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
+#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
+#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
+#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
+#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
+#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
+#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
+#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
+#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
+#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
+#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
+
+/* Bit masks for SDH_FIFO_CNT */
+#define                FIFO_COUNT  0x7fff     /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
+#define               SD_CARD_DET  0x10       /* SD Card Detect */
+
+/* Bit masks for SDH_E_MASK */
+#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
+#define                   SCD_MSK  0x40       /* Mask Card Detect */
+
+/* Bit masks for SDH_CFG */
+#define                   CLKS_EN  0x1        /* Clocks Enable */
+#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
+#define                       MWE  0x8        /* Moving Window Enable */
+#define                    SD_RST  0x10       /* SDMMC Reset */
+#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
+#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
+#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
+
+/* Bit masks for SDH_RD_WAIT_EN */
+#define                       RWR  0x1        /* Read Wait Request */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/spi.h b/arch/blackfin/include/asm/mach-common/bits/spi.h
new file mode 100644
index 0000000..869dcb0
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/spi.h
@@ -0,0 +1,67 @@
+/*
+ * SPI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SPI__
+#define __BFIN_PERIPHERAL_SPI__
+
+/* SPI_CTL Masks */
+#define	TIMOD			0x0003	/* Transfer Initiate Mode */
+#define RDBR_CORE		0x0000	/* RDBR Read Initiates, IRQ When RDBR Full */
+#define	TDBR_CORE		0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA		0x0002	/* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA		0x0003	/* DMA Write, DMA Until FIFO Full */
+#define SZ			0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE			0x0010	/* Slave-Select Input Enable */
+#define EMISO			0x0020	/* Enable MISO As Output */
+#define SIZE			0x0100	/* Size of Words (16/8* Bits) */
+#define LSBF			0x0200	/* LSB First */
+#define CPHA			0x0400	/* Clock Phase */
+#define CPOL			0x0800	/* Clock Polarity */
+#define MSTR			0x1000	/* Master/Slave* */
+#define WOM			0x2000	/* Write Open Drain Master */
+#define SPE			0x4000	/* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1			0x0002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2			0x0004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3			0x0008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4			0x0010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5			0x0020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6			0x0040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7			0x0080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1			0x0200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2			0x0400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3			0x0800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4			0x1000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5			0x2000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6			0x4000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7			0x8000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P			0x0001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P			0x0002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P			0x0003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P			0x0004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P			0x0005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P			0x0006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P			0x0007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P			0x0009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P			0x000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P			0x000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P			0x000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P			0x000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P			0x000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P			0x000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF			0x0001	/* SPI Finished (Single-Word Transfer Complete) */
+#define MODF			0x0002	/* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE			0x0004	/* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS			0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY			0x0010	/* Receive Error (Data Received With RDBR Full) */
+#define RXS			0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL			0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/sport.h b/arch/blackfin/include/asm/mach-common/bits/sport.h
new file mode 100644
index 0000000..88e7a5d
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/sport.h
@@ -0,0 +1,89 @@
+/*
+ * SPORT Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_SPORT__
+#define __BFIN_PERIPHERAL_SPORT__
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN			0x0001	/* TX enable */
+#define ITCLK			0x0002	/* Internal TX Clock Select */
+#define TDTYPE			0x000C	/* TX Data Formatting Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define TLSBIT			0x0010	/* TX Bit Order */
+#define ITFS			0x0200	/* Internal TX Frame Sync Select */
+#define TFSR			0x0400	/* TX Frame Sync Required Select */
+#define DITFS			0x0800	/* Data Independent TX Frame Sync Select */
+#define LTFS			0x1000	/* Low TX Frame Sync Select */
+#define LATFS			0x2000	/* Late TX Frame Sync Select */
+#define TCKFE			0x4000	/* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN			0x001F	/* TX Word Length */
+#define TXSE			0x0100	/* TX Secondary Enable */
+#define TSFSE			0x0200	/* TX Stereo Frame Sync Enable */
+#define TRFST			0x0400	/* TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN			0x0001	/* RX enable */
+#define IRCLK			0x0002	/* Internal RX Clock Select */
+#define RDTYPE			0x000C	/* RX Data Formatting Select */
+#define DTYPE_NORM		0x0004	/* Data Format Normal */
+#define DTYPE_ULAW		0x0008	/* Compand Using u-Law */
+#define DTYPE_ALAW		0x000C	/* Compand Using A-Law */
+#define RLSBIT			0x0010	/* RX Bit Order */
+#define IRFS			0x0200	/* Internal RX Frame Sync Select */
+#define RFSR			0x0400	/* RX Frame Sync Required Select */
+#define LRFS			0x1000	/* Low RX Frame Sync Select */
+#define LARFS			0x2000	/* Late RX Frame Sync Select */
+#define RCKFE			0x4000	/* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN			0x001F	/* RX Word Length */
+#define RXSE			0x0100	/* RX Secondary Enable */
+#define RSFSE			0x0200	/* RX Stereo Frame Sync Enable */
+#define RRFST			0x0400	/* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE			0x0001	/* RX FIFO Not Empty Status */
+#define RUVF			0x0002	/* RX Underflow Status */
+#define ROVF			0x0004	/* RX Overflow Status */
+#define TXF			0x0008	/* TX FIFO Full Status */
+#define TUVF			0x0010	/* TX Underflow Status */
+#define TOVF			0x0020	/* TX Overflow Status */
+#define TXHRE			0x0040	/* TX Hold Register Empty */
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE			0xF000	/* Multichannel Window Size Field */
+#define WOFF			0x03FF	/* Multichannel Window Offset Field */
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM			0x0003	/* Multichannel Clock Recovery Mode */
+#define REC_BYPASS		0x0000	/* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4		0x0002	/* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16		0x0003	/* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE			0x0004	/* Multichannel DMA Transmit Packing */
+#define MCDRXPE			0x0008	/* Multichannel DMA Receive Packing */
+#define MCMEN			0x0010	/* Multichannel Frame Mode Enable */
+#define FSDR			0x0080	/* Multichannel Frame Sync to Data Relationship */
+#define MFD			0xF000	/* Multichannel Frame Delay */
+#define MFD_0			0x0000	/* Multichannel Frame Delay = 0 */
+#define MFD_1			0x1000	/* Multichannel Frame Delay = 1 */
+#define MFD_2			0x2000	/* Multichannel Frame Delay = 2 */
+#define MFD_3			0x3000	/* Multichannel Frame Delay = 3 */
+#define MFD_4			0x4000	/* Multichannel Frame Delay = 4 */
+#define MFD_5			0x5000	/* Multichannel Frame Delay = 5 */
+#define MFD_6			0x6000	/* Multichannel Frame Delay = 6 */
+#define MFD_7			0x7000	/* Multichannel Frame Delay = 7 */
+#define MFD_8			0x8000	/* Multichannel Frame Delay = 8 */
+#define MFD_9			0x9000	/* Multichannel Frame Delay = 9 */
+#define MFD_10			0xA000	/* Multichannel Frame Delay = 10 */
+#define MFD_11			0xB000	/* Multichannel Frame Delay = 11 */
+#define MFD_12			0xC000	/* Multichannel Frame Delay = 12 */
+#define MFD_13			0xD000	/* Multichannel Frame Delay = 13 */
+#define MFD_14			0xE000	/* Multichannel Frame Delay = 14 */
+#define MFD_15			0xF000	/* Multichannel Frame Delay = 15 */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/timer.h b/arch/blackfin/include/asm/mach-common/bits/timer.h
new file mode 100644
index 0000000..9513f80
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/timer.h
@@ -0,0 +1,78 @@
+/*
+ * General Purpose Timer Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TIMER__
+#define __BFIN_PERIPHERAL_TIMER__
+
+/* TIMER_ENABLE Masks */
+#define TIMEN0			0x0001		/* Enable Timer 0					*/
+#define TIMEN1			0x0002		/* Enable Timer 1					*/
+#define TIMEN2			0x0004		/* Enable Timer 2					*/
+#define TIMEN3			0x0008		/* Enable Timer 3					*/
+#define TIMEN4			0x0010		/* Enable Timer 4					*/
+#define TIMEN5			0x0020		/* Enable Timer 5					*/
+#define TIMEN6			0x0040		/* Enable Timer 6					*/
+#define TIMEN7			0x0080		/* Enable Timer 7					*/
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
+#define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
+#define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
+#define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
+#define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
+#define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
+#define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
+#define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
+
+/* TIMER_STATUS Masks */
+#define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
+#define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
+#define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
+#define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
+#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
+#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
+#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
+#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
+#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
+#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
+#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
+#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
+#define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
+#define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
+#define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
+#define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
+#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
+#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
+#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
+#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
+#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
+#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
+#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
+#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
+#define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
+#define EXT_CLK			0x0003	/* External Clock Mode					*/
+#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
+#define PERIOD_CNT		0x0008	/* Period Count							*/
+#define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
+#define TIN_SEL			0x0020	/* Timer Input Select					*/
+#define OUT_DIS			0x0040	/* Output Pad Disable					*/
+#define CLK_SEL			0x0080	/* Timer Clock Select					*/
+#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
+#define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
+#define ERR_TYP			0xC000	/* Error Type							*/
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/trace.h b/arch/blackfin/include/asm/mach-common/bits/trace.h
new file mode 100644
index 0000000..13e2134
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/trace.h
@@ -0,0 +1,19 @@
+/*
+ * Trace Unit Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TRACE__
+#define __BFIN_PERIPHERAL_TRACE__
+
+/* Trace Buffer Control (TBUFCTL) Register Masks */
+#define TBUFPWR       0x00000001
+#define TBUFEN        0x00000002
+#define TBUFOVF       0x00000004
+#define CMPLB_SINGLE  0x00000008
+#define CMPLP_DOUBLE  0x00000010
+#define CMPLB         (CMPLB_SINGLE | CMPLP_DOUBLE)
+
+/* Trace Buffer Status (TBUFSTAT) Register Masks */
+#define TBUFCNT       0x0000001F
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/twi.h b/arch/blackfin/include/asm/mach-common/bits/twi.h
new file mode 100644
index 0000000..8fa7d9f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/twi.h
@@ -0,0 +1,77 @@
+/*
+ * TWI Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_TWI__
+#define __BFIN_PERIPHERAL_TWI__
+
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define	CLKLOW(x)		((x) & 0xFF)		/* Periods Clock Is Held Low */
+#define CLKHI(y)		(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define	PRESCALE		0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
+#define	TWI_ENA			0x0080	/* TWI Enable */
+#define	SCCB			0x0200	/* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTL Masks */
+#define	SEN			0x0001	/* Slave Enable */
+#define	SADD_LEN		0x0002	/* Slave Address Length */
+#define	STDVAL			0x0004	/* Slave Transmit Data Valid */
+#define	TSC_NAK			0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer */
+#define	GEN			0x0010	/* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define	SDIR			0x0001	/* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL			0x0002	/* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define	MEN			0x0001	/* Master Mode Enable */
+#define	MADD_LEN		0x0002	/* Master Address Length */
+#define	MDIR			0x0004	/* Master Transmit Direction (RX/TX*) */
+#define	FAST			0x0008	/* Use Fast Mode Timing Specs */
+#define	STOP			0x0010	/* Issue Stop Condition */
+#define	RSTART			0x0020	/* Repeat Start or Stop* At End Of Transfer */
+#define	DCNT			0x3FC0	/* Data Bytes To Transfer */
+#define	SDAOVR			0x4000	/* Serial Data Override */
+#define	SCLOVR			0x8000	/* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define	MPROG			0x0001	/* Master Transfer In Progress */
+#define	LOSTARB			0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
+#define	ANAK			0x0004	/* Address Not Acknowledged */
+#define	DNAK			0x0008	/* Data Not Acknowledged */
+#define	BUFRDERR		0x0010	/* Buffer Read Error */
+#define	BUFWRERR		0x0020	/* Buffer Write Error */
+#define	SDASEN			0x0040	/* Serial Data Sense */
+#define	SCLSEN			0x0080	/* Serial Clock Sense */
+#define	BUSBUSY			0x0100	/* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define	SINIT			0x0001	/* Slave Transfer Initiated */
+#define	SCOMP			0x0002	/* Slave Transfer Complete */
+#define	SERR			0x0004	/* Slave Transfer Error */
+#define	SOVF			0x0008	/* Slave Overflow */
+#define	MCOMP			0x0010	/* Master Transfer Complete */
+#define	MERR			0x0020	/* Master Transfer Error */
+#define	XMTSERV			0x0040	/* Transmit FIFO Service */
+#define	RCVSERV			0x0080	/* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define	XMTFLUSH		0x0001	/* Transmit Buffer Flush */
+#define	RCVFLUSH		0x0002	/* Receive Buffer Flush */
+#define	XMTINTLEN		0x0004	/* Transmit Buffer Interrupt Length */
+#define	RCVINTLEN		0x0008	/* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define	XMTSTAT			0x0003	/* Transmit FIFO Status */
+#define	XMT_EMPTY		0x0000	/* Transmit FIFO Empty */
+#define	XMT_HALF		0x0001	/* Transmit FIFO Has 1 Byte To Write */
+#define	XMT_FULL		0x0003	/* Transmit FIFO Full (2 Bytes To Write) */
+
+#define	RCVSTAT			0x000C	/* Receive FIFO Status */
+#define	RCV_EMPTY		0x0000	/* Receive FIFO Empty */
+#define	RCV_HALF		0x0004	/* Receive FIFO Has 1 Byte To Read */
+#define	RCV_FULL		0x000C	/* Receive FIFO Full (2 Bytes To Read) */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/uart.h b/arch/blackfin/include/asm/mach-common/bits/uart.h
new file mode 100644
index 0000000..ac1ba11
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/uart.h
@@ -0,0 +1,98 @@
+/*
+ * UART Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_UART__
+#define __BFIN_PERIPHERAL_UART__
+
+/* UARTx_LCR Masks */
+#define WLS			0x03	/* Word Length Select */
+#define WLS_5			0x00	/* 5 bit word */
+#define WLS_6			0x01	/* 6 bit word */
+#define WLS_7			0x02	/* 7 bit word */
+#define WLS_8			0x03	/* 8 bit word */
+#define STB			0x04	/* Stop Bits */
+#define PEN			0x08	/* Parity Enable */
+#define EPS			0x10	/* Even Parity Select */
+#define STP			0x20	/* Stick Parity */
+#define SB			0x40	/* Set Break */
+#define DLAB			0x80	/* Divisor Latch Access */
+
+#define DLAB_P			0x07
+#define SB_P			0x06
+#define STP_P			0x05
+#define EPS_P			0x04
+#define PEN_P			0x03
+#define STB_P			0x02
+#define WLS_P1			0x01
+#define WLS_P0			0x00
+
+/* UARTx_MCR Mask */
+#define XOFF			0x01	/* Transmitter off */
+#define MRTS			0x02	/* Manual Request to Send */
+#define RFIT			0x04	/* Receive FIFO IRQ Threshold */
+#define RFRT			0x08	/* Receive FIFO RTS Threshold */
+#define LOOP_ENA		0x10	/* Loopback Mode Enable */
+#define FCPOL			0x20	/* Flow Control Pin Polarity */
+#define ARTS			0x40	/* Auto RTS generation for RX handshake */
+#define ACTS			0x80	/* Auto CTS operation for TX handshake */
+
+#define XOFF_P			0
+#define MRTS_P			1
+#define RFIT_P			2
+#define RFRT_P			3
+#define LOOP_ENA_P		4
+#define FCPOL_P			5
+#define ARTS_P			6
+#define ACTS_P			7
+
+/* UARTx_LSR Masks */
+#define DR			0x01	/* Data Ready */
+#define OE			0x02	/* Overrun Error */
+#define PE			0x04	/* Parity Error */
+#define FE			0x08	/* Framing Error */
+#define BI			0x10	/* Break Interrupt */
+#define THRE			0x20	/* THR Empty */
+#define TEMT			0x40	/* TSR and UART_THR Empty */
+
+#define DR_P			0x00
+#define OE_P			0x01
+#define PE_P			0x02
+#define FE_P			0x03
+#define BI_P			0x04
+#define THRE_P			0x05
+#define TEMT_P			0x06
+
+/* UARTx_IER Masks */
+#define ERBFI			0x01	/* Enable Receive Buffer Full Interrupt */
+#define ETBEI			0x02	/* Enable Transmit Buffer Empty Interrupt */
+#define ELSI			0x04	/* Enable RX Status Interrupt */
+
+#define ERBFI_P			0x00
+#define ETBEI_P			0x01
+#define ELSI_P			0x02
+
+/* UARTx_IIR Masks */
+#define NINT			0x01	/* Pending Interrupt */
+#define STATUS			0x06	/* Highest Priority Pending Interrupt */
+
+#define NINT_P			0x00
+#define STATUS_P0		0x01
+#define STATUS_P1		0x02
+
+/* UARTx_GCTL Masks */
+#define UCEN			0x01	/* Enable UARTx Clocks */
+#define IREN			0x02	/* Enable IrDA Mode */
+#define TPOLC			0x04	/* IrDA TX Polarity Change */
+#define RPOLC			0x08	/* IrDA RX Polarity Change */
+#define FPE			0x10	/* Force Parity Error On Transmit */
+#define FFE			0x20	/* Force Framing Error On Transmit */
+
+#define UCEN_P			0x00
+#define IREN_P			0x01
+#define TPOLC_P			0x02
+#define RPOLC_P			0x03
+#define FPE_P			0x04
+#define FFE_P			0x05
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/usb.h b/arch/blackfin/include/asm/mach-common/bits/usb.h
new file mode 100644
index 0000000..c639058
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/usb.h
@@ -0,0 +1,264 @@
+/*
+ * USB Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_USB__
+#define __BFIN_PERIPHERAL_USB__
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS	0x7f	/* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM		0x1	/* enable SuspendM output */
+#define SUSPEND_MODE		0x2	/* Suspend Mode indicator */
+#define RESUME_MODE		0x4	/* DMA Mode */
+#define RESET			0x8	/* Reset indicator */
+#define HS_MODE			0x10	/* High Speed mode indicator */
+#define HS_ENABLE		0x20	/* high Speed Enable */
+#define SOFT_CONN		0x40	/* Soft connect */
+#define ISO_UPDATE		0x80	/* Isochronous update */
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX			0x1	/* Tx Endpoint 0 interrupt */
+#define EP1_TX			0x2	/* Tx Endpoint 1 interrupt */
+#define EP2_TX			0x4	/* Tx Endpoint 2 interrupt */
+#define EP3_TX			0x8	/* Tx Endpoint 3 interrupt */
+#define EP4_TX			0x10	/* Tx Endpoint 4 interrupt */
+#define EP5_TX			0x20	/* Tx Endpoint 5 interrupt */
+#define EP6_TX			0x40	/* Tx Endpoint 6 interrupt */
+#define EP7_TX			0x80	/* Tx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX			0x2	/* Rx Endpoint 1 interrupt */
+#define EP2_RX			0x4	/* Rx Endpoint 2 interrupt */
+#define EP3_RX			0x8	/* Rx Endpoint 3 interrupt */
+#define EP4_RX			0x10	/* Rx Endpoint 4 interrupt */
+#define EP5_RX			0x20	/* Rx Endpoint 5 interrupt */
+#define EP6_RX			0x40	/* Rx Endpoint 6 interrupt */
+#define EP7_RX			0x80	/* Rx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E		0x1	/* Endpoint 0 interrupt Enable */
+#define EP1_TX_E		0x2	/* Tx Endpoint 1 interrupt enable */
+#define EP2_TX_E		0x4	/* Tx Endpoint 2 interrupt enable */
+#define EP3_TX_E		0x8	/* Tx Endpoint 3 interrupt enable */
+#define EP4_TX_E		0x10	/* Tx Endpoint 4 interrupt enable */
+#define EP5_TX_E		0x20	/* Tx Endpoint 5 interrupt enable */
+#define EP6_TX_E		0x40	/* Tx Endpoint 6 interrupt enable */
+#define EP7_TX_E		0x80	/* Tx Endpoint 7 interrupt enable */
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E		0x02	/* Rx Endpoint 1 interrupt enable */
+#define EP2_RX_E		0x04	/* Rx Endpoint 2 interrupt enable */
+#define EP3_RX_E		0x08	/* Rx Endpoint 3 interrupt enable */
+#define EP4_RX_E		0x10	/* Rx Endpoint 4 interrupt enable */
+#define EP5_RX_E		0x20	/* Rx Endpoint 5 interrupt enable */
+#define EP6_RX_E		0x40	/* Rx Endpoint 6 interrupt enable */
+#define EP7_RX_E		0x80	/* Rx Endpoint 7 interrupt enable */
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B		0x01	/* Suspend indicator */
+#define RESUME_B		0x02	/* Resume indicator */
+#define RESET_OR_BABLE_B	0x04	/* Reset/babble indicator */
+#define SOF_B			0x08	/* Start of frame */
+#define CONN_B			0x10	/* Connection indicator */
+#define DISCON_B		0x20	/* Disconnect indicator */
+#define SESSION_REQ_B		0x40	/* Session Request */
+#define VBUS_ERROR_B		0x80	/* Vbus threshold indicator */
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE		0x01	/* Suspend indicator int enable */
+#define RESUME_BE		0x02	/* Resume indicator int enable */
+#define RESET_OR_BABLE_BE	0x04	/* Reset/babble indicator int enable */
+#define SOF_BE			0x08	/* Start of frame int enable */
+#define CONN_BE			0x10	/* Connection indicator int enable */
+#define DISCON_BE		0x20	/* Disconnect indicator int enable */
+#define SESSION_REQ_BE		0x40	/* Session Request int enable */
+#define VBUS_ERROR_BE		0x80	/* Vbus threshold indicator int enable */
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER		0x7ff	/* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT	0xf	/* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA		0x0001	/* enables USB module */
+#define EP1_TX_ENA		0x0002	/* Transmit endpoint 1 enable */
+#define EP2_TX_ENA		0x0004	/* Transmit endpoint 2 enable */
+#define EP3_TX_ENA		0x0008	/* Transmit endpoint 3 enable */
+#define EP4_TX_ENA		0x0010	/* Transmit endpoint 4 enable */
+#define EP5_TX_ENA		0x0020	/* Transmit endpoint 5 enable */
+#define EP6_TX_ENA		0x0040	/* Transmit endpoint 6 enable */
+#define EP7_TX_ENA		0x0080	/* Transmit endpoint 7 enable */
+#define EP1_RX_ENA		0x0100	/* Receive endpoint 1 enable */
+#define EP2_RX_ENA		0x0200	/* Receive endpoint 2 enable */
+#define EP3_RX_ENA		0x0400	/* Receive endpoint 3 enable */
+#define EP4_RX_ENA		0x0800	/* Receive endpoint 4 enable */
+#define EP5_RX_ENA		0x1000	/* Receive endpoint 5 enable */
+#define EP6_RX_ENA		0x2000	/* Receive endpoint 6 enable */
+#define EP7_RX_ENA		0x4000	/* Receive endpoint 7 enable */
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION			0x1	/* session indicator */
+#define HOST_REQ		0x2	/* Host negotiation request */
+#define HOST_MODE		0x4	/* indicates USBDRC is a host */
+#define VBUS0			0x8	/* Vbus level indicator[0] */
+#define VBUS1			0x10	/* Vbus level indicator[1] */
+#define LSDEV			0x20	/* Low-speed indicator */
+#define FSDEV			0x40	/* Full or High-speed indicator */
+#define B_DEVICE		0x80	/* A' or 'B' device indicator */
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON		0x1	/* indicator to drive VBUS control circuit */
+#define DRIVE_VBUS_OFF		0x2	/* indicator to shut off charge pump */
+#define CHRG_VBUS_START		0x4	/* indicator for external circuit to start charging VBUS */
+#define CHRG_VBUS_END		0x8	/* indicator for external circuit to end charging VBUS */
+#define DISCHRG_VBUS_START	0x10	/* indicator to start discharging VBUS */
+#define DISCHRG_VBUS_END	0x20	/* indicator to stop discharging VBUS */
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA	0x01	/* enable DRIVE_VBUS_ON interrupt */
+#define DRIVE_VBUS_OFF_ENA	0x02	/* enable DRIVE_VBUS_OFF interrupt */
+#define CHRG_VBUS_START_ENA	0x04	/* enable CHRG_VBUS_START interrupt */
+#define CHRG_VBUS_END_ENA	0x08	/* enable CHRG_VBUS_END interrupt */
+#define DISCHRG_VBUS_START_ENA	0x10	/* enable DISCHRG_VBUS_START interrupt */
+#define DISCHRG_VBUS_END_ENA	0x20	/* enable DISCHRG_VBUS_END interrupt */
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY		0x1	/* data packet receive indicator */
+#define TXPKTRDY		0x2	/* data packet in FIFO indicator */
+#define STALL_SENT		0x4	/* STALL handshake sent */
+#define DATAEND			0x8	/* Data end indicator */
+#define SETUPEND		0x10	/* Setup end */
+#define SENDSTALL		0x20	/* Send STALL handshake */
+#define SERVICED_RXPKTRDY	0x40	/* used to clear the RxPktRdy bit */
+#define SERVICED_SETUPEND	0x80	/* used to clear the SetupEnd bit */
+#define FLUSHFIFO		0x100	/* flush endpoint FIFO */
+#define STALL_RECEIVED_H	0x4	/* STALL handshake received host mode */
+#define SETUPPKT_H		0x8	/* send Setup token host mode */
+#define ERROR_H			0x10	/* timeout error indicator host mode */
+#define REQPKT_H		0x20	/* Request an IN transaction host mode */
+#define STATUSPKT_H		0x40	/* Status stage transaction host mode */
+#define NAK_TIMEOUT_H		0x80	/* EP0 halted after a NAK host mode */
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT		0x7f	/* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT		0x1f	/* frames/micro frames count after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T	0x7ff	/* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R	0x7ff	/* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T		0x1	/* data packet in FIFO indicator */
+#define FIFO_NOT_EMPTY_T	0x2	/* FIFO not empty */
+#define UNDERRUN_T		0x4	/* TxPktRdy not set for an IN token */
+#define FLUSHFIFO_T		0x8	/* flush endpoint FIFO */
+#define STALL_SEND_T		0x10	/* issue a Stall handshake */
+#define STALL_SENT_T		0x20	/* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_T	0x40	/* clear endpoint data toggle */
+#define INCOMPTX_T		0x80	/* indicates that a large packet is split */
+#define DMAREQMODE_T		0x400	/* DMA mode (0 or 1) selection */
+#define FORCE_DATATOGGLE_T	0x800	/* Force data toggle */
+#define DMAREQ_ENA_T		0x1000	/* Enable DMA request for Tx EP */
+#define ISO_T			0x4000	/* enable Isochronous transfers */
+#define AUTOSET_T		0x8000	/* allows TxPktRdy to be set automatically */
+#define ERROR_TH		0x4	/* error condition host mode */
+#define STALL_RECEIVED_TH	0x20	/* Stall handshake received host mode */
+#define NAK_TIMEOUT_TH		0x80	/* NAK timeout host mode */
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT		0x1fff	/* Byte len for the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R		0x1	/* data packet in FIFO indicator */
+#define FIFO_FULL_R		0x2	/* FIFO not empty */
+#define OVERRUN_R		0x4	/* TxPktRdy not set for an IN token */
+#define DATAERROR_R		0x8	/* Out packet cannot be loaded into Rx FIFO */
+#define FLUSHFIFO_R		0x10	/* flush endpoint FIFO */
+#define STALL_SEND_R		0x20	/* issue a Stall handshake */
+#define STALL_SENT_R		0x40	/* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_R	0x80	/* clear endpoint data toggle */
+#define INCOMPRX_R		0x100	/* indicates that a large packet is split */
+#define DMAREQMODE_R		0x800	/* DMA mode (0 or 1) selection */
+#define DISNYET_R		0x1000	/* disable Nyet handshakes */
+#define DMAREQ_ENA_R		0x2000	/* Enable DMA request for Tx EP */
+#define ISO_R			0x4000	/* enable Isochronous transfers */
+#define AUTOCLEAR_R		0x8000	/* allows TxPktRdy to be set automatically */
+#define ERROR_RH		0x4	/* TxPktRdy not set for an IN token host mode */
+#define REQPKT_RH		0x20	/* request an IN transaction host mode */
+#define STALL_RECEIVED_RH	0x40	/* Stall handshake received host mode */
+#define INCOMPRX_RH		0x100	/* large packet is split host mode */
+#define DMAREQMODE_RH		0x800	/* DMA mode (0 or 1) selection host mode */
+#define AUTOREQ_RH		0x4000	/* sets ReqPkt automatically host mode */
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT		0x1fff	/* Packet byte len in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T		0xf	/* EP number */
+#define PROTOCOL_T		0xc	/* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL	0xff	/* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R		0xf	/* EP number */
+#define PROTOCOL_R		0xc	/* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL	0xff	/* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT		0x1	/* DMA0 pending interrupt */
+#define DMA1_INT		0x2	/* DMA1 pending interrupt */
+#define DMA2_INT		0x4	/* DMA2 pending interrupt */
+#define DMA3_INT		0x8	/* DMA3 pending interrupt */
+#define DMA4_INT		0x10	/* DMA4 pending interrupt */
+#define DMA5_INT		0x20	/* DMA5 pending interrupt */
+#define DMA6_INT		0x40	/* DMA6 pending interrupt */
+#define DMA7_INT		0x80	/* DMA7 pending interrupt */
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA			0x1	/* DMA enable */
+#define DIRECTION		0x2	/* direction of DMA transfer */
+#define MODE			0x4	/* DMA Bus error */
+#define INT_ENA			0x8	/* Interrupt enable */
+#define EPNUM			0xf0	/* EP number */
+#define BUSERROR		0x100	/* DMA Bus error */
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/watchdog.h b/arch/blackfin/include/asm/mach-common/bits/watchdog.h
new file mode 100644
index 0000000..75924f9
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/watchdog.h
@@ -0,0 +1,19 @@
+/*
+ * Watchdog Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_WATCHDOG__
+#define __BFIN_PERIPHERAL_WATCHDOG__
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV			0x0006	/* event generated on roll over */
+#define WDEV_RESET		0x0000	/* generate reset event on roll over */
+#define WDEV_NMI		0x0002	/* generate NMI event on roll over */
+#define WDEV_GPI		0x0004	/* generate GP IRQ on roll over */
+#define WDEV_NONE		0x0006	/* no event on roll over */
+#define WDEN			0x0FF0	/* enable watchdog */
+#define WDDIS			0x0AD0	/* disable watchdog */
+#define WDRO			0x8000	/* watchdog rolled over latch */
+
+#endif
diff --git a/arch/blackfin/include/asm/mem_map.h b/arch/blackfin/include/asm/mem_map.h
new file mode 100644
index 0000000..3e361d6
--- /dev/null
+++ b/arch/blackfin/include/asm/mem_map.h
@@ -0,0 +1,26 @@
+/*
+ * Common Blackfin memory map
+ *
+ * Copyright 2004-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MEM_MAP_H__
+#define __BFIN_MEM_MAP_H__
+
+/* Every Blackfin so far has MMRs like this */
+#ifndef COREMMR_BASE
+# define COREMMR_BASE 0xFFE00000
+#endif
+#ifndef SYSMMR_BASE
+# define SYSMMR_BASE  0xFFC00000
+#endif
+
+/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */
+#ifndef L1_SRAM_SCRATCH
+# define L1_SRAM_SCRATCH      0xFFB00000
+# define L1_SRAM_SCRATCH_SIZE 0x1000
+# define L1_SRAM_SCRATCH_END  (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/net.h b/arch/blackfin/include/asm/net.h
new file mode 100644
index 0000000..97cb466
--- /dev/null
+++ b/arch/blackfin/include/asm/net.h
@@ -0,0 +1,28 @@
+/*
+ * net.h - misc Blackfin network helpers
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_RAND_MAC__
+#define __ASM_BFIN_RAND_MAC__
+
+/* If the board does not have a real MAC assigned to it, then generate a
+ * locally administrated pseudo-random one based on CYCLES and compile date.
+ */
+static inline void bfin_gen_rand_mac(uchar *mac_addr)
+{
+	/* make something up */
+	const char s[] = __DATE__;
+	size_t i;
+	u32 cycles;
+	for (i = 0; i < 6; ++i) {
+		asm("%0 = CYCLES;" : "=r" (cycles));
+		mac_addr[i] = cycles ^ s[i];
+	}
+	mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */
+}
+
+#endif
diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h
new file mode 100644
index 0000000..000ffe5
--- /dev/null
+++ b/arch/blackfin/include/asm/posix_types.h
@@ -0,0 +1,91 @@
+/*
+ * U-boot - posix_types.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H
+#define __ARCH_BLACKFIN_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short __kernel_dev_t;
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned int __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+
+#define BOOL_WAS_DEFINED
+typedef enum { false = 0, true = 1 } bool;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+	int val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef	__FD_SET
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef	__FD_CLR
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef	__FD_ISSET
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif				/* defined(__KERNEL__) */
+
+#endif
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
new file mode 100644
index 0000000..d700cce
--- /dev/null
+++ b/arch/blackfin/include/asm/processor.h
@@ -0,0 +1,35 @@
+/*
+ * U-boot - processor.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * This file is based on
+ * include/asm-m68k/processor.h
+ * Changes made by Akbar Hussain Lineo, Inc, May 2001 for BLACKFIN
+ * Copyright (C) 1995 Hamish Macdonald
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_BLACKFIN_PROCESSOR_H
+#define __ASM_BLACKFIN_PROCESSOR_H
+
+/* Stub to make stupid common code happy */
+
+#endif
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
new file mode 100644
index 0000000..251d5e6
--- /dev/null
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2004-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _BFIN_PTRACE_H
+#define _BFIN_PTRACE_H
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 7 are data registers R0-R7
+ *       8 - 15 are address registers P0-P7
+ *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ *      32 - 33 A registers A0 & A1
+ *      34 -    status register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *      32-33 --- Low 32-bit of A0&1
+ *      34-35 --- High 8-bit of A0&1
+ */
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long orig_pc;
+	long ipend;
+	long seqstat;
+	long rete;
+	long retn;
+	long retx;
+	long pc;		/* PC == RETI */
+	long rets;
+	long reserved;		/* Used as scratch during system calls */
+	long astat;
+	long lb1;
+	long lb0;
+	long lt1;
+	long lt0;
+	long lc1;
+	long lc0;
+	long a1w;
+	long a1x;
+	long a0w;
+	long a0x;
+	long b3;
+	long b2;
+	long b1;
+	long b0;
+	long l3;
+	long l2;
+	long l1;
+	long l0;
+	long m3;
+	long m2;
+	long m1;
+	long m0;
+	long i3;
+	long i2;
+	long i1;
+	long i0;
+	long usp;
+	long fp;
+	long p5;
+	long p4;
+	long p3;
+	long p2;
+	long p1;
+	long p0;
+	long r7;
+	long r6;
+	long r5;
+	long r4;
+	long r3;
+	long r2;
+	long r1;
+	long r0;
+	long orig_r0;
+	long orig_p0;
+	long syscfg;
+};
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13	/* ptrace signal  */
+
+#define PTRACE_GETFDPIC           31	/* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC       0	/* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP     1	/* [addr] request the interpreter loadmap */
+
+#define PS_S  (0x0002)
+
+#ifdef __KERNEL__
+
+/* user_mode returns true if only one bit is set in IPEND, other than the
+   master interrupt enable.  */
+#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
+#define instruction_pointer(regs) ((regs)->pc)
+#define user_stack_pointer(regs)  ((regs)->usp)
+#define profile_pc(regs) instruction_pointer(regs)
+extern void show_regs(struct pt_regs *);
+
+#define arch_has_single_step()	(1)
+extern void user_enable_single_step(struct task_struct *);
+/* see arch/blackfin/kernel/ptrace.c about this redirect */
+#define user_disable_single_step(child) ptrace_disable(child)
+
+/*
+ * Get the address of the live pt_regs for the specified task.
+ * These are saved onto the top kernel stack when the process
+ * is not running.
+ *
+ * Note: if a user thread is execve'd from kernel space, the
+ * kernel stack will not be empty on entry to the kernel, so
+ * ptracing these tasks will fail.
+ */
+#define task_pt_regs(task) \
+	(struct pt_regs *) \
+	    ((unsigned long)task_stack_page(task) + \
+	     (THREAD_SIZE - sizeof(struct pt_regs)))
+
+#endif  /*  __KERNEL__  */
+
+#endif				/* __ASSEMBLY__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ */
+
+#define PT_R0 204
+#define PT_R1 200
+#define PT_R2 196
+#define PT_R3 192
+#define PT_R4 188
+#define PT_R5 184
+#define PT_R6 180
+#define PT_R7 176
+#define PT_P0 172
+#define PT_P1 168
+#define PT_P2 164
+#define PT_P3 160
+#define PT_P4 156
+#define PT_P5 152
+#define PT_FP 148
+#define PT_USP 144
+#define PT_I0 140
+#define PT_I1 136
+#define PT_I2 132
+#define PT_I3 128
+#define PT_M0 124
+#define PT_M1 120
+#define PT_M2 116
+#define PT_M3 112
+#define PT_L0 108
+#define PT_L1 104
+#define PT_L2 100
+#define PT_L3 96
+#define PT_B0 92
+#define PT_B1 88
+#define PT_B2 84
+#define PT_B3 80
+#define PT_A0X 76
+#define PT_A0W 72
+#define PT_A1X 68
+#define PT_A1W 64
+#define PT_LC0 60
+#define PT_LC1 56
+#define PT_LT0 52
+#define PT_LT1 48
+#define PT_LB0 44
+#define PT_LB1 40
+#define PT_ASTAT 36
+#define PT_RESERVED 32
+#define PT_RETS 28
+#define PT_PC 24
+#define PT_RETX 20
+#define PT_RETN 16
+#define PT_RETE 12
+#define PT_SEQSTAT 8
+#define PT_IPEND 4
+
+#define PT_ORIG_R0 208
+#define PT_ORIG_P0 212
+#define PT_SYSCFG 216
+#define PT_TEXT_ADDR 220
+#define PT_TEXT_END_ADDR 224
+#define PT_DATA_ADDR 228
+#define PT_FDPIC_EXEC 232
+#define PT_FDPIC_INTERP 236
+
+#endif				/* _BFIN_PTRACE_H */
diff --git a/arch/blackfin/include/asm/sdh.h b/arch/blackfin/include/asm/sdh.h
new file mode 100644
index 0000000..2c2f63e
--- /dev/null
+++ b/arch/blackfin/include/asm/sdh.h
@@ -0,0 +1,17 @@
+/*
+ * sdh.h, export bfin_mmc_init
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_SDH_H__
+#define __ASM_SDH_H__
+
+#include <mmc.h>
+#include <asm/u-boot.h>
+
+int bfin_mmc_init(bd_t *bis);
+
+#endif
diff --git a/arch/blackfin/include/asm/shared_resources.h b/arch/blackfin/include/asm/shared_resources.h
new file mode 100644
index 0000000..2ac8990
--- /dev/null
+++ b/arch/blackfin/include/asm/shared_resources.h
@@ -0,0 +1,33 @@
+/*
+ * U-boot - setup.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _SHARED_RESOURCES_H_
+#define _SHARED_RESOURCES_H_
+
+void swap_to(int device_id);
+
+#define FLASH	 0
+#define ETHERNET 1
+
+#endif /* _SHARED_RESOURCES_H_ */
diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h
new file mode 100644
index 0000000..7b1573c
--- /dev/null
+++ b/arch/blackfin/include/asm/signal.h
@@ -0,0 +1 @@
+#include <asm-generic/signal.h>
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
new file mode 100644
index 0000000..117f44c
--- /dev/null
+++ b/arch/blackfin/include/asm/string.h
@@ -0,0 +1,79 @@
+/*
+ * U-boot - string.h String functions
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Changed by Lineo Inc. May 2001 */
+
+#ifndef _BLACKFINNOMMU_STRING_H_
+#define _BLACKFINNOMMU_STRING_H_
+
+#ifdef __KERNEL__		/* only set these up for kernel code */
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRNCMP
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMMOVE
+
+extern char *strcpy(char *dest, const char *src);
+extern char *strncpy(char *dest, const char *src, size_t n);
+extern int strcmp(const char *cs, const char *ct);
+extern int strncmp(const char *cs, const char *ct, size_t count);
+extern void *memcpy(void *dest, const void *src, size_t count);
+extern void *memset(void *s, int c, size_t count);
+extern int memcmp(const void *, const void *, size_t);
+extern void *memmove(void *dest, const void *src, size_t count);
+
+#else				/* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY	1
+#define __HAVE_ARCH_STRNCPY	1
+#define __HAVE_ARCH_STRCAT	1
+#define __HAVE_ARCH_STRNCAT	1
+#define __HAVE_ARCH_STRCMP	1
+#define __HAVE_ARCH_STRNCMP	1
+#define __HAVE_ARCH_STRNICMP	1
+#define __HAVE_ARCH_STRCHR	1
+#define __HAVE_ARCH_STRRCHR	1
+#define __HAVE_ARCH_STRSTR	1
+#define __HAVE_ARCH_STRLEN	1
+#define __HAVE_ARCH_STRNLEN	1
+#define __HAVE_ARCH_MEMSET	1
+#define __HAVE_ARCH_MEMCPY	1
+#define __HAVE_ARCH_MEMMOVE	1
+#define __HAVE_ARCH_MEMSCAN	1
+#define __HAVE_ARCH_MEMCMP	1
+#define __HAVE_ARCH_MEMCHR	1
+#define __HAVE_ARCH_STRTOK	1
+
+#endif				/* KERNEL */
+
+#endif				/* _BLACKFIN_STRING_H_ */
diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h
new file mode 100644
index 0000000..6bc7208
--- /dev/null
+++ b/arch/blackfin/include/asm/system.h
@@ -0,0 +1,121 @@
+/*
+ * U-boot - system.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_SYSTEM_H
+#define _BLACKFIN_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"sti %0;" \
+		: \
+		: "d" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"cli %0;" \
+			: "=d" (__tmp_dummy) \
+		); \
+	} while (0)
+
+# define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"cli %0;" \
+		: "=&d" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"cli %0;" \
+		"sti %0;" \
+		: "=d" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t"::)
+#define mb()			asm volatile (""   : : :"memory")
+#define rmb()			asm volatile (""   : : :"memory")
+#define wmb()			asm volatile (""   : : :"memory")
+#define set_rmb(var, value)	do { xchg(&var, value); } while (0)
+#define set_mb(var, value)	set_rmb(var, value)
+#define set_wmb(var, value)	do { var = value; wmb(); } while (0)
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+struct __xchg_dummy {
+	unsigned long a[100];
+};
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+				   int size)
+{
+	unsigned long tmp = 0;
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+
+	switch (size) {
+	case 1:
+		__asm__ __volatile__
+			("%0 = b%2 (z);\n\t"
+			 "b%2 = %1;\n\t"
+			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+		break;
+	case 2:
+		__asm__ __volatile__
+			("%0 = w%2 (z);\n\t"
+			 "w%2 = %1;\n\t"
+			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+		break;
+	case 4:
+		__asm__ __volatile__
+			("%0 = %2;\n\t"
+			 "%2 = %1;\n\t"
+			 : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+		break;
+	}
+	local_irq_restore(flags);
+	return tmp;
+}
+
+#endif	/* _BLACKFIN_SYSTEM_H */
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
new file mode 100644
index 0000000..7422d3d
--- /dev/null
+++ b/arch/blackfin/include/asm/traps.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright 2004-2009 Analog Devices Inc.
+ *                 2001 Lineo, Inc
+ *                        Tony Kou
+ *                 1993 Hamish Macdonald
+ *
+ * Licensed under the GPL-2
+ */
+
+#ifndef _BFIN_TRAPS_H
+#define _BFIN_TRAPS_H
+
+#define VEC_SYS		(0)
+#define VEC_EXCPT01	(1)
+#define VEC_EXCPT02	(2)
+#define VEC_EXCPT03	(3)
+#define VEC_EXCPT04	(4)
+#define VEC_EXCPT05	(5)
+#define VEC_EXCPT06	(6)
+#define VEC_EXCPT07	(7)
+#define VEC_EXCPT08	(8)
+#define VEC_EXCPT09	(9)
+#define VEC_EXCPT10	(10)
+#define VEC_EXCPT11	(11)
+#define VEC_EXCPT12	(12)
+#define VEC_EXCPT13	(13)
+#define VEC_EXCPT14	(14)
+#define VEC_EXCPT15	(15)
+#define VEC_STEP	(16)
+#define VEC_OVFLOW	(17)
+#define VEC_UNDEF_I	(33)
+#define VEC_ILGAL_I	(34)
+#define VEC_CPLB_VL	(35)
+#define VEC_MISALI_D	(36)
+#define VEC_UNCOV	(37)
+#define VEC_CPLB_M	(38)
+#define VEC_CPLB_MHIT	(39)
+#define VEC_WATCH	(40)
+#define VEC_ISTRU_VL	(41)	/*ADSP-BF535 only (MH) */
+#define VEC_MISALI_I	(42)
+#define VEC_CPLB_I_VL	(43)
+#define VEC_CPLB_I_M	(44)
+#define VEC_CPLB_I_MHIT	(45)
+#define VEC_ILL_RES	(46)	/* including unvalid supervisor mode insn */
+/* The hardware reserves (63) for future use - we use it to tell our
+ * normal exception handling code we have a hardware error
+ */
+#define VEC_HWERR	(63)
+
+#endif				/* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/types.h b/arch/blackfin/include/asm/types.h
new file mode 100644
index 0000000..2160ba0
--- /dev/null
+++ b/arch/blackfin/include/asm/types.h
@@ -0,0 +1,86 @@
+/*
+ * U-boot - types.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _BLACKFIN_TYPES_H
+#define _BLACKFIN_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+/* HK0617   -- Changes to unsigned long temporarily */
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
new file mode 100644
index 0000000..a6e6cf0f
--- /dev/null
+++ b/arch/blackfin/include/asm/u-boot.h
@@ -0,0 +1,48 @@
+/*
+ * U-boot - u-boot.h Structure declarations for board specific data
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+typedef struct bd_info {
+	int bi_baudrate;		/* serial console baudrate */
+	unsigned long bi_ip_addr;	/* IP Address */
+	unsigned long bi_boot_params;	/* where this board expects params */
+	unsigned long bi_memstart;	/* start of DRAM memory */
+	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
+	unsigned long bi_flashstart;	/* start of FLASH memory */
+	unsigned long bi_flashsize;	/* size  of FLASH memory */
+	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
+	const char *bi_r_version;
+	const char *bi_cpu;
+	const char *bi_board_name;
+	unsigned long bi_vco;
+	unsigned long bi_cclk;
+	unsigned long bi_sclk;
+} bd_t;
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/blackfin/include/asm/unaligned.h b/arch/blackfin/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/blackfin/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/blackfin/lib/.gitignore b/arch/blackfin/lib/.gitignore
new file mode 100644
index 0000000..09f1be0
--- /dev/null
+++ b/arch/blackfin/lib/.gitignore
@@ -0,0 +1 @@
+u-boot.lds
diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile
new file mode 100644
index 0000000..3bdba75
--- /dev/null
+++ b/arch/blackfin/lib/Makefile
@@ -0,0 +1,65 @@
+#
+# U-boot Makefile
+#
+# Copyright (c) 2005-2008 Analog Devices Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
+
+LIB	= $(obj)lib$(ARCH).a
+
+SOBJS-y	+= ins.o
+SOBJS-y	+= memcmp.o
+SOBJS-y	+= memcpy.o
+SOBJS-y	+= memmove.o
+SOBJS-y	+= memset.o
+SOBJS-y	+= outs.o
+SOBJS-$(CONFIG_CMD_KGDB) += __kgdb.o
+
+COBJS-y	+= board.o
+COBJS-y	+= boot.o
+COBJS-y	+= cache.o
+COBJS-y	+= clocks.o
+COBJS-$(CONFIG_CMD_CACHE_DUMP) += cmd_cache_dump.o
+COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-y	+= muldi3.o
+COBJS-$(CONFIG_POST) += post.o tests.o
+COBJS-y	+= string.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S
new file mode 100644
index 0000000..cba4179
--- /dev/null
+++ b/arch/blackfin/lib/__kgdb.S
@@ -0,0 +1,155 @@
+
+#include <asm/linkage.h>
+
+/* save stack context for non-local goto
+ * int kgdb_setjmp(long *buf)
+ */
+
+ENTRY(_kgdb_setjmp)
+	[--SP] = p0; 	/* Save P0 */
+	p0 = r0;
+	r0 = [SP++];	/* Load P0 into R0 */
+
+	[p0 + 0x00] = r0;       /* GP address registers */
+	[p0 + 0x04] = p1;
+	[p0 + 0x08] = p2;
+	[p0 + 0x0C] = p3;
+	[p0 + 0x10] = p4;
+	[p0 + 0x14] = p5;
+	[p0 + 0x18] = FP;       /* frame pointer */
+	[p0 + 0x1C] = SP;       /* stack pointer */
+
+	[p0 + 0x20] = p0;       /* data regs */
+	[p0 + 0x24] = r1;
+	[p0 + 0x28] = r2;
+	[p0 + 0x2C] = r3;
+	[p0 + 0x30] = r4;
+	[p0 + 0x34] = r5;
+	[p0 + 0x38] = r6;
+	[p0 + 0x3C] = r7;
+
+	r0 = ASTAT;	[p0 + 0x40] = r0;
+
+	/* loop counters */
+	r0 = LC0;	[p0 + 0x44] = r0;
+	r0 = LC1;	[p0 + 0x48] = r0;
+
+	/* Accumulator */
+	r0 = A0.w;	[p0 + 0x4C] = r0;
+	r0.l = A0.x;	[p0 + 0x50] = r0;
+	r0 = A1.w;	[p0 + 0x54] = r0;
+	r0.l = A1.x;	[p0 + 0x58] = r0;
+
+	/* index registers */
+	r0 = i0;	[p0 + 0x5C] = r0;
+	r0 = i1;	[p0 + 0x60] = r0;
+	r0 = i2;	[p0 + 0x64] = r0;
+	r0 = i3;	[p0 + 0x68] = r0;
+
+	/* modifier registers */
+	r0 = m0;	[p0 + 0x6C] = r0;
+	r0 = m1;	[p0 + 0x70] = r0;
+	r0 = m2;	[p0 + 0x74] = r0;
+	r0 = m3;	[p0 + 0x78] = r0;
+
+	/* length registers */
+	r0 = l0;	[p0 + 0x7C] = r0;
+	r0 = l1;	[p0 + 0x80] = r0;
+	r0 = l2;	[p0 + 0x84] = r0;
+	r0 = l3;	[p0 + 0x88] = r0;
+
+	/* base registers */
+	r0 = b0;	[p0 + 0x8C] = r0;
+	r0 = b1;	[p0 + 0x90] = r0;
+	r0 = b2;	[p0 + 0x94] = r0;
+	r0 = b3;	[p0 + 0x98] = r0;
+
+	/* store return address */
+	r0 = RETS;	[p0 + 0x9C] = r0;
+
+	R0 = 0;
+	RTS;
+ENDPROC(_kgdb_setjmp)
+
+/*
+ * non-local jump to a saved stack context
+ * longjmp(long *buf, int val)
+ */
+
+ENTRY(_kgdb_longjmp)
+	p0 = r0;
+	r0 = [p0 + 0x00];
+	[--sp] = r0;
+
+	/* GP address registers - skip p0 for now*/
+	p1 = [p0 + 0x04];
+	p2 = [p0 + 0x08];
+	p3 = [p0 + 0x0C];
+	p4 = [p0 + 0x10];
+	p5 = [p0 + 0x14];
+	/* frame pointer */
+	fp = [p0 + 0x18];
+	/* stack pointer */
+	r0 = [sp++];
+	sp = [p0 + 0x1C];
+	[--sp] = r0;
+	[--sp] = r1;
+
+	/* data regs */
+	r0 = [p0 + 0x20];
+	r1 = [p0 + 0x24];
+	r2 = [p0 + 0x28];
+	r3 = [p0 + 0x2C];
+	r4 = [p0 + 0x30];
+	r5 = [p0 + 0x34];
+	r6 = [p0 + 0x38];
+	r7 = [p0 + 0x3C];
+
+	r0 = [p0 + 0x40];	ASTAT = r0;
+
+	/* loop counters */
+	r0 = [p0 + 0x44];	LC0 = r0;
+	r0 = [p0 + 0x48];	LC1 = r0;
+
+	/* Accumulator */
+	r0 = [p0 + 0x4C];	A0.w = r0;
+	r0 = [p0 + 0x50];	A0.x = r0;
+	r0 = [p0 + 0x54];	A1.w = r0;
+	r0 = [p0 + 0x58];	A1.x = r0;
+
+	/* index registers */
+	r0 = [p0 + 0x5C];	i0 = r0;
+	r0 = [p0 + 0x60];	i1 = r0;
+	r0 = [p0 + 0x64];	i2 = r0;
+	r0 = [p0 + 0x68];	i3 = r0;
+
+	/* modifier registers */
+	r0 = [p0 + 0x6C];	m0 = r0;
+	r0 = [p0 + 0x70];	m1 = r0;
+	r0 = [p0 + 0x74];	m2 = r0;
+	r0 = [p0 + 0x78];	m3 = r0;
+
+	/* length registers */
+	r0 = [p0 + 0x7C];	l0 = r0;
+	r0 = [p0 + 0x80];	l1 = r0;
+	r0 = [p0 + 0x84];	l2 = r0;
+	r0 = [p0 + 0x88];	l3 = r0;
+
+	/* base registers */
+	r0 = [p0 + 0x8C];	b0 = r0;
+	r0 = [p0 + 0x90];	b1 = r0;
+	r0 = [p0 + 0x94];	b2 = r0;
+	r0 = [p0 + 0x98];	b3 = r0;
+
+	/* store return address */
+	r0 = [p0 + 0x9C];	RETS = r0;
+
+	/* fixup R0 & P0 */
+	r0 = [sp++];
+	p0 = [sp++];
+	CC = R0 == 0;
+	IF !CC JUMP .Lfinished;
+	R0 = 1;
+.Lfinished:
+	RTS;
+ENDPROC(_kgdb_longjmp)
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
new file mode 100644
index 0000000..4e9bb19
--- /dev/null
+++ b/arch/blackfin/lib/board.c
@@ -0,0 +1,419 @@
+/*
+ * U-boot - board.c First C file to be called contains init routines
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <stdio_dev.h>
+#include <environment.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <net.h>
+#include <timestamp.h>
+#include <status_led.h>
+#include <version.h>
+
+#include <asm/cplb.h>
+#include <asm/mach-common/bits/mpu.h>
+#include <kgdb.h>
+
+#ifdef CONFIG_CMD_NAND
+#include <nand.h>	/* cannot even include nand.h if it isnt configured */
+#endif
+
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
+#if defined(CONFIG_POST)
+#include <post.h>
+int post_flag;
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")";
+
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+	serial_puts("Early: ");
+	serial_puts(s);
+#endif
+}
+
+static int display_banner(void)
+{
+	printf("\n\n%s\n\n", version_string);
+	printf("CPU:   ADSP " MK_STR(CONFIG_BFIN_CPU) " "
+		"(Detected Rev: 0.%d) "
+		"(%s boot)\n",
+		bfin_revid(),
+		get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
+	return 0;
+}
+
+static int init_baudrate(void)
+{
+	char baudrate[15];
+	int i = getenv_r("baudrate", baudrate, sizeof(baudrate));
+	gd->bd->bi_baudrate = gd->baudrate = (i > 0)
+	    ? simple_strtoul(baudrate, NULL, 10)
+	    : CONFIG_BAUDRATE;
+	return 0;
+}
+
+static void display_global_data(void)
+{
+	bd_t *bd;
+
+#ifndef CONFIG_DEBUG_EARLY_SERIAL
+	return;
+#endif
+
+	bd = gd->bd;
+	printf(" gd: %p\n", gd);
+	printf(" |-flags: %lx\n", gd->flags);
+	printf(" |-board_type: %lx\n", gd->board_type);
+	printf(" |-baudrate: %lu\n", gd->baudrate);
+	printf(" |-have_console: %lx\n", gd->have_console);
+	printf(" |-ram_size: %lx\n", gd->ram_size);
+	printf(" |-env_addr: %lx\n", gd->env_addr);
+	printf(" |-env_valid: %lx\n", gd->env_valid);
+	printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
+	printf(" \\-bd: %p\n", gd->bd);
+	printf("   |-bi_baudrate: %x\n", bd->bi_baudrate);
+	printf("   |-bi_ip_addr: %lx\n", bd->bi_ip_addr);
+	printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
+	printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
+	printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
+	printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
+	printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
+	printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
+}
+
+#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
+#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
+void init_cplbtables(void)
+{
+	volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
+	volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA;
+	uint32_t extern_memory;
+	size_t i;
+
+	void icplb_add(uint32_t addr, uint32_t data)
+	{
+		*(ICPLB_ADDR + i) = addr;
+		*(ICPLB_DATA + i) = data;
+	}
+	void dcplb_add(uint32_t addr, uint32_t data)
+	{
+		*(DCPLB_ADDR + i) = addr;
+		*(DCPLB_DATA + i) = data;
+	}
+
+	/* populate a few common entries ... we'll let
+	 * the memory map and cplb exception handler do
+	 * the rest of the work.
+	 */
+	i = 0;
+	ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
+	ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
+	DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
+	DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
+
+	icplb_add(0xFFA00000, L1_IMEMORY);
+	dcplb_add(0xFF800000, L1_DMEMORY);
+	++i;
+
+	if (CONFIG_MEM_SIZE) {
+		uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
+		uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN;
+		mbase &= CPLB_PAGE_MASK;
+		mend &= CPLB_PAGE_MASK;
+
+		icplb_add(mbase, SDRAM_IKERNEL);
+		dcplb_add(mbase, SDRAM_DKERNEL);
+		++i;
+
+		/*
+		 * If the monitor crosses a 4 meg boundary, we'll need
+		 * to lock two entries for it.  We assume it doesn't
+		 * cross two 4 meg boundaries ...
+		 */
+		if (mbase != mend) {
+			icplb_add(mend, SDRAM_IKERNEL);
+			dcplb_add(mend, SDRAM_DKERNEL);
+			++i;
+		}
+	}
+
+	icplb_add(0x20000000, SDRAM_INON_CHBL);
+	dcplb_add(0x20000000, SDRAM_EBIU);
+	++i;
+
+	/* Add entries for the rest of external RAM up to the bootrom */
+	extern_memory = 0;
+
+#ifdef CONFIG_DEBUG_NULL_PTR
+	icplb_add(extern_memory, (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+	dcplb_add(extern_memory, (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
+	++i;
+	icplb_add(extern_memory, SDRAM_IKERNEL);
+	dcplb_add(extern_memory, SDRAM_DKERNEL);
+	extern_memory += CPLB_PAGE_SIZE;
+	++i;
+#endif
+
+	while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) {
+		icplb_add(extern_memory, SDRAM_IGENERIC);
+		dcplb_add(extern_memory, SDRAM_DGENERIC);
+		extern_memory += CPLB_PAGE_SIZE;
+		++i;
+	}
+	while (i < 16) {
+		icplb_add(0, 0);
+		dcplb_add(0, 0);
+		++i;
+	}
+}
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *
+ * The requirements for any new initalization function is simple: it
+ * receives a pointer to the "global data" structure as it's only
+ * argument, and returns an integer return code, where 0 means
+ * "continue" and != 0 means "fatal error, hang the system".
+ */
+
+extern int watchdog_init(void);
+extern int exception_init(void);
+extern int irq_init(void);
+extern int timer_init(void);
+
+void board_init_f(ulong bootflag)
+{
+	ulong addr;
+	bd_t *bd;
+	char buf[32];
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+	serial_early_puts("Board early init flash\n");
+	board_early_init_f();
+#endif
+
+	serial_early_puts("Init CPLB tables\n");
+	init_cplbtables();
+
+	serial_early_puts("Exceptions setup\n");
+	exception_init();
+
+#ifndef CONFIG_ICACHE_OFF
+	serial_early_puts("Turn on ICACHE\n");
+	icache_enable();
+#endif
+#ifndef CONFIG_DCACHE_OFF
+	serial_early_puts("Turn on DCACHE\n");
+	dcache_enable();
+#endif
+
+#ifdef CONFIG_WATCHDOG
+	serial_early_puts("Setting up external watchdog\n");
+	watchdog_init();
+#endif
+
+#ifdef DEBUG
+	if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
+		hang();
+#endif
+	serial_early_puts("Init global data\n");
+	gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
+	memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
+
+	/* Board data initialization */
+	addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t));
+
+	/* Align to 4 byte boundary */
+	addr &= ~(4 - 1);
+	bd = (bd_t *) addr;
+	gd->bd = bd;
+	memset((void *)bd, 0, sizeof(bd_t));
+
+	bd->bi_r_version = version_string;
+	bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+	bd->bi_board_name = BFIN_BOARD_NAME;
+	bd->bi_vco = get_vco();
+	bd->bi_cclk = get_cclk();
+	bd->bi_sclk = get_sclk();
+	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+
+	/* Initialize */
+	serial_early_puts("IRQ init\n");
+	irq_init();
+	serial_early_puts("Environment init\n");
+	env_init();
+	serial_early_puts("Baudrate init\n");
+	init_baudrate();
+	serial_early_puts("Serial init\n");
+	serial_init();
+	serial_early_puts("Console init flash\n");
+	console_init_f();
+	serial_early_puts("End of early debugging\n");
+	display_banner();
+
+	checkboard();
+	timer_init();
+
+	printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
+	printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
+	printf("System: %s MHz\n", strmhz(buf, get_sclk()));
+
+	printf("RAM:   ");
+	print_size(bd->bi_memsize, "\n");
+#if defined(CONFIG_POST)
+	post_init_f();
+	post_bootmode_init();
+	post_run(NULL, POST_ROM | post_bootmode_get(0));
+#endif
+
+	board_init_r((gd_t *) gd, 0x20000010);
+}
+
+static void board_net_init_r(bd_t *bd)
+{
+#ifdef CONFIG_BITBANGMII
+	bb_miiphy_init();
+#endif
+#ifdef CONFIG_CMD_NET
+	char *s;
+
+	if ((s = getenv("bootfile")) != NULL)
+		copy_filename(BootFile, s, sizeof(BootFile));
+
+	bd->bi_ip_addr = getenv_IPaddr("ipaddr");
+
+	printf("Net:   ");
+	eth_initialize(gd->bd);
+#endif
+}
+
+void board_init_r(gd_t * id, ulong dest_addr)
+{
+	char *s;
+	bd_t *bd;
+	gd = id;
+	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
+	bd = gd->bd;
+
+#if defined(CONFIG_POST)
+	post_output_backlog();
+	post_reloc();
+#endif
+
+	/* initialize malloc() area */
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
+
+#if	!defined(CONFIG_SYS_NO_FLASH)
+	/* Initialize the flash and protect u-boot by default */
+	extern flash_info_t flash_info[];
+	puts("Flash: ");
+	ulong size = flash_init();
+	print_size(size, "\n");
+	flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+		&flash_info[0]);
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+	bd->bi_flashsize = size;
+	bd->bi_flashoffset = 0;
+#else
+	bd->bi_flashstart = 0;
+	bd->bi_flashsize = 0;
+	bd->bi_flashoffset = 0;
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:  ");
+	mmc_initialize(bd);
+#endif
+
+	/* relocate environment function pointers etc. */
+	env_relocate();
+
+	/* Initialize stdio devices */
+	stdio_init();
+	jumptable_init();
+
+	/* Initialize the console (after the relocation and devices init) */
+	console_init_r();
+
+#ifdef CONFIG_CMD_KGDB
+	puts("KGDB:  ");
+	kgdb_init();
+#endif
+
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
+	status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF);
+#endif
+
+	/* Initialize from environment */
+	if ((s = getenv("loadaddr")) != NULL)
+		load_addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_MISC_INIT_R)
+	/* miscellaneous platform dependent initialisations */
+	misc_init_r();
+#endif
+
+	board_net_init_r(bd);
+
+	display_global_data();
+
+#if defined(CONFIG_POST)
+	if (post_flag)
+		post_run(NULL, POST_RAM | post_bootmode_get(0));
+#endif
+
+	if (bfin_os_log_check()) {
+		puts("\nLog buffer from operating system:\n");
+		bfin_os_log_dump();
+		puts("\n");
+	}
+
+	/* main_loop() can return to retry autoboot, if so just run it again. */
+	for (;;)
+		main_loop();
+}
+
+void hang(void)
+{
+#ifdef CONFIG_STATUS_LED
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+	status_led_set(STATUS_LED_CRASH, STATUS_LED_BLINKING);
+#endif
+	puts("### ERROR ### Please RESET the board ###\n");
+	while (1)
+		/* If a JTAG emulator is hooked up, we'll automatically trigger
+		 * a breakpoint in it.  If one isn't, this is just a NOP.
+		 */
+		asm("emuexcpt;");
+}
diff --git a/arch/blackfin/lib/boot.c b/arch/blackfin/lib/boot.c
new file mode 100644
index 0000000..951d5b0
--- /dev/null
+++ b/arch/blackfin/lib/boot.c
@@ -0,0 +1,63 @@
+/*
+ * U-boot - boot.c - misc boot helper functions
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <asm/blackfin.h>
+
+#ifdef SHARED_RESOURCES
+extern void swap_to(int device_id);
+#endif
+
+static char *make_command_line(void)
+{
+	char *dest = (char *)CONFIG_LINUX_CMDLINE_ADDR;
+	char *bootargs = getenv("bootargs");
+
+	if (bootargs == NULL)
+		return NULL;
+
+	strncpy(dest, bootargs, CONFIG_LINUX_CMDLINE_SIZE);
+	dest[CONFIG_LINUX_CMDLINE_SIZE - 1] = 0;
+	return dest;
+}
+
+extern ulong bfin_poweron_retx;
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	int	(*appl) (char *cmdline);
+	char	*cmdline;
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+#ifdef SHARED_RESOURCES
+	swap_to(FLASH);
+#endif
+
+	appl = (int (*)(char *))images->ep;
+
+	printf("Starting Kernel at = %p\n", appl);
+	cmdline = make_command_line();
+	icache_disable();
+	dcache_disable();
+	asm __volatile__(
+		"RETX = %[retx];"
+		"CALL (%0);"
+		:
+		: "p"(appl), "q0"(cmdline), [retx] "d"(bfin_poweron_retx)
+	);
+	/* does not return */
+
+	return 1;
+}
diff --git a/arch/blackfin/lib/cache.c b/arch/blackfin/lib/cache.c
new file mode 100644
index 0000000..0a321a4
--- /dev/null
+++ b/arch/blackfin/lib/cache.c
@@ -0,0 +1,113 @@
+/*
+ * U-boot - cache.c
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	void *start_addr, *end_addr;
+	int istatus, dstatus;
+
+	/* no need to flush stuff in on chip memory (L1/L2/etc...) */
+	if (addr >= 0xE0000000)
+		return;
+
+	start_addr = (void *)addr;
+	end_addr = (void *)(addr + size);
+	istatus = icache_status();
+	dstatus = dcache_status();
+
+	if (istatus) {
+		if (dstatus)
+			blackfin_icache_dcache_flush_range(start_addr, end_addr);
+		else
+			blackfin_icache_flush_range(start_addr, end_addr);
+	} else if (dstatus)
+		blackfin_dcache_flush_range(start_addr, end_addr);
+}
+
+#ifdef CONFIG_DCACHE_WB
+static void flushinv_all_dcache(void)
+{
+	u32 way, bank, subbank, set;
+	u32 status, addr;
+	u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+	for (bank = 0; bank < 2; ++bank) {
+		if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+			continue;
+
+		for (way = 0; way < 2; ++way)
+			for (subbank = 0; subbank < 4; ++subbank)
+				for (set = 0; set < 64; ++set) {
+
+					bfin_write_DTEST_COMMAND(
+						way << 26 |
+						bank << 23 |
+						subbank << 16 |
+						set << 5
+					);
+					CSYNC();
+					status = bfin_read_DTEST_DATA0();
+
+					/* only worry about valid/dirty entries */
+					if ((status & 0x3) != 0x3)
+						continue;
+
+					/* construct the address using the tag */
+					addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+					/* flush it */
+					__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
+				}
+	}
+}
+#endif
+
+void icache_enable(void)
+{
+	bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+	SSYNC();
+}
+
+void icache_disable(void)
+{
+	bfin_write_IMEM_CONTROL(0);
+	SSYNC();
+}
+
+int icache_status(void)
+{
+	return bfin_read_IMEM_CONTROL() & IMC;
+}
+
+void dcache_enable(void)
+{
+	bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+	SSYNC();
+}
+
+void dcache_disable(void)
+{
+#ifdef CONFIG_DCACHE_WB
+	bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ENDCPLB));
+	flushinv_all_dcache();
+#endif
+	bfin_write_DMEM_CONTROL(0);
+	SSYNC();
+}
+
+int dcache_status(void)
+{
+	return bfin_read_DMEM_CONTROL() & ACACHE_BCACHE;
+}
diff --git a/arch/blackfin/lib/clocks.c b/arch/blackfin/lib/clocks.c
new file mode 100644
index 0000000..0be395b
--- /dev/null
+++ b/arch/blackfin/lib/clocks.c
@@ -0,0 +1,77 @@
+/*
+ * clocks.c - figure out sclk/cclk/vco and such
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+
+/* Get the voltage input multiplier */
+static u_long cached_vco_pll_ctl, cached_vco;
+u_long get_vco(void)
+{
+	u_long msel;
+
+	u_long pll_ctl = bfin_read_PLL_CTL();
+	if (pll_ctl == cached_vco_pll_ctl)
+		return cached_vco;
+	else
+		cached_vco_pll_ctl = pll_ctl;
+
+	msel = (pll_ctl >> 9) & 0x3F;
+	if (0 == msel)
+		msel = 64;
+
+	cached_vco = CONFIG_CLKIN_HZ;
+	cached_vco >>= (1 & pll_ctl);	/* DF bit */
+	cached_vco *= msel;
+	return cached_vco;
+}
+
+/* Get the Core clock */
+static u_long cached_cclk_pll_div, cached_cclk;
+u_long get_cclk(void)
+{
+	u_long csel, ssel;
+
+	if (bfin_read_PLL_STAT() & 0x1)
+		return CONFIG_CLKIN_HZ;
+
+	ssel = bfin_read_PLL_DIV();
+	if (ssel == cached_cclk_pll_div)
+		return cached_cclk;
+	else
+		cached_cclk_pll_div = ssel;
+
+	csel = ((ssel >> 4) & 0x03);
+	ssel &= 0xf;
+	if (ssel && ssel < (1 << csel))	/* SCLK > CCLK */
+		cached_cclk = get_vco() / ssel;
+	else
+		cached_cclk = get_vco() >> csel;
+	return cached_cclk;
+}
+
+/* Get the System clock */
+static u_long cached_sclk_pll_div, cached_sclk;
+u_long get_sclk(void)
+{
+	u_long ssel;
+
+	if (bfin_read_PLL_STAT() & 0x1)
+		return CONFIG_CLKIN_HZ;
+
+	ssel = bfin_read_PLL_DIV();
+	if (ssel == cached_sclk_pll_div)
+		return cached_sclk;
+	else
+		cached_sclk_pll_div = ssel;
+
+	ssel &= 0xf;
+
+	cached_sclk = get_vco() / ssel;
+	return cached_sclk;
+}
diff --git a/arch/blackfin/lib/cmd_cache_dump.c b/arch/blackfin/lib/cmd_cache_dump.c
new file mode 100644
index 0000000..de5840e
--- /dev/null
+++ b/arch/blackfin/lib/cmd_cache_dump.c
@@ -0,0 +1,145 @@
+/*
+ * U-boot - cmd_cache_dump.c
+ *
+ * Copyright (c) 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
+
+static int check_limit(const char *type, size_t start_limit, size_t end_limit, size_t start, size_t end)
+{
+	if (start >= start_limit && start <= end_limit && \
+	    end <= end_limit && end >= start_limit && \
+	    start <= end)
+		return 0;
+
+	printf("%s limit violation: %zu <= (user:%zu) <= (user:%zu) <= %zu\n",
+		type, start_limit, start, end, end_limit);
+	return 1;
+}
+
+int do_icache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int cache_status = icache_status();
+
+	if (cache_status)
+		icache_disable();
+
+	uint32_t cmd_base, tag, cache_upper, cache_lower;
+
+	size_t way, way_start = 0, way_end = 3;
+	size_t sbnk, sbnk_start = 0, sbnk_end = 3;
+	size_t set, set_start = 0, set_end = 31;
+	size_t dw;
+
+	if (argc > 1) {
+		way_start = way_end = simple_strtoul(argv[1], NULL, 10);
+		if (argc > 2) {
+			sbnk_start = sbnk_end = simple_strtoul(argv[2], NULL, 10);
+			if (argc > 3)
+				set_start = set_end = simple_strtoul(argv[3], NULL, 10);
+		}
+	}
+
+	if (check_limit("way", 0, 3, way_start, way_end) || \
+	    check_limit("subbank", 0, 3, sbnk_start, sbnk_end) || \
+	    check_limit("set", 0, 31, set_start, set_end))
+		return 1;
+
+	puts("Way:Subbank:Set: [valid-tag lower upper] {invalid-tag lower upper}...\n");
+
+	for (way = way_start; way <= way_end; ++way) {
+		for (sbnk = sbnk_start; sbnk <= sbnk_end; ++sbnk) {
+			for (set = set_start; set <= set_end; ++set) {
+				printf("%zu:%zu:%2zu: ", way, sbnk, set);
+				for (dw = 0; dw < 4; ++dw) {
+					if (ctrlc())
+						return 1;
+
+					cmd_base = \
+						(way  << 26) | \
+						(sbnk << 16) | \
+						(set  <<  5) | \
+						(dw   <<  3);
+
+					/* first read the tag */
+					bfin_write_ITEST_COMMAND(cmd_base | 0x0);
+					SSYNC();
+					tag = bfin_read_ITEST_DATA0();
+					printf("%c%08x ", (tag & 0x1 ? ' ' : '{'), tag);
+
+					/* grab the data at this loc */
+					bfin_write_ITEST_COMMAND(cmd_base | 0x4);
+					SSYNC();
+					cache_lower = bfin_read_ITEST_DATA0();
+					cache_upper = bfin_read_ITEST_DATA1();
+					printf("%08x %08x%c ", cache_lower, cache_upper, (tag & 0x1 ? ' ' : '}'));
+				}
+				puts("\n");
+			}
+		}
+	}
+
+	if (cache_status)
+		icache_enable();
+
+	return 0;
+}
+
+U_BOOT_CMD(icache_dump, 4, 0, do_icache_dump,
+	"icache_dump - dump current instruction cache\n",
+	"[way] [subbank] [set]");
+
+int do_dcache_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	u32 way, bank, subbank, set;
+	u32 status, addr;
+	u32 dmem_ctl = bfin_read_DMEM_CONTROL();
+
+	for (bank = 0; bank < 2; ++bank) {
+		if (!(dmem_ctl & (1 << (DMC1_P - bank))))
+			continue;
+
+		for (way = 0; way < 2; ++way)
+			for (subbank = 0; subbank < 4; ++subbank) {
+				printf("%i:%i:%i:\t", bank, way, subbank);
+				for (set = 0; set < 64; ++set) {
+
+					if (ctrlc())
+						return 1;
+
+					/* retrieve a cache tag */
+					bfin_write_DTEST_COMMAND(
+						way << 26 |
+						bank << 23 |
+						subbank << 16 |
+						set << 5
+					);
+					CSYNC();
+					status = bfin_read_DTEST_DATA0();
+
+					/* construct the address using the tag */
+					addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
+
+					/* show it */
+					if (set && !(set % 4))
+						puts("\n\t");
+					printf("%c%08x%c%08x%c ", (status & 0x1 ? '[' : '{'), status, (status & 0x2 ? 'd' : ' '), addr, (status & 0x1 ? ']' : '}'));
+				}
+				puts("\n");
+			}
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(dcache_dump, 4, 0, do_dcache_dump,
+	"dcache_dump - dump current data cache\n",
+	"[bank] [way] [subbank] [set]");
diff --git a/arch/blackfin/lib/ins.S b/arch/blackfin/lib/ins.S
new file mode 100644
index 0000000..4519596
--- /dev/null
+++ b/arch/blackfin/lib/ins.S
@@ -0,0 +1,117 @@
+/*
+ * arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
+ *
+ * Copyright 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <asm/blackfin.h>
+
+.align 2
+
+#ifdef CONFIG_IPIPE
+# define DO_CLI \
+	[--sp] = rets; \
+	[--sp] = (P5:0); \
+	sp += -12; \
+	call ___ipipe_disable_root_irqs_hw; \
+	sp += 12; \
+	(P5:0) = [sp++];
+# define CLI_INNER_NOP
+#else
+# define DO_CLI cli R3;
+# define CLI_INNER_NOP nop; nop; nop;
+#endif
+
+#ifdef CONFIG_IPIPE
+# define DO_STI \
+	sp += -12; \
+	call ___ipipe_enable_root_irqs_hw; \
+	sp += 12; \
+2:	rets = [sp++];
+#else
+# define DO_STI 2: sti R3;
+#endif
+
+#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
+# define CLI_OUTER DO_CLI;
+# define STI_OUTER DO_STI;
+# define CLI_INNER 1:
+# if ANOMALY_05000416
+#  define STI_INNER nop; 2: nop;
+# else
+#  define STI_INNER 2:
+# endif
+#else
+# define CLI_OUTER
+# define STI_OUTER
+# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
+# define STI_INNER DO_STI;
+#endif
+
+/*
+ * Reads on the Blackfin are speculative. In Blackfin terms, this means they
+ * can be interrupted at any time (even after they have been issued on to the
+ * external bus), and re-issued after the interrupt occurs.
+ *
+ * If a FIFO is sitting on the end of the read, it will see two reads,
+ * when the core only sees one. The FIFO receives the read which is cancelled,
+ * and not delivered to the core.
+ *
+ * To solve this, interrupts are turned off before reads occur to I/O space.
+ * There are 3 versions of all these functions
+ *  - turns interrupts off every read (higher overhead, but lower latency)
+ *  - turns interrupts off every loop (low overhead, but longer latency)
+ *  - DMA version, which do not suffer from this issue. DMA versions have
+ *      different name (prefixed by dma_ ), and are located in
+ *      ../kernel/bfin_dma_5xx.c
+ * Using the dma related functions are recommended for transfering large
+ * buffers in/out of FIFOs.
+ */
+
+#define COMMON_INS(func, ops) \
+ENTRY(_ins##func) \
+	P0 = R0;	/* P0 = port */ \
+	CLI_OUTER;	/* 3 instructions before first read access */ \
+	P1 = R1;	/* P1 = address */ \
+	P2 = R2;	/* P2 = count */ \
+	SSYNC; \
+ \
+	LSETUP(1f, 2f) LC0 = P2; \
+	CLI_INNER; \
+	ops; \
+	STI_INNER; \
+ \
+	STI_OUTER; \
+	RTS; \
+ENDPROC(_ins##func)
+
+COMMON_INS(l, \
+	R0 = [P0]; \
+	[P1++] = R0; \
+)
+
+COMMON_INS(w, \
+	R0 = W[P0]; \
+	W[P1++] = R0; \
+)
+
+COMMON_INS(w_8, \
+	R0 = W[P0]; \
+	B[P1++] = R0; \
+	R0 = R0 >> 8; \
+	B[P1++] = R0; \
+)
+
+COMMON_INS(b, \
+	R0 = B[P0]; \
+	B[P1++] = R0; \
+)
+
+COMMON_INS(l_16, \
+	R0 = [P0]; \
+	W[P1++] = R0; \
+	R0 = R0 >> 16; \
+	W[P1++] = R0; \
+)
diff --git a/arch/blackfin/lib/kgdb.c b/arch/blackfin/lib/kgdb.c
new file mode 100644
index 0000000..bd62d71
--- /dev/null
+++ b/arch/blackfin/lib/kgdb.c
@@ -0,0 +1,423 @@
+/*
+ * U-boot - architecture specific kgdb code
+ *
+ * Copyright 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <kgdb.h>
+#include <asm/processor.h>
+#include <asm/mach-common/bits/core.h>
+#include "kgdb.h"
+#include <asm/deferred.h>
+#include <asm/traps.h>
+#include <asm/signal.h>
+
+void kgdb_enter(struct pt_regs *regs, kgdb_data *kdp)
+{
+	/* disable interrupts */
+	disable_interrupts();
+
+	/* reply to host that an exception has occurred */
+	kdp->sigval = kgdb_trap(regs);
+
+	/* send the PC and the Stack Pointer */
+	kdp->nregs = 2;
+	kdp->regs[0].num = BFIN_PC;
+	kdp->regs[0].val = regs->pc;
+
+	kdp->regs[1].num = BFIN_SP;
+	kdp->regs[1].val = (unsigned long)regs;
+
+}
+
+void kgdb_exit(struct pt_regs *regs, kgdb_data *kdp)
+{
+	if (kdp->extype & KGDBEXIT_WITHADDR)
+		printf("KGDBEXIT_WITHADDR\n");
+
+	switch (kdp->extype & KGDBEXIT_TYPEMASK) {
+	case KGDBEXIT_KILL:
+		printf("KGDBEXIT_KILL:\n");
+		break;
+	case KGDBEXIT_CONTINUE:
+		/* Make sure the supervisor single step bit is clear */
+		regs->syscfg &= ~1;
+		break;
+	case KGDBEXIT_SINGLE:
+		/* set the supervisor single step bit */
+		regs->syscfg |= 1;
+		break;
+	default:
+		printf("KGDBEXIT : %d\n", kdp->extype);
+	}
+
+	/* enable interrupts */
+	enable_interrupts();
+}
+
+int kgdb_trap(struct pt_regs *regs)
+{
+	/* ipend doesn't get filled in properly */
+	switch (regs->seqstat & EXCAUSE) {
+	case VEC_EXCPT01:
+		return SIGTRAP;
+	case VEC_EXCPT03:
+		return SIGSEGV;
+	case VEC_EXCPT02:
+		return SIGTRAP;
+	case VEC_EXCPT04 ... VEC_EXCPT15:
+		return SIGILL;
+	case VEC_STEP:
+		return SIGTRAP;
+	case VEC_OVFLOW:
+		return SIGTRAP;
+	case VEC_UNDEF_I:
+		return SIGILL;
+	case VEC_ILGAL_I:
+		return SIGILL;
+	case VEC_CPLB_VL:
+		return SIGSEGV;
+	case VEC_MISALI_D:
+		return SIGBUS;
+	case VEC_UNCOV:
+		return SIGILL;
+	case VEC_CPLB_MHIT:
+		return SIGSEGV;
+	case VEC_MISALI_I:
+		return SIGBUS;
+	case VEC_CPLB_I_VL:
+		return SIGBUS;
+	case VEC_CPLB_I_MHIT:
+		return SIGSEGV;
+	default:
+		return SIGBUS;
+	}
+}
+
+/*
+ * getregs - gets the pt_regs, and gives them to kgdb's buffer
+ */
+int kgdb_getregs(struct pt_regs *regs, char *buf, int max)
+{
+	unsigned long *gdb_regs = (unsigned long *)buf;
+
+	if (max < NUMREGBYTES)
+		kgdb_error(KGDBERR_NOSPACE);
+
+	if ((unsigned long)gdb_regs & 3)
+		kgdb_error(KGDBERR_ALIGNFAULT);
+
+	gdb_regs[BFIN_R0] = regs->r0;
+	gdb_regs[BFIN_R1] = regs->r1;
+	gdb_regs[BFIN_R2] = regs->r2;
+	gdb_regs[BFIN_R3] = regs->r3;
+	gdb_regs[BFIN_R4] = regs->r4;
+	gdb_regs[BFIN_R5] = regs->r5;
+	gdb_regs[BFIN_R6] = regs->r6;
+	gdb_regs[BFIN_R7] = regs->r7;
+	gdb_regs[BFIN_P0] = regs->p0;
+	gdb_regs[BFIN_P1] = regs->p1;
+	gdb_regs[BFIN_P2] = regs->p2;
+	gdb_regs[BFIN_P3] = regs->p3;
+	gdb_regs[BFIN_P4] = regs->p4;
+	gdb_regs[BFIN_P5] = regs->p5;
+	gdb_regs[BFIN_SP] = (unsigned long)regs;
+	gdb_regs[BFIN_FP] = regs->fp;
+	gdb_regs[BFIN_I0] = regs->i0;
+	gdb_regs[BFIN_I1] = regs->i1;
+	gdb_regs[BFIN_I2] = regs->i2;
+	gdb_regs[BFIN_I3] = regs->i3;
+	gdb_regs[BFIN_M0] = regs->m0;
+	gdb_regs[BFIN_M1] = regs->m1;
+	gdb_regs[BFIN_M2] = regs->m2;
+	gdb_regs[BFIN_M3] = regs->m3;
+	gdb_regs[BFIN_B0] = regs->b0;
+	gdb_regs[BFIN_B1] = regs->b1;
+	gdb_regs[BFIN_B2] = regs->b2;
+	gdb_regs[BFIN_B3] = regs->b3;
+	gdb_regs[BFIN_L0] = regs->l0;
+	gdb_regs[BFIN_L1] = regs->l1;
+	gdb_regs[BFIN_L2] = regs->l2;
+	gdb_regs[BFIN_L3] = regs->l3;
+	gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
+	gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
+	gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
+	gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
+	gdb_regs[BFIN_ASTAT] = regs->astat;
+	gdb_regs[BFIN_RETS] = regs->rets;
+	gdb_regs[BFIN_LC0] = regs->lc0;
+	gdb_regs[BFIN_LT0] = regs->lt0;
+	gdb_regs[BFIN_LB0] = regs->lb0;
+	gdb_regs[BFIN_LC1] = regs->lc1;
+	gdb_regs[BFIN_LT1] = regs->lt1;
+	gdb_regs[BFIN_LB1] = regs->lb1;
+	gdb_regs[BFIN_CYCLES] = 0;
+	gdb_regs[BFIN_CYCLES2] = 0;
+	gdb_regs[BFIN_USP] = regs->usp;
+	gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
+	gdb_regs[BFIN_SYSCFG] = regs->syscfg;
+	gdb_regs[BFIN_RETI] = regs->pc;
+	gdb_regs[BFIN_RETX] = regs->retx;
+	gdb_regs[BFIN_RETN] = regs->retn;
+	gdb_regs[BFIN_RETE] = regs->rete;
+	gdb_regs[BFIN_PC] = regs->pc;
+	gdb_regs[BFIN_CC] = 0;
+	gdb_regs[BFIN_EXTRA1] = 0;
+	gdb_regs[BFIN_EXTRA2] = 0;
+	gdb_regs[BFIN_EXTRA3] = 0;
+	gdb_regs[BFIN_IPEND] = regs->ipend;
+
+	return NUMREGBYTES;
+}
+
+/*
+ * putreg - put kgdb's reg (regno) into the pt_regs
+ */
+void kgdb_putreg(struct pt_regs *regs, int regno, char *buf, int length)
+{
+	unsigned long *ptr = (unsigned long *)buf;
+
+	if (regno < 0 || regno > BFIN_NUM_REGS)
+		kgdb_error(KGDBERR_BADPARAMS);
+
+	if (length < 4)
+		kgdb_error(KGDBERR_NOSPACE);
+
+	if ((unsigned long)ptr & 3)
+		kgdb_error(KGDBERR_ALIGNFAULT);
+
+	switch (regno) {
+	case BFIN_R0:
+		regs->r0 = *ptr;
+		break;
+	case BFIN_R1:
+		regs->r1 = *ptr;
+		break;
+	case BFIN_R2:
+		regs->r2 = *ptr;
+		break;
+	case BFIN_R3:
+		regs->r3 = *ptr;
+		break;
+	case BFIN_R4:
+		regs->r4 = *ptr;
+		break;
+	case BFIN_R5:
+		regs->r5 = *ptr;
+		break;
+	case BFIN_R6:
+		regs->r6 = *ptr;
+		break;
+	case BFIN_R7:
+		regs->r7 = *ptr;
+		break;
+	case BFIN_P0:
+		regs->p0 = *ptr;
+		break;
+	case BFIN_P1:
+		regs->p1 = *ptr;
+		break;
+	case BFIN_P2:
+		regs->p2 = *ptr;
+		break;
+	case BFIN_P3:
+		regs->p3 = *ptr;
+		break;
+	case BFIN_P4:
+		regs->p4 = *ptr;
+		break;
+	case BFIN_P5:
+		regs->p5 = *ptr;
+		break;
+	case BFIN_SP:
+		regs->reserved = *ptr;
+		break;
+	case BFIN_FP:
+		regs->fp = *ptr;
+		break;
+	case BFIN_I0:
+		regs->i0 = *ptr;
+		break;
+	case BFIN_I1:
+		regs->i1 = *ptr;
+		break;
+	case BFIN_I2:
+		regs->i2 = *ptr;
+		break;
+	case BFIN_I3:
+		regs->i3 = *ptr;
+		break;
+	case BFIN_M0:
+		regs->m0 = *ptr;
+		break;
+	case BFIN_M1:
+		regs->m1 = *ptr;
+		break;
+	case BFIN_M2:
+		regs->m2 = *ptr;
+		break;
+	case BFIN_M3:
+		regs->m3 = *ptr;
+		break;
+	case BFIN_B0:
+		regs->b0 = *ptr;
+		break;
+	case BFIN_B1:
+		regs->b1 = *ptr;
+		break;
+	case BFIN_B2:
+		regs->b2 = *ptr;
+		break;
+	case BFIN_B3:
+		regs->b3 = *ptr;
+		break;
+	case BFIN_L0:
+		regs->l0 = *ptr;
+		break;
+	case BFIN_L1:
+		regs->l1 = *ptr;
+		break;
+	case BFIN_L2:
+		regs->l2 = *ptr;
+		break;
+	case BFIN_L3:
+		regs->l3 = *ptr;
+		break;
+	case BFIN_A0_DOT_X:
+		regs->a0x = *ptr;
+		break;
+	case BFIN_A0_DOT_W:
+		regs->a0w = *ptr;
+		break;
+	case BFIN_A1_DOT_X:
+		regs->a1x = *ptr;
+		break;
+	case BFIN_A1_DOT_W:
+		regs->a1w = *ptr;
+		break;
+	case BFIN_ASTAT:
+		regs->astat = *ptr;
+		break;
+	case BFIN_RETS:
+		regs->rets = *ptr;
+		break;
+	case BFIN_LC0:
+		regs->lc0 = *ptr;
+		break;
+	case BFIN_LT0:
+		regs->lt0 = *ptr;
+		break;
+	case BFIN_LB0:
+		regs->lb0 = *ptr;
+		break;
+	case BFIN_LC1:
+		regs->lc1 = *ptr;
+		break;
+	case BFIN_LT1:
+		regs->lt1 = *ptr;
+		break;
+	case BFIN_LB1:
+		regs->lb1 = *ptr;
+		break;
+/*
+  BFIN_CYCLES,
+  BFIN_CYCLES2,
+  BFIN_USP,
+  BFIN_SEQSTAT,
+  BFIN_SYSCFG,
+*/
+	case BFIN_RETX:
+		regs->retx = *ptr;
+		break;
+	case BFIN_RETN:
+		regs->retn = *ptr;
+		break;
+	case BFIN_RETE:
+		regs->rete = *ptr;
+		break;
+	case BFIN_PC:
+		regs->pc = *ptr;
+		break;
+
+	default:
+		kgdb_error(KGDBERR_BADPARAMS);
+	}
+}
+
+void kgdb_putregs(struct pt_regs *regs, char *buf, int length)
+{
+	unsigned long *gdb_regs = (unsigned long *)buf;
+
+	if (length != BFIN_NUM_REGS)
+		kgdb_error(KGDBERR_NOSPACE);
+
+	if ((unsigned long)gdb_regs & 3)
+		kgdb_error(KGDBERR_ALIGNFAULT);
+
+	regs->r0 = gdb_regs[BFIN_R0];
+	regs->r1 = gdb_regs[BFIN_R1];
+	regs->r2 = gdb_regs[BFIN_R2];
+	regs->r3 = gdb_regs[BFIN_R3];
+	regs->r4 = gdb_regs[BFIN_R4];
+	regs->r5 = gdb_regs[BFIN_R5];
+	regs->r6 = gdb_regs[BFIN_R6];
+	regs->r7 = gdb_regs[BFIN_R7];
+	regs->p0 = gdb_regs[BFIN_P0];
+	regs->p1 = gdb_regs[BFIN_P1];
+	regs->p2 = gdb_regs[BFIN_P2];
+	regs->p3 = gdb_regs[BFIN_P3];
+	regs->p4 = gdb_regs[BFIN_P4];
+	regs->p5 = gdb_regs[BFIN_P5];
+	regs->fp = gdb_regs[BFIN_FP];
+/*	regs->sp = gdb_regs[BFIN_ ]; */
+	regs->i0 = gdb_regs[BFIN_I0];
+	regs->i1 = gdb_regs[BFIN_I1];
+	regs->i2 = gdb_regs[BFIN_I2];
+	regs->i3 = gdb_regs[BFIN_I3];
+	regs->m0 = gdb_regs[BFIN_M0];
+	regs->m1 = gdb_regs[BFIN_M1];
+	regs->m2 = gdb_regs[BFIN_M2];
+	regs->m3 = gdb_regs[BFIN_M3];
+	regs->b0 = gdb_regs[BFIN_B0];
+	regs->b1 = gdb_regs[BFIN_B1];
+	regs->b2 = gdb_regs[BFIN_B2];
+	regs->b3 = gdb_regs[BFIN_B3];
+	regs->l0 = gdb_regs[BFIN_L0];
+	regs->l1 = gdb_regs[BFIN_L1];
+	regs->l2 = gdb_regs[BFIN_L2];
+	regs->l3 = gdb_regs[BFIN_L3];
+	regs->a0x = gdb_regs[BFIN_A0_DOT_X];
+	regs->a0w = gdb_regs[BFIN_A0_DOT_W];
+	regs->a1x = gdb_regs[BFIN_A1_DOT_X];
+	regs->a1w = gdb_regs[BFIN_A1_DOT_W];
+	regs->rets = gdb_regs[BFIN_RETS];
+	regs->lc0 = gdb_regs[BFIN_LC0];
+	regs->lt0 = gdb_regs[BFIN_LT0];
+	regs->lb0 = gdb_regs[BFIN_LB0];
+	regs->lc1 = gdb_regs[BFIN_LC1];
+	regs->lt1 = gdb_regs[BFIN_LT1];
+	regs->lb1 = gdb_regs[BFIN_LB1];
+	regs->usp = gdb_regs[BFIN_USP];
+	regs->syscfg = gdb_regs[BFIN_SYSCFG];
+	regs->retx = gdb_regs[BFIN_PC];
+	regs->retn = gdb_regs[BFIN_RETN];
+	regs->rete = gdb_regs[BFIN_RETE];
+	regs->pc = gdb_regs[BFIN_PC];
+
+#if 0	/* can't change these */
+	regs->astat = gdb_regs[BFIN_ASTAT];
+	regs->seqstat = gdb_regs[BFIN_SEQSTAT];
+	regs->ipend = gdb_regs[BFIN_IPEND];
+#endif
+
+}
+
+void kgdb_breakpoint(int argc, char *argv[])
+{
+	asm volatile ("excpt 0x1\n");
+}
diff --git a/arch/blackfin/lib/kgdb.h b/arch/blackfin/lib/kgdb.h
new file mode 100644
index 0000000..18f1f49
--- /dev/null
+++ b/arch/blackfin/lib/kgdb.h
@@ -0,0 +1,160 @@
+/* Blackfin KGDB header
+ *
+ * Copyright 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BLACKFIN_KGDB_H__
+#define __ASM_BLACKFIN_KGDB_H__
+
+/* gdb locks */
+#define KGDB_MAX_NO_CPUS 8
+
+/*
+ * BUFMAX defines the maximum number of characters in inbound/outbound buffers.
+ * At least NUMREGBYTES*2 are needed for register packets.
+ * Longer buffer is needed to list all threads.
+ */
+#define BUFMAX 2048
+
+enum regnames {
+  /* Core Registers */
+  BFIN_R0 = 0,
+  BFIN_R1,
+  BFIN_R2,
+  BFIN_R3,
+  BFIN_R4,
+  BFIN_R5,
+  BFIN_R6,
+  BFIN_R7,
+  BFIN_P0,
+  BFIN_P1,
+  BFIN_P2,
+  BFIN_P3,
+  BFIN_P4,
+  BFIN_P5,
+  BFIN_SP,
+  BFIN_FP,
+  BFIN_I0,
+  BFIN_I1,
+  BFIN_I2,
+  BFIN_I3,
+  BFIN_M0,
+  BFIN_M1,
+  BFIN_M2,
+  BFIN_M3,
+  BFIN_B0,
+  BFIN_B1,
+  BFIN_B2,
+  BFIN_B3,
+  BFIN_L0,
+  BFIN_L1,
+  BFIN_L2,
+  BFIN_L3,
+  BFIN_A0_DOT_X,
+  BFIN_A0_DOT_W,
+  BFIN_A1_DOT_X,
+  BFIN_A1_DOT_W,
+  BFIN_ASTAT,
+  BFIN_RETS,
+  BFIN_LC0,
+  BFIN_LT0,
+  BFIN_LB0,
+  BFIN_LC1,
+  BFIN_LT1,
+  BFIN_LB1,
+  BFIN_CYCLES,
+  BFIN_CYCLES2,
+  BFIN_USP,
+  BFIN_SEQSTAT,
+  BFIN_SYSCFG,
+  BFIN_RETI,
+  BFIN_RETX,
+  BFIN_RETN,
+  BFIN_RETE,
+
+  /* Pseudo Registers */
+  BFIN_PC,
+  BFIN_CC,
+  BFIN_EXTRA1,		/* Address of .text section.  */
+  BFIN_EXTRA2,		/* Address of .data section.  */
+  BFIN_EXTRA3,		/* Address of .bss section.  */
+  BFIN_FDPIC_EXEC,
+  BFIN_FDPIC_INTERP,
+
+  /* MMRs */
+  BFIN_IPEND,
+
+  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
+  BFIN_NUM_REGS		/* The number of all registers.  */
+};
+
+/* Number of bytes of registers.  */
+#define NUMREGBYTES (BFIN_NUM_REGS * 4)
+
+static inline void arch_kgdb_breakpoint(void)
+{
+	asm volatile ("EXCPT 2;");
+}
+#define BREAK_INSTR_SIZE	2
+#define CACHE_FLUSH_IS_SAFE	1
+#define GDB_ADJUSTS_BREAK_OFFSET
+#define GDB_SKIP_HW_WATCH_TEST
+#define HW_INST_WATCHPOINT_NUM	6
+#define HW_WATCHPOINT_NUM	8
+#define TYPE_INST_WATCHPOINT	0
+#define TYPE_DATA_WATCHPOINT	1
+
+/* Instruction watchpoint address control register bits mask */
+#define WPPWR		0x1
+#define WPIREN01	0x2
+#define WPIRINV01	0x4
+#define WPIAEN0		0x8
+#define WPIAEN1		0x10
+#define WPICNTEN0	0x20
+#define WPICNTEN1	0x40
+#define EMUSW0		0x80
+#define EMUSW1		0x100
+#define WPIREN23	0x200
+#define WPIRINV23	0x400
+#define WPIAEN2		0x800
+#define WPIAEN3		0x1000
+#define WPICNTEN2	0x2000
+#define WPICNTEN3	0x4000
+#define EMUSW2		0x8000
+#define EMUSW3		0x10000
+#define WPIREN45	0x20000
+#define WPIRINV45	0x40000
+#define WPIAEN4		0x80000
+#define WPIAEN5		0x100000
+#define WPICNTEN4	0x200000
+#define WPICNTEN5	0x400000
+#define EMUSW4		0x800000
+#define EMUSW5		0x1000000
+#define WPAND		0x2000000
+
+/* Data watchpoint address control register bits mask */
+#define WPDREN01	0x1
+#define WPDRINV01	0x2
+#define WPDAEN0		0x4
+#define WPDAEN1		0x8
+#define WPDCNTEN0	0x10
+#define WPDCNTEN1	0x20
+
+#define WPDSRC0		0xc0
+#define WPDACC0_OFFSET	8
+#define WPDSRC1		0xc00
+#define WPDACC1_OFFSET	12
+
+/* Watchpoint status register bits mask */
+#define STATIA0		0x1
+#define STATIA1		0x2
+#define STATIA2		0x4
+#define STATIA3		0x8
+#define STATIA4		0x10
+#define STATIA5		0x20
+#define STATDA0		0x40
+#define STATDA1		0x80
+
+#endif
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
new file mode 100644
index 0000000..6c834a7
--- /dev/null
+++ b/arch/blackfin/lib/memcmp.S
@@ -0,0 +1,103 @@
+/*
+ * File: memcmp.S
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+/*
+ * C Library function MEMCMP
+ * R0 = First Address
+ * R1 = Second Address
+ * R2 = count
+ * Favours word aligned data.
+ */
+
+.globl _memcmp;
+.type _memcmp, STT_FUNC;
+_memcmp:
+	I1 = P3;
+	P0 = R0;			/* P0 = s1 address */
+	P3 = R1;			/* P3 = s2 Address  */
+	P2 = R2 ;			/* P2 = count */
+	CC = R2 <= 7(IU);
+	IF CC JUMP  .Ltoo_small;
+	I0 = R1;			/* s2 */
+	R1 = R1 | R0;		/* OR addresses together */
+	R1 <<= 30;		/* check bottom two bits */
+	CC =  AZ;			/* AZ set if zero. */
+	IF !CC JUMP  .Lbytes ;	/* Jump if addrs not aligned. */
+
+	P1 = P2 >> 2;		/* count = n/4 */
+	R3 =  3;
+	R2 = R2 & R3;		/* remainder */
+	P2 = R2;			/* set remainder */
+
+	LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
+.Lquad_loop_s:
+	NOP;
+	R0 = [P0++];
+	R1 = [I0++];
+	CC = R0 == R1;
+	IF !CC JUMP .Lquad_different;
+.Lquad_loop_e:
+	NOP;
+
+	P3 = I0;			/* s2 */
+.Ltoo_small:
+	CC = P2 == 0;		/* Check zero count*/
+	IF CC JUMP .Lfinished;	/* very unlikely*/
+
+.Lbytes:
+	LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
+.Lbyte_loop_s:
+	R1 = B[P3++](Z);	/* *s2 */
+	R0 = B[P0++](Z);	/* *s1 */
+	CC = R0 == R1;
+	IF !CC JUMP .Ldifferent;
+.Lbyte_loop_e:
+	NOP;
+
+.Ldifferent:
+	R0 = R0 - R1;
+	P3 = I1;
+	RTS;
+
+.Lquad_different:
+/* We've read two quads which don't match.
+ * Can't just compare them, because we're
+ * a little-endian machine, so the MSBs of
+ * the regs occur at later addresses in the
+ * string.
+ * Arrange to re-read those two quads again,
+ * byte-by-byte.
+ */
+	P0 += -4;		/* back up to the start of the */
+	P3 = I0;		/* quads, and increase the*/
+	P2 += 4;		/* remainder count*/
+	P3 += -4;
+	JUMP .Lbytes;
+
+.Lfinished:
+	R0 = 0;
+	P3 = I1;
+	RTS;
+
+.size _memcmp, .-_memcmp
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
new file mode 100644
index 0000000..e6b359a
--- /dev/null
+++ b/arch/blackfin/lib/memcpy.S
@@ -0,0 +1,117 @@
+/*
+ * File: memcpy.S
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+.globl _memcpy_ASM;
+.type _memcpy_ASM, STT_FUNC;
+_memcpy_ASM:
+	CC = R2 <=  0;	/* length not positive?*/
+	IF CC JUMP  .L_P1L2147483647;	/* Nothing to do */
+
+	P0 = R0 ;	/* dst*/
+	P1 = R1 ;	/* src*/
+	P2 = R2 ;	/* length */
+
+	/* check for overlapping data */
+	CC = R1 < R0;	/* src < dst */
+	IF !CC JUMP .Lno_overlap;
+	R3 = R1 + R2;
+	CC = R0 < R3;	/* and dst < src+len */
+	IF CC JUMP .Lhas_overlap;
+
+.Lno_overlap:
+	/* Check for aligned data.*/
+
+	R3 = R1 | R0;
+	R0 = 0x3;
+	R3 = R3 & R0;
+	CC = R3;	/* low bits set on either address? */
+	IF CC JUMP .Lnot_aligned;
+
+	/* Both addresses are word-aligned, so we can copy
+	at least part of the data using word copies.*/
+	P2 = P2 >> 2;
+	CC = P2 <= 2;
+	IF !CC JUMP .Lmore_than_seven;
+	/* less than eight bytes... */
+	P2 = R2;
+	LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
+	R0 = R1;	/* setup src address for return */
+.Lthree_start:
+	R3 = B[P1++] (X);
+.Lthree_end:
+	B[P0++] = R3;
+
+	RTS;
+
+.Lmore_than_seven:
+	/* There's at least eight bytes to copy. */
+	P2 += -1;	/* because we unroll one iteration */
+	LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
+	R0 = R1;
+	I1 = P1;
+	R3 = [I1++];
+.Lword_loop:
+	MNOP || [P0++] = R3 || R3 = [I1++];
+
+	[P0++] = R3;
+	/* Any remaining bytes to copy? */
+	R3 = 0x3;
+	R3 = R2 & R3;
+	CC = R3 == 0;
+	P1 = I1;	/* in case there's something left, */
+	IF !CC JUMP .Lbytes_left;
+	RTS;
+.Lbytes_left:	P2 = R3;
+.Lnot_aligned:
+	/* From here, we're copying byte-by-byte. */
+	LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
+	R0 = R1;	/* Save src address for return */
+.Lbyte_start:
+	R1 = B[P1++] (X);
+.Lbyte_end:
+	B[P0++] = R1;
+
+.L_P1L2147483647:
+	RTS;
+
+.Lhas_overlap:
+/* Need to reverse the copying, because the
+ * dst would clobber the src.
+ * Don't bother to work out alignment for
+ * the reverse case.
+ */
+	R0 = R1;	/* save src for later. */
+	P0 = P0 + P2;
+	P0 += -1;
+	P1 = P1 + P2;
+	P1 += -1;
+	LSETUP(.Lover_start, .Lover_end) LC0=P2;
+.Lover_start:
+	R1 = B[P1--] (X);
+.Lover_end:
+	B[P0--] = R1;
+
+	RTS;
+
+.size _memcpy_ASM, .-_memcpy_ASM
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
new file mode 100644
index 0000000..e385c4f
--- /dev/null
+++ b/arch/blackfin/lib/memmove.S
@@ -0,0 +1,96 @@
+/*
+ * File: memmove.S
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+/*
+ * C Library function MEMMOVE
+ * R0 = To Address (leave unchanged to form result)
+ * R1 = From Address
+ * R2 = count
+ * Data may overlap
+ */
+
+.globl _memmove;
+.type _memmove, STT_FUNC;
+_memmove:
+	I1 = P3;
+	P0 = R0;                  /* P0 = To address */
+	P3 = R1;                  /* P3 = From Address */
+	P2 = R2 ;                 /* P2 = count */
+	CC = P2 == 0;             /* Check zero count*/
+	IF CC JUMP .Lfinished;    /* very unlikely */
+
+	CC = R1 < R0 (IU);        /* From < To */
+	IF !CC JUMP .Lno_overlap;
+	R3 = R1 + R2;
+	CC = R0 <= R3 (IU);       /* (From+len) >= To */
+	IF CC JUMP .Loverlap;
+.Lno_overlap:
+	R3 = 11;
+	CC = R2 <= R3;
+	IF CC JUMP  .Lbytes;
+	R3 = R1 | R0;             /* OR addresses together */
+	R3 <<= 30;                /* check bottom two bits */
+	CC =  AZ;                 /* AZ set if zero.*/
+	IF !CC JUMP  .Lbytes ;    /* Jump if addrs not aligned.*/
+
+	I0 = P3;
+	P1 = P2 >> 2;             /* count = n/4 */
+	P1 += -1;
+	R3 =  3;
+	R2 = R2 & R3;             /* remainder */
+	P2 = R2;                  /* set remainder */
+	R1 = [I0++];
+
+	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
+.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
+	[P0++] = R1;
+
+	CC = P2 == 0;             /* any remaining bytes? */
+	P3 = I0;                  /* Ammend P3 to updated ptr. */
+	IF !CC JUMP .Lbytes;
+	P3 = I1;
+	RTS;
+
+.Lbytes:     LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
+.Lbyte2_s:   R1 = B[P3++](Z);
+.Lbyte2_e:   B[P0++] = R1;
+
+.Lfinished:  P3 = I1;
+	RTS;
+
+.Loverlap:
+	P2 += -1;
+	P0 = P0 + P2;
+	P3 = P3 + P2;
+	R1 = B[P3--] (Z);
+	CC = P2 == 0;
+	IF CC JUMP .Lno_loop;
+	LSETUP (.Lol_s, .Lol_e) LC0 = P2;
+.Lol_s:    B[P0--] = R1;
+.Lol_e:    R1 = B[P3--] (Z);
+.Lno_loop: B[P0] = R1;
+	P3 = I1;
+	RTS;
+
+.size _memmove, .-_memmove
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
new file mode 100644
index 0000000..26f63cd
--- /dev/null
+++ b/arch/blackfin/lib/memset.S
@@ -0,0 +1,96 @@
+/*
+ * File: memset.S
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.align 2
+
+/*
+ * C Library function MEMSET
+ * R0 = address (leave unchanged to form result)
+ * R1 = filler byte
+ * R2 = count
+ * Favours word aligned data.
+ */
+
+.globl _memset;
+.type _memset, STT_FUNC;
+_memset:
+	P0 = R0 ;              /* P0 = address */
+	P2 = R2 ;              /* P2 = count   */
+	R3 = R0 + R2;          /* end          */
+	CC = R2 <= 7(IU);
+	IF CC JUMP  .Ltoo_small;
+	R1 = R1.B (Z);         /* R1 = fill char */
+	R2 =  3;
+	R2 = R0 & R2;          /* addr bottom two bits */
+	CC =  R2 == 0;             /* AZ set if zero.	*/
+	IF !CC JUMP  .Lforce_align ;  /* Jump if addr not aligned. */
+
+.Laligned:
+	P1 = P2 >> 2;          /* count = n/4        */
+	R2 = R1 <<  8;         /* create quad filler */
+	R2.L = R2.L + R1.L(NS);
+	R2.H = R2.L + R1.H(NS);
+	P2 = R3;
+
+	LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
+.Lquad_loop:
+	[P0++] = R2;
+
+	CC = P0 == P2;
+	IF !CC JUMP .Lbytes_left;
+	RTS;
+
+.Lbytes_left:
+	R2 = R3;                /* end point */
+	R3 = P0;                /* current position */
+	R2 = R2 - R3;           /* bytes left */
+	P2 = R2;
+
+.Ltoo_small:
+	CC = P2 == 0;           /* Check zero count */
+	IF CC JUMP .Lfinished;    /* Unusual */
+
+.Lbytes:
+	LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
+.Lbyte_loop:
+	B[P0++] = R1;
+
+.Lfinished:
+	RTS;
+
+.Lforce_align:
+	CC = BITTST (R0, 0);  /* odd byte */
+	R0 = 4;
+	R0 = R0 - R2;
+	P1 = R0;
+	R0 = P0;		    /* Recover return address */
+	IF !CC JUMP .Lskip1;
+	B[P0++] = R1;
+.Lskip1:
+	CC = R2 <= 2;          /* 2 bytes */
+	P2 -= P1;              /* reduce count */
+	IF !CC JUMP .Laligned;
+	B[P0++] = R1;
+	B[P0++] = R1;
+	JUMP .Laligned;
+
+.size _memset, .-_memset
diff --git a/arch/blackfin/lib/muldi3.c b/arch/blackfin/lib/muldi3.c
new file mode 100644
index 0000000..bf1ca53
--- /dev/null
+++ b/arch/blackfin/lib/muldi3.c
@@ -0,0 +1,92 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+do {									\
+	USItype __x0, __x1, __x2, __x3;					\
+	USItype __ul, __vl, __uh, __vh;					\
+									\
+	__ul = __ll_lowpart (u);					\
+	__uh = __ll_highpart (u);					\
+	__vl = __ll_lowpart (v);					\
+	__vh = __ll_highpart (v);					\
+									\
+	__x0 = (USItype) __ul * __vl;					\
+	__x1 = (USItype) __ul * __vh;					\
+	__x2 = (USItype) __uh * __vl;					\
+	__x3 = (USItype) __uh * __vh;					\
+									\
+	__x1 += __ll_highpart (__x0);/* this can't give carry */	\
+	__x1 += __x2;	/* but this indeed can */			\
+	if (__x1 < __x2)	/* did we get it? */			\
+		__x3 += __ll_B;	/* yes, add it in the proper pos. */	\
+									\
+	(w1) = __x3 + __ll_highpart (__x1);				\
+	(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);	\
+} while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v)						\
+	({DIunion __w;							\
+	umul_ppmm (__w.s.high, __w.s.low, u, v);			\
+	__w.ll; })
+#endif
+
+typedef unsigned int USItype __attribute__ ((mode(SI)));
+typedef int SItype __attribute__ ((mode(SI)));
+typedef int DItype __attribute__ ((mode(DI)));
+typedef int word_type __attribute__ ((mode(__word__)));
+
+struct DIstruct {
+	SItype low, high;
+};
+typedef union {
+	struct DIstruct s;
+	DItype ll;
+} DIunion;
+
+DItype __muldi3(DItype u, DItype v)
+{
+	DIunion w;
+	DIunion uu, vv;
+
+	uu.ll = u, vv.ll = v;
+	/*  panic("kernel panic for __muldi3"); */
+	w.ll = __umulsidi3(uu.s.low, vv.s.low);
+	w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+		     + (USItype) uu.s.high * (USItype) vv.s.low);
+
+	return w.ll;
+}
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
new file mode 100644
index 0000000..90c6033
--- /dev/null
+++ b/arch/blackfin/lib/outs.S
@@ -0,0 +1,60 @@
+/*
+ * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
+ *
+ * Copyright 2005-2009 Analog Devices Inc.
+ *                2005 BuyWays BV
+ *                      Bas Vermeulen <bas@buyways.nl>
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <asm/linkage.h>
+
+.align 2
+
+ENTRY(_outsl)
+	P0 = R0;	/* P0 = port */
+	P1 = R1;	/* P1 = address */
+	P2 = R2;	/* P2 = count */
+
+	LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
+.Llong_loop_s: R0 = [P1++];
+.Llong_loop_e: [P0] = R0;
+	RTS;
+ENDPROC(_outsl)
+
+ENTRY(_outsw)
+	P0 = R0;	/* P0 = port */
+	P1 = R1;	/* P1 = address */
+	P2 = R2;	/* P2 = count */
+
+	LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
+.Lword_loop_s: R0 = W[P1++];
+.Lword_loop_e: W[P0] = R0;
+	RTS;
+ENDPROC(_outsw)
+
+ENTRY(_outsb)
+	P0 = R0;	/* P0 = port */
+	P1 = R1;	/* P1 = address */
+	P2 = R2;	/* P2 = count */
+
+	LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
+.Lbyte_loop_s: R0 = B[P1++];
+.Lbyte_loop_e: B[P0] = R0;
+	RTS;
+ENDPROC(_outsb)
+
+ENTRY(_outsw_8)
+	P0 = R0;	/* P0 = port */
+	P1 = R1;	/* P1 = address */
+	P2 = R2;	/* P2 = count */
+
+	LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
+.Lword8_loop_s: R1 = B[P1++];
+		R0 = B[P1++];
+		R0 = R0 << 8;
+		R0 = R0 + R1;
+.Lword8_loop_e: W[P0] = R0;
+	RTS;
+ENDPROC(_outsw_8)
diff --git a/arch/blackfin/lib/post.c b/arch/blackfin/lib/post.c
new file mode 100644
index 0000000..faf6b96
--- /dev/null
+++ b/arch/blackfin/lib/post.c
@@ -0,0 +1,421 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <watchdog.h>
+#include <post.h>
+
+#ifdef CONFIG_LOGBUFFER
+#include <logbuff.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define POST_MAX_NUMBER		32
+
+#define BOOTMODE_MAGIC	0xDEAD0000
+
+int post_init_f(void)
+{
+	int res = 0;
+	unsigned int i;
+
+	for (i = 0; i < post_list_size; i++) {
+		struct post_test *test = post_list + i;
+
+		if (test->init_f && test->init_f()) {
+			res = -1;
+		}
+	}
+
+	gd->post_init_f_time = post_time_ms(0);
+	if (!gd->post_init_f_time) {
+		printf
+		    ("post/post.c: post_time_ms seems not to be implemented\n");
+	}
+
+	return res;
+}
+
+void post_bootmode_init(void)
+{
+	int bootmode = post_bootmode_get(0);
+	int newword;
+
+	if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) {
+		newword = BOOTMODE_MAGIC | POST_SLOWTEST;
+	} else if (bootmode == 0) {
+		newword = BOOTMODE_MAGIC | POST_POWERON;
+	} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
+		newword = BOOTMODE_MAGIC | POST_NORMAL;
+	} else {
+		/* Use old value */
+		newword = post_word_load() & ~POST_COLDBOOT;
+	}
+
+	if (bootmode == 0) {
+		/* We are booting after power-on */
+		newword |= POST_COLDBOOT;
+	}
+
+	post_word_store(newword);
+
+	/* Reset activity record */
+	gd->post_log_word = 0;
+}
+
+int post_bootmode_get(unsigned int *last_test)
+{
+	unsigned long word = post_word_load();
+	int bootmode;
+
+	if ((word & 0xFFFF0000) != BOOTMODE_MAGIC) {
+		return 0;
+	}
+
+	bootmode = word & 0x7F;
+
+	if (last_test && (bootmode & POST_POWERTEST)) {
+		*last_test = (word >> 8) & 0xFF;
+	}
+
+	return bootmode;
+}
+
+/* POST tests run before relocation only mark status bits .... */
+static void post_log_mark_start(unsigned long testid)
+{
+	gd->post_log_word |= (testid) << 16;
+}
+
+static void post_log_mark_succ(unsigned long testid)
+{
+	gd->post_log_word |= testid;
+}
+
+/* ... and the messages are output once we are relocated */
+void post_output_backlog(void)
+{
+	int j;
+
+	for (j = 0; j < post_list_size; j++) {
+		if (gd->post_log_word & (post_list[j].testid << 16)) {
+			post_log("POST %s ", post_list[j].cmd);
+			if (gd->post_log_word & post_list[j].testid)
+				post_log("PASSED\n");
+			else {
+				post_log("FAILED\n");
+				show_boot_progress (-31);
+			}
+		}
+	}
+}
+
+static void post_bootmode_test_on(unsigned int last_test)
+{
+	unsigned long word = post_word_load();
+
+	word |= POST_POWERTEST;
+
+	word |= (last_test & 0xFF) << 8;
+
+	post_word_store(word);
+}
+
+static void post_bootmode_test_off(void)
+{
+	unsigned long word = post_word_load();
+
+	word &= ~POST_POWERTEST;
+
+	post_word_store(word);
+}
+
+static void post_get_flags(int *test_flags)
+{
+	int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
+	char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
+	int varnum = sizeof(var) / sizeof(var[0]);
+	char list[128];		/* long enough for POST list */
+	char *name;
+	char *s;
+	int last;
+	int i, j;
+
+	for (j = 0; j < post_list_size; j++) {
+		test_flags[j] = post_list[j].flags;
+	}
+
+	for (i = 0; i < varnum; i++) {
+		if (getenv_r(var[i], list, sizeof(list)) <= 0)
+			continue;
+
+		for (j = 0; j < post_list_size; j++) {
+			test_flags[j] &= ~flag[i];
+		}
+
+		last = 0;
+		name = list;
+		while (!last) {
+			while (*name && *name == ' ')
+				name++;
+			if (*name == 0)
+				break;
+			s = name + 1;
+			while (*s && *s != ' ')
+				s++;
+			if (*s == 0)
+				last = 1;
+			else
+				*s = 0;
+
+			for (j = 0; j < post_list_size; j++) {
+				if (strcmp(post_list[j].cmd, name) == 0) {
+					test_flags[j] |= flag[i];
+					break;
+				}
+			}
+
+			if (j == post_list_size) {
+				printf("No such test: %s\n", name);
+			}
+
+			name = s + 1;
+		}
+	}
+
+	for (j = 0; j < post_list_size; j++) {
+		if (test_flags[j] & POST_POWERON) {
+			test_flags[j] |= POST_SLOWTEST;
+		}
+	}
+}
+
+static int post_run_single(struct post_test *test,
+			   int test_flags, int flags, unsigned int i)
+{
+	if ((flags & test_flags & POST_ALWAYS) &&
+	    (flags & test_flags & POST_MEM)) {
+		WATCHDOG_RESET();
+
+		if (!(flags & POST_REBOOT)) {
+			if ((test_flags & POST_REBOOT)
+			    && !(flags & POST_MANUAL)) {
+				post_bootmode_test_on(i);
+			}
+
+			if (test_flags & POST_PREREL)
+				post_log_mark_start(test->testid);
+			else
+				post_log("POST %s ", test->cmd);
+		}
+
+		if (test_flags & POST_PREREL) {
+			if ((*test->test) (flags) == 0)
+				post_log_mark_succ(test->testid);
+		} else {
+			if ((*test->test) (flags) != 0) {
+				post_log("FAILED\n");
+				show_boot_progress (-32);
+			} else
+				post_log("PASSED\n");
+		}
+
+		if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) {
+			post_bootmode_test_off();
+		}
+
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+int post_run(char *name, int flags)
+{
+	unsigned int i;
+	int test_flags[POST_MAX_NUMBER];
+
+	post_get_flags(test_flags);
+
+	if (name == NULL) {
+		unsigned int last;
+
+		if (post_bootmode_get(&last) & POST_POWERTEST) {
+			if (last < post_list_size &&
+			    (flags & test_flags[last] & POST_ALWAYS) &&
+			    (flags & test_flags[last] & POST_MEM)) {
+
+				post_run_single(post_list + last,
+						test_flags[last],
+						flags | POST_REBOOT, last);
+
+				for (i = last + 1; i < post_list_size; i++) {
+					post_run_single(post_list + i,
+							test_flags[i],
+							flags, i);
+				}
+			}
+		} else {
+			for (i = 0; i < post_list_size; i++) {
+				post_run_single(post_list + i,
+						test_flags[i], flags, i);
+			}
+		}
+
+		return 0;
+	} else {
+		for (i = 0; i < post_list_size; i++) {
+			if (strcmp(post_list[i].cmd, name) == 0)
+				break;
+		}
+
+		if (i < post_list_size) {
+			return post_run_single(post_list + i,
+					       test_flags[i], flags, i);
+		} else {
+			return -1;
+		}
+	}
+}
+
+static int post_info_single(struct post_test *test, int full)
+{
+	if (test->flags & POST_MANUAL) {
+		if (full)
+			printf("%s - %s\n"
+			       "  %s\n", test->cmd, test->name, test->desc);
+		else
+			printf("  %-15s - %s\n", test->cmd, test->name);
+
+		return 0;
+	} else {
+		return -1;
+	}
+}
+
+int post_info(char *name)
+{
+	unsigned int i;
+
+	if (name == NULL) {
+		for (i = 0; i < post_list_size; i++) {
+			post_info_single(post_list + i, 0);
+		}
+
+		return 0;
+	} else {
+		for (i = 0; i < post_list_size; i++) {
+			if (strcmp(post_list[i].cmd, name) == 0)
+				break;
+		}
+
+		if (i < post_list_size) {
+			return post_info_single(post_list + i, 1);
+		} else {
+			return -1;
+		}
+	}
+}
+
+int post_log(char *format, ...)
+{
+	va_list args;
+	uint i;
+	char printbuffer[CONFIG_SYS_PBSIZE];
+
+	va_start(args, format);
+
+	/* For this to work, printbuffer must be larger than
+	 * anything we ever want to print.
+	 */
+	i = vsprintf(printbuffer, format, args);
+	va_end(args);
+
+#ifdef CONFIG_LOGBUFFER
+	/* Send to the logbuffer */
+	logbuff_log(printbuffer);
+#else
+	/* Send to the stdout file */
+	puts(printbuffer);
+#endif
+
+	return 0;
+}
+
+void post_reloc(void)
+{
+	unsigned int i;
+
+	/*
+	 * We have to relocate the test table manually
+	 */
+	for (i = 0; i < post_list_size; i++) {
+		ulong addr;
+		struct post_test *test = post_list + i;
+
+		if (test->name) {
+			addr = (ulong) (test->name) + gd->reloc_off;
+			test->name = (char *)addr;
+		}
+
+		if (test->cmd) {
+			addr = (ulong) (test->cmd) + gd->reloc_off;
+			test->cmd = (char *)addr;
+		}
+
+		if (test->desc) {
+			addr = (ulong) (test->desc) + gd->reloc_off;
+			test->desc = (char *)addr;
+		}
+
+		if (test->test) {
+			addr = (ulong) (test->test) + gd->reloc_off;
+			test->test = (int (*)(int flags))addr;
+		}
+
+		if (test->init_f) {
+			addr = (ulong) (test->init_f) + gd->reloc_off;
+			test->init_f = (int (*)(void))addr;
+		}
+
+		if (test->reloc) {
+			addr = (ulong) (test->reloc) + gd->reloc_off;
+			test->reloc = (void (*)(void))addr;
+
+			test->reloc();
+		}
+	}
+}
+
+/*
+ * Some tests (e.g. SYSMON) need the time when post_init_f started,
+ * but we cannot use get_timer() at this point.
+ *
+ * On PowerPC we implement it using the timebase register.
+ */
+unsigned long post_time_ms(unsigned long base)
+{
+	return (unsigned long)get_ticks() / (get_tbclk() / CONFIG_SYS_HZ) - base;
+}
diff --git a/arch/blackfin/lib/string.c b/arch/blackfin/lib/string.c
new file mode 100644
index 0000000..e344d3b
--- /dev/null
+++ b/arch/blackfin/lib/string.c
@@ -0,0 +1,274 @@
+/*
+ * U-boot - string.c Contains library routines.
+ *
+ * Copyright (c) 2005-2008 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <asm/mach-common/bits/dma.h>
+
+char *strcpy(char *dest, const char *src)
+{
+	char *xdest = dest;
+	char temp = 0;
+
+	__asm__ __volatile__ (
+		"1:\t%2 = B [%1++] (Z);\n\t"
+		"B [%0++] = %2;\n\t"
+		"CC = %2;\n\t"
+		"if cc jump 1b (bp);\n"
+		: "=a"(dest), "=a"(src), "=d"(temp)
+		: "0"(dest), "1"(src), "2"(temp)
+		: "memory");
+
+	return xdest;
+}
+
+char *strncpy(char *dest, const char *src, size_t n)
+{
+	char *xdest = dest;
+	char temp = 0;
+
+	if (n == 0)
+		return xdest;
+
+	__asm__ __volatile__ (
+		"1:\t%3 = B [%1++] (Z);\n\t"
+		"B [%0++] = %3;\n\t"
+		"CC = %3;\n\t"
+		"if ! cc jump 2f;\n\t"
+		"%2 += -1;\n\t"
+		"CC = %2 == 0;\n\t"
+		"if ! cc jump 1b (bp);\n"
+		"2:\n"
+		: "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
+		: "0"(dest), "1"(src), "2"(n), "3"(temp)
+		: "memory");
+
+	return xdest;
+}
+
+int strcmp(const char *cs, const char *ct)
+{
+	char __res1, __res2;
+
+	__asm__ (
+		"1:\t%2 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%3 = B[%1++] (Z);\n\t"	/* get *ct */
+		"CC = %2 == %3;\n\t"	/* compare a byte */
+		"if ! cc jump 2f;\n\t"	/* not equal, break out */
+		"CC = %2;\n\t"	/* at end of cs? */
+		"if cc jump 1b (bp);\n\t"	/* no, keep going */
+		"jump.s 3f;\n"	/* strings are equal */
+		"2:\t%2 = %2 - %3;\n"	/* *cs - *ct */
+		"3:\n"
+		: "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
+		: "0"(cs), "1"(ct));
+
+	return __res1;
+}
+
+int strncmp(const char *cs, const char *ct, size_t count)
+{
+	char __res1, __res2;
+
+	if (!count)
+		return 0;
+
+	__asm__(
+		"1:\t%3 = B[%0++] (Z);\n\t"	/* get *cs */
+		"%4 = B[%1++] (Z);\n\t"	/* get *ct */
+		"CC = %3 == %4;\n\t"	/* compare a byte */
+		"if ! cc jump 3f;\n\t"	/* not equal, break out */
+		"CC = %3;\n\t"	/* at end of cs? */
+		"if ! cc jump 4f;\n\t"	/* yes, all done */
+		"%2 += -1;\n\t"	/* no, adjust count */
+		"CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"	/* more to do, keep going */
+		"2:\t%3 = 0;\n\t"	/* strings are equal */
+		"jump.s    4f;\n" "3:\t%3 = %3 - %4;\n"	/* *cs - *ct */
+		"4:"
+		: "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
+		: "0"(cs), "1"(ct), "2"(count));
+
+	return __res1;
+}
+
+#ifdef bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR
+# define bfin_write_MDMA_D0_X_COUNT    bfin_write_MDMA1_D0_X_COUNT
+# define bfin_write_MDMA_D0_X_MODIFY   bfin_write_MDMA1_D0_X_MODIFY
+# define bfin_write_MDMA_D0_CONFIG     bfin_write_MDMA1_D0_CONFIG
+# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR
+# define bfin_write_MDMA_S0_X_COUNT    bfin_write_MDMA1_S0_X_COUNT
+# define bfin_write_MDMA_S0_X_MODIFY   bfin_write_MDMA1_S0_X_MODIFY
+# define bfin_write_MDMA_S0_CONFIG     bfin_write_MDMA1_S0_CONFIG
+# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
+# define bfin_read_MDMA_D0_IRQ_STATUS  bfin_read_MDMA1_D0_IRQ_STATUS
+#endif
+/* This version misbehaves for count values of 0 and 2^16+.
+ * Perhaps we should detect that ?  Nowhere do we actually
+ * use dma memcpy for those types of lengths though ...
+ */
+void dma_memcpy_nocache(void *dst, const void *src, size_t count)
+{
+	uint16_t wdsize, mod;
+
+	/* Disable DMA in case it's still running (older u-boot's did not
+	 * always turn them off).  Do it before the if statement below so
+	 * we can be cheap and not do a SSYNC() due to the forced abort.
+	 */
+	bfin_write_MDMA_D0_CONFIG(0);
+	bfin_write_MDMA_S0_CONFIG(0);
+	bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
+
+	/* Scratchpad cannot be a DMA source or destination */
+	if (((unsigned long)src >= L1_SRAM_SCRATCH &&
+	     (unsigned long)src < L1_SRAM_SCRATCH_END) ||
+	    ((unsigned long)dst >= L1_SRAM_SCRATCH &&
+	     (unsigned long)dst < L1_SRAM_SCRATCH_END))
+		hang();
+
+	if (((unsigned long)dst | (unsigned long)src | count) & 0x1) {
+		wdsize = WDSIZE_8;
+		mod = 1;
+	} else if (((unsigned long)dst | (unsigned long)src | count) & 0x2) {
+		wdsize = WDSIZE_16;
+		count >>= 1;
+		mod = 2;
+	} else {
+		wdsize = WDSIZE_32;
+		count >>= 2;
+		mod = 4;
+	}
+
+	/* Copy sram functions from sdram to sram */
+	/* Setup destination start address */
+	bfin_write_MDMA_D0_START_ADDR(dst);
+	/* Setup destination xcount */
+	bfin_write_MDMA_D0_X_COUNT(count);
+	/* Setup destination xmodify */
+	bfin_write_MDMA_D0_X_MODIFY(mod);
+
+	/* Setup Source start address */
+	bfin_write_MDMA_S0_START_ADDR(src);
+	/* Setup Source xcount */
+	bfin_write_MDMA_S0_X_COUNT(count);
+	/* Setup Source xmodify */
+	bfin_write_MDMA_S0_X_MODIFY(mod);
+
+	/* Enable source DMA */
+	bfin_write_MDMA_S0_CONFIG(wdsize | DMAEN);
+	bfin_write_MDMA_D0_CONFIG(wdsize | DMAEN | WNR | DI_EN);
+	SSYNC();
+
+	while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+		continue;
+
+	bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
+	bfin_write_MDMA_D0_CONFIG(0);
+	bfin_write_MDMA_S0_CONFIG(0);
+}
+/* We should do a dcache invalidate on the destination after the dma, but since
+ * we lack such hardware capability, we'll flush/invalidate the destination
+ * before the dma and bank on the idea that u-boot is single threaded.
+ */
+void *dma_memcpy(void *dst, const void *src, size_t count)
+{
+	if (dcache_status()) {
+		blackfin_dcache_flush_range(src, src + count);
+		blackfin_dcache_flush_invalidate_range(dst, dst + count);
+	}
+
+	dma_memcpy_nocache(dst, src, count);
+
+	if (icache_status())
+		blackfin_icache_flush_range(dst, dst + count);
+
+	return dst;
+}
+
+/*
+ * memcpy - Copy one area of memory to another
+ * @dest: Where to copy to
+ * @src: Where to copy from
+ * @count: The size of the area.
+ *
+ * We need to have this wrapper in memcpy() as common code may call memcpy()
+ * to load up L1 regions.  Consider loading an ELF which has sections with
+ * LMA's pointing to L1.  The common code ELF loader will simply use memcpy()
+ * to move the ELF's sections into the right place.  We need to catch that
+ * here and redirect to dma_memcpy().
+ */
+extern void *memcpy_ASM(void *dst, const void *src, size_t count);
+void *memcpy(void *dst, const void *src, size_t count)
+{
+	if (!count)
+		return dst;
+
+#ifdef CONFIG_CMD_KGDB
+	if (src >= (void *)SYSMMR_BASE) {
+		if (count == 2 && (unsigned long)src % 2 == 0) {
+			u16 mmr = bfin_read16(src);
+			memcpy(dst, &mmr, sizeof(mmr));
+			return dst;
+		}
+		if (count == 4 && (unsigned long)src % 4 == 0) {
+			u32 mmr = bfin_read32(src);
+			memcpy(dst, &mmr, sizeof(mmr));
+			return dst;
+		}
+		/* Failed for some reason */
+		memset(dst, 0xad, count);
+		return dst;
+	}
+	if (dst >= (void *)SYSMMR_BASE) {
+		if (count == 2 && (unsigned long)dst % 2 == 0) {
+			u16 mmr;
+			memcpy(&mmr, src, sizeof(mmr));
+			bfin_write16(dst, mmr);
+			return dst;
+		}
+		if (count == 4 && (unsigned long)dst % 4 == 0) {
+			u32 mmr;
+			memcpy(&mmr, src, sizeof(mmr));
+			bfin_write32(dst, mmr);
+			return dst;
+		}
+		/* Failed for some reason */
+		memset(dst, 0xad, count);
+		return dst;
+	}
+#endif
+
+	/* if L1 is the source or dst, use DMA */
+	if (addr_bfin_on_chip_mem(dst) || addr_bfin_on_chip_mem(src))
+		return dma_memcpy(dst, src, count);
+	else
+		/* No L1 is involved, so just call regular memcpy */
+		return memcpy_ASM(dst, src, count);
+}
diff --git a/arch/blackfin/lib/tests.c b/arch/blackfin/lib/tests.c
new file mode 100644
index 0000000..bf7fba0
--- /dev/null
+++ b/arch/blackfin/lib/tests.c
@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Be sure to mark tests to be run before relocation as such with the
+ * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
+ * logbuffer support is enabled.
+ */
+
+#include <common.h>
+#include <config.h>
+
+#include <post.h>
+#define CONFIG_SYS_POST_FLASH  0x00004000
+#define CONFIG_SYS_POST_LED    0x00008000
+#define CONFIG_SYS_POST_BUTTON 0x00010000
+
+extern int cache_post_test(int flags);
+extern int watchdog_post_test(int flags);
+extern int i2c_post_test(int flags);
+extern int rtc_post_test(int flags);
+extern int memory_post_test(int flags);
+extern int cpu_post_test(int flags);
+extern int uart_post_test(int flags);
+extern int ether_post_test(int flags);
+extern int spi_post_test(int flags);
+extern int usb_post_test(int flags);
+extern int spr_post_test(int flags);
+extern int sysmon_post_test(int flags);
+extern int dsp_post_test(int flags);
+extern int codec_post_test(int flags);
+
+extern int sysmon_init_f(void);
+
+extern void sysmon_reloc(void);
+
+extern int flash_post_test(int flags);
+extern int led_post_test(int flags);
+extern int button_post_test(int flags);
+
+struct post_test post_list[] = {
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
+	{
+	 "Cache test",
+	 "cache",
+	 "This test verifies the CPU cache operation.",
+	 POST_RAM | POST_ALWAYS,
+	 &cache_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_CACHE},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
+	{
+	 "Watchdog timer test",
+	 "watchdog",
+	 "This test checks the watchdog timer.",
+	 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
+	 &watchdog_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_WATCHDOG},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_I2C
+	{
+	 "I2C test",
+	 "i2c",
+	 "This test verifies the I2C operation.",
+	 POST_RAM | POST_ALWAYS,
+	 &i2c_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_I2C},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_RTC
+	{
+	 "RTC test",
+	 "rtc",
+	 "This test verifies the RTC operation.",
+	 POST_RAM | POST_SLOWTEST | POST_MANUAL,
+	 &rtc_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_RTC},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
+	{
+	 "Memory test",
+	 "memory",
+	 "This test checks RAM.",
+	 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
+	 &memory_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_MEMORY},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_CPU
+	{
+	 "CPU test",
+	 "cpu",
+	 "This test verifies the arithmetic logic unit of" " CPU.",
+	 POST_RAM | POST_ALWAYS,
+	 &cpu_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_CPU},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	{
+	 "UART test",
+	 "uart",
+	 "This test verifies the UART operation.",
+	 POST_RAM | POST_SLOWTEST | POST_MANUAL,
+	 &uart_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_UART},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_ETHER
+	{
+	 "ETHERNET test",
+	 "ethernet",
+	 "This test verifies the ETHERNET operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &ether_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_ETHER},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_SPI
+	{
+	 "SPI test",
+	 "spi",
+	 "This test verifies the SPI operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &spi_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_SPI},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_USB
+	{
+	 "USB test",
+	 "usb",
+	 "This test verifies the USB operation.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &usb_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_USB},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_SPR
+	{
+	 "SPR test",
+	 "spr",
+	 "This test checks SPR contents.",
+	 POST_ROM | POST_ALWAYS | POST_PREREL,
+	 &spr_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_SPR},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
+	{
+	 "SYSMON test",
+	 "sysmon",
+	 "This test monitors system hardware.",
+	 POST_RAM | POST_ALWAYS,
+	 &sysmon_post_test,
+	 &sysmon_init_f,
+	 &sysmon_reloc,
+	 CONFIG_SYS_POST_SYSMON},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_DSP
+	{
+	 "DSP test",
+	 "dsp",
+	 "This test checks any connected DSP(s).",
+	 POST_RAM | POST_MANUAL,
+	 &dsp_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_DSP},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_CODEC
+	{
+	 "CODEC test",
+	 "codec",
+	 "This test checks any connected codec(s).",
+	 POST_RAM | POST_MANUAL,
+	 &codec_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_CODEC},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_FLASH
+	{
+	 "FLASH test",
+	 "flash",
+	 "This test checks flash.",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &flash_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_FLASH},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_LED
+	{
+	 "LED test",
+	 "LED",
+	 "This test checks LED ",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &led_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_LED},
+#endif
+#if CONFIG_POST & CONFIG_SYS_POST_BUTTON
+	{
+	 "Button test",
+	 "button",
+	 "This test checks Button ",
+	 POST_RAM | POST_ALWAYS | POST_MANUAL,
+	 &button_post_test,
+	 NULL,
+	 NULL,
+	 CONFIG_SYS_POST_BUTTON},
+#endif
+
+};
+
+unsigned int post_list_size = sizeof(post_list) / sizeof(struct post_test);
diff --git a/arch/blackfin/lib/u-boot.lds.S b/arch/blackfin/lib/u-boot.lds.S
new file mode 100644
index 0000000..9163d20
--- /dev/null
+++ b/arch/blackfin/lib/u-boot.lds.S
@@ -0,0 +1,153 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2010 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+
+#ifndef LDS_BOARD_TEXT
+# define LDS_BOARD_TEXT
+#endif
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
+#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
+# define L1_CODE_ORIGIN L1_INST_SRAM
+#else
+# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+#if CONFIG_MEM_SIZE
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+# define ram_code ram
+# define ram_data ram
+#else
+# define ram_code l1_code
+# define ram_data l1_data
+#endif
+	l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
+	l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+	.text.pre :
+	{
+		arch/blackfin/cpu/start.o (.text .text.*)
+
+		LDS_BOARD_TEXT
+	} >ram_code
+
+	.text.init :
+	{
+		arch/blackfin/cpu/initcode.o (.text .text.*)
+	} >ram_code
+	__initcode_lma = LOADADDR(.text.init);
+	__initcode_len = SIZEOF(.text.init);
+
+	.text :
+	{
+		*(.text .text.*)
+	} >ram_code
+
+	.rodata :
+	{
+		. = ALIGN(4);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+		. = ALIGN(4);
+	} >ram_data
+
+	.data :
+	{
+		. = ALIGN(4);
+		*(.data .data.*)
+		*(.data1)
+		*(.sdata)
+		*(.sdata2)
+		*(.dynamic)
+		CONSTRUCTORS
+	} >ram_data
+
+	.u_boot_cmd :
+	{
+		___u_boot_cmd_start = .;
+		*(.u_boot_cmd)
+		___u_boot_cmd_end = .;
+	} >ram_data
+
+	.text_l1 :
+	{
+		. = ALIGN(4);
+		__stext_l1 = .;
+		*(.l1.text)
+		. = ALIGN(4);
+		__etext_l1 = .;
+	} >l1_code AT>ram_code
+	__text_l1_lma = LOADADDR(.text_l1);
+	__text_l1_len = SIZEOF(.text_l1);
+	ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
+
+	.data_l1 :
+	{
+		. = ALIGN(4);
+		__sdata_l1 = .;
+		*(.l1.data)
+		*(.l1.bss)
+		. = ALIGN(4);
+		__edata_l1 = .;
+	} >l1_data AT>ram_data
+	__data_l1_lma = LOADADDR(.data_l1);
+	__data_l1_len = SIZEOF(.data_l1);
+	ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")
+
+	.bss :
+	{
+		. = ALIGN(4);
+		*(.sbss) *(.scommon)
+		*(.dynbss)
+		*(.bss .bss.*)
+		*(COMMON)
+	} >ram_data
+	__bss_vma = ADDR(.bss);
+	__bss_len = SIZEOF(.bss);
+}