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| author | Peter Tyser <ptyser@xes-inc.com> | 2010-04-12 22:28:04 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-04-13 09:13:03 +0200 |
| commit | ea0364f1bbfed1e3ea711147420875cf338fe77a (patch) | |
| tree | 15c051bc4d2e94c1661c73e1b87c22c7beda7c24 /arch/blackfin/lib/outs.S | |
| parent | 89f39e177e7b0152aa1d3152baa25d986e36cdcf (diff) | |
| download | u-boot-imx-ea0364f1bbfed1e3ea711147420875cf338fe77a.zip u-boot-imx-ea0364f1bbfed1e3ea711147420875cf338fe77a.tar.gz u-boot-imx-ea0364f1bbfed1e3ea711147420875cf338fe77a.tar.bz2 | |
Move lib_$ARCH directories to arch/$ARCH/lib
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk
This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'arch/blackfin/lib/outs.S')
| -rw-r--r-- | arch/blackfin/lib/outs.S | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S new file mode 100644 index 0000000..90c6033 --- /dev/null +++ b/arch/blackfin/lib/outs.S @@ -0,0 +1,60 @@ +/* + * Implementation of outs{bwl} for BlackFin processors using zero overhead loops. + * + * Copyright 2005-2009 Analog Devices Inc. + * 2005 BuyWays BV + * Bas Vermeulen <bas@buyways.nl> + * + * Licensed under the GPL-2. + */ + +#include <asm/linkage.h> + +.align 2 + +ENTRY(_outsl) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2; +.Llong_loop_s: R0 = [P1++]; +.Llong_loop_e: [P0] = R0; + RTS; +ENDPROC(_outsl) + +ENTRY(_outsw) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2; +.Lword_loop_s: R0 = W[P1++]; +.Lword_loop_e: W[P0] = R0; + RTS; +ENDPROC(_outsw) + +ENTRY(_outsb) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2; +.Lbyte_loop_s: R0 = B[P1++]; +.Lbyte_loop_e: B[P0] = R0; + RTS; +ENDPROC(_outsb) + +ENTRY(_outsw_8) + P0 = R0; /* P0 = port */ + P1 = R1; /* P1 = address */ + P2 = R2; /* P2 = count */ + + LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2; +.Lword8_loop_s: R1 = B[P1++]; + R0 = B[P1++]; + R0 = R0 << 8; + R0 = R0 + R1; +.Lword8_loop_e: W[P0] = R0; + RTS; +ENDPROC(_outsw_8) |