Blackfin: punt old *p style volatile MMR defines

These are unused now, so punt them to clean things up.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

24 files changed, 0 insertions, 13223 deletions

diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
index f65b439..6bca938 100644
--- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -6,1499 +6,1000 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF52x_extended__
 
-#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
 #define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
 #define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
 #define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
 #define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
 #define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
 #define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
 #define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
 #define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
 #define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
 #define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
 #define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
 #define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
 #define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
 #define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
 #define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
 #define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
 #define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
 #define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
 #define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
 #define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
 #define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
 #define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
 #define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
 #define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
 #define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
 #define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
 #define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
 #define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
 #define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
 #define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
 #define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
 #define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
 #define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
 #define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
 #define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
 #define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 #define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
 #define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
 #define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
 #define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
 #define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
 #define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
 #define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
 #define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
 #define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
 #define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
 #define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
 #define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
 #define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
 #define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
 #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
 #define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
 #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
 #define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
 #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
 #define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
 #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
 #define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
 #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
 #define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
 #define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
 #define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
 #define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
 #define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
 #define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
 #define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
 #define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
 #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
 #define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
 #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
 #define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
 #define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
 #define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
 #define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
 #define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
 #define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
 #define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
 #define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
 #define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
 #define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
 #define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
 #define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
 #define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
 #define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
 #define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
 #define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
 #define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
 #define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
 #define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
 #define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
 #define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
 #define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
 #define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
 #define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
 #define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
 #define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
 #define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
 #define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
 #define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
 #define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
 #define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
 #define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
 #define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
 #define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
 #define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
 #define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
 #define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pPORTF_MUX                     ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */
 #define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define pPORTG_MUX                     ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */
 #define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define pPORTH_MUX                     ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */
 #define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define pPORTF_DRIVE                   ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */
 #define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
 #define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define pPORTG_DRIVE                   ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */
 #define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
 #define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define pPORTH_DRIVE                   ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */
 #define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
 #define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define pPORTF_SLEW                    ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */
 #define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
 #define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
-#define pPORTG_SLEW                    ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */
 #define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
 #define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
-#define pPORTH_SLEW                    ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */
 #define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
 #define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
-#define pPORTF_HYSTERESIS              ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */
 #define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
 #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define pPORTG_HYSTERESIS              ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */
 #define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
 #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define pPORTH_HYSTERESIS              ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */
 #define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
 #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define pNONGPIO_DRIVE                 ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */
 #define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
 #define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define pNONGPIO_SLEW                  ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */
 #define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
 #define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
-#define pNONGPIO_HYSTERESIS            ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */
 #define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
 #define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define pPFCTL                         ((uint32_t volatile *)PFCTL)
 #define bfin_read_PFCTL()              bfin_read32(PFCTL)
 #define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
 #define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
 #define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
 #define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
 #define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
 #define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
 #define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
 #define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
 #define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
index 987cc86..da90346 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
@@ -10,331 +10,222 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
index 390f3dc..dce5c70 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
@@ -10,331 +10,222 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
index 9ec89c6..93e1d5a 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
@@ -10,838 +10,560 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
index 8fe29db..09800c4 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
@@ -10,838 +10,560 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
index 9438862..dfc4fcb 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
@@ -10,1075 +10,718 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
 #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
 #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
 #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
 #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
 #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
 #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
 #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
 #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
 #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
 #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
 #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
 #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
 #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
 #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
 #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
 #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
 #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
 #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
 #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
 #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
 #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
 #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
 #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
 #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
 #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
 #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
 #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
 #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
 #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
 #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
 #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
 #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
 #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
 #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
 #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
 #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
 #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
 #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
 #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
 #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
 #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
 #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
 #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
 #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
 #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
 #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
 #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
 #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
 #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
 #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
 #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
index fb9b307..18e2370 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
@@ -10,1075 +10,718 @@
 
 #include "ADSP-EDN-BF52x-extended_cdef.h"
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
 #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
 #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
 #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
 #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
 #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
 #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
 #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
 #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
 #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
 #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
 #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
 #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
 #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
 #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
 #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
 #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
 #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
 #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
 #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
 #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
 #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
 #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
 #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
 #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
 #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
 #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
 #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
 #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
 #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
 #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
 #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
 #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
 #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
 #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
 #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
 #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
 #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
 #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
 #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
 #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
 #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
 #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
 #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
 #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
 #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
 #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
 #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
 #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
 #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
 #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
 #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
index 0700875..b12bcbb 100644
--- a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h
@@ -6,2744 +6,1830 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF534_extended__
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration Register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
 #define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
 #define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK                     ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
 #define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
 #define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR                       ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
 #define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
 #define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define pSIC_IWR                       ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
 #define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
 #define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */
 #define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
 #define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
 #define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */
 #define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */
 #define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */
 #define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */
 #define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */
 #define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */
 #define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */
 #define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */
 #define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
 #define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */
 #define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
 #define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */
 #define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
 #define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */
 #define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
 #define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
 #define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
 #define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */
 #define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
 #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
 #define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
 #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
 #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
 #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
 #define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
 #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
 #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
 #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */
 #define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
 #define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */
 #define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
 #define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */
 #define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
 #define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */
 #define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
 #define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */
 #define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
 #define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */
 #define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 #define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */
 #define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
 #define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */
 #define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */
 #define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
 #define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */
 #define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */
 #define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define pTWI_CLKDIV                    ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */
 #define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
 #define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define pTWI_CONTROL                   ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
 #define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define pTWI_SLAVE_CTL                 ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */
 #define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
 #define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define pTWI_SLAVE_STAT                ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */
 #define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
 #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define pTWI_SLAVE_ADDR                ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */
 #define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
 #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define pTWI_MASTER_CTL                ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */
 #define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
 #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define pTWI_MASTER_STAT               ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */
 #define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
 #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define pTWI_MASTER_ADDR               ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */
 #define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
 #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define pTWI_INT_STAT                  ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
 #define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define pTWI_INT_MASK                  ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */
 #define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
 #define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define pTWI_FIFO_CTL                  ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */
 #define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
 #define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define pTWI_FIFO_STAT                 ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */
 #define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
 #define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define pTWI_XMT_DATA8                 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
 #define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define pTWI_XMT_DATA16                ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
 #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define pTWI_RCV_DATA8                 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
 #define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define pTWI_RCV_DATA16                ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
 #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define pPORTGIO                       ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */
 #define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
 #define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define pPORTGIO_CLEAR                 ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
 #define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define pPORTGIO_SET                   ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
 #define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define pPORTGIO_TOGGLE                ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */
 #define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
 #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define pPORTGIO_MASKA                 ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
 #define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define pPORTGIO_MASKA_CLEAR           ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
 #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define pPORTGIO_MASKA_SET             ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
 #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define pPORTGIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
 #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define pPORTGIO_MASKB                 ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
 #define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define pPORTGIO_MASKB_CLEAR           ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
 #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define pPORTGIO_MASKB_SET             ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
 #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define pPORTGIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
 #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define pPORTGIO_DIR                   ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */
 #define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
 #define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define pPORTGIO_POLAR                 ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */
 #define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
 #define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define pPORTGIO_EDGE                  ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */
 #define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
 #define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define pPORTGIO_BOTH                  ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */
 #define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
 #define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define pPORTGIO_INEN                  ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */
 #define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
 #define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define pPORTHIO                       ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */
 #define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
 #define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define pPORTHIO_CLEAR                 ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */
 #define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
 #define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define pPORTHIO_SET                   ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */
 #define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
 #define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define pPORTHIO_TOGGLE                ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */
 #define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
 #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define pPORTHIO_MASKA                 ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
 #define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define pPORTHIO_MASKA_CLEAR           ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
 #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define pPORTHIO_MASKA_SET             ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
 #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define pPORTHIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */
 #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
 #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define pPORTHIO_MASKB                 ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
 #define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define pPORTHIO_MASKB_CLEAR           ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
 #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define pPORTHIO_MASKB_SET             ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
 #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define pPORTHIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */
 #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
 #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define pPORTHIO_DIR                   ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */
 #define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
 #define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define pPORTHIO_POLAR                 ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */
 #define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
 #define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define pPORTHIO_EDGE                  ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */
 #define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
 #define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define pPORTHIO_BOTH                  ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */
 #define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
 #define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define pPORTHIO_INEN                  ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */
 #define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
 #define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_IER                     ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */
 #define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
 #define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_IIR                     ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */
 #define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
 #define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pCAN_MC1                       ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */
 #define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
 #define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
-#define pCAN_MD1                       ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */
 #define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
 #define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
-#define pCAN_TRS1                      ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */
 #define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
 #define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
-#define pCAN_TRR1                      ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */
 #define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
 #define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
-#define pCAN_TA1                       ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */
 #define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
 #define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
-#define pCAN_AA1                       ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */
 #define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
 #define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
-#define pCAN_RMP1                      ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */
 #define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
 #define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
-#define pCAN_RML1                      ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */
 #define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
 #define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
-#define pCAN_MBTIF1                    ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */
 #define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
 #define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
-#define pCAN_MBRIF1                    ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive  Interrupt Flag reg 1 */
 #define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
 #define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
-#define pCAN_MBIM1                     ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */
 #define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
 #define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
-#define pCAN_RFH1                      ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */
 #define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
 #define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
-#define pCAN_OPSS1                     ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */
 #define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
 #define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
-#define pCAN_MC2                       ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */
 #define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
 #define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
-#define pCAN_MD2                       ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */
 #define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
 #define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
-#define pCAN_TRS2                      ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */
 #define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
 #define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
-#define pCAN_TRR2                      ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */
 #define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
 #define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
-#define pCAN_TA2                       ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */
 #define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
 #define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
-#define pCAN_AA2                       ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */
 #define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
 #define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
-#define pCAN_RMP2                      ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */
 #define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
 #define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
-#define pCAN_RML2                      ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */
 #define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
 #define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
-#define pCAN_MBTIF2                    ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */
 #define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
 #define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
-#define pCAN_MBRIF2                    ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive  Interrupt Flag reg 2 */
 #define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
 #define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
-#define pCAN_MBIM2                     ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */
 #define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
 #define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
-#define pCAN_RFH2                      ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */
 #define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
 #define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
-#define pCAN_OPSS2                     ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */
 #define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
 #define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
-#define pCAN_CLOCK                     ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */
 #define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
 #define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
-#define pCAN_TIMING                    ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */
 #define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
 #define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
-#define pCAN_DEBUG                     ((uint16_t volatile *)CAN_DEBUG) /* Config register */
 #define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
 #define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
-#define pCAN_STATUS                    ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */
 #define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
 #define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
-#define pCAN_CEC                       ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */
 #define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
 #define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
-#define pCAN_GIS                       ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */
 #define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
 #define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
-#define pCAN_GIM                       ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */
 #define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
 #define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
-#define pCAN_GIF                       ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */
 #define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
 #define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
-#define pCAN_CONTROL                   ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */
 #define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
 #define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
-#define pCAN_INTR                      ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */
 #define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
 #define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
-#define pCAN_VERSION                   ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */
 #define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
 #define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
-#define pCAN_MBTD                      ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */
 #define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
 #define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
-#define pCAN_EWR                       ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */
 #define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
 #define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
-#define pCAN_ESR                       ((uint16_t volatile *)CAN_ESR) /* Error Status Register */
 #define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
 #define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
-#define pCAN_UCREG                     ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */
 #define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
 #define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
-#define pCAN_UCCNT                     ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */
 #define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
 #define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
-#define pCAN_UCRC                      ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */
 #define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
 #define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
-#define pCAN_UCCNF                     ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */
 #define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
 #define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
-#define pCAN_VERSION2                  ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */
 #define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
 #define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
-#define pCAN_AM00L                     ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */
 #define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
 #define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
-#define pCAN_AM00H                     ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */
 #define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
 #define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
-#define pCAN_AM01L                     ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask  */
 #define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
 #define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
-#define pCAN_AM01H                     ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */
 #define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
 #define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
-#define pCAN_AM02L                     ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask  */
 #define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
 #define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
-#define pCAN_AM02H                     ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */
 #define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
 #define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
-#define pCAN_AM03L                     ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask  */
 #define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
 #define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
-#define pCAN_AM03H                     ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */
 #define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
 #define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
-#define pCAN_AM04L                     ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask  */
 #define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
 #define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
-#define pCAN_AM04H                     ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */
 #define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
 #define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
-#define pCAN_AM05L                     ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask  */
 #define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
 #define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
-#define pCAN_AM05H                     ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */
 #define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
 #define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
-#define pCAN_AM06L                     ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask  */
 #define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
 #define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
-#define pCAN_AM06H                     ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */
 #define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
 #define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
-#define pCAN_AM07L                     ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask  */
 #define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
 #define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
-#define pCAN_AM07H                     ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */
 #define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
 #define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
-#define pCAN_AM08L                     ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask  */
 #define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
 #define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
-#define pCAN_AM08H                     ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */
 #define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
 #define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
-#define pCAN_AM09L                     ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask  */
 #define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
 #define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
-#define pCAN_AM09H                     ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */
 #define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
 #define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
-#define pCAN_AM10L                     ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask  */
 #define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
 #define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
-#define pCAN_AM10H                     ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */
 #define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
 #define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
-#define pCAN_AM11L                     ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask  */
 #define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
 #define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
-#define pCAN_AM11H                     ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */
 #define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
 #define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
-#define pCAN_AM12L                     ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask  */
 #define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
 #define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
-#define pCAN_AM12H                     ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */
 #define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
 #define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
-#define pCAN_AM13L                     ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask  */
 #define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
 #define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
-#define pCAN_AM13H                     ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */
 #define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
 #define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
-#define pCAN_AM14L                     ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask  */
 #define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
 #define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
-#define pCAN_AM14H                     ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */
 #define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
 #define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
-#define pCAN_AM15L                     ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask  */
 #define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
 #define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
-#define pCAN_AM15H                     ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */
 #define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
 #define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
-#define pCAN_AM16L                     ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask  */
 #define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
 #define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
-#define pCAN_AM16H                     ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */
 #define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
 #define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
-#define pCAN_AM17L                     ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask  */
 #define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
 #define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
-#define pCAN_AM17H                     ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */
 #define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
 #define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
-#define pCAN_AM18L                     ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask  */
 #define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
 #define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
-#define pCAN_AM18H                     ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */
 #define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
 #define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
-#define pCAN_AM19L                     ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask  */
 #define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
 #define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
-#define pCAN_AM19H                     ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */
 #define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
 #define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
-#define pCAN_AM20L                     ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask  */
 #define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
 #define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
-#define pCAN_AM20H                     ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */
 #define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
 #define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
-#define pCAN_AM21L                     ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask  */
 #define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
 #define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
-#define pCAN_AM21H                     ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */
 #define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
 #define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
-#define pCAN_AM22L                     ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask  */
 #define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
 #define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
-#define pCAN_AM22H                     ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */
 #define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
 #define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
-#define pCAN_AM23L                     ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask  */
 #define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
 #define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
-#define pCAN_AM23H                     ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */
 #define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
 #define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
-#define pCAN_AM24L                     ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask  */
 #define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
 #define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
-#define pCAN_AM24H                     ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */
 #define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
 #define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
-#define pCAN_AM25L                     ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask  */
 #define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
 #define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
-#define pCAN_AM25H                     ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */
 #define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
 #define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
-#define pCAN_AM26L                     ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask  */
 #define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
 #define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
-#define pCAN_AM26H                     ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */
 #define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
 #define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
-#define pCAN_AM27L                     ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask  */
 #define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
 #define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
-#define pCAN_AM27H                     ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */
 #define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
 #define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
-#define pCAN_AM28L                     ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask  */
 #define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
 #define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
-#define pCAN_AM28H                     ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */
 #define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
 #define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
-#define pCAN_AM29L                     ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask  */
 #define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
 #define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
-#define pCAN_AM29H                     ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */
 #define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
 #define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
-#define pCAN_AM30L                     ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask  */
 #define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
 #define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
-#define pCAN_AM30H                     ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */
 #define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
 #define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
-#define pCAN_AM31L                     ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask  */
 #define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
 #define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
-#define pCAN_AM31H                     ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */
 #define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
 #define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
-#define pCAN_MB00_DATA0                ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
 #define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define pCAN_MB00_DATA1                ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
 #define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define pCAN_MB00_DATA2                ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
 #define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define pCAN_MB00_DATA3                ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
 #define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define pCAN_MB00_LENGTH               ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */
 #define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
 #define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define pCAN_MB00_TIMESTAMP            ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */
 #define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
 #define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define pCAN_MB00_ID0                  ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */
 #define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
 #define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
-#define pCAN_MB00_ID1                  ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */
 #define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
 #define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
-#define pCAN_MB01_DATA0                ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register  */
 #define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
 #define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define pCAN_MB01_DATA1                ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
 #define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define pCAN_MB01_DATA2                ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
 #define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define pCAN_MB01_DATA3                ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
 #define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define pCAN_MB01_LENGTH               ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */
 #define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
 #define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define pCAN_MB01_TIMESTAMP            ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */
 #define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
 #define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define pCAN_MB01_ID0                  ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */
 #define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
 #define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
-#define pCAN_MB01_ID1                  ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */
 #define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
 #define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
-#define pCAN_MB02_DATA0                ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register  */
 #define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
 #define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define pCAN_MB02_DATA1                ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
 #define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define pCAN_MB02_DATA2                ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
 #define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define pCAN_MB02_DATA3                ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
 #define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define pCAN_MB02_LENGTH               ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register    */
 #define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
 #define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define pCAN_MB02_TIMESTAMP            ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */
 #define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
 #define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define pCAN_MB02_ID0                  ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */
 #define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
 #define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
-#define pCAN_MB02_ID1                  ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */
 #define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
 #define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
-#define pCAN_MB03_DATA0                ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register  */
 #define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
 #define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define pCAN_MB03_DATA1                ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
 #define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define pCAN_MB03_DATA2                ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
 #define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define pCAN_MB03_DATA3                ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
 #define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define pCAN_MB03_LENGTH               ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */
 #define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
 #define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define pCAN_MB03_TIMESTAMP            ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */
 #define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
 #define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define pCAN_MB03_ID0                  ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */
 #define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
 #define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
-#define pCAN_MB03_ID1                  ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */
 #define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
 #define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
-#define pCAN_MB04_DATA0                ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
 #define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define pCAN_MB04_DATA1                ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
 #define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define pCAN_MB04_DATA2                ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
 #define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define pCAN_MB04_DATA3                ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
 #define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define pCAN_MB04_LENGTH               ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */
 #define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
 #define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define pCAN_MB04_TIMESTAMP            ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */
 #define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
 #define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define pCAN_MB04_ID0                  ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */
 #define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
 #define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
-#define pCAN_MB04_ID1                  ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */
 #define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
 #define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
-#define pCAN_MB05_DATA0                ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register  */
 #define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
 #define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define pCAN_MB05_DATA1                ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
 #define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define pCAN_MB05_DATA2                ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
 #define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define pCAN_MB05_DATA3                ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
 #define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define pCAN_MB05_LENGTH               ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */
 #define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
 #define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define pCAN_MB05_TIMESTAMP            ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */
 #define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
 #define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define pCAN_MB05_ID0                  ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */
 #define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
 #define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
-#define pCAN_MB05_ID1                  ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */
 #define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
 #define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
-#define pCAN_MB06_DATA0                ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register  */
 #define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
 #define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define pCAN_MB06_DATA1                ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
 #define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define pCAN_MB06_DATA2                ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
 #define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define pCAN_MB06_DATA3                ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
 #define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define pCAN_MB06_LENGTH               ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */
 #define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
 #define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define pCAN_MB06_TIMESTAMP            ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */
 #define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
 #define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define pCAN_MB06_ID0                  ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */
 #define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
 #define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
-#define pCAN_MB06_ID1                  ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */
 #define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
 #define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
-#define pCAN_MB07_DATA0                ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
 #define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define pCAN_MB07_DATA1                ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
 #define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define pCAN_MB07_DATA2                ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
 #define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define pCAN_MB07_DATA3                ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
 #define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define pCAN_MB07_LENGTH               ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */
 #define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
 #define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define pCAN_MB07_TIMESTAMP            ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */
 #define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
 #define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define pCAN_MB07_ID0                  ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */
 #define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
 #define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
-#define pCAN_MB07_ID1                  ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */
 #define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
 #define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
-#define pCAN_MB08_DATA0                ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
 #define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define pCAN_MB08_DATA1                ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
 #define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define pCAN_MB08_DATA2                ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
 #define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define pCAN_MB08_DATA3                ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
 #define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define pCAN_MB08_LENGTH               ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */
 #define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
 #define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define pCAN_MB08_TIMESTAMP            ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */
 #define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
 #define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define pCAN_MB08_ID0                  ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */
 #define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
 #define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
-#define pCAN_MB08_ID1                  ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */
 #define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
 #define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
-#define pCAN_MB09_DATA0                ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
 #define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define pCAN_MB09_DATA1                ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
 #define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define pCAN_MB09_DATA2                ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
 #define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define pCAN_MB09_DATA3                ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
 #define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define pCAN_MB09_LENGTH               ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */
 #define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
 #define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define pCAN_MB09_TIMESTAMP            ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */
 #define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
 #define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define pCAN_MB09_ID0                  ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */
 #define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
 #define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
-#define pCAN_MB09_ID1                  ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */
 #define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
 #define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
-#define pCAN_MB10_DATA0                ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
 #define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define pCAN_MB10_DATA1                ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
 #define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define pCAN_MB10_DATA2                ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
 #define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define pCAN_MB10_DATA3                ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
 #define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define pCAN_MB10_LENGTH               ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */
 #define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
 #define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define pCAN_MB10_TIMESTAMP            ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */
 #define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
 #define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define pCAN_MB10_ID0                  ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */
 #define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
 #define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
-#define pCAN_MB10_ID1                  ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */
 #define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
 #define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
-#define pCAN_MB11_DATA0                ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
 #define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define pCAN_MB11_DATA1                ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
 #define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define pCAN_MB11_DATA2                ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
 #define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define pCAN_MB11_DATA3                ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
 #define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define pCAN_MB11_LENGTH               ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */
 #define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
 #define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define pCAN_MB11_TIMESTAMP            ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */
 #define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
 #define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define pCAN_MB11_ID0                  ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */
 #define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
 #define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
-#define pCAN_MB11_ID1                  ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */
 #define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
 #define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
-#define pCAN_MB12_DATA0                ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
 #define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define pCAN_MB12_DATA1                ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
 #define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define pCAN_MB12_DATA2                ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
 #define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define pCAN_MB12_DATA3                ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
 #define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define pCAN_MB12_LENGTH               ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */
 #define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
 #define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define pCAN_MB12_TIMESTAMP            ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */
 #define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
 #define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define pCAN_MB12_ID0                  ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */
 #define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
 #define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
-#define pCAN_MB12_ID1                  ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */
 #define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
 #define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
-#define pCAN_MB13_DATA0                ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
 #define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define pCAN_MB13_DATA1                ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
 #define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define pCAN_MB13_DATA2                ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
 #define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define pCAN_MB13_DATA3                ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
 #define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define pCAN_MB13_LENGTH               ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */
 #define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
 #define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define pCAN_MB13_TIMESTAMP            ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */
 #define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
 #define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define pCAN_MB13_ID0                  ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */
 #define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
 #define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
-#define pCAN_MB13_ID1                  ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */
 #define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
 #define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
-#define pCAN_MB14_DATA0                ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
 #define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define pCAN_MB14_DATA1                ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
 #define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define pCAN_MB14_DATA2                ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
 #define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define pCAN_MB14_DATA3                ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
 #define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define pCAN_MB14_LENGTH               ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */
 #define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
 #define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define pCAN_MB14_TIMESTAMP            ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */
 #define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
 #define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define pCAN_MB14_ID0                  ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */
 #define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
 #define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
-#define pCAN_MB14_ID1                  ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */
 #define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
 #define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
-#define pCAN_MB15_DATA0                ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
 #define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define pCAN_MB15_DATA1                ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
 #define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define pCAN_MB15_DATA2                ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
 #define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define pCAN_MB15_DATA3                ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
 #define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define pCAN_MB15_LENGTH               ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */
 #define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
 #define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define pCAN_MB15_TIMESTAMP            ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */
 #define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
 #define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define pCAN_MB15_ID0                  ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */
 #define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
 #define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
-#define pCAN_MB15_ID1                  ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */
 #define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
 #define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
-#define pCAN_MB16_DATA0                ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
 #define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define pCAN_MB16_DATA1                ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
 #define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define pCAN_MB16_DATA2                ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
 #define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define pCAN_MB16_DATA3                ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
 #define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define pCAN_MB16_LENGTH               ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */
 #define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
 #define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define pCAN_MB16_TIMESTAMP            ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */
 #define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
 #define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define pCAN_MB16_ID0                  ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */
 #define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
 #define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
-#define pCAN_MB16_ID1                  ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */
 #define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
 #define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
-#define pCAN_MB17_DATA0                ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
 #define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define pCAN_MB17_DATA1                ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
 #define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define pCAN_MB17_DATA2                ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
 #define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define pCAN_MB17_DATA3                ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
 #define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define pCAN_MB17_LENGTH               ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */
 #define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
 #define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define pCAN_MB17_TIMESTAMP            ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */
 #define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
 #define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define pCAN_MB17_ID0                  ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */
 #define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
 #define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
-#define pCAN_MB17_ID1                  ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */
 #define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
 #define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
-#define pCAN_MB18_DATA0                ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
 #define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define pCAN_MB18_DATA1                ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
 #define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define pCAN_MB18_DATA2                ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
 #define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define pCAN_MB18_DATA3                ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
 #define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define pCAN_MB18_LENGTH               ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */
 #define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
 #define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define pCAN_MB18_TIMESTAMP            ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */
 #define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
 #define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define pCAN_MB18_ID0                  ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */
 #define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
 #define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
-#define pCAN_MB18_ID1                  ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */
 #define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
 #define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
-#define pCAN_MB19_DATA0                ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
 #define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define pCAN_MB19_DATA1                ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
 #define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define pCAN_MB19_DATA2                ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
 #define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define pCAN_MB19_DATA3                ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
 #define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define pCAN_MB19_LENGTH               ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */
 #define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
 #define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define pCAN_MB19_TIMESTAMP            ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */
 #define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
 #define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define pCAN_MB19_ID0                  ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */
 #define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
 #define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
-#define pCAN_MB19_ID1                  ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */
 #define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
 #define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
-#define pCAN_MB20_DATA0                ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
 #define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define pCAN_MB20_DATA1                ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
 #define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define pCAN_MB20_DATA2                ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
 #define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define pCAN_MB20_DATA3                ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
 #define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define pCAN_MB20_LENGTH               ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */
 #define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
 #define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define pCAN_MB20_TIMESTAMP            ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */
 #define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
 #define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define pCAN_MB20_ID0                  ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */
 #define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
 #define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
-#define pCAN_MB20_ID1                  ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */
 #define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
 #define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
-#define pCAN_MB21_DATA0                ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
 #define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define pCAN_MB21_DATA1                ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
 #define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define pCAN_MB21_DATA2                ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
 #define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define pCAN_MB21_DATA3                ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
 #define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define pCAN_MB21_LENGTH               ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */
 #define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
 #define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define pCAN_MB21_TIMESTAMP            ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */
 #define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
 #define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define pCAN_MB21_ID0                  ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */
 #define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
 #define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
-#define pCAN_MB21_ID1                  ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */
 #define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
 #define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
-#define pCAN_MB22_DATA0                ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
 #define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define pCAN_MB22_DATA1                ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
 #define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define pCAN_MB22_DATA2                ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
 #define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define pCAN_MB22_DATA3                ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
 #define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define pCAN_MB22_LENGTH               ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */
 #define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
 #define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define pCAN_MB22_TIMESTAMP            ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */
 #define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
 #define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define pCAN_MB22_ID0                  ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */
 #define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
 #define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
-#define pCAN_MB22_ID1                  ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */
 #define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
 #define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
-#define pCAN_MB23_DATA0                ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
 #define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define pCAN_MB23_DATA1                ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
 #define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define pCAN_MB23_DATA2                ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
 #define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define pCAN_MB23_DATA3                ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
 #define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define pCAN_MB23_LENGTH               ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */
 #define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
 #define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define pCAN_MB23_TIMESTAMP            ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */
 #define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
 #define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define pCAN_MB23_ID0                  ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */
 #define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
 #define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
-#define pCAN_MB23_ID1                  ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */
 #define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
 #define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
-#define pCAN_MB24_DATA0                ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
 #define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define pCAN_MB24_DATA1                ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
 #define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define pCAN_MB24_DATA2                ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
 #define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define pCAN_MB24_DATA3                ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
 #define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define pCAN_MB24_LENGTH               ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */
 #define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
 #define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define pCAN_MB24_TIMESTAMP            ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */
 #define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
 #define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define pCAN_MB24_ID0                  ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */
 #define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
 #define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
-#define pCAN_MB24_ID1                  ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */
 #define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
 #define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
-#define pCAN_MB25_DATA0                ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
 #define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define pCAN_MB25_DATA1                ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
 #define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define pCAN_MB25_DATA2                ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
 #define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define pCAN_MB25_DATA3                ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
 #define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define pCAN_MB25_LENGTH               ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */
 #define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
 #define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define pCAN_MB25_TIMESTAMP            ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */
 #define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
 #define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define pCAN_MB25_ID0                  ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */
 #define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
 #define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
-#define pCAN_MB25_ID1                  ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */
 #define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
 #define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
-#define pCAN_MB26_DATA0                ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
 #define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define pCAN_MB26_DATA1                ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
 #define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define pCAN_MB26_DATA2                ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
 #define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define pCAN_MB26_DATA3                ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
 #define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define pCAN_MB26_LENGTH               ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */
 #define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
 #define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define pCAN_MB26_TIMESTAMP            ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */
 #define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
 #define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define pCAN_MB26_ID0                  ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */
 #define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
 #define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
-#define pCAN_MB26_ID1                  ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */
 #define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
 #define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
-#define pCAN_MB27_DATA0                ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
 #define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define pCAN_MB27_DATA1                ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
 #define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define pCAN_MB27_DATA2                ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
 #define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define pCAN_MB27_DATA3                ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
 #define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define pCAN_MB27_LENGTH               ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */
 #define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
 #define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define pCAN_MB27_TIMESTAMP            ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */
 #define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
 #define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define pCAN_MB27_ID0                  ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */
 #define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
 #define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
-#define pCAN_MB27_ID1                  ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */
 #define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
 #define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
-#define pCAN_MB28_DATA0                ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
 #define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define pCAN_MB28_DATA1                ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
 #define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define pCAN_MB28_DATA2                ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
 #define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define pCAN_MB28_DATA3                ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
 #define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define pCAN_MB28_LENGTH               ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */
 #define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
 #define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define pCAN_MB28_TIMESTAMP            ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */
 #define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
 #define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define pCAN_MB28_ID0                  ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */
 #define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
 #define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
-#define pCAN_MB28_ID1                  ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */
 #define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
 #define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
-#define pCAN_MB29_DATA0                ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
 #define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define pCAN_MB29_DATA1                ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
 #define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define pCAN_MB29_DATA2                ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
 #define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define pCAN_MB29_DATA3                ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
 #define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define pCAN_MB29_LENGTH               ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */
 #define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
 #define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define pCAN_MB29_TIMESTAMP            ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */
 #define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
 #define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define pCAN_MB29_ID0                  ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */
 #define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
 #define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
-#define pCAN_MB29_ID1                  ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */
 #define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
 #define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
-#define pCAN_MB30_DATA0                ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
 #define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define pCAN_MB30_DATA1                ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
 #define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define pCAN_MB30_DATA2                ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
 #define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define pCAN_MB30_DATA3                ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
 #define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define pCAN_MB30_LENGTH               ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */
 #define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
 #define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define pCAN_MB30_TIMESTAMP            ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */
 #define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
 #define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define pCAN_MB30_ID0                  ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */
 #define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
 #define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
-#define pCAN_MB30_ID1                  ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */
 #define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
 #define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
-#define pCAN_MB31_DATA0                ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */
 #define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
 #define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define pCAN_MB31_DATA1                ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */
 #define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
 #define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define pCAN_MB31_DATA2                ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */
 #define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
 #define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define pCAN_MB31_DATA3                ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */
 #define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
 #define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define pCAN_MB31_LENGTH               ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */
 #define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
 #define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define pCAN_MB31_TIMESTAMP            ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */
 #define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
 #define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define pCAN_MB31_ID0                  ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */
 #define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
 #define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
-#define pCAN_MB31_ID1                  ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */
 #define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
 #define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORT_MUX                      ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */
 #define bfin_read_PORT_MUX()           bfin_read16(PORT_MUX)
 #define bfin_write_PORT_MUX(val)       bfin_write16(PORT_MUX, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR)
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define pPFCTL                         ((uint32_t volatile *)PFCTL)
 #define bfin_read_PFCTL()              bfin_read32(PFCTL)
 #define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
 #define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
 #define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
 #define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
 #define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
 #define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
 #define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
 #define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
 #define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
index d753b5e..6116298 100644
--- a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h
@@ -10,241 +10,162 @@
 
 #include "ADSP-EDN-BF534-extended_cdef.h"
 
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
 #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
 #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
 #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
 #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
 #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
 #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
 #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
 #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
 #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
 #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
 #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
 #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
 #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
 #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
 #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
 #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
 #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
 #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
 #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
 #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
 #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
 #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
 #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
 #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
 #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
 #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
 #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
 #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
 #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
 #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
 #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
 #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
 #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
 #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
 #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
 #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
 #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
 #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
 #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
 #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
 #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
 #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
 #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
 #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
 #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
 #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
 #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
 #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
 #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
 #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
 #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
index 5eff57d..8723b57 100644
--- a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h
@@ -10,241 +10,162 @@
 
 #include "ADSP-EDN-BF534-extended_cdef.h"
 
-#define pEMAC_OPMODE                   ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define pEMAC_ADDRLO                   ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
 #define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define pEMAC_ADDRHI                   ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */
 #define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
 #define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define pEMAC_HASHLO                   ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */
 #define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
 #define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define pEMAC_HASHHI                   ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */
 #define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
 #define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define pEMAC_STAADD                   ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */
 #define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
 #define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define pEMAC_STADAT                   ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */
 #define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
 #define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define pEMAC_FLC                      ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */
 #define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
 #define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define pEMAC_VLAN1                    ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */
 #define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
 #define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define pEMAC_VLAN2                    ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */
 #define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
 #define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define pEMAC_WKUP_CTL                 ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */
 #define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
 #define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define pEMAC_WKUP_FFMSK0              ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
 #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define pEMAC_WKUP_FFMSK1              ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
 #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define pEMAC_WKUP_FFMSK2              ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
 #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define pEMAC_WKUP_FFMSK3              ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */
 #define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
 #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define pEMAC_WKUP_FFCMD               ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */
 #define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
 #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define pEMAC_WKUP_FFOFF               ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */
 #define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
 #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define pEMAC_WKUP_FFCRC0              ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
 #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define pEMAC_WKUP_FFCRC1              ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */
 #define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
 #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define pEMAC_SYSCTL                   ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */
 #define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
 #define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define pEMAC_SYSTAT                   ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */
 #define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
 #define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define pEMAC_RX_STAT                  ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */
 #define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
 #define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define pEMAC_RX_STKY                  ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */
 #define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
 #define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define pEMAC_RX_IRQE                  ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
 #define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define pEMAC_TX_STAT                  ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */
 #define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
 #define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define pEMAC_TX_STKY                  ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */
 #define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
 #define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define pEMAC_TX_IRQE                  ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */
 #define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
 #define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define pEMAC_MMC_CTL                  ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */
 #define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
 #define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define pEMAC_MMC_RIRQS                ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
 #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define pEMAC_MMC_RIRQE                ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
 #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define pEMAC_MMC_TIRQS                ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */
 #define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
 #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define pEMAC_MMC_TIRQE                ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */
 #define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
 #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define pEMAC_RXC_OK                   ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */
 #define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
 #define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define pEMAC_RXC_FCS                  ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */
 #define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
 #define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define pEMAC_RXC_ALIGN                ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */
 #define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
 #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define pEMAC_RXC_OCTET                ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */
 #define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
 #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define pEMAC_RXC_DMAOVF               ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */
 #define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
 #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define pEMAC_RXC_UNICST               ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */
 #define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
 #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define pEMAC_RXC_MULTI                ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */
 #define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
 #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define pEMAC_RXC_BROAD                ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */
 #define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
 #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define pEMAC_RXC_LNERRI               ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
 #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define pEMAC_RXC_LNERRO               ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */
 #define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
 #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define pEMAC_RXC_LONG                 ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */
 #define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
 #define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define pEMAC_RXC_MACCTL               ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */
 #define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
 #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define pEMAC_RXC_OPCODE               ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */
 #define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
 #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define pEMAC_RXC_PAUSE                ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */
 #define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
 #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define pEMAC_RXC_ALLFRM               ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */
 #define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
 #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define pEMAC_RXC_ALLOCT               ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */
 #define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
 #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define pEMAC_RXC_TYPED                ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count  */
 #define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
 #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define pEMAC_RXC_SHORT                ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */
 #define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
 #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define pEMAC_RXC_EQ64                 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
 #define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define pEMAC_RXC_LT128                ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
 #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define pEMAC_RXC_LT256                ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
 #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define pEMAC_RXC_LT512                ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
 #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define pEMAC_RXC_LT1024               ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
 #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define pEMAC_RXC_GE1024               ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
 #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define pEMAC_TXC_OK                   ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */
 #define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
 #define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define pEMAC_TXC_1COL                 ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */
 #define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
 #define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define pEMAC_TXC_GT1COL               ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */
 #define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
 #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define pEMAC_TXC_OCTET                ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */
 #define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
 #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define pEMAC_TXC_DEFER                ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */
 #define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
 #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define pEMAC_TXC_LATECL               ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */
 #define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
 #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define pEMAC_TXC_XS_COL               ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */
 #define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
 #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define pEMAC_TXC_DMAUND               ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */
 #define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
 #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define pEMAC_TXC_CRSERR               ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */
 #define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
 #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define pEMAC_TXC_UNICST               ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */
 #define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
 #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define pEMAC_TXC_MULTI                ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */
 #define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
 #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define pEMAC_TXC_BROAD                ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */
 #define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
 #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define pEMAC_TXC_XS_DFR               ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */
 #define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
 #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define pEMAC_TXC_MACCTL               ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */
 #define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
 #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define pEMAC_TXC_ALLFRM               ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */
 #define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
 #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define pEMAC_TXC_ALLOCT               ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */
 #define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
 #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define pEMAC_TXC_EQ64                 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */
 #define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
 #define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define pEMAC_TXC_LT128                ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count  64 <= x < 128 */
 #define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
 #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define pEMAC_TXC_LT256                ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */
 #define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
 #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define pEMAC_TXC_LT512                ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */
 #define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
 #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define pEMAC_TXC_LT1024               ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
 #define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
 #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define pEMAC_TXC_GE1024               ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */
 #define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
 #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define pEMAC_TXC_ABORT                ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */
 #define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
 #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
index 51d9cf2..ee2699c 100644
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h
@@ -6,4372 +6,2915 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF542_extended__
 
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
 #define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
 #define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
 #define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
 #define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
 #define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
 #define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
 #define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
 #define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
 #define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
 #define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
 #define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
 #define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
 #define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
 #define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
 #define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
 #define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
 #define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
 #define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
 #define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
 #define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
 #define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 #define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 #define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 #define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 #define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 #define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 #define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 #define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 #define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 #define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 #define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 #define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 #define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 #define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 #define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 #define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 #define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 #define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 #define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 #define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 #define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 #define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 #define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 #define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 #define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 #define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 #define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 #define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 #define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 #define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 #define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 #define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 #define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 #define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 #define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 #define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 #define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 #define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 #define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 #define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 #define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 #define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 #define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 #define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 #define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 #define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 #define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 #define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 #define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 #define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 #define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 #define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 #define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 #define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 #define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 #define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 #define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 #define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 #define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 #define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 #define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 #define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 #define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 #define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 #define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 #define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 #define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 #define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 #define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 #define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 #define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 #define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 #define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 #define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 #define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 #define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 #define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 #define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 #define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 #define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 #define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 #define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 #define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 #define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 #define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 #define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 #define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 #define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 #define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 #define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 #define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 #define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 #define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 #define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 #define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 #define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 #define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 #define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 #define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 #define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 #define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 #define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 #define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 #define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 #define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 #define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 #define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 #define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 #define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 #define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 #define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 #define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 #define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 #define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 #define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 #define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 #define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 #define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 #define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 #define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 #define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 #define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 #define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 #define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 #define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 #define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 #define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 #define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
 #define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
 #define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
 #define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
 #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
 #define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
 #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
 #define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
 #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
 #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
 #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
 #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
 #define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
 #define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
 #define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
 #define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
 #define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
 #define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
 #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
 #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
 #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
 #define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
 #define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
 #define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
 #define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
 #define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
 #define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
 #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
 #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
 #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
 #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
 #define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
 #define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
 #define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
 #define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
 #define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
 #define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
 #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
 #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
 #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
 #define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
 #define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
 #define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
 #define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
 #define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
 #define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
 #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
 #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
 #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
 #define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
 #define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
 #define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
 #define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
 #define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
 #define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
 #define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
 #define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
 #define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
 #define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
 #define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
 #define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
 #define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
 #define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
 #define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
 #define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
 #define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
 #define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
 #define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
 #define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
 #define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
 #define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
 #define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
 #define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
 #define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
 #define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
 #define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
 #define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
 #define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
 #define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
 #define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
 #define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
 #define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
 #define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
 #define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
 #define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
 #define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
 #define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
 #define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
 #define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
 #define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
 #define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
 #define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
 #define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
 #define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
 #define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
 #define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
 #define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
 #define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
 #define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
 #define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
 #define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
 #define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
 #define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
 #define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
 #define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
 #define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
 #define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
 #define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
 #define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
 #define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
 #define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
 #define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
 #define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
 #define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
 #define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
 #define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
 #define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
 #define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
 #define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
 #define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
 #define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
 #define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
 #define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
 #define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
 #define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
 #define bfin_read_PORTA()              bfin_read16(PORTA)
 #define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
 #define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
 #define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
 #define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
 #define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
 #define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
 #define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
 #define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
 #define bfin_read_PORTB()              bfin_read16(PORTB)
 #define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
 #define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
 #define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
 #define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
 #define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
 #define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
 #define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
 #define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
 #define bfin_read_PORTC()              bfin_read16(PORTC)
 #define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
 #define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
 #define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
 #define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
 #define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
 #define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
 #define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
 #define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
 #define bfin_read_PORTD()              bfin_read16(PORTD)
 #define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
 #define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
 #define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
 #define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
 #define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
 #define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
 #define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
 #define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
 #define bfin_read_PORTE()              bfin_read16(PORTE)
 #define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
 #define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
 #define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
 #define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
 #define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
 #define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
 #define bfin_read_PORTF()              bfin_read16(PORTF)
 #define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
 #define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
 #define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
 #define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
 #define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
 #define bfin_read_PORTG()              bfin_read16(PORTG)
 #define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
 #define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
 #define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
 #define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
 #define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
 #define bfin_read_PORTH()              bfin_read16(PORTH)
 #define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
 #define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
 #define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
 #define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
 #define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
 #define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
 #define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
 #define bfin_read_PORTI()              bfin_read16(PORTI)
 #define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
 #define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
 #define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
 #define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
 #define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
 #define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
 #define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
 #define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
 #define bfin_read_PORTJ()              bfin_read16(PORTJ)
 #define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
 #define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
 #define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
 #define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
 #define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
 #define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
 #define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
 #define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
 #define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
 #define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
 #define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
 #define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
 #define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 #define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
 #define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
 #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
 #define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
 #define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
 #define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
 #define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
 #define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
 #define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
 #define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
 #define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
 #define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
 #define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 #define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
 #define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
 #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
 #define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
 #define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
 #define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
 #define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
 #define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
 #define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
 #define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
 #define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
 #define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
 #define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 #define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
 #define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
 #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
 #define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
 #define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
 #define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
 #define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
 #define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
 #define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
 #define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
 #define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
 #define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
 #define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 #define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
 #define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
 #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
 #define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
 #define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
 #define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
 #define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
 #define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
 #define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
 #define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
 #define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
 #define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
 #define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
 #define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
 #define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
 #define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
 #define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
 #define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
 #define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
 #define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
 #define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
 #define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
 #define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
 #define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
 #define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
 #define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
 #define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
 #define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
 #define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
 #define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
 #define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
 #define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
 #define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
 #define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
 #define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
 #define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
 #define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
 #define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
 #define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
 #define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
 #define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
 #define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
 #define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
 #define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
 #define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
 #define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
 #define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
 #define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
 #define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
 #define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
 #define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
 #define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
 #define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
 #define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
 #define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
 #define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
 #define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
 #define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
 #define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
 #define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
 #define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
 #define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
 #define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
 #define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
 #define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
 #define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
 #define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
 #define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
 #define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
 #define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
 #define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
 #define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
 #define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
 #define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
 #define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
 #define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
 #define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
 #define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
 #define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
 #define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
 #define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
 #define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
 #define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
 #define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
 #define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
 #define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
 #define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
 #define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
 #define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
 #define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
 #define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
 #define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
 #define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
 #define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
 #define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
 #define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
 #define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
 #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
 #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
 #define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
 #define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
 #define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
 #define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
 #define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
 #define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
 #define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
 #define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
 #define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
 #define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
 #define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
 #define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
 #define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
 #define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
 #define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
 #define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
 #define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
 #define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
 #define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
 #define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
 #define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
 #define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
 #define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
 #define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 #define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
 #define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
 #define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
 #define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
 #define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
 #define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
 #define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
 #define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
 #define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
 #define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
 #define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
 #define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
 #define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
 #define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
 #define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
 #define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
 #define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
 #define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
 #define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
 #define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
 #define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 #define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
 #define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
 #define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
 #define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
 #define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
 #define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
 #define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
 #define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
 #define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
 #define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
 #define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
 #define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
 #define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
 #define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
 #define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
 #define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
 #define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
 #define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
 #define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
 #define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
 #define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
 #define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
 #define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
 #define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
 #define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
 #define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
 #define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
 #define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
 #define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
 #define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
 #define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
 #define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
 #define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
 #define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
 #define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
 #define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
 #define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
 #define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
 #define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
 #define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
 #define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
 #define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
 #define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
 #define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
 #define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
 #define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
 #define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
 #define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
 #define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
 #define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
 #define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
 #define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
 #define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
 #define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
 #define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
 #define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
 #define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
 #define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
 #define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
 #define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
 #define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
 #define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
 #define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
 #define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
 #define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
 #define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
 #define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
 #define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
 #define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
 #define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
 #define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
 #define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
 #define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
 #define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
 #define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
 #define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
 #define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
 #define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
 #define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
 #define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
 #define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
 #define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
 #define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
 #define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
 #define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
 #define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
 #define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
 #define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
 #define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
 #define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
 #define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
 #define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
 #define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
 #define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
 #define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
 #define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
 #define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
 #define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
 #define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
 #define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
 #define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
 #define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
 #define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
 #define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
 #define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
 #define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
 #define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
 #define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
 #define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
 #define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
 #define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
 #define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
 #define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
 #define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
 #define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
 #define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
 #define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
 #define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
 #define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
 #define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
 #define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
 #define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
 #define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
 #define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
 #define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
 #define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
 #define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
 #define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
 #define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
 #define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
 #define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
 #define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
 #define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
 #define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
 #define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
 #define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
 #define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
 #define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
 #define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
 #define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
 #define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
 #define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
 #define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
 #define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
 #define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
 #define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
 #define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
 #define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
 #define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
 #define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
 #define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
 #define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
 #define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
 #define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
 #define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
 #define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
 #define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
 #define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
 #define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
 #define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
 #define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
 #define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
 #define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
 #define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
 #define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
 #define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
 #define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
 #define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
 #define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
 #define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
 #define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
 #define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
 #define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
 #define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
 #define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
 #define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
 #define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
 #define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
 #define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
 #define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
 #define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
 #define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
 #define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
 #define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
 #define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
 #define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
 #define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
 #define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
 #define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
 #define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
 #define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
 #define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
 #define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
 #define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
 #define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
 #define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
 #define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
 #define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
 #define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
 #define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
 #define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
 #define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
 #define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
 #define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
 #define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
 #define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
 #define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
 #define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
 #define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
 #define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
 #define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
 #define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
 #define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
 #define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
 #define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
 #define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
 #define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
 #define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
 #define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
 #define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
 #define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
 #define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
 #define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
 #define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
 #define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
 #define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
 #define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
 #define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
 #define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
 #define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
 #define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
 #define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
 #define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
 #define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
 #define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
 #define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
 #define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
 #define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
 #define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
 #define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
 #define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
 #define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
 #define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
 #define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
 #define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
 #define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
 #define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
 #define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
 #define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
 #define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
 #define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
 #define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
 #define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
 #define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
 #define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
 #define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
 #define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
 #define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
 #define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
 #define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
 #define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
 #define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
 #define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
 #define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
 #define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
 #define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
 #define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
 #define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
 #define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
 #define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
 #define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
 #define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
 #define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
 #define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
 #define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
 #define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
 #define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
 #define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
 #define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
 #define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
 #define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
 #define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
 #define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
 #define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
 #define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
 #define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
 #define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
 #define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
 #define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
 #define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
 #define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
 #define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
 #define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
 #define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
 #define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
 #define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
 #define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
 #define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
 #define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
 #define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
 #define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
 #define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
 #define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
 #define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
 #define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
 #define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
 #define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
 #define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
 #define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
 #define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
 #define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
 #define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
 #define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
 #define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
 #define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
 #define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
 #define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
 #define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
 #define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
 #define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
 #define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
 #define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
 #define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
 #define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
 #define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
 #define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
 #define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
 #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
 #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
 #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
 #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
 #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
 #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
 #define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
 #define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
 #define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
 #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
 #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
 #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
 #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
 #define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
 #define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
 #define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
 #define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
 #define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
 #define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
 #define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
 #define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
 #define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
 #define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
 #define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
 #define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
 #define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
 #define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
 #define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
 #define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
 #define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
 #define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
 #define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
 #define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
 #define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
 #define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
 #define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
 #define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
 #define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
 #define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
 #define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
 #define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
 #define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
 #define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
 #define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
 #define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
 #define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
 #define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
 #define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
 #define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
 #define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
 #define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
 #define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
 #define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
 #define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
 #define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
 #define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
 #define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
 #define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
 #define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
 #define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
 #define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
 #define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
 #define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
 #define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
 #define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
 #define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
 #define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
 #define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
 #define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
 #define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
 #define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
 #define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
 #define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
 #define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
 #define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
 #define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
 #define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
 #define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
 #define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
 #define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
 #define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
 #define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
index 4c0fdf5..67a3746 100644
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
@@ -6,4966 +6,3311 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF544_extended__
 
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
 #define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
 #define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
 #define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
 #define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
 #define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
 #define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
 #define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
 #define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
 #define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
 #define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
 #define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
 #define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
 #define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
 #define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
 #define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
 #define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
 #define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
 #define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
 #define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
 #define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
 #define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 #define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 #define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 #define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 #define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 #define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 #define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 #define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 #define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 #define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 #define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 #define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 #define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 #define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 #define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 #define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 #define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 #define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 #define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 #define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 #define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 #define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 #define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 #define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 #define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 #define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 #define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 #define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 #define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 #define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 #define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 #define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 #define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 #define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 #define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 #define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 #define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 #define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 #define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 #define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 #define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 #define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 #define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 #define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 #define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 #define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 #define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 #define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 #define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 #define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 #define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 #define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 #define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 #define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 #define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 #define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 #define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 #define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 #define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 #define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 #define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 #define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 #define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 #define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 #define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 #define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 #define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 #define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 #define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 #define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 #define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 #define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 #define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 #define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 #define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 #define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 #define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 #define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 #define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 #define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 #define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 #define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 #define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 #define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 #define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 #define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 #define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 #define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 #define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 #define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 #define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 #define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 #define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 #define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 #define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 #define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 #define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 #define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 #define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 #define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 #define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 #define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 #define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 #define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 #define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 #define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 #define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 #define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 #define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 #define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 #define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 #define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 #define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 #define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 #define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 #define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 #define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 #define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 #define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 #define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 #define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 #define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 #define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 #define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 #define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 #define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 #define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 #define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
 #define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
 #define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
 #define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
 #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
 #define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
 #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
 #define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
 #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
 #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
 #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
 #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
 #define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
 #define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
 #define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
 #define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
 #define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
 #define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
 #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
 #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
 #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
 #define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
 #define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
 #define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
 #define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
 #define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
 #define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
 #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
 #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
 #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
 #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
 #define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
 #define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
 #define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
 #define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
 #define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
 #define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
 #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
 #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
 #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
 #define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
 #define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
 #define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
 #define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
 #define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
 #define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
 #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
 #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
 #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
 #define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
 #define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
 #define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
 #define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
 #define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
 #define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
 #define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
 #define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
 #define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
 #define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
 #define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
 #define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
 #define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
 #define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
 #define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
 #define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
 #define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
 #define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
 #define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
 #define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
 #define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
 #define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
 #define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
 #define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
 #define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
 #define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
 #define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
 #define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
 #define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
 #define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
 #define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
 #define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
 #define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
 #define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
 #define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
 #define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
 #define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
 #define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
 #define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
 #define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
 #define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
 #define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
 #define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
 #define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
 #define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
 #define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
 #define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
 #define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
 #define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
 #define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
 #define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
 #define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
 #define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
 #define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
 #define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
 #define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
 #define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
 #define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
 #define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
 #define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
 #define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
 #define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
 #define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
 #define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
 #define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
 #define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
 #define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
 #define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
 #define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
 #define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
 #define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
 #define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
 #define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
 #define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
 #define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
 #define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
 #define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
 #define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
 #define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
 #define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
 #define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
 #define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
 #define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
 #define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
 #define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
 #define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
 #define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
 #define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
 #define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
 #define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
 #define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
 #define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
 #define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
 #define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
 #define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
 #define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
 #define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
 #define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
 #define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
 #define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
 #define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
 #define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
 #define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
 #define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
 #define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
 #define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
 #define bfin_read_PORTA()              bfin_read16(PORTA)
 #define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
 #define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
 #define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
 #define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
 #define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
 #define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
 #define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
 #define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
 #define bfin_read_PORTB()              bfin_read16(PORTB)
 #define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
 #define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
 #define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
 #define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
 #define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
 #define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
 #define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
 #define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
 #define bfin_read_PORTC()              bfin_read16(PORTC)
 #define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
 #define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
 #define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
 #define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
 #define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
 #define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
 #define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
 #define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
 #define bfin_read_PORTD()              bfin_read16(PORTD)
 #define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
 #define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
 #define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
 #define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
 #define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
 #define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
 #define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
 #define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
 #define bfin_read_PORTE()              bfin_read16(PORTE)
 #define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
 #define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
 #define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
 #define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
 #define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
 #define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
 #define bfin_read_PORTF()              bfin_read16(PORTF)
 #define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
 #define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
 #define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
 #define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
 #define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
 #define bfin_read_PORTG()              bfin_read16(PORTG)
 #define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
 #define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
 #define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
 #define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
 #define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
 #define bfin_read_PORTH()              bfin_read16(PORTH)
 #define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
 #define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
 #define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
 #define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
 #define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
 #define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
 #define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
 #define bfin_read_PORTI()              bfin_read16(PORTI)
 #define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
 #define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
 #define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
 #define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
 #define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
 #define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
 #define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
 #define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
 #define bfin_read_PORTJ()              bfin_read16(PORTJ)
 #define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
 #define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
 #define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
 #define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
 #define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
 #define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
 #define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
 #define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
 #define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
 #define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
 #define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
 #define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
 #define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 #define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
 #define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
 #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
 #define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
 #define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
 #define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
 #define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
 #define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
 #define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
 #define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
 #define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
 #define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
 #define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 #define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
 #define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
 #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
 #define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
 #define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
 #define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
 #define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
 #define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
 #define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
 #define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
 #define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
 #define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
 #define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 #define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
 #define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
 #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
 #define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
 #define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
 #define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
 #define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
 #define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
 #define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
 #define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
 #define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
 #define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
 #define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 #define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
 #define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
 #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
 #define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
 #define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
 #define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
 #define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
 #define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
 #define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
 #define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
 #define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
 #define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
 #define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
 #define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
 #define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
 #define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
 #define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
 #define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
 #define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
 #define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
 #define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
 #define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
 #define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
 #define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
 #define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
 #define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
 #define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
 #define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
 #define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
 #define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
 #define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
 #define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
 #define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
 #define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
 #define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
 #define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
 #define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
 #define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
 #define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
 #define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
 #define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
 #define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
 #define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
 #define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
 #define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
 #define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
 #define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
 #define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
 #define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
 #define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
 #define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
 #define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
 #define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
 #define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
 #define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
 #define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
 #define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
 #define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
 #define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
 #define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
 #define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
 #define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
 #define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
 #define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
 #define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
 #define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
 #define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
 #define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
 #define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
 #define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
 #define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
 #define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
 #define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
 #define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 #define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
 #define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
 #define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
 #define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
 #define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
 #define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
 #define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
 #define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
 #define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
 #define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
 #define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
 #define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
 #define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
 #define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
 #define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
 #define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
 #define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
 #define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
 #define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
 #define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
 #define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 #define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
 #define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
 #define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
 #define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
 #define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
 #define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
 #define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
 #define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
 #define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
 #define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
 #define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
 #define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
 #define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
 #define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
 #define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
 #define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
 #define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
 #define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
 #define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
 #define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
 #define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
 #define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
 #define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
 #define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
 #define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
 #define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
 #define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
 #define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
 #define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
 #define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
 #define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
 #define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
 #define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
 #define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
 #define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
 #define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
 #define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
 #define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
 #define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
 #define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
 #define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
 #define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
 #define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
 #define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
 #define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
 #define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
 #define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
 #define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
 #define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
 #define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
 #define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
 #define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
 #define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
 #define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
 #define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
 #define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
 #define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
 #define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
 #define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
 #define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
 #define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
 #define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
 #define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
 #define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
 #define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
 #define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
 #define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
 #define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
 #define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
 #define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
 #define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
 #define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
 #define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
 #define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
 #define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
 #define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
 #define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
 #define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
 #define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
 #define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
 #define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
 #define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
 #define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
 #define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
 #define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
 #define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
 #define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
 #define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
 #define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
 #define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
 #define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
 #define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
 #define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
 #define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
 #define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
 #define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
 #define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
 #define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
 #define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
 #define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
 #define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
 #define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
 #define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
 #define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
 #define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
 #define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
 #define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
 #define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
 #define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
 #define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
 #define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
 #define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
 #define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
 #define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
 #define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
 #define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
 #define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
 #define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
 #define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
 #define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
 #define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
 #define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
 #define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
 #define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
 #define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
 #define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
 #define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
 #define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
 #define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
 #define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
 #define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
 #define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
 #define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
 #define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
 #define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
 #define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
 #define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
 #define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
 #define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
 #define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
 #define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
 #define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
 #define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
 #define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
 #define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
 #define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
 #define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
 #define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
 #define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
 #define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
 #define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
 #define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
 #define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
 #define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
 #define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
 #define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
 #define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
 #define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
 #define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
 #define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
 #define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
 #define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
 #define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
 #define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
 #define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
 #define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
 #define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
 #define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
 #define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
 #define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
 #define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
 #define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
 #define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
 #define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
 #define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
 #define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
 #define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
 #define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
 #define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
 #define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
 #define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
 #define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
 #define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
 #define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
 #define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
 #define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
 #define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
 #define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
 #define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
 #define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
 #define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
 #define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
 #define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
 #define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
 #define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
 #define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
 #define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
 #define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
 #define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
 #define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
 #define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
 #define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
 #define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
 #define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
 #define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
 #define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
 #define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
 #define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
 #define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
 #define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
 #define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
 #define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
 #define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
 #define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
 #define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
 #define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
 #define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
 #define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
 #define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
 #define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
 #define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
 #define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
 #define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
 #define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
 #define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
 #define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
 #define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
 #define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
 #define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
 #define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
 #define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
 #define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
 #define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
 #define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
 #define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
 #define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
 #define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
 #define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
 #define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
 #define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
 #define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
 #define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
 #define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
 #define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
 #define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
 #define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
 #define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
 #define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
 #define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
 #define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
 #define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
 #define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
 #define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
 #define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
 #define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
 #define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
 #define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
 #define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
 #define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
 #define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
 #define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
 #define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
 #define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
 #define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
 #define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
 #define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
 #define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
 #define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
 #define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
 #define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
 #define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
 #define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
 #define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
 #define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
 #define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
 #define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
 #define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
 #define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
 #define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
 #define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
 #define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
 #define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
 #define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
 #define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
 #define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
 #define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
 #define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
 #define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
 #define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
 #define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
 #define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
 #define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
 #define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
 #define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
 #define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
 #define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
 #define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
 #define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
 #define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
 #define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
 #define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
 #define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
 #define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
 #define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
 #define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
 #define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
 #define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
 #define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
 #define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
 #define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
 #define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
 #define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
 #define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
 #define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
 #define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
 #define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
 #define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
 #define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
 #define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
 #define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
 #define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
 #define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
 #define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
 #define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
 #define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
 #define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
 #define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
 #define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
 #define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
 #define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
 #define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
 #define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
 #define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
 #define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
 #define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
 #define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
 #define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
 #define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
 #define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
 #define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
 #define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
 #define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
 #define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
 #define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
 #define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
 #define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
 #define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
 #define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
 #define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
 #define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
 #define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
 #define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
 #define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
 #define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
 #define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
 #define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
 #define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
 #define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
 #define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
 #define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
 #define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
 #define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
 #define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
 #define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
 #define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
 #define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
 #define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
 #define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
 #define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
 #define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
 #define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
 #define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
 #define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
 #define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
 #define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
 #define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
 #define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
 #define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
 #define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
 #define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
 #define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
 #define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
 #define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
 #define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
 #define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
 #define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
 #define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
 #define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
 #define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
 #define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
 #define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
 #define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
 #define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
 #define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
 #define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
 #define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
 #define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
 #define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
 #define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
 #define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
 #define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
 #define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
 #define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
 #define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
 #define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
 #define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
 #define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
 #define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
 #define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
 #define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
 #define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
 #define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
 #define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
 #define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
 #define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
 #define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
 #define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
 #define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
 #define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
 #define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
 #define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
 #define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
 #define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
 #define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
 #define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
 #define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
 #define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
 #define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
 #define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
 #define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
 #define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
 #define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
 #define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
 #define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
 #define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
 #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
 #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
 #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
 #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
 #define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
 #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
 #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
 #define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
 #define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
 #define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
 #define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
 #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
 #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
 #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
 #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
 #define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
 #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
 #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
 #define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
 #define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
 #define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
 #define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
 #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
 #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
 #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
 #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
 #define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
 #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
 #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
 #define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
 #define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
 #define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
 #define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
 #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
 #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
 #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
 #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
 #define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
 #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
 #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
 #define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
 #define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
 #define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
 #define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
 #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
 #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
 #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
 #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
 #define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
 #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
 #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
 #define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
 #define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
 #define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
 #define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
 #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
 #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
 #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
 #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
 #define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
 #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
 #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
 #define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
 #define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
 #define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
 #define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
 #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
 #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
 #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
 #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
 #define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
 #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
 #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
 #define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
 #define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
 #define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
 #define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
 #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
 #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
 #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
 #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
 #define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
 #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
 #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
 #define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
 #define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
 #define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
 #define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
 #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
 #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
 #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
 #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
 #define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
 #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
 #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
 #define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
 #define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
 #define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
 #define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
 #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
 #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
 #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
 #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
 #define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
 #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
 #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
 #define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
 #define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
 #define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
 #define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
 #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
 #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
 #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
 #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
 #define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
 #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
 #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
 #define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
 #define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
 #define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
 #define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
 #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
 #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
 #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
 #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
 #define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
 #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
 #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
 #define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
 #define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
 #define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
 #define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
 #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
 #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
 #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
 #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
 #define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
 #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
 #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
 #define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
 #define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
 #define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
 #define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
 #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
 #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
 #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
 #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
 #define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
 #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
 #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
 #define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
 #define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
 #define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
 #define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
 #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
 #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
 #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
 #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
 #define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
 #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
 #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
 #define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
 #define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
 #define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
 #define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
 #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
 #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
 #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
 #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
 #define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
 #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
 #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
 #define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
 #define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
 #define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
 #define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
 #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
 #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
 #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
 #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
 #define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
 #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
 #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
 #define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
 #define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
 #define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
 #define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
 #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
 #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
 #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
 #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
 #define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
 #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
 #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
 #define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
 #define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
 #define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
 #define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
 #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
 #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
 #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
 #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
 #define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
 #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
 #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
 #define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
 #define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
 #define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
 #define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
 #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
 #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
 #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
 #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
 #define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
 #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
 #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
 #define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
 #define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
 #define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
 #define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
 #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
 #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
 #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
 #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
 #define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
 #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
 #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
 #define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
 #define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
 #define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
 #define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
 #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
 #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
 #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
 #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
 #define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
 #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
 #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
 #define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
 #define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
 #define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
 #define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
 #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
 #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
 #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
 #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
 #define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
 #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
 #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
 #define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
 #define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
 #define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
 #define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
 #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
 #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
 #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
 #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
 #define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
 #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
 #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
 #define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
 #define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
 #define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
 #define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
 #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
 #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
 #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
 #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
 #define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
 #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
 #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
 #define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
 #define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
 #define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
 #define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
 #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
 #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
 #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
 #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
 #define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
 #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
 #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
 #define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
 #define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
 #define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
 #define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
 #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
 #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
 #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
 #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
 #define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
 #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
 #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
 #define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
 #define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
 #define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
 #define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
 #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
 #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
 #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
 #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
 #define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
 #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
 #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
 #define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
 #define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
 #define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
 #define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
 #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
 #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
 #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
 #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
 #define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
 #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
 #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
 #define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
 #define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
 #define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
 #define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
 #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
 #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
 #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
 #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
 #define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
 #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
 #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
 #define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
 #define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
 #define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
 #define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
 #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
 #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
 #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
 #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
 #define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
 #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
 #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
 #define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
 #define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
 #define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
 #define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
 #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
 #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
 #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
 #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
 #define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
 #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
 #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
 #define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
 #define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
 #define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
 #define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
 #define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
 #define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
 #define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
 #define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
 #define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
 #define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
 #define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
 #define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
 #define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
 #define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
 #define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
 #define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
 #define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
 #define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
 #define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
 #define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
 #define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
 #define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
 #define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
 #define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
 #define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
 #define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
 #define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
 #define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
 #define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
 #define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
 #define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
 #define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
 #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
 #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
 #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
 #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
 #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
 #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
 #define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
 #define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
 #define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
 #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
 #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
 #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
 #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
 #define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
 #define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
 #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
 #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
 #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
 #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
 #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
 #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
 #define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
 #define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
 #define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
 #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
 #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
 #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
 #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
 #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
 #define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
 #define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
 #define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
 #define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
 #define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
 #define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
 #define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
 #define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
 #define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
 #define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
 #define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
 #define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
 #define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
 #define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
 #define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
 #define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
 #define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
 #define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
 #define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
 #define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
 #define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
 #define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
 #define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
 #define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
 #define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
 #define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
 #define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
 #define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
 #define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
 #define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
 #define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
 #define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
 #define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
 #define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
 #define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
 #define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
 #define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
 #define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
 #define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
 #define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
 #define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
 #define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
 #define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
 #define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
 #define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
 #define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
 #define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
 #define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
 #define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
 #define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
 #define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
 #define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
 #define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
 #define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
 #define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
 #define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
 #define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
 #define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
 #define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
 #define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
 #define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
 #define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
 #define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
 #define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
 #define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
 #define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
 #define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
 #define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
 #define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
index e0f76ae..782822a 100644
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h
@@ -6,3609 +6,2406 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF547_extended__
 
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
 #define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
 #define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
 #define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
 #define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
 #define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
 #define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
 #define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
 #define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
 #define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
 #define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
 #define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
 #define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
 #define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
 #define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
 #define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
 #define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
 #define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
 #define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
 #define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
 #define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
 #define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 #define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 #define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 #define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 #define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 #define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 #define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 #define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 #define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 #define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 #define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 #define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 #define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 #define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 #define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 #define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 #define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 #define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 #define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 #define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 #define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 #define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 #define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 #define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 #define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 #define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 #define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 #define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 #define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 #define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 #define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 #define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 #define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 #define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 #define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 #define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 #define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 #define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 #define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 #define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 #define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 #define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 #define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 #define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 #define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 #define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 #define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 #define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 #define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 #define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 #define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 #define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 #define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 #define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 #define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 #define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 #define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 #define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 #define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 #define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 #define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 #define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 #define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 #define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 #define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 #define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 #define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 #define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 #define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 #define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 #define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 #define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 #define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 #define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 #define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 #define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 #define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 #define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 #define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 #define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 #define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 #define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 #define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 #define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 #define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 #define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 #define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 #define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 #define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 #define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 #define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 #define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 #define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 #define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 #define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 #define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 #define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 #define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 #define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 #define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 #define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 #define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 #define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 #define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 #define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 #define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 #define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 #define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 #define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 #define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 #define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 #define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 #define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 #define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 #define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 #define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 #define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 #define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 #define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 #define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 #define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 #define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 #define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 #define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 #define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 #define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 #define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 #define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
 #define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
 #define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
 #define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
 #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
 #define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
 #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
 #define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
 #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
 #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
 #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
 #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
 #define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
 #define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
 #define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
 #define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
 #define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
 #define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
 #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
 #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
 #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
 #define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
 #define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
 #define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
 #define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
 #define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
 #define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
 #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
 #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
 #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
 #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
 #define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
 #define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
 #define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
 #define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
 #define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
 #define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
 #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
 #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
 #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
 #define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
 #define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
 #define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
 #define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
 #define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
 #define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
 #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
 #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
 #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
 #define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
 #define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
 #define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
 #define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
 #define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
 #define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
 #define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
 #define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
 #define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
 #define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
 #define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
 #define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
 #define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
 #define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
 #define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
 #define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
 #define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
 #define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
 #define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
 #define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
 #define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
 #define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
 #define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
 #define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
 #define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
 #define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
 #define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
 #define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
 #define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
 #define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
 #define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
 #define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
 #define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
 #define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
 #define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
 #define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
 #define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
 #define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
 #define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
 #define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
 #define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
 #define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
 #define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
 #define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
 #define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
 #define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
 #define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
 #define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
 #define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
 #define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
 #define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
 #define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
 #define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
 #define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
 #define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
 #define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
 #define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
 #define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
 #define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
 #define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
 #define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
 #define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
 #define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
 #define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
 #define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
 #define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
 #define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
 #define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
 #define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
 #define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
 #define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
 #define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
 #define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
 #define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
 #define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
 #define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
 #define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
 #define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
 #define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
 #define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
 #define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
 #define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
 #define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
 #define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
 #define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
 #define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
 #define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
 #define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
 #define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
 #define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
 #define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
 #define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
 #define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
 #define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
 #define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
 #define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
 #define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
 #define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
 #define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
 #define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
 #define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
 #define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
 #define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
 #define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
 #define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
 #define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
 #define bfin_read_PORTA()              bfin_read16(PORTA)
 #define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
 #define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
 #define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
 #define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
 #define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
 #define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
 #define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
 #define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
 #define bfin_read_PORTB()              bfin_read16(PORTB)
 #define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
 #define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
 #define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
 #define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
 #define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
 #define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
 #define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
 #define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
 #define bfin_read_PORTC()              bfin_read16(PORTC)
 #define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
 #define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
 #define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
 #define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
 #define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
 #define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
 #define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
 #define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
 #define bfin_read_PORTD()              bfin_read16(PORTD)
 #define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
 #define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
 #define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
 #define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
 #define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
 #define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
 #define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
 #define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
 #define bfin_read_PORTE()              bfin_read16(PORTE)
 #define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
 #define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
 #define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
 #define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
 #define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
 #define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
 #define bfin_read_PORTF()              bfin_read16(PORTF)
 #define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
 #define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
 #define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
 #define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
 #define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
 #define bfin_read_PORTG()              bfin_read16(PORTG)
 #define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
 #define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
 #define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
 #define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
 #define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
 #define bfin_read_PORTH()              bfin_read16(PORTH)
 #define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
 #define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
 #define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
 #define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
 #define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
 #define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
 #define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
 #define bfin_read_PORTI()              bfin_read16(PORTI)
 #define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
 #define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
 #define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
 #define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
 #define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
 #define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
 #define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
 #define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
 #define bfin_read_PORTJ()              bfin_read16(PORTJ)
 #define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
 #define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
 #define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
 #define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
 #define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
 #define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
 #define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
 #define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
 #define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
 #define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
 #define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
 #define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
 #define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 #define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
 #define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
 #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
 #define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
 #define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
 #define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
 #define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
 #define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
 #define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
 #define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
 #define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
 #define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
 #define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 #define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
 #define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
 #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
 #define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
 #define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
 #define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
 #define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
 #define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
 #define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
 #define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
 #define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
 #define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
 #define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 #define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
 #define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
 #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
 #define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
 #define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
 #define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
 #define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
 #define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
 #define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
 #define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
 #define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
 #define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
 #define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 #define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
 #define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
 #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
 #define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
 #define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
 #define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
 #define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
 #define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
 #define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
 #define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
 #define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
 #define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
 #define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
 #define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
 #define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
 #define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
 #define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
 #define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
 #define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
 #define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
 #define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
 #define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
 #define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
 #define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
 #define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
 #define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
 #define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
 #define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
 #define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
 #define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
 #define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
 #define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
 #define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
 #define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
 #define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
 #define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
 #define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
 #define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
 #define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
 #define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
 #define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
 #define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
 #define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
 #define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
 #define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
 #define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
 #define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
 #define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
 #define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
 #define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
 #define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
 #define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
 #define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
 #define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
 #define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
 #define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
 #define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
 #define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
 #define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
 #define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
 #define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
 #define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
 #define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
 #define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
 #define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
 #define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
 #define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
 #define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
 #define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
 #define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
 #define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
 #define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
 #define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
 #define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
 #define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
 #define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
 #define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
 #define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
 #define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
 #define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
 #define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
 #define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
 #define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
 #define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
 #define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
 #define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
 #define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
 #define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
 #define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
 #define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
 #define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
 #define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
 #define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
 #define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
 #define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
 #define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
 #define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
 #define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
 #define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
 #define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
 #define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
 #define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
 #define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
 #define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
 #define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
 #define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
 #define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
 #define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
 #define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
 #define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
 #define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
 #define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
 #define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
 #define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
 #define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
 #define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
 #define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
 #define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
 #define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
 #define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
 #define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
 #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
 #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
 #define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
 #define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
 #define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
 #define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
 #define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
 #define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
 #define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
 #define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
 #define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
 #define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
 #define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
 #define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
 #define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
 #define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
 #define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
 #define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
 #define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
 #define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
 #define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
 #define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
 #define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
 #define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
 #define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
 #define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
 #define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
 #define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
 #define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
 #define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
 #define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
 #define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
 #define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
 #define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
 #define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
 #define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
 #define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
 #define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
 #define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
 #define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
 #define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
 #define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
 #define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
 #define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
 #define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
 #define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
 #define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 #define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
 #define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
 #define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
 #define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
 #define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
 #define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
 #define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
 #define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
 #define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
 #define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
 #define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
 #define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
 #define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
 #define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
 #define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
 #define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
 #define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
 #define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
 #define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
 #define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
 #define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 #define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
 #define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
 #define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
 #define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
 #define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
 #define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
 #define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
 #define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
 #define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
 #define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
 #define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
 #define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
 #define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
 #define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
 #define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
 #define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
 #define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
 #define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
 #define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
 #define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
 #define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
 #define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
 #define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
 #define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
 #define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
 #define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
 #define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
 #define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
 #define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
 #define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
 #define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
 #define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
 #define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
 #define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
 #define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
 #define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
 #define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
 #define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
 #define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
 #define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
 #define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
 #define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
 #define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
 #define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
 #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
 #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
 #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
 #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
 #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
 #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
 #define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
 #define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
 #define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
 #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
 #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
 #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
 #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
 #define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
 #define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
 #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
 #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
 #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
 #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
 #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
 #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
 #define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
 #define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
 #define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
 #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
 #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
 #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
 #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
 #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
 #define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
 #define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
 #define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
 #define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
 #define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
 #define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
 #define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
 #define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
 #define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
 #define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
 #define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
 #define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
 #define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
 #define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
 #define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
 #define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
 #define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
 #define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
 #define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
 #define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
 #define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
 #define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
 #define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
 #define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
 #define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
 #define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
 #define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
 #define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
 #define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
 #define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
 #define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
 #define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
 #define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
 #define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
 #define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
 #define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
 #define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
 #define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
 #define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
 #define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
 #define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
 #define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
 #define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
 #define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
 #define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
 #define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
 #define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
 #define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
 #define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
 #define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
 #define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
 #define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
 #define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
 #define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
 #define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
 #define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
 #define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
 #define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
 #define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
 #define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
 #define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
 #define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
 #define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
 #define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
 #define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
 #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
 #define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
 #define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
 #define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
 #define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
 #define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
 #define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
 #define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
 #define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
 #define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
 #define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
 #define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
 #define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
 #define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
 #define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
 #define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
 #define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
 #define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
 #define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
 #define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
 #define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
 #define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
 #define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
 #define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
index caf2f6f..af59606 100644
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h
@@ -6,5781 +6,3854 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF548_extended__
 
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
 #define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
 #define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
 #define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
 #define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
 #define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
 #define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
 #define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
 #define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
 #define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
 #define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
 #define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
 #define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
 #define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
 #define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
 #define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
 #define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
 #define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
 #define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
 #define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
 #define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
 #define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 #define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 #define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 #define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 #define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 #define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 #define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 #define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 #define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 #define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 #define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 #define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 #define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 #define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 #define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 #define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 #define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 #define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 #define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 #define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 #define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 #define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 #define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 #define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 #define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 #define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 #define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 #define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 #define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 #define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 #define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 #define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 #define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 #define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 #define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 #define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 #define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 #define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 #define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 #define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 #define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 #define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 #define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 #define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 #define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 #define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 #define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 #define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 #define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 #define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 #define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 #define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 #define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 #define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 #define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 #define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 #define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 #define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 #define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 #define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 #define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 #define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 #define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 #define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 #define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 #define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 #define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 #define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 #define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 #define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 #define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 #define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 #define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 #define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 #define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 #define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 #define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 #define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 #define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 #define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 #define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 #define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 #define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 #define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 #define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 #define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 #define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 #define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 #define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 #define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 #define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 #define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 #define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 #define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 #define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 #define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 #define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 #define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 #define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 #define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 #define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 #define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 #define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 #define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 #define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 #define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 #define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 #define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 #define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 #define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 #define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 #define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 #define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 #define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 #define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 #define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 #define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 #define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 #define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 #define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 #define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 #define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 #define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 #define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 #define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 #define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 #define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 #define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
 #define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
 #define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
 #define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
 #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
 #define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
 #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
 #define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
 #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
 #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
 #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
 #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
 #define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
 #define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
 #define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
 #define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
 #define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
 #define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
 #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
 #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
 #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
 #define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
 #define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
 #define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
 #define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
 #define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
 #define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
 #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
 #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
 #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
 #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
 #define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
 #define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
 #define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
 #define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
 #define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
 #define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
 #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
 #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
 #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
 #define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
 #define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
 #define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
 #define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
 #define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
 #define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
 #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
 #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
 #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
 #define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
 #define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
 #define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
 #define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
 #define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
 #define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
 #define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
 #define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
 #define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
 #define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
 #define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
 #define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
 #define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
 #define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
 #define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
 #define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
 #define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
 #define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
 #define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
 #define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
 #define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
 #define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
 #define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
 #define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
 #define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
 #define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
 #define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
 #define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
 #define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
 #define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
 #define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
 #define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
 #define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
 #define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
 #define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
 #define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
 #define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
 #define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
 #define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
 #define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
 #define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
 #define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
 #define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
 #define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
 #define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
 #define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
 #define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
 #define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
 #define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
 #define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
 #define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
 #define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
 #define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
 #define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
 #define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
 #define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
 #define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
 #define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
 #define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
 #define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
 #define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
 #define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
 #define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
 #define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
 #define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
 #define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
 #define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
 #define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
 #define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
 #define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
 #define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
 #define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
 #define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
 #define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
 #define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
 #define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
 #define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
 #define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
 #define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
 #define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
 #define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
 #define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
 #define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
 #define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
 #define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
 #define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
 #define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
 #define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
 #define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
 #define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
 #define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
 #define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
 #define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
 #define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
 #define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
 #define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
 #define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
 #define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
 #define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
 #define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
 #define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
 #define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
 #define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
 #define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
 #define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
 #define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
 #define bfin_read_PORTA()              bfin_read16(PORTA)
 #define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
 #define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
 #define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
 #define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
 #define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
 #define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
 #define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
 #define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
 #define bfin_read_PORTB()              bfin_read16(PORTB)
 #define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
 #define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
 #define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
 #define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
 #define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
 #define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
 #define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
 #define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
 #define bfin_read_PORTC()              bfin_read16(PORTC)
 #define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
 #define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
 #define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
 #define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
 #define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
 #define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
 #define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
 #define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
 #define bfin_read_PORTD()              bfin_read16(PORTD)
 #define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
 #define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
 #define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
 #define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
 #define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
 #define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
 #define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
 #define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
 #define bfin_read_PORTE()              bfin_read16(PORTE)
 #define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
 #define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
 #define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
 #define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
 #define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
 #define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
 #define bfin_read_PORTF()              bfin_read16(PORTF)
 #define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
 #define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
 #define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
 #define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
 #define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
 #define bfin_read_PORTG()              bfin_read16(PORTG)
 #define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
 #define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
 #define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
 #define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
 #define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
 #define bfin_read_PORTH()              bfin_read16(PORTH)
 #define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
 #define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
 #define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
 #define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
 #define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
 #define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
 #define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
 #define bfin_read_PORTI()              bfin_read16(PORTI)
 #define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
 #define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
 #define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
 #define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
 #define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
 #define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
 #define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
 #define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
 #define bfin_read_PORTJ()              bfin_read16(PORTJ)
 #define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
 #define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
 #define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
 #define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
 #define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
 #define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
 #define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
 #define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
 #define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
 #define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
 #define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
 #define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
 #define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 #define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
 #define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
 #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
 #define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
 #define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
 #define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
 #define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
 #define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
 #define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
 #define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
 #define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
 #define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
 #define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 #define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
 #define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
 #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
 #define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
 #define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
 #define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
 #define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
 #define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
 #define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
 #define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
 #define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
 #define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
 #define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 #define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
 #define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
 #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
 #define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
 #define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
 #define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
 #define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
 #define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
 #define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
 #define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
 #define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
 #define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
 #define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 #define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
 #define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
 #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
 #define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
 #define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
 #define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
 #define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
 #define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
 #define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
 #define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
 #define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
 #define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
 #define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
 #define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
 #define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
 #define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
 #define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
 #define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
 #define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
 #define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
 #define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
 #define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
 #define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
 #define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
 #define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
 #define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
 #define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
 #define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
 #define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
 #define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
 #define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
 #define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
 #define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
 #define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
 #define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
 #define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
 #define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
 #define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
 #define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
 #define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
 #define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
 #define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
 #define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
 #define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
 #define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
 #define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
 #define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
 #define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
 #define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
 #define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
 #define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
 #define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
 #define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
 #define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
 #define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
 #define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
 #define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
 #define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
 #define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
 #define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
 #define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
 #define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
 #define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
 #define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
 #define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
 #define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
 #define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
 #define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
 #define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
 #define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
 #define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
 #define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
 #define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
 #define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
 #define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
 #define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
 #define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
 #define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
 #define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
 #define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
 #define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
 #define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
 #define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
 #define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
 #define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
 #define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
 #define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
 #define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
 #define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
 #define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
 #define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
 #define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
 #define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
 #define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
 #define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
 #define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
 #define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
 #define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
 #define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
 #define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
 #define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
 #define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
 #define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
 #define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
 #define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
 #define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
 #define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
 #define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
 #define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
 #define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
 #define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
 #define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
 #define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
 #define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
 #define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
 #define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
 #define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
 #define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
 #define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
 #define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
 #define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
 #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
 #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
 #define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
 #define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
 #define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
 #define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
 #define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
 #define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
 #define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
 #define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
 #define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
 #define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
 #define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
 #define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
 #define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
 #define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
 #define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
 #define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
 #define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
 #define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
 #define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
 #define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
 #define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
 #define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
 #define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
 #define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
 #define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
 #define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
 #define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
 #define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
 #define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
 #define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
 #define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
 #define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
 #define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
 #define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
 #define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
 #define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
 #define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
 #define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
 #define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
 #define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
 #define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
 #define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
 #define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
 #define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
 #define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 #define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
 #define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
 #define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
 #define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
 #define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
 #define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
 #define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
 #define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
 #define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
 #define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
 #define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
 #define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
 #define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
 #define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
 #define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
 #define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
 #define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
 #define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
 #define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
 #define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
 #define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 #define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
 #define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
 #define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
 #define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
 #define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
 #define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
 #define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
 #define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
 #define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
 #define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
 #define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
 #define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
 #define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
 #define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
 #define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
 #define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
 #define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
 #define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
 #define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
 #define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
 #define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
 #define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
 #define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
 #define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
 #define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
 #define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
 #define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
 #define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
 #define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
 #define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
 #define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
 #define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
 #define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
 #define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
 #define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
 #define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
 #define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
 #define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
 #define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
 #define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
 #define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
 #define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
 #define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
 #define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
 #define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
 #define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
 #define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
 #define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
 #define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
 #define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
 #define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
 #define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
 #define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
 #define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
 #define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
 #define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
 #define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
 #define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
 #define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
 #define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
 #define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
 #define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
 #define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
 #define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
 #define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
 #define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
 #define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
 #define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
 #define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
 #define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
 #define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
 #define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
 #define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
 #define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
 #define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
 #define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
 #define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
 #define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
 #define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
 #define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
 #define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
 #define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
 #define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
 #define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
 #define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
 #define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
 #define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
 #define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
 #define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
 #define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
 #define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
 #define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
 #define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
 #define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
 #define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
 #define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
 #define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
 #define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
 #define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
 #define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
 #define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
 #define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
 #define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
 #define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
 #define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
 #define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
 #define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
 #define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
 #define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
 #define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
 #define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
 #define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
 #define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
 #define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
 #define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
 #define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
 #define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
 #define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
 #define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
 #define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
 #define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
 #define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
 #define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
 #define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
 #define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
 #define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
 #define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
 #define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
 #define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
 #define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
 #define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
 #define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
 #define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
 #define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
 #define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
 #define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
 #define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
 #define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
 #define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
 #define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
 #define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
 #define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
 #define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
 #define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
 #define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
 #define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
 #define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
 #define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
 #define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
 #define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
 #define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
 #define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
 #define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
 #define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
 #define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
 #define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
 #define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
 #define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
 #define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
 #define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
 #define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
 #define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
 #define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
 #define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
 #define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
 #define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
 #define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
 #define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
 #define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
 #define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
 #define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
 #define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
 #define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
 #define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
 #define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
 #define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
 #define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
 #define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
 #define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
 #define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
 #define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
 #define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
 #define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
 #define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
 #define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
 #define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
 #define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
 #define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
 #define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
 #define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
 #define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
 #define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
 #define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
 #define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
 #define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
 #define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
 #define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
 #define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
 #define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
 #define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
 #define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
 #define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
 #define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
 #define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
 #define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
 #define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
 #define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
 #define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
 #define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
 #define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
 #define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
 #define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
 #define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
 #define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
 #define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
 #define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
 #define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
 #define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
 #define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
 #define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
 #define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
 #define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
 #define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
 #define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
 #define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
 #define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
 #define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
 #define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
 #define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
 #define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
 #define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
 #define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
 #define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
 #define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
 #define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
 #define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
 #define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
 #define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
 #define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
 #define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
 #define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
 #define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
 #define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
 #define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
 #define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
 #define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
 #define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
 #define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
 #define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
 #define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
 #define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
 #define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
 #define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
 #define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
 #define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
 #define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
 #define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
 #define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
 #define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
 #define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
 #define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
 #define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
 #define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
 #define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
 #define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
 #define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
 #define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
 #define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
 #define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
 #define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
 #define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
 #define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
 #define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
 #define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
 #define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
 #define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
 #define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
 #define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
 #define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
 #define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
 #define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
 #define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
 #define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
 #define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
 #define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
 #define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
 #define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
 #define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
 #define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
 #define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
 #define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
 #define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
 #define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
 #define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
 #define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
 #define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
 #define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
 #define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
 #define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
 #define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
 #define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
 #define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
 #define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
 #define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
 #define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
 #define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
 #define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
 #define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
 #define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
 #define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
 #define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
 #define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
 #define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
 #define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
 #define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
 #define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
 #define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
 #define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
 #define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
 #define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
 #define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
 #define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
 #define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
 #define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
 #define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
 #define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
 #define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
 #define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
 #define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
 #define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
 #define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
 #define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
 #define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
 #define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
 #define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
 #define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
 #define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
 #define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
 #define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
 #define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
 #define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
 #define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
 #define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
 #define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
 #define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
 #define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
 #define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
 #define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
 #define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
 #define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
 #define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
 #define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
 #define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
 #define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
 #define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
 #define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
 #define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
 #define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
 #define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
 #define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
 #define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
 #define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
 #define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
 #define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
 #define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
 #define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
 #define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
 #define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
 #define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
 #define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
 #define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
 #define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
 #define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
 #define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
 #define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
 #define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
 #define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
 #define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
 #define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
 #define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
 #define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
 #define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
 #define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
 #define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
 #define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
 #define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
 #define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
 #define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
 #define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
 #define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
 #define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
 #define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
 #define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
 #define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
 #define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
 #define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
 #define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
 #define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
 #define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
 #define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
 #define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
 #define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
 #define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
 #define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
 #define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
 #define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
 #define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
 #define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
 #define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
 #define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
 #define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
 #define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
 #define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
 #define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
 #define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
 #define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
 #define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
 #define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
 #define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
 #define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
 #define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
 #define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
 #define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
 #define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
 #define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
 #define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
 #define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
 #define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
 #define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
 #define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
 #define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
 #define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
 #define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
 #define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
 #define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
 #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
 #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
 #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
 #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
 #define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
 #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
 #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
 #define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
 #define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
 #define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
 #define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
 #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
 #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
 #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
 #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
 #define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
 #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
 #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
 #define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
 #define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
 #define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
 #define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
 #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
 #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
 #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
 #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
 #define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
 #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
 #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
 #define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
 #define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
 #define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
 #define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
 #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
 #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
 #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
 #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
 #define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
 #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
 #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
 #define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
 #define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
 #define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
 #define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
 #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
 #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
 #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
 #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
 #define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
 #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
 #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
 #define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
 #define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
 #define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
 #define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
 #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
 #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
 #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
 #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
 #define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
 #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
 #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
 #define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
 #define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
 #define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
 #define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
 #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
 #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
 #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
 #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
 #define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
 #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
 #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
 #define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
 #define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
 #define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
 #define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
 #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
 #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
 #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
 #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
 #define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
 #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
 #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
 #define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
 #define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
 #define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
 #define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
 #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
 #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
 #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
 #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
 #define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
 #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
 #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
 #define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
 #define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
 #define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
 #define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
 #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
 #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
 #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
 #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
 #define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
 #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
 #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
 #define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
 #define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
 #define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
 #define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
 #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
 #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
 #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
 #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
 #define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
 #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
 #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
 #define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
 #define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
 #define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
 #define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
 #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
 #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
 #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
 #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
 #define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
 #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
 #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
 #define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
 #define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
 #define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
 #define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
 #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
 #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
 #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
 #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
 #define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
 #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
 #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
 #define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
 #define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
 #define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
 #define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
 #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
 #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
 #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
 #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
 #define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
 #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
 #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
 #define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
 #define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
 #define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
 #define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
 #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
 #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
 #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
 #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
 #define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
 #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
 #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
 #define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
 #define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
 #define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
 #define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
 #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
 #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
 #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
 #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
 #define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
 #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
 #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
 #define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
 #define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
 #define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
 #define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
 #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
 #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
 #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
 #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
 #define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
 #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
 #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
 #define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
 #define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
 #define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
 #define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
 #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
 #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
 #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
 #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
 #define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
 #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
 #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
 #define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
 #define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
 #define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
 #define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
 #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
 #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
 #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
 #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
 #define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
 #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
 #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
 #define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
 #define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
 #define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
 #define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
 #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
 #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
 #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
 #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
 #define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
 #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
 #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
 #define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
 #define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
 #define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
 #define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
 #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
 #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
 #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
 #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
 #define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
 #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
 #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
 #define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
 #define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
 #define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
 #define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
 #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
 #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
 #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
 #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
 #define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
 #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
 #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
 #define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
 #define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
 #define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
 #define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
 #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
 #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
 #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
 #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
 #define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
 #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
 #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
 #define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
 #define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
 #define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
 #define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
 #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
 #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
 #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
 #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
 #define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
 #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
 #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
 #define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
 #define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
 #define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
 #define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
 #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
 #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
 #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
 #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
 #define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
 #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
 #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
 #define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
 #define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
 #define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
 #define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
 #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
 #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
 #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
 #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
 #define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
 #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
 #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
 #define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
 #define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
 #define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
 #define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
 #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
 #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
 #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
 #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
 #define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
 #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
 #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
 #define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
 #define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
 #define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
 #define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
 #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
 #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
 #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
 #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
 #define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
 #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
 #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
 #define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
 #define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
 #define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
 #define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
 #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
 #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
 #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
 #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
 #define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
 #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
 #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
 #define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
 #define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
 #define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
 #define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
 #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
 #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
 #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
 #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
 #define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
 #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
 #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
 #define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
 #define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
 #define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
 #define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
 #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
 #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
 #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
 #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
 #define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
 #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
 #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
 #define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
 #define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
 #define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
 #define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
 #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
 #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
 #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
 #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
 #define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
 #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
 #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
 #define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
 #define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
 #define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
 #define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
 #define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
 #define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
 #define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
 #define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
 #define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
 #define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
 #define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
 #define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
 #define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
 #define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
 #define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
 #define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
 #define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
 #define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
 #define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
 #define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
 #define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
 #define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
 #define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
 #define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
 #define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
 #define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
 #define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
 #define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
 #define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
 #define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
 #define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
 #define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
 #define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
 #define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
 #define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
 #define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
 #define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
 #define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
 #define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
 #define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
 #define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
 #define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
 #define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
 #define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
 #define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
 #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
 #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
 #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
 #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
 #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
 #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
 #define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
 #define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
 #define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
 #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
 #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
 #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
 #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
 #define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
 #define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
 #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
 #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
 #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
 #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
 #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
 #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
 #define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
 #define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
 #define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
 #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
 #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
 #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
 #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
 #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
 #define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
 #define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
 #define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
 #define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
 #define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
 #define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
 #define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
 #define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
 #define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
 #define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
 #define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
 #define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
 #define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
 #define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
 #define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
 #define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
 #define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
 #define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
 #define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
 #define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
 #define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
 #define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
 #define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
 #define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
 #define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
 #define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
 #define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
 #define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
 #define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
 #define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
 #define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
 #define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
 #define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
 #define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
 #define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
 #define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
 #define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
 #define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
 #define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
 #define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
 #define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
 #define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
 #define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
 #define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
 #define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
 #define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
 #define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
 #define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
 #define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
 #define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
 #define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
 #define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
 #define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
 #define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
 #define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
 #define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
 #define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
 #define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
 #define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
 #define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
 #define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
 #define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
 #define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
 #define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
 #define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
 #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
 #define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
 #define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
 #define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
 #define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
 #define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
 #define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
 #define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
 #define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
 #define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
 #define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
 #define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
 #define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
 #define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
 #define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
 #define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
 #define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
 #define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
 #define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
 #define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
 #define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
 #define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
 #define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
 #define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
index af90e4c..497b0a8 100644
--- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h
@@ -6,6129 +6,4086 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__
 #define __BFIN_CDEF_ADSP_EDN_BF549_extended__
 
-#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
 #define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
 #define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
 #define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
 #define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
 #define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
 #define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
-#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
 #define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
 #define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
 #define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
 #define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
 #define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
 #define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
-#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
 #define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
 #define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
 #define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
 #define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
 #define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
 #define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
 #define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
 #define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
 #define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
 #define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
 #define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
 #define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
 #define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
 #define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
 #define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
 #define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
-#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
 #define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
 #define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
-#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
 #define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
 #define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
-#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
 #define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
 #define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
-#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
 #define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
 #define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
-#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
 #define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
 #define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
-#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
 #define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
 #define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
-#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
 #define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
 #define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
-#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
 #define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
 #define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
-#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
 #define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
 #define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
 #define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
 #define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
 #define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
 #define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
 #define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
 #define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
 #define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
 #define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
 #define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
 #define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
 #define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
 #define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
 #define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
 #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
 #define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
 #define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
 #define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
 #define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
 #define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
 #define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
 #define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
 #define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
 #define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
 #define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
 #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
 #define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
 #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
 #define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
 #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
 #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
 #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
 #define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
 #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
 #define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
 #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
 #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
 #define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
 #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
 #define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
 #define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
 #define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
 #define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
 #define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
 #define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
 #define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
 #define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
 #define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
 #define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
 #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
 #define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
 #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
 #define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
 #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
 #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
 #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
 #define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
 #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
 #define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
 #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
 #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
 #define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
 #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
 #define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
 #define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
 #define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
 #define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
 #define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
 #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
 #define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
 #define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
 #define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
 #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
 #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
 #define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
 #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
 #define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
 #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
 #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
 #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
 #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
 #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
 #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
 #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
 #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
 #define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
 #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
 #define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
 #define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
 #define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
 #define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
 #define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
 #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
 #define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
 #define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
 #define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
 #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
 #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
 #define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
 #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
 #define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
 #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
 #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
 #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
 #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
 #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
 #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
 #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
 #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
-#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
 #define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
 #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
-#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
 #define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
 #define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
-#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
 #define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
 #define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
-#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
 #define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
 #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
-#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
 #define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
 #define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
-#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
 #define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
 #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
-#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
 #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
-#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
 #define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
 #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
-#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
 #define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
 #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
-#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
 #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
 #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
 #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
 #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
-#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
 #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
 #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
-#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
 #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
-#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
 #define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
 #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
-#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
 #define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
 #define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
-#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
 #define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
 #define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
-#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
 #define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
 #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
-#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
 #define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
 #define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
-#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
 #define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
 #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
-#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
 #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
-#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
 #define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
 #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
-#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
 #define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
 #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
-#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
 #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
 #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
 #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
 #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
-#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
 #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
 #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
-#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
 #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
-#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
 #define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
 #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
-#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
 #define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
 #define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
-#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
 #define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
 #define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
-#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
 #define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
 #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
-#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
 #define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
 #define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
-#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
 #define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
 #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
-#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
 #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
-#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
 #define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
 #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
-#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
 #define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
 #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
-#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
 #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
 #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
 #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
 #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
-#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
 #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
 #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
-#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
 #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
-#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
 #define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
 #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
-#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
 #define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
 #define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
-#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
 #define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
 #define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
-#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
 #define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
 #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
-#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
 #define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
 #define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
-#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
 #define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
 #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
-#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
 #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
-#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
 #define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
 #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
-#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
 #define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
 #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
-#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
 #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
 #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
 #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
 #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
-#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
 #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
 #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
-#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
 #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
-#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
 #define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
 #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
-#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
 #define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
 #define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
-#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
 #define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
 #define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
-#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
 #define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
 #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
-#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
 #define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
 #define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
-#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
 #define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
 #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
-#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
 #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
-#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
 #define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
 #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
-#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
 #define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
 #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
-#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
 #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
 #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
 #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
 #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
-#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
 #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
 #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
-#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
 #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
-#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
 #define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
 #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
-#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
 #define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
 #define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
-#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
 #define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
 #define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
-#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
 #define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
 #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
-#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
 #define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
 #define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
-#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
 #define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
 #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
-#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
 #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
-#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
 #define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
 #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
-#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
 #define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
 #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
-#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
 #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
 #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
 #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
 #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
-#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
 #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
 #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
-#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
 #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
-#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
 #define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
 #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
-#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
 #define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
 #define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
-#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
 #define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
 #define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
-#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
 #define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
 #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
-#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
 #define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
 #define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
-#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
 #define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
 #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
-#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
 #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
-#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
 #define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
 #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
-#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
 #define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
 #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
-#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
 #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
 #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
 #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
 #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
-#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
 #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
 #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
-#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
 #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
-#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
 #define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
 #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
-#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
 #define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
 #define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
-#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
 #define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
 #define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
-#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
 #define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
 #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
-#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
 #define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
 #define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
-#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
 #define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
 #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
-#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
 #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
-#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
 #define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
 #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
-#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
 #define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
 #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
-#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
 #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
 #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
 #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
-#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
 #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
-#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
 #define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
 #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
-#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
 #define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
 #define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
-#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
 #define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
 #define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
-#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
 #define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
 #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
-#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
 #define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
 #define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
-#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
 #define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
 #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
-#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
 #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
-#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
 #define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
 #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
-#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
 #define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
 #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
-#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
 #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
 #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
 #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
 #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
-#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
 #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
 #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
-#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
 #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
-#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
 #define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
 #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
-#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
 #define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
 #define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
-#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
 #define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
 #define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
-#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
 #define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
 #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
-#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
 #define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
 #define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
-#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
 #define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
 #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
-#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
 #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
-#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
 #define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
 #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
-#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
 #define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
 #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
-#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
 #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
 #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
 #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
 #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
-#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
 #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
 #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
-#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
 #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
-#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
 #define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
 #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
-#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
 #define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
 #define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
-#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
 #define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
 #define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
-#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
 #define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
 #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
-#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
 #define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
 #define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
-#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
 #define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
 #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
-#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
 #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
-#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
 #define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
 #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
-#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
 #define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
 #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
-#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
 #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
 #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
 #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
 #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
-#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
 #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
 #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
-#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
 #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
-#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
 #define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
 #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
-#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
 #define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
 #define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
-#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
 #define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
 #define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
-#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
 #define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
 #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
-#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
 #define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
 #define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
-#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
 #define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
 #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
-#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
 #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
-#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
 #define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
 #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
-#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
 #define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
 #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
-#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
 #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
 #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
 #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
 #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
-#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
 #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
 #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
 #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
 #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
 #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
 #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
-#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
 #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
-#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
 #define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
 #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
-#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
 #define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
 #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
-#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
 #define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
 #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
-#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
 #define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
 #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
-#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
 #define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
 #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
-#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
 #define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
-#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
 #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
 #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
 #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
 #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
 #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
-#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
 #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
-#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
 #define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
 #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
-#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
 #define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
 #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
-#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
 #define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
 #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
-#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
 #define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
 #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
-#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
 #define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
 #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
-#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
 #define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
-#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
 #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
 #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
 #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
 #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
 #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
 #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
-#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
 #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
-#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
 #define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
 #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
-#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
 #define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
 #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
-#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
 #define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
 #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
-#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
 #define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
 #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
-#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
 #define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
 #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
 #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
-#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
 #define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
-#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
 #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
 #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
 #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
 #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
 #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
 #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
 #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
-#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
 #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
-#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
 #define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
 #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
-#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
 #define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
 #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
-#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
 #define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
 #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
-#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
 #define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
 #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
-#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
 #define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
 #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
 #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
-#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
 #define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
-#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
 #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
 #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
 #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
 #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
 #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
 #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
 #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
 #define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
 #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
 #define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
 #define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
 #define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
 #define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
 #define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
 #define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
 #define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
 #define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
 #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
 #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
 #define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
 #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
 #define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
 #define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
 #define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
 #define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
 #define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
 #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
 #define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
 #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
 #define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
 #define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
 #define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
 #define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
 #define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
-#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
 #define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
 #define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
-#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
 #define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
 #define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
-#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
 #define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
 #define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
-#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
 #define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
 #define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
-#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
 #define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
 #define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
-#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
 #define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
 #define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
-#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
 #define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
 #define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
-#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
 #define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
 #define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
-#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
 #define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
 #define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
-#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
 #define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
 #define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
-#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
 #define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
 #define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
-#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
 #define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
 #define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
-#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
 #define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
 #define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
-#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
 #define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
 #define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
-#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
 #define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
 #define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
-#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
 #define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
 #define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
-#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
 #define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
 #define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
-#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
 #define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
 #define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
-#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
 #define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
 #define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
-#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
 #define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
 #define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
-#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
 #define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
 #define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
-#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
 #define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
 #define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
-#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
 #define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
 #define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
-#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
 #define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
 #define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
-#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
 #define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
 #define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
-#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
 #define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
 #define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
-#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
 #define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
 #define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
-#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
 #define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
 #define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
-#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
 #define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
 #define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
-#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
 #define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
 #define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
-#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
 #define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
 #define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
-#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
 #define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
 #define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
-#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
 #define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
 #define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
-#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
 #define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
 #define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
-#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
 #define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
 #define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
-#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
 #define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
 #define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
-#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
 #define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
 #define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
-#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
 #define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
 #define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
-#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
 #define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
 #define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
-#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
 #define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
-#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
 #define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
-#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
 #define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
-#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
 #define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
 #define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
-#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
 #define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
 #define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
-#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
 #define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
-#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
 #define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
-#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
 #define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
-#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
 #define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
 #define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
-#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
 #define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
 #define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
-#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
 #define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
 #define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
-#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
 #define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
 #define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
-#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
 #define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
 #define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
-#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
 #define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
 #define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
-#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
 #define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
 #define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
-#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
 #define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
 #define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
-#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
 #define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
 #define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
 #define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
 #define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
 #define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
 #define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
 #define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
 #define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
-#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
 #define bfin_read_PORTA()              bfin_read16(PORTA)
 #define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
-#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
 #define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
-#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
 #define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
-#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
 #define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
-#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
 #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
 #define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
-#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
 #define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
-#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
 #define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
 #define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
-#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
 #define bfin_read_PORTB()              bfin_read16(PORTB)
 #define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
-#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
 #define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
-#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
 #define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
-#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
 #define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
-#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
 #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
 #define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
-#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
 #define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
-#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
 #define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
 #define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
-#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
 #define bfin_read_PORTC()              bfin_read16(PORTC)
 #define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
-#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
 #define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
-#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
 #define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
-#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
 #define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
-#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
 #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
 #define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
-#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
 #define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
-#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
 #define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
 #define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
-#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
 #define bfin_read_PORTD()              bfin_read16(PORTD)
 #define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
-#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
 #define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
-#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
 #define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
-#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
 #define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
-#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
 #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
 #define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
-#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
 #define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
-#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
 #define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
 #define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
-#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
 #define bfin_read_PORTE()              bfin_read16(PORTE)
 #define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
-#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
 #define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
-#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
 #define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
-#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
 #define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
-#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
 #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
 #define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
-#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
 #define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
-#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
 #define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
 #define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
 #define bfin_read_PORTF()              bfin_read16(PORTF)
 #define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
-#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
 #define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
-#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
 #define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
-#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
 #define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
-#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
 #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
 #define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
-#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
 #define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
-#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
 #define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
 #define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
 #define bfin_read_PORTG()              bfin_read16(PORTG)
 #define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
-#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
 #define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
-#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
 #define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
-#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
 #define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
-#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
 #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
 #define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
-#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
 #define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
-#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
 #define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
 #define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
 #define bfin_read_PORTH()              bfin_read16(PORTH)
 #define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
-#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
 #define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
-#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
 #define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
-#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
 #define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
-#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
 #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
 #define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
-#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
 #define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
-#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
 #define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
 #define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
-#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
 #define bfin_read_PORTI()              bfin_read16(PORTI)
 #define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
-#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
 #define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
-#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
 #define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
-#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
 #define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
-#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
 #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
 #define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
-#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
 #define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
-#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
 #define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
 #define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
-#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
 #define bfin_read_PORTJ()              bfin_read16(PORTJ)
 #define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
-#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
 #define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
 #define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
-#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
 #define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
 #define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
-#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
 #define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
 #define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
-#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
 #define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
 #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
 #define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
 #define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
-#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
 #define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
 #define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
-#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
 #define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
-#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
 #define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
-#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
 #define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
 #define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
-#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
 #define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
 #define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
-#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
 #define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
-#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
 #define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
-#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
 #define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
-#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
 #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
-#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
 #define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
-#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
 #define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
 #define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
-#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
 #define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
-#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
 #define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
-#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
 #define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
 #define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
-#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
 #define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
 #define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
-#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
 #define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
-#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
 #define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
-#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
 #define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
-#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
 #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
-#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
 #define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
-#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
 #define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
 #define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
-#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
 #define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
-#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
 #define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
-#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
 #define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
 #define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
-#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
 #define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
 #define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
-#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
 #define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
-#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
 #define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
-#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
 #define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
-#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
 #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
-#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
 #define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
-#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
 #define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
 #define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
-#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
 #define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
-#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
 #define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
-#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
 #define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
 #define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
-#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
 #define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
 #define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
-#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
 #define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
-#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
 #define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
-#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
 #define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
-#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
 #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
-#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
 #define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
-#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
 #define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
 #define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
 #define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
 #define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
 #define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
 #define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
 #define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
 #define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
 #define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
 #define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
 #define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
 #define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
 #define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
 #define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
 #define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
 #define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
 #define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
 #define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
 #define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
 #define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
 #define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
 #define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
 #define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
-#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
 #define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
 #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
-#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
 #define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
 #define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
-#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
 #define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
 #define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
-#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
 #define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
 #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
-#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
 #define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
 #define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
 #define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
 #define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
 #define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
 #define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
 #define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
 #define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
 #define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
 #define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
 #define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
 #define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
 #define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
 #define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
 #define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
 #define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
 #define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
 #define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
 #define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
 #define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
 #define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
 #define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
 #define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
 #define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
 #define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
 #define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
 #define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
 #define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
 #define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
 #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
 #define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
 #define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
 #define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
 #define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
 #define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
 #define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
 #define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pMXVR_CONFIG                   ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */
 #define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
 #define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
-#define pMXVR_STATE_0                  ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */
 #define bfin_read_MXVR_STATE_0()       bfin_read32(MXVR_STATE_0)
 #define bfin_write_MXVR_STATE_0(val)   bfin_write32(MXVR_STATE_0, val)
-#define pMXVR_STATE_1                  ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */
 #define bfin_read_MXVR_STATE_1()       bfin_read32(MXVR_STATE_1)
 #define bfin_write_MXVR_STATE_1(val)   bfin_write32(MXVR_STATE_1, val)
-#define pMXVR_INT_STAT_0               ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */
 #define bfin_read_MXVR_INT_STAT_0()    bfin_read32(MXVR_INT_STAT_0)
 #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
-#define pMXVR_INT_STAT_1               ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */
 #define bfin_read_MXVR_INT_STAT_1()    bfin_read32(MXVR_INT_STAT_1)
 #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
-#define pMXVR_INT_EN_0                 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */
 #define bfin_read_MXVR_INT_EN_0()      bfin_read32(MXVR_INT_EN_0)
 #define bfin_write_MXVR_INT_EN_0(val)  bfin_write32(MXVR_INT_EN_0, val)
-#define pMXVR_INT_EN_1                 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */
 #define bfin_read_MXVR_INT_EN_1()      bfin_read32(MXVR_INT_EN_1)
 #define bfin_write_MXVR_INT_EN_1(val)  bfin_write32(MXVR_INT_EN_1, val)
-#define pMXVR_POSITION                 ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */
 #define bfin_read_MXVR_POSITION()      bfin_read16(MXVR_POSITION)
 #define bfin_write_MXVR_POSITION(val)  bfin_write16(MXVR_POSITION, val)
-#define pMXVR_MAX_POSITION             ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */
 #define bfin_read_MXVR_MAX_POSITION()  bfin_read16(MXVR_MAX_POSITION)
 #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
-#define pMXVR_DELAY                    ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */
 #define bfin_read_MXVR_DELAY()         bfin_read16(MXVR_DELAY)
 #define bfin_write_MXVR_DELAY(val)     bfin_write16(MXVR_DELAY, val)
-#define pMXVR_MAX_DELAY                ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */
 #define bfin_read_MXVR_MAX_DELAY()     bfin_read16(MXVR_MAX_DELAY)
 #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
-#define pMXVR_LADDR                    ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */
 #define bfin_read_MXVR_LADDR()         bfin_read32(MXVR_LADDR)
 #define bfin_write_MXVR_LADDR(val)     bfin_write32(MXVR_LADDR, val)
-#define pMXVR_GADDR                    ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */
 #define bfin_read_MXVR_GADDR()         bfin_read16(MXVR_GADDR)
 #define bfin_write_MXVR_GADDR(val)     bfin_write16(MXVR_GADDR, val)
-#define pMXVR_AADDR                    ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */
 #define bfin_read_MXVR_AADDR()         bfin_read32(MXVR_AADDR)
 #define bfin_write_MXVR_AADDR(val)     bfin_write32(MXVR_AADDR, val)
-#define pMXVR_ALLOC_0                  ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */
 #define bfin_read_MXVR_ALLOC_0()       bfin_read32(MXVR_ALLOC_0)
 #define bfin_write_MXVR_ALLOC_0(val)   bfin_write32(MXVR_ALLOC_0, val)
-#define pMXVR_ALLOC_1                  ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */
 #define bfin_read_MXVR_ALLOC_1()       bfin_read32(MXVR_ALLOC_1)
 #define bfin_write_MXVR_ALLOC_1(val)   bfin_write32(MXVR_ALLOC_1, val)
-#define pMXVR_ALLOC_2                  ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */
 #define bfin_read_MXVR_ALLOC_2()       bfin_read32(MXVR_ALLOC_2)
 #define bfin_write_MXVR_ALLOC_2(val)   bfin_write32(MXVR_ALLOC_2, val)
-#define pMXVR_ALLOC_3                  ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */
 #define bfin_read_MXVR_ALLOC_3()       bfin_read32(MXVR_ALLOC_3)
 #define bfin_write_MXVR_ALLOC_3(val)   bfin_write32(MXVR_ALLOC_3, val)
-#define pMXVR_ALLOC_4                  ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */
 #define bfin_read_MXVR_ALLOC_4()       bfin_read32(MXVR_ALLOC_4)
 #define bfin_write_MXVR_ALLOC_4(val)   bfin_write32(MXVR_ALLOC_4, val)
-#define pMXVR_ALLOC_5                  ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */
 #define bfin_read_MXVR_ALLOC_5()       bfin_read32(MXVR_ALLOC_5)
 #define bfin_write_MXVR_ALLOC_5(val)   bfin_write32(MXVR_ALLOC_5, val)
-#define pMXVR_ALLOC_6                  ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */
 #define bfin_read_MXVR_ALLOC_6()       bfin_read32(MXVR_ALLOC_6)
 #define bfin_write_MXVR_ALLOC_6(val)   bfin_write32(MXVR_ALLOC_6, val)
-#define pMXVR_ALLOC_7                  ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */
 #define bfin_read_MXVR_ALLOC_7()       bfin_read32(MXVR_ALLOC_7)
 #define bfin_write_MXVR_ALLOC_7(val)   bfin_write32(MXVR_ALLOC_7, val)
-#define pMXVR_ALLOC_8                  ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */
 #define bfin_read_MXVR_ALLOC_8()       bfin_read32(MXVR_ALLOC_8)
 #define bfin_write_MXVR_ALLOC_8(val)   bfin_write32(MXVR_ALLOC_8, val)
-#define pMXVR_ALLOC_9                  ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */
 #define bfin_read_MXVR_ALLOC_9()       bfin_read32(MXVR_ALLOC_9)
 #define bfin_write_MXVR_ALLOC_9(val)   bfin_write32(MXVR_ALLOC_9, val)
-#define pMXVR_ALLOC_10                 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */
 #define bfin_read_MXVR_ALLOC_10()      bfin_read32(MXVR_ALLOC_10)
 #define bfin_write_MXVR_ALLOC_10(val)  bfin_write32(MXVR_ALLOC_10, val)
-#define pMXVR_ALLOC_11                 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */
 #define bfin_read_MXVR_ALLOC_11()      bfin_read32(MXVR_ALLOC_11)
 #define bfin_write_MXVR_ALLOC_11(val)  bfin_write32(MXVR_ALLOC_11, val)
-#define pMXVR_ALLOC_12                 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */
 #define bfin_read_MXVR_ALLOC_12()      bfin_read32(MXVR_ALLOC_12)
 #define bfin_write_MXVR_ALLOC_12(val)  bfin_write32(MXVR_ALLOC_12, val)
-#define pMXVR_ALLOC_13                 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */
 #define bfin_read_MXVR_ALLOC_13()      bfin_read32(MXVR_ALLOC_13)
 #define bfin_write_MXVR_ALLOC_13(val)  bfin_write32(MXVR_ALLOC_13, val)
-#define pMXVR_ALLOC_14                 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */
 #define bfin_read_MXVR_ALLOC_14()      bfin_read32(MXVR_ALLOC_14)
 #define bfin_write_MXVR_ALLOC_14(val)  bfin_write32(MXVR_ALLOC_14, val)
-#define pMXVR_SYNC_LCHAN_0             ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */
 #define bfin_read_MXVR_SYNC_LCHAN_0()  bfin_read32(MXVR_SYNC_LCHAN_0)
 #define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define pMXVR_SYNC_LCHAN_1             ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */
 #define bfin_read_MXVR_SYNC_LCHAN_1()  bfin_read32(MXVR_SYNC_LCHAN_1)
 #define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define pMXVR_SYNC_LCHAN_2             ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */
 #define bfin_read_MXVR_SYNC_LCHAN_2()  bfin_read32(MXVR_SYNC_LCHAN_2)
 #define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define pMXVR_SYNC_LCHAN_3             ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */
 #define bfin_read_MXVR_SYNC_LCHAN_3()  bfin_read32(MXVR_SYNC_LCHAN_3)
 #define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define pMXVR_SYNC_LCHAN_4             ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */
 #define bfin_read_MXVR_SYNC_LCHAN_4()  bfin_read32(MXVR_SYNC_LCHAN_4)
 #define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define pMXVR_SYNC_LCHAN_5             ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */
 #define bfin_read_MXVR_SYNC_LCHAN_5()  bfin_read32(MXVR_SYNC_LCHAN_5)
 #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define pMXVR_SYNC_LCHAN_6             ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */
 #define bfin_read_MXVR_SYNC_LCHAN_6()  bfin_read32(MXVR_SYNC_LCHAN_6)
 #define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define pMXVR_SYNC_LCHAN_7             ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */
 #define bfin_read_MXVR_SYNC_LCHAN_7()  bfin_read32(MXVR_SYNC_LCHAN_7)
 #define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
-#define pMXVR_DMA0_CONFIG              ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */
 #define bfin_read_MXVR_DMA0_CONFIG()   bfin_read32(MXVR_DMA0_CONFIG)
 #define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
-#define pMXVR_DMA0_START_ADDR          ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */
 #define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR)
 #define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val)
-#define pMXVR_DMA0_COUNT               ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */
 #define bfin_read_MXVR_DMA0_COUNT()    bfin_read16(MXVR_DMA0_COUNT)
 #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
-#define pMXVR_DMA0_CURR_ADDR           ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */
 #define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR)
 #define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val)
-#define pMXVR_DMA0_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */
 #define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
 #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-#define pMXVR_DMA1_CONFIG              ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */
 #define bfin_read_MXVR_DMA1_CONFIG()   bfin_read32(MXVR_DMA1_CONFIG)
 #define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
-#define pMXVR_DMA1_START_ADDR          ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */
 #define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR)
 #define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val)
-#define pMXVR_DMA1_COUNT               ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */
 #define bfin_read_MXVR_DMA1_COUNT()    bfin_read16(MXVR_DMA1_COUNT)
 #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
-#define pMXVR_DMA1_CURR_ADDR           ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */
 #define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR)
 #define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val)
-#define pMXVR_DMA1_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */
 #define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
 #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-#define pMXVR_DMA2_CONFIG              ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */
 #define bfin_read_MXVR_DMA2_CONFIG()   bfin_read32(MXVR_DMA2_CONFIG)
 #define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
-#define pMXVR_DMA2_START_ADDR          ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */
 #define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR)
 #define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val)
-#define pMXVR_DMA2_COUNT               ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */
 #define bfin_read_MXVR_DMA2_COUNT()    bfin_read16(MXVR_DMA2_COUNT)
 #define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
-#define pMXVR_DMA2_CURR_ADDR           ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */
 #define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR)
 #define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val)
-#define pMXVR_DMA2_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */
 #define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
 #define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-#define pMXVR_DMA3_CONFIG              ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */
 #define bfin_read_MXVR_DMA3_CONFIG()   bfin_read32(MXVR_DMA3_CONFIG)
 #define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
-#define pMXVR_DMA3_START_ADDR          ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */
 #define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR)
 #define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val)
-#define pMXVR_DMA3_COUNT               ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */
 #define bfin_read_MXVR_DMA3_COUNT()    bfin_read16(MXVR_DMA3_COUNT)
 #define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
-#define pMXVR_DMA3_CURR_ADDR           ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */
 #define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR)
 #define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val)
-#define pMXVR_DMA3_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */
 #define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
 #define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-#define pMXVR_DMA4_CONFIG              ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */
 #define bfin_read_MXVR_DMA4_CONFIG()   bfin_read32(MXVR_DMA4_CONFIG)
 #define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
-#define pMXVR_DMA4_START_ADDR          ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */
 #define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR)
 #define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val)
-#define pMXVR_DMA4_COUNT               ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */
 #define bfin_read_MXVR_DMA4_COUNT()    bfin_read16(MXVR_DMA4_COUNT)
 #define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
-#define pMXVR_DMA4_CURR_ADDR           ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */
 #define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR)
 #define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val)
-#define pMXVR_DMA4_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */
 #define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
 #define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-#define pMXVR_DMA5_CONFIG              ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */
 #define bfin_read_MXVR_DMA5_CONFIG()   bfin_read32(MXVR_DMA5_CONFIG)
 #define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
-#define pMXVR_DMA5_START_ADDR          ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */
 #define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR)
 #define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val)
-#define pMXVR_DMA5_COUNT               ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */
 #define bfin_read_MXVR_DMA5_COUNT()    bfin_read16(MXVR_DMA5_COUNT)
 #define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
-#define pMXVR_DMA5_CURR_ADDR           ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */
 #define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR)
 #define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val)
-#define pMXVR_DMA5_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */
 #define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
 #define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-#define pMXVR_DMA6_CONFIG              ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */
 #define bfin_read_MXVR_DMA6_CONFIG()   bfin_read32(MXVR_DMA6_CONFIG)
 #define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
-#define pMXVR_DMA6_START_ADDR          ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */
 #define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR)
 #define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val)
-#define pMXVR_DMA6_COUNT               ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */
 #define bfin_read_MXVR_DMA6_COUNT()    bfin_read16(MXVR_DMA6_COUNT)
 #define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
-#define pMXVR_DMA6_CURR_ADDR           ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */
 #define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR)
 #define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val)
-#define pMXVR_DMA6_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */
 #define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
 #define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-#define pMXVR_DMA7_CONFIG              ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */
 #define bfin_read_MXVR_DMA7_CONFIG()   bfin_read32(MXVR_DMA7_CONFIG)
 #define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
-#define pMXVR_DMA7_START_ADDR          ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */
 #define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR)
 #define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val)
-#define pMXVR_DMA7_COUNT               ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */
 #define bfin_read_MXVR_DMA7_COUNT()    bfin_read16(MXVR_DMA7_COUNT)
 #define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
-#define pMXVR_DMA7_CURR_ADDR           ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */
 #define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR)
 #define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val)
-#define pMXVR_DMA7_CURR_COUNT          ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */
 #define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
 #define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-#define pMXVR_AP_CTL                   ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */
 #define bfin_read_MXVR_AP_CTL()        bfin_read16(MXVR_AP_CTL)
 #define bfin_write_MXVR_AP_CTL(val)    bfin_write16(MXVR_AP_CTL, val)
-#define pMXVR_APRB_START_ADDR          ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */
 #define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR)
 #define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val)
-#define pMXVR_APRB_CURR_ADDR           ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */
 #define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR)
 #define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val)
-#define pMXVR_APTB_START_ADDR          ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */
 #define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR)
 #define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val)
-#define pMXVR_APTB_CURR_ADDR           ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */
 #define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR)
 #define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val)
-#define pMXVR_CM_CTL                   ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */
 #define bfin_read_MXVR_CM_CTL()        bfin_read32(MXVR_CM_CTL)
 #define bfin_write_MXVR_CM_CTL(val)    bfin_write32(MXVR_CM_CTL, val)
-#define pMXVR_CMRB_START_ADDR          ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */
 #define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR)
 #define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val)
-#define pMXVR_CMRB_CURR_ADDR           ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */
 #define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR)
 #define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val)
-#define pMXVR_CMTB_START_ADDR          ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */
 #define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR)
 #define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val)
-#define pMXVR_CMTB_CURR_ADDR           ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */
 #define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR)
 #define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val)
-#define pMXVR_RRDB_START_ADDR          ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */
 #define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR)
 #define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val)
-#define pMXVR_RRDB_CURR_ADDR           ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */
 #define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR)
 #define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val)
-#define pMXVR_PAT_DATA_0               ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */
 #define bfin_read_MXVR_PAT_DATA_0()    bfin_read32(MXVR_PAT_DATA_0)
 #define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
-#define pMXVR_PAT_EN_0                 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */
 #define bfin_read_MXVR_PAT_EN_0()      bfin_read32(MXVR_PAT_EN_0)
 #define bfin_write_MXVR_PAT_EN_0(val)  bfin_write32(MXVR_PAT_EN_0, val)
-#define pMXVR_PAT_DATA_1               ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */
 #define bfin_read_MXVR_PAT_DATA_1()    bfin_read32(MXVR_PAT_DATA_1)
 #define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
-#define pMXVR_PAT_EN_1                 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */
 #define bfin_read_MXVR_PAT_EN_1()      bfin_read32(MXVR_PAT_EN_1)
 #define bfin_write_MXVR_PAT_EN_1(val)  bfin_write32(MXVR_PAT_EN_1, val)
-#define pMXVR_FRAME_CNT_0              ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */
 #define bfin_read_MXVR_FRAME_CNT_0()   bfin_read16(MXVR_FRAME_CNT_0)
 #define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
-#define pMXVR_FRAME_CNT_1              ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */
 #define bfin_read_MXVR_FRAME_CNT_1()   bfin_read16(MXVR_FRAME_CNT_1)
 #define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
-#define pMXVR_ROUTING_0                ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */
 #define bfin_read_MXVR_ROUTING_0()     bfin_read32(MXVR_ROUTING_0)
 #define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
-#define pMXVR_ROUTING_1                ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */
 #define bfin_read_MXVR_ROUTING_1()     bfin_read32(MXVR_ROUTING_1)
 #define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
-#define pMXVR_ROUTING_2                ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */
 #define bfin_read_MXVR_ROUTING_2()     bfin_read32(MXVR_ROUTING_2)
 #define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
-#define pMXVR_ROUTING_3                ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */
 #define bfin_read_MXVR_ROUTING_3()     bfin_read32(MXVR_ROUTING_3)
 #define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
-#define pMXVR_ROUTING_4                ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */
 #define bfin_read_MXVR_ROUTING_4()     bfin_read32(MXVR_ROUTING_4)
 #define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
-#define pMXVR_ROUTING_5                ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */
 #define bfin_read_MXVR_ROUTING_5()     bfin_read32(MXVR_ROUTING_5)
 #define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
-#define pMXVR_ROUTING_6                ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */
 #define bfin_read_MXVR_ROUTING_6()     bfin_read32(MXVR_ROUTING_6)
 #define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
-#define pMXVR_ROUTING_7                ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */
 #define bfin_read_MXVR_ROUTING_7()     bfin_read32(MXVR_ROUTING_7)
 #define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
-#define pMXVR_ROUTING_8                ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */
 #define bfin_read_MXVR_ROUTING_8()     bfin_read32(MXVR_ROUTING_8)
 #define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
-#define pMXVR_ROUTING_9                ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */
 #define bfin_read_MXVR_ROUTING_9()     bfin_read32(MXVR_ROUTING_9)
 #define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
-#define pMXVR_ROUTING_10               ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */
 #define bfin_read_MXVR_ROUTING_10()    bfin_read32(MXVR_ROUTING_10)
 #define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
-#define pMXVR_ROUTING_11               ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */
 #define bfin_read_MXVR_ROUTING_11()    bfin_read32(MXVR_ROUTING_11)
 #define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
-#define pMXVR_ROUTING_12               ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */
 #define bfin_read_MXVR_ROUTING_12()    bfin_read32(MXVR_ROUTING_12)
 #define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
-#define pMXVR_ROUTING_13               ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */
 #define bfin_read_MXVR_ROUTING_13()    bfin_read32(MXVR_ROUTING_13)
 #define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
-#define pMXVR_ROUTING_14               ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */
 #define bfin_read_MXVR_ROUTING_14()    bfin_read32(MXVR_ROUTING_14)
 #define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
-#define pMXVR_BLOCK_CNT                ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */
 #define bfin_read_MXVR_BLOCK_CNT()     bfin_read16(MXVR_BLOCK_CNT)
 #define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
-#define pMXVR_CLK_CTL                  ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */
 #define bfin_read_MXVR_CLK_CTL()       bfin_read32(MXVR_CLK_CTL)
 #define bfin_write_MXVR_CLK_CTL(val)   bfin_write32(MXVR_CLK_CTL, val)
-#define pMXVR_CDRPLL_CTL               ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */
 #define bfin_read_MXVR_CDRPLL_CTL()    bfin_read32(MXVR_CDRPLL_CTL)
 #define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
-#define pMXVR_FMPLL_CTL                ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */
 #define bfin_read_MXVR_FMPLL_CTL()     bfin_read32(MXVR_FMPLL_CTL)
 #define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
-#define pMXVR_PIN_CTL                  ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */
 #define bfin_read_MXVR_PIN_CTL()       bfin_read16(MXVR_PIN_CTL)
 #define bfin_write_MXVR_PIN_CTL(val)   bfin_write16(MXVR_PIN_CTL, val)
-#define pMXVR_SCLK_CNT                 ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */
 #define bfin_read_MXVR_SCLK_CNT()      bfin_read16(MXVR_SCLK_CNT)
 #define bfin_write_MXVR_SCLK_CNT(val)  bfin_write16(MXVR_SCLK_CNT, val)
-#define pKPAD_CTL                      ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */
 #define bfin_read_KPAD_CTL()           bfin_read16(KPAD_CTL)
 #define bfin_write_KPAD_CTL(val)       bfin_write16(KPAD_CTL, val)
-#define pKPAD_PRESCALE                 ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */
 #define bfin_read_KPAD_PRESCALE()      bfin_read16(KPAD_PRESCALE)
 #define bfin_write_KPAD_PRESCALE(val)  bfin_write16(KPAD_PRESCALE, val)
-#define pKPAD_MSEL                     ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */
 #define bfin_read_KPAD_MSEL()          bfin_read16(KPAD_MSEL)
 #define bfin_write_KPAD_MSEL(val)      bfin_write16(KPAD_MSEL, val)
-#define pKPAD_ROWCOL                   ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */
 #define bfin_read_KPAD_ROWCOL()        bfin_read16(KPAD_ROWCOL)
 #define bfin_write_KPAD_ROWCOL(val)    bfin_write16(KPAD_ROWCOL, val)
-#define pKPAD_STAT                     ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */
 #define bfin_read_KPAD_STAT()          bfin_read16(KPAD_STAT)
 #define bfin_write_KPAD_STAT(val)      bfin_write16(KPAD_STAT, val)
-#define pKPAD_SOFTEVAL                 ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */
 #define bfin_read_KPAD_SOFTEVAL()      bfin_read16(KPAD_SOFTEVAL)
 #define bfin_write_KPAD_SOFTEVAL(val)  bfin_write16(KPAD_SOFTEVAL, val)
-#define pSDH_PWR_CTL                   ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */
 #define bfin_read_SDH_PWR_CTL()        bfin_read16(SDH_PWR_CTL)
 #define bfin_write_SDH_PWR_CTL(val)    bfin_write16(SDH_PWR_CTL, val)
-#define pSDH_CLK_CTL                   ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */
 #define bfin_read_SDH_CLK_CTL()        bfin_read16(SDH_CLK_CTL)
 #define bfin_write_SDH_CLK_CTL(val)    bfin_write16(SDH_CLK_CTL, val)
-#define pSDH_ARGUMENT                  ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */
 #define bfin_read_SDH_ARGUMENT()       bfin_read32(SDH_ARGUMENT)
 #define bfin_write_SDH_ARGUMENT(val)   bfin_write32(SDH_ARGUMENT, val)
-#define pSDH_COMMAND                   ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */
 #define bfin_read_SDH_COMMAND()        bfin_read16(SDH_COMMAND)
 #define bfin_write_SDH_COMMAND(val)    bfin_write16(SDH_COMMAND, val)
-#define pSDH_RESP_CMD                  ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */
 #define bfin_read_SDH_RESP_CMD()       bfin_read16(SDH_RESP_CMD)
 #define bfin_write_SDH_RESP_CMD(val)   bfin_write16(SDH_RESP_CMD, val)
-#define pSDH_RESPONSE0                 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */
 #define bfin_read_SDH_RESPONSE0()      bfin_read32(SDH_RESPONSE0)
 #define bfin_write_SDH_RESPONSE0(val)  bfin_write32(SDH_RESPONSE0, val)
-#define pSDH_RESPONSE1                 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */
 #define bfin_read_SDH_RESPONSE1()      bfin_read32(SDH_RESPONSE1)
 #define bfin_write_SDH_RESPONSE1(val)  bfin_write32(SDH_RESPONSE1, val)
-#define pSDH_RESPONSE2                 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */
 #define bfin_read_SDH_RESPONSE2()      bfin_read32(SDH_RESPONSE2)
 #define bfin_write_SDH_RESPONSE2(val)  bfin_write32(SDH_RESPONSE2, val)
-#define pSDH_RESPONSE3                 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */
 #define bfin_read_SDH_RESPONSE3()      bfin_read32(SDH_RESPONSE3)
 #define bfin_write_SDH_RESPONSE3(val)  bfin_write32(SDH_RESPONSE3, val)
-#define pSDH_DATA_TIMER                ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */
 #define bfin_read_SDH_DATA_TIMER()     bfin_read32(SDH_DATA_TIMER)
 #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
-#define pSDH_DATA_LGTH                 ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */
 #define bfin_read_SDH_DATA_LGTH()      bfin_read16(SDH_DATA_LGTH)
 #define bfin_write_SDH_DATA_LGTH(val)  bfin_write16(SDH_DATA_LGTH, val)
-#define pSDH_DATA_CTL                  ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */
 #define bfin_read_SDH_DATA_CTL()       bfin_read16(SDH_DATA_CTL)
 #define bfin_write_SDH_DATA_CTL(val)   bfin_write16(SDH_DATA_CTL, val)
-#define pSDH_DATA_CNT                  ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */
 #define bfin_read_SDH_DATA_CNT()       bfin_read16(SDH_DATA_CNT)
 #define bfin_write_SDH_DATA_CNT(val)   bfin_write16(SDH_DATA_CNT, val)
-#define pSDH_STATUS                    ((uint32_t volatile *)SDH_STATUS) /* SDH Status */
 #define bfin_read_SDH_STATUS()         bfin_read32(SDH_STATUS)
 #define bfin_write_SDH_STATUS(val)     bfin_write32(SDH_STATUS, val)
-#define pSDH_STATUS_CLR                ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */
 #define bfin_read_SDH_STATUS_CLR()     bfin_read16(SDH_STATUS_CLR)
 #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
-#define pSDH_MASK0                     ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */
 #define bfin_read_SDH_MASK0()          bfin_read32(SDH_MASK0)
 #define bfin_write_SDH_MASK0(val)      bfin_write32(SDH_MASK0, val)
-#define pSDH_MASK1                     ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */
 #define bfin_read_SDH_MASK1()          bfin_read32(SDH_MASK1)
 #define bfin_write_SDH_MASK1(val)      bfin_write32(SDH_MASK1, val)
-#define pSDH_FIFO_CNT                  ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */
 #define bfin_read_SDH_FIFO_CNT()       bfin_read16(SDH_FIFO_CNT)
 #define bfin_write_SDH_FIFO_CNT(val)   bfin_write16(SDH_FIFO_CNT, val)
-#define pSDH_FIFO                      ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */
 #define bfin_read_SDH_FIFO()           bfin_read32(SDH_FIFO)
 #define bfin_write_SDH_FIFO(val)       bfin_write32(SDH_FIFO, val)
-#define pSDH_E_STATUS                  ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */
 #define bfin_read_SDH_E_STATUS()       bfin_read16(SDH_E_STATUS)
 #define bfin_write_SDH_E_STATUS(val)   bfin_write16(SDH_E_STATUS, val)
-#define pSDH_E_MASK                    ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */
 #define bfin_read_SDH_E_MASK()         bfin_read16(SDH_E_MASK)
 #define bfin_write_SDH_E_MASK(val)     bfin_write16(SDH_E_MASK, val)
-#define pSDH_CFG                       ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */
 #define bfin_read_SDH_CFG()            bfin_read16(SDH_CFG)
 #define bfin_write_SDH_CFG(val)        bfin_write16(SDH_CFG, val)
-#define pSDH_RD_WAIT_EN                ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */
 #define bfin_read_SDH_RD_WAIT_EN()     bfin_read16(SDH_RD_WAIT_EN)
 #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
-#define pSDH_PID0                      ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */
 #define bfin_read_SDH_PID0()           bfin_read16(SDH_PID0)
 #define bfin_write_SDH_PID0(val)       bfin_write16(SDH_PID0, val)
-#define pSDH_PID1                      ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */
 #define bfin_read_SDH_PID1()           bfin_read16(SDH_PID1)
 #define bfin_write_SDH_PID1(val)       bfin_write16(SDH_PID1, val)
-#define pSDH_PID2                      ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */
 #define bfin_read_SDH_PID2()           bfin_read16(SDH_PID2)
 #define bfin_write_SDH_PID2(val)       bfin_write16(SDH_PID2, val)
-#define pSDH_PID3                      ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */
 #define bfin_read_SDH_PID3()           bfin_read16(SDH_PID3)
 #define bfin_write_SDH_PID3(val)       bfin_write16(SDH_PID3, val)
-#define pSDH_PID4                      ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */
 #define bfin_read_SDH_PID4()           bfin_read16(SDH_PID4)
 #define bfin_write_SDH_PID4(val)       bfin_write16(SDH_PID4, val)
-#define pSDH_PID5                      ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */
 #define bfin_read_SDH_PID5()           bfin_read16(SDH_PID5)
 #define bfin_write_SDH_PID5(val)       bfin_write16(SDH_PID5, val)
-#define pSDH_PID6                      ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */
 #define bfin_read_SDH_PID6()           bfin_read16(SDH_PID6)
 #define bfin_write_SDH_PID6(val)       bfin_write16(SDH_PID6, val)
-#define pSDH_PID7                      ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */
 #define bfin_read_SDH_PID7()           bfin_read16(SDH_PID7)
 #define bfin_write_SDH_PID7(val)       bfin_write16(SDH_PID7, val)
-#define pATAPI_CONTROL                 ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */
 #define bfin_read_ATAPI_CONTROL()      bfin_read16(ATAPI_CONTROL)
 #define bfin_write_ATAPI_CONTROL(val)  bfin_write16(ATAPI_CONTROL, val)
-#define pATAPI_STATUS                  ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */
 #define bfin_read_ATAPI_STATUS()       bfin_read16(ATAPI_STATUS)
 #define bfin_write_ATAPI_STATUS(val)   bfin_write16(ATAPI_STATUS, val)
-#define pATAPI_DEV_ADDR                ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */
 #define bfin_read_ATAPI_DEV_ADDR()     bfin_read16(ATAPI_DEV_ADDR)
 #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
-#define pATAPI_DEV_TXBUF               ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */
 #define bfin_read_ATAPI_DEV_TXBUF()    bfin_read16(ATAPI_DEV_TXBUF)
 #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
-#define pATAPI_DEV_RXBUF               ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */
 #define bfin_read_ATAPI_DEV_RXBUF()    bfin_read16(ATAPI_DEV_RXBUF)
 #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
-#define pATAPI_INT_MASK                ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */
 #define bfin_read_ATAPI_INT_MASK()     bfin_read16(ATAPI_INT_MASK)
 #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
-#define pATAPI_INT_STATUS              ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */
 #define bfin_read_ATAPI_INT_STATUS()   bfin_read16(ATAPI_INT_STATUS)
 #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
-#define pATAPI_XFER_LEN                ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */
 #define bfin_read_ATAPI_XFER_LEN()     bfin_read16(ATAPI_XFER_LEN)
 #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
-#define pATAPI_LINE_STATUS             ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */
 #define bfin_read_ATAPI_LINE_STATUS()  bfin_read16(ATAPI_LINE_STATUS)
 #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
-#define pATAPI_SM_STATE                ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */
 #define bfin_read_ATAPI_SM_STATE()     bfin_read16(ATAPI_SM_STATE)
 #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
-#define pATAPI_TERMINATE               ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */
 #define bfin_read_ATAPI_TERMINATE()    bfin_read16(ATAPI_TERMINATE)
 #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
-#define pATAPI_PIO_TFRCNT              ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */
 #define bfin_read_ATAPI_PIO_TFRCNT()   bfin_read16(ATAPI_PIO_TFRCNT)
 #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define pATAPI_DMA_TFRCNT              ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */
 #define bfin_read_ATAPI_DMA_TFRCNT()   bfin_read16(ATAPI_DMA_TFRCNT)
 #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define pATAPI_UMAIN_TFRCNT            ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */
 #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
 #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define pATAPI_UDMAOUT_TFRCNT          ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */
 #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
 #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define pATAPI_REG_TIM_0               ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */
 #define bfin_read_ATAPI_REG_TIM_0()    bfin_read16(ATAPI_REG_TIM_0)
 #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
-#define pATAPI_PIO_TIM_0               ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */
 #define bfin_read_ATAPI_PIO_TIM_0()    bfin_read16(ATAPI_PIO_TIM_0)
 #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
-#define pATAPI_PIO_TIM_1               ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */
 #define bfin_read_ATAPI_PIO_TIM_1()    bfin_read16(ATAPI_PIO_TIM_1)
 #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
-#define pATAPI_MULTI_TIM_0             ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */
 #define bfin_read_ATAPI_MULTI_TIM_0()  bfin_read16(ATAPI_MULTI_TIM_0)
 #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define pATAPI_MULTI_TIM_1             ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */
 #define bfin_read_ATAPI_MULTI_TIM_1()  bfin_read16(ATAPI_MULTI_TIM_1)
 #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define pATAPI_MULTI_TIM_2             ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */
 #define bfin_read_ATAPI_MULTI_TIM_2()  bfin_read16(ATAPI_MULTI_TIM_2)
 #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define pATAPI_ULTRA_TIM_0             ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_0()  bfin_read16(ATAPI_ULTRA_TIM_0)
 #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define pATAPI_ULTRA_TIM_1             ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_1()  bfin_read16(ATAPI_ULTRA_TIM_1)
 #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define pATAPI_ULTRA_TIM_2             ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_2()  bfin_read16(ATAPI_ULTRA_TIM_2)
 #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define pATAPI_ULTRA_TIM_3             ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */
 #define bfin_read_ATAPI_ULTRA_TIM_3()  bfin_read16(ATAPI_ULTRA_TIM_3)
 #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
-#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
 #define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
 #define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
 #define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
 #define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
 #define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
 #define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
 #define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
 #define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
 #define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
 #define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
 #define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
 #define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
 #define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
 #define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
 #define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
 #define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
 #define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
 #define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
 #define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
 #define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
 #define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
 #define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
 #define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
 #define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
 #define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
 #define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
 #define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
 #define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
 #define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
 #define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
 #define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
-#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
 #define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
 #define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
-#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
 #define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
 #define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
-#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
 #define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
 #define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
-#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
 #define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
 #define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
-#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
 #define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
 #define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
-#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
 #define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
 #define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
-#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
 #define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
 #define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
-#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
 #define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
 #define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
-#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
 #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
-#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
 #define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
 #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
 #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
-#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
 #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
 #define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
 #define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
-#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
 #define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
 #define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
-#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
 #define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
 #define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
-#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
 #define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
 #define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
-#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
 #define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
 #define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
-#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
 #define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
 #define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
-#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
 #define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
 #define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
-#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
 #define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
 #define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
-#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
 #define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
 #define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
-#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
 #define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
 #define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
-#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
-#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
 #define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
-#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
-#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
-#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
 #define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
 #define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
-#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
 #define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
 #define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
-#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
 #define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
 #define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
-#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
 #define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
 #define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
-#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
 #define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
 #define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
-#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
 #define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
 #define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
-#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
 #define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
 #define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
-#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
 #define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
 #define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
-#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
 #define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
 #define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
-#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
 #define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
 #define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
-#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
 #define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
-#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
 #define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
-#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
 #define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
-#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
 #define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
-#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
 #define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
 #define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
-#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
 #define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
 #define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
-#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
 #define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
 #define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
-#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
 #define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
 #define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
-#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
 #define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
 #define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
-#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
 #define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
-#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
 #define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
 #define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
-#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
 #define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
 #define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
-#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
 #define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
 #define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
-#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
 #define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
-#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
 #define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
-#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
 #define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
-#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
 #define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
-#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
 #define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
-#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
 #define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
 #define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
-#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
 #define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
 #define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
-#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
 #define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
 #define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
-#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
 #define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
 #define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
-#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
 #define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
-#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
 #define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
 #define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
-#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
 #define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
 #define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
-#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
 #define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
 #define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
-#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
 #define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
-#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
 #define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
-#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
 #define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
-#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
 #define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
-#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
 #define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
-#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
 #define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
 #define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
-#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
 #define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
 #define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
-#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
 #define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
 #define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
-#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
 #define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
 #define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
-#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
 #define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
 #define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
-#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
 #define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
 #define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
-#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
 #define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
 #define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
-#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
 #define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
 #define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
-#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
 #define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
 #define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
-#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
 #define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
 #define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
-#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
 #define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
 #define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
-#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
 #define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
 #define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
-#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
 #define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
 #define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
-#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
 #define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
 #define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
-#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
 #define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
 #define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
-#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
 #define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
 #define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
-#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
 #define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
-#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
 #define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
-#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
 #define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
-#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
 #define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
-#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
 #define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
-#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
 #define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
-#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
 #define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
-#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
 #define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
-#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
 #define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
-#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
 #define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
-#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
 #define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
-#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
 #define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
-#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
 #define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
-#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
 #define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
-#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
 #define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
-#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
 #define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
-#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
 #define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
-#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
 #define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
-#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
 #define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
-#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
 #define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
-#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
 #define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
-#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
 #define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
-#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
 #define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
-#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
 #define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
-#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
 #define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
-#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
 #define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
-#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
 #define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
-#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
 #define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
-#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
 #define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
-#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
 #define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
-#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
 #define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
-#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
 #define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
-#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
 #define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
-#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
 #define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
-#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
 #define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
-#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
 #define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
-#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
 #define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
-#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
 #define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
-#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
 #define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
-#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
 #define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
-#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
 #define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
-#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
 #define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
-#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
 #define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
-#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
 #define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
-#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
 #define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
-#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
 #define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
-#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
 #define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
-#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
 #define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
-#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
 #define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
-#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
 #define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
-#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
 #define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
-#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
 #define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
-#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
 #define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
-#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
 #define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
-#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
 #define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
-#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
 #define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
-#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
 #define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
-#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
 #define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
-#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
 #define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
-#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
 #define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
-#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
 #define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
-#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
 #define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
-#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
 #define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
-#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
 #define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
-#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
 #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
-#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
 #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
-#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
 #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
-#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
 #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
-#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
 #define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
 #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
-#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
 #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
 #define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
 #define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
-#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
 #define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
 #define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
-#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
 #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
-#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
 #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
-#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
 #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
-#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
 #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
-#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
 #define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
 #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
-#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
 #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
 #define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
 #define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
-#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
 #define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
 #define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
-#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
 #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
-#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
 #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
-#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
 #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
-#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
 #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
-#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
 #define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
 #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
-#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
 #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
 #define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
 #define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
-#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
 #define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
 #define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
-#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
 #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
-#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
 #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
-#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
 #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
-#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
 #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
-#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
 #define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
 #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
-#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
 #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
 #define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
 #define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
-#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
 #define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
 #define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
-#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
 #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
-#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
 #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
-#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
 #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
-#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
 #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
-#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
 #define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
 #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
-#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
 #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
 #define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
 #define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
-#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
 #define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
 #define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
-#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
 #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
-#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
 #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
-#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
 #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
-#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
 #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
-#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
 #define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
 #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
-#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
 #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
 #define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
 #define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
-#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
 #define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
 #define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
-#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
 #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
-#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
 #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
-#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
 #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
-#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
 #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
-#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
 #define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
 #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
-#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
 #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
 #define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
 #define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
-#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
 #define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
 #define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
-#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
 #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
-#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
 #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
-#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
 #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
-#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
 #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
-#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
 #define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
 #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
-#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
 #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
 #define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
 #define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
-#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
 #define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
 #define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
-#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
 #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
-#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
 #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
-#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
 #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
-#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
 #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
-#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
 #define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
 #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
-#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
 #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
 #define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
 #define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
-#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
 #define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
 #define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
-#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
 #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
-#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
 #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
-#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
 #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
-#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
 #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
-#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
 #define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
 #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
-#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
 #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
 #define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
 #define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
-#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
 #define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
 #define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
-#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
 #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
-#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
 #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
-#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
 #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
-#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
 #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
-#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
 #define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
 #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
-#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
 #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
 #define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
 #define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
-#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
 #define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
 #define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
-#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
 #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
-#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
 #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
-#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
 #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
-#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
 #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
-#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
 #define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
 #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
-#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
 #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
 #define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
 #define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
-#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
 #define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
 #define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
-#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
 #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
-#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
 #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
-#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
 #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
-#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
 #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
-#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
 #define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
 #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
-#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
 #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
 #define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
 #define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
-#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
 #define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
 #define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
-#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
 #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
-#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
 #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
-#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
 #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
-#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
 #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
-#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
 #define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
 #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
-#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
 #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
 #define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
 #define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
-#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
 #define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
 #define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
-#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
 #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
-#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
 #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
-#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
 #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
-#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
 #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
-#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
 #define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
 #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
-#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
 #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
 #define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
 #define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
-#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
 #define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
 #define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
-#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
 #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
-#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
 #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
-#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
 #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
-#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
 #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
-#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
 #define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
 #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
-#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
 #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
 #define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
 #define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
-#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
 #define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
 #define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
-#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
 #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
-#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
 #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
-#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
 #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
-#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
 #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
-#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
 #define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
 #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
-#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
 #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
 #define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
 #define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
-#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
 #define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
 #define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
-#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
 #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
-#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
 #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
-#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
 #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
-#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
 #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
-#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
 #define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
 #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
-#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
 #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
 #define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
 #define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
-#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
 #define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
 #define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
-#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
 #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
-#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
 #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
-#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
 #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
-#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
 #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
-#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
 #define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
 #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
-#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
 #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
 #define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
 #define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
-#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
 #define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
 #define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
-#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
 #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
-#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
 #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
-#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
 #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
-#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
 #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
-#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
 #define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
 #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
-#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
 #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
 #define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
 #define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
-#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
 #define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
 #define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
-#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
 #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
-#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
 #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
-#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
 #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
-#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
 #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
-#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
 #define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
 #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
-#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
 #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
 #define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
 #define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
-#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
 #define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
 #define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
-#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
 #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
-#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
 #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
-#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
 #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
-#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
 #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
-#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
 #define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
 #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
-#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
 #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
 #define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
 #define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
-#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
 #define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
 #define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
-#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
 #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
-#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
 #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
-#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
 #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
-#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
 #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
-#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
 #define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
 #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
-#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
 #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
 #define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
 #define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
-#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
 #define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
 #define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
-#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
 #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
-#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
 #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
-#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
 #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
-#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
 #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
-#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
 #define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
 #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
-#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
 #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
 #define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
 #define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
-#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
 #define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
 #define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
-#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
 #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
-#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
 #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
-#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
 #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
-#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
 #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
-#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
 #define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
 #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
-#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
 #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
 #define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
 #define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
-#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
 #define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
 #define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
-#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
 #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
-#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
 #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
-#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
 #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
-#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
 #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
-#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
 #define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
 #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
-#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
 #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
 #define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
 #define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
-#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
 #define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
 #define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
-#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
 #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
-#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
 #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
-#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
 #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
-#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
 #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
-#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
 #define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
 #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
-#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
 #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
 #define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
 #define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
-#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
 #define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
 #define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
-#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
 #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
-#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
 #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
-#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
 #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
-#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
 #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
-#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
 #define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
 #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
-#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
 #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
 #define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
 #define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
-#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
 #define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
 #define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
-#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
 #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
-#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
 #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
-#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
 #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
-#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
 #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
-#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
 #define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
 #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
-#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
 #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
 #define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
 #define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
-#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
 #define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
 #define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
-#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
 #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
-#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
 #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
-#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
 #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
-#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
 #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
-#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
 #define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
 #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
-#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
 #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
 #define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
 #define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
-#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
 #define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
 #define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
-#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
 #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
-#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
 #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
-#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
 #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
-#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
 #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
-#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
 #define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
 #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
-#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
 #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
 #define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
 #define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
-#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
 #define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
 #define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
-#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
 #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
-#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
 #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
-#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
 #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
-#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
 #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
-#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
 #define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
 #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
-#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
 #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
 #define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
 #define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
-#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
 #define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
 #define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
-#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
 #define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
 #define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
-#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
 #define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
 #define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
-#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
 #define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
 #define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
-#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
 #define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
 #define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
-#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
 #define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
 #define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
-#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
 #define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
 #define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
-#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
 #define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
 #define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
-#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
 #define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
 #define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
-#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
 #define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
-#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
 #define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
 #define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
-#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
 #define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
 #define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
-#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
 #define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
 #define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
-#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
 #define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
 #define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
-#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
 #define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
 #define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
-#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
 #define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
 #define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
-#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
 #define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
 #define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
-#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
 #define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
 #define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
-#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
 #define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
 #define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
-#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
 #define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
 #define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
-#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
 #define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
 #define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
-#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
 #define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
 #define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
-#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
 #define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
-#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
 #define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
 #define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
-#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
 #define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
 #define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
-#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
 #define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
 #define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
-#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
 #define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
 #define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
-#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
 #define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
 #define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
-#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
 #define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
 #define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
-#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
 #define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
 #define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
-#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
 #define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
 #define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
-#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
 #define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
 #define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
-#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
 #define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
 #define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
-#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
 #define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
 #define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
-#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
 #define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
 #define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
-#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
 #define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
 #define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
-#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
 #define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
 #define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
-#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
 #define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
 #define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
-#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
 #define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
 #define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
-#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
 #define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
 #define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
-#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
 #define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
 #define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
-#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
 #define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
 #define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
-#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
 #define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
 #define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
-#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
 #define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
-#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
 #define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
-#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
 #define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
-#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
 #define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
-#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
 #define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
-#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
 #define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
-#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
 #define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
-#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
 #define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
-#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
 #define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
-#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
 #define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
-#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
 #define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
-#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
 #define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
-#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
 #define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
-#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
 #define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
-#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
 #define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
-#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
 #define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
-#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
 #define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
-#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
 #define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
-#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
 #define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
-#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
 #define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
-#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
 #define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
-#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
 #define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
-#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
 #define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
-#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
 #define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
-#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
 #define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
-#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
 #define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
-#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
 #define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
-#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
 #define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
-#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
 #define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
-#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
 #define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
-#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
 #define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
-#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
 #define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
-#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
 #define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
-#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
 #define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
-#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
 #define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
-#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
 #define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
-#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
 #define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
-#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
 #define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
-#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
 #define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
-#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
 #define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
-#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
 #define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
-#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
 #define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
-#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
 #define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
-#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
 #define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
-#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
 #define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
-#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
 #define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
-#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
 #define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
-#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
 #define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
-#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
 #define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
-#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
 #define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
-#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
 #define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
-#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
 #define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
-#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
 #define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
-#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
 #define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
-#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
 #define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
-#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
 #define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
-#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
 #define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
-#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
 #define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
-#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
 #define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
-#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
 #define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
-#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
 #define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
-#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
 #define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
-#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
 #define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
 #define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
-#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
 #define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
 #define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
-#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
 #define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
 #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
-#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
 #define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
 #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
-#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
 #define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
 #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
-#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
 #define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
 #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
-#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
 #define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
 #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
-#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
 #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
 #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
 #define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
 #define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
-#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
 #define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
 #define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
-#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
 #define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
 #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
-#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
 #define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
 #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
-#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
 #define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
 #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
-#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
 #define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
 #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
-#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
 #define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
 #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
-#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
 #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
 #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
 #define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
 #define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
-#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
 #define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
 #define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
-#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
 #define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
 #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
-#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
 #define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
 #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
-#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
 #define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
 #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
-#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
 #define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
 #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
-#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
 #define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
 #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
-#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
 #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
 #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
 #define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
 #define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
-#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
 #define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
 #define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
-#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
 #define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
 #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
-#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
 #define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
 #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
-#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
 #define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
 #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
-#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
 #define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
 #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
-#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
 #define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
 #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
-#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
 #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
 #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
 #define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
 #define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
-#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
 #define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
 #define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
-#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
 #define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
 #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
-#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
 #define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
 #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
-#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
 #define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
 #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
-#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
 #define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
 #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
-#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
 #define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
 #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
-#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
 #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
 #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
 #define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
 #define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
-#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
 #define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
 #define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
-#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
 #define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
 #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
-#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
 #define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
 #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
-#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
 #define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
 #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
-#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
 #define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
 #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
-#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
 #define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
 #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
-#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
 #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
 #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
 #define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
 #define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
-#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
 #define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
 #define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
-#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
 #define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
 #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
-#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
 #define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
 #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
-#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
 #define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
 #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
-#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
 #define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
 #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
-#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
 #define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
 #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
-#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
 #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
 #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
 #define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
 #define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
-#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
 #define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
 #define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
-#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
 #define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
 #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
-#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
 #define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
 #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
-#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
 #define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
 #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
-#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
 #define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
 #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
-#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
 #define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
 #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
-#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
 #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
 #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
 #define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
 #define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
-#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
 #define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
 #define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
-#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
 #define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
 #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
-#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
 #define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
 #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
-#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
 #define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
 #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
-#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
 #define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
 #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
-#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
 #define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
 #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
-#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
 #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
 #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
 #define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
 #define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
-#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
 #define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
 #define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
-#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
 #define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
 #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
-#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
 #define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
 #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
-#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
 #define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
 #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
-#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
 #define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
 #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
-#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
 #define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
 #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
-#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
 #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
 #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
 #define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
 #define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
-#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
 #define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
 #define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
-#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
 #define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
 #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
-#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
 #define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
 #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
-#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
 #define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
 #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
-#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
 #define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
 #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
-#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
 #define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
 #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
-#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
 #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
 #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
 #define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
 #define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
-#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
 #define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
 #define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
-#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
 #define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
 #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
-#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
 #define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
 #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
-#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
 #define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
 #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
-#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
 #define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
 #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
-#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
 #define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
 #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
-#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
 #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
 #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
 #define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
 #define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
-#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
 #define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
 #define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
-#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
 #define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
 #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
-#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
 #define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
 #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
-#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
 #define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
 #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
-#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
 #define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
 #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
-#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
 #define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
 #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
-#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
 #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
 #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
 #define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
 #define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
-#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
 #define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
 #define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
-#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
 #define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
 #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
-#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
 #define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
 #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
-#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
 #define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
 #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
-#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
 #define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
 #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
-#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
 #define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
 #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
-#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
 #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
 #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
 #define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
 #define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
-#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
 #define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
 #define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
-#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
 #define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
 #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
-#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
 #define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
 #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
-#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
 #define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
 #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
-#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
 #define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
 #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
-#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
 #define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
 #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
-#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
 #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
 #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
 #define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
 #define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
-#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
 #define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
 #define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
-#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
 #define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
 #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
-#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
 #define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
 #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
-#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
 #define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
 #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
-#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
 #define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
 #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
-#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
 #define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
 #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
-#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
 #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
 #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
 #define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
 #define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
-#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
 #define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
 #define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
-#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
 #define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
 #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
-#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
 #define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
 #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
-#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
 #define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
 #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
-#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
 #define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
 #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
-#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
 #define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
 #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
-#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
 #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
 #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
 #define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
 #define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
-#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
 #define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
 #define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
-#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
 #define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
 #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
-#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
 #define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
 #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
-#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
 #define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
 #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
-#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
 #define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
 #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
-#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
 #define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
 #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
-#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
 #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
 #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
 #define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
 #define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
-#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
 #define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
 #define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
-#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
 #define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
 #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
-#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
 #define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
 #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
-#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
 #define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
 #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
-#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
 #define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
 #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
-#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
 #define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
 #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
-#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
 #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
 #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
 #define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
 #define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
-#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
 #define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
 #define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
-#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
 #define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
 #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
-#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
 #define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
 #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
-#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
 #define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
 #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
-#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
 #define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
 #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
-#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
 #define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
 #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
-#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
 #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
 #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
 #define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
 #define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
-#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
 #define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
 #define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
-#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
 #define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
 #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
-#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
 #define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
 #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
-#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
 #define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
 #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
-#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
 #define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
 #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
-#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
 #define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
 #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
-#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
 #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
 #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
 #define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
 #define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
-#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
 #define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
 #define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
-#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
 #define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
 #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
-#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
 #define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
 #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
-#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
 #define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
 #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
-#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
 #define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
 #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
-#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
 #define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
 #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
-#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
 #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
 #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
 #define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
 #define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
-#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
 #define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
 #define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
-#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
 #define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
 #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
-#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
 #define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
 #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
-#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
 #define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
 #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
-#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
 #define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
 #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
-#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
 #define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
 #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
-#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
 #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
 #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
 #define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
 #define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
-#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
 #define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
 #define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
-#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
 #define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
 #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
-#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
 #define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
 #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
-#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
 #define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
 #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
-#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
 #define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
 #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
-#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
 #define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
 #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
-#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
 #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
 #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
 #define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
 #define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
-#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
 #define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
 #define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
-#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
 #define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
 #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
-#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
 #define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
 #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
-#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
 #define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
 #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
-#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
 #define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
 #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
-#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
 #define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
 #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
-#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
 #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
 #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
 #define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
 #define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
-#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
 #define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
 #define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
-#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
 #define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
 #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
-#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
 #define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
 #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
-#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
 #define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
 #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
-#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
 #define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
 #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
-#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
 #define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
 #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
-#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
 #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
 #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
 #define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
 #define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
-#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
 #define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
 #define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
-#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
 #define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
 #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
-#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
 #define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
 #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
-#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
 #define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
 #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
-#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
 #define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
 #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
-#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
 #define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
 #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
-#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
 #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
 #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
 #define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
 #define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
-#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
 #define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
 #define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
-#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
 #define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
 #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
-#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
 #define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
 #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
-#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
 #define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
 #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
-#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
 #define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
 #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
-#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
 #define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
 #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
-#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
 #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
 #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
 #define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
 #define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
-#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
 #define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
 #define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
-#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
 #define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
 #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
-#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
 #define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
 #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
-#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
 #define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
 #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
-#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
 #define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
 #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
-#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
 #define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
 #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
-#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
 #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
 #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
 #define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
 #define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
-#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
 #define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
 #define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
-#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
 #define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
 #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
-#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
 #define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
 #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
-#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
 #define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
 #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
-#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
 #define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
 #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
-#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
 #define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
 #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
-#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
 #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
 #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
 #define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
 #define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
-#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
 #define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
 #define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
-#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
 #define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
 #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
-#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
 #define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
 #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
-#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
 #define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
 #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
-#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
 #define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
 #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
-#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
 #define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
 #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
-#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
 #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
 #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
 #define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
 #define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
-#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
 #define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
 #define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
-#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
 #define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
 #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
-#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
 #define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
 #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
-#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
 #define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
 #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
-#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
 #define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
 #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
-#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
 #define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
 #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
-#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
 #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
 #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
 #define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
 #define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
-#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
 #define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
 #define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
-#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
 #define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
 #define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
 #define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
 #define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
 #define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
 #define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
 #define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
 #define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
 #define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
 #define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
 #define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
 #define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
 #define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
 #define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
 #define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
 #define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
 #define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
 #define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
 #define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
 #define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
 #define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
 #define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
 #define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
 #define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
 #define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
 #define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define pSPI2_CTL                      ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */
 #define bfin_read_SPI2_CTL()           bfin_read16(SPI2_CTL)
 #define bfin_write_SPI2_CTL(val)       bfin_write16(SPI2_CTL, val)
-#define pSPI2_FLG                      ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */
 #define bfin_read_SPI2_FLG()           bfin_read16(SPI2_FLG)
 #define bfin_write_SPI2_FLG(val)       bfin_write16(SPI2_FLG, val)
-#define pSPI2_STAT                     ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */
 #define bfin_read_SPI2_STAT()          bfin_read16(SPI2_STAT)
 #define bfin_write_SPI2_STAT(val)      bfin_write16(SPI2_STAT, val)
-#define pSPI2_TDBR                     ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */
 #define bfin_read_SPI2_TDBR()          bfin_read16(SPI2_TDBR)
 #define bfin_write_SPI2_TDBR(val)      bfin_write16(SPI2_TDBR, val)
-#define pSPI2_RDBR                     ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */
 #define bfin_read_SPI2_RDBR()          bfin_read16(SPI2_RDBR)
 #define bfin_write_SPI2_RDBR(val)      bfin_write16(SPI2_RDBR, val)
-#define pSPI2_BAUD                     ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */
 #define bfin_read_SPI2_BAUD()          bfin_read16(SPI2_BAUD)
 #define bfin_write_SPI2_BAUD(val)      bfin_write16(SPI2_BAUD, val)
-#define pSPI2_SHADOW                   ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */
 #define bfin_read_SPI2_SHADOW()        bfin_read16(SPI2_SHADOW)
 #define bfin_write_SPI2_SHADOW(val)    bfin_write16(SPI2_SHADOW, val)
-#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
 #define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
-#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
 #define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
-#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
 #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
-#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
 #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
-#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
 #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
-#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
 #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
-#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
 #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
-#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
 #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
-#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
 #define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
-#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
 #define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
-#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
 #define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
-#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
 #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
-#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
 #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
-#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
 #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
-#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
 #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
-#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
 #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
-#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
 #define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
 #define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
-#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
 #define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
 #define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
-#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
 #define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
 #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
-#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
 #define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
 #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
-#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
 #define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
 #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
-#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
 #define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
 #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
-#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
 #define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
 #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
-#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
 #define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
 #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
-#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
 #define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
 #define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
-#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
 #define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
 #define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
-#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
 #define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
 #define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
-#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
 #define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
 #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
-#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
 #define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
 #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
-#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
 #define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
 #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
-#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
 #define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
 #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
-#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
 #define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
 #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
 #define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
 #define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
-#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
 #define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
 #define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
-#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
 #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
-#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
 #define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
-#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
 #define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
-#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
 #define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
 #define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
-#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
 #define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
 #define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
-#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
 #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
-#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
 #define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
-#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
 #define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
 #define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
-#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
 #define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
 #define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
-#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
 #define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
-#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
 #define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
-#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
 #define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
 #define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
-#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
 #define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
-#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
 #define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
-#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
 #define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
-#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
 #define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
-#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
 #define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
-#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
 #define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
-#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
 #define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
-#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
 #define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
-#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
 #define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
 #define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
-#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
 #define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
 #define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
-#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
 #define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
 #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
-#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
 #define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
 #define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
-#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
 #define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
-#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
 #define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
 #define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
-#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
 #define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
 #define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
-#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
 #define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
-#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
 #define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
 #define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
-#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
 #define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
 #define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
-#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
 #define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
 #define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
-#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
 #define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
 #define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
-#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
 #define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
 #define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
-#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
 #define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
 #define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
-#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
 #define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
 #define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
-#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
 #define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
 #define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
-#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
 #define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
 #define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
-#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
 #define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
 #define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
-#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
 #define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
 #define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
-#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
 #define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
 #define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
-#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
 #define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
 #define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
-#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
 #define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
 #define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
-#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
 #define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
 #define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
 #define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
 #define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
 #define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
 #define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
 #define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
 #define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
 #define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
 #define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
 #define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
 #define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
 #define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
 #define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
 #define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
-#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
 #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
 #define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
 #define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
 #define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
 #define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
 #define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
 #define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
 #define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
 #define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
 #define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
 #define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
 #define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
 #define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
 #define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
 #define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
 #define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
 #define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
 #define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
 #define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
 #define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
-#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
 #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
 #define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
 #define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
 #define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
 #define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define pUART2_DLL                     ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART2_DLL()          bfin_read16(UART2_DLL)
 #define bfin_write_UART2_DLL(val)      bfin_write16(UART2_DLL, val)
-#define pUART2_DLH                     ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART2_DLH()          bfin_read16(UART2_DLH)
 #define bfin_write_UART2_DLH(val)      bfin_write16(UART2_DLH, val)
-#define pUART2_GCTL                    ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */
 #define bfin_read_UART2_GCTL()         bfin_read16(UART2_GCTL)
 #define bfin_write_UART2_GCTL(val)     bfin_write16(UART2_GCTL, val)
-#define pUART2_LCR                     ((uint16_t volatile *)UART2_LCR) /* Line Control Register */
 #define bfin_read_UART2_LCR()          bfin_read16(UART2_LCR)
 #define bfin_write_UART2_LCR(val)      bfin_write16(UART2_LCR, val)
-#define pUART2_MCR                     ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */
 #define bfin_read_UART2_MCR()          bfin_read16(UART2_MCR)
 #define bfin_write_UART2_MCR(val)      bfin_write16(UART2_MCR, val)
-#define pUART2_LSR                     ((uint16_t volatile *)UART2_LSR) /* Line Status Register */
 #define bfin_read_UART2_LSR()          bfin_read16(UART2_LSR)
 #define bfin_write_UART2_LSR(val)      bfin_write16(UART2_LSR, val)
-#define pUART2_MSR                     ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */
 #define bfin_read_UART2_MSR()          bfin_read16(UART2_MSR)
 #define bfin_write_UART2_MSR(val)      bfin_write16(UART2_MSR, val)
-#define pUART2_SCR                     ((uint16_t volatile *)UART2_SCR) /* Scratch Register */
 #define bfin_read_UART2_SCR()          bfin_read16(UART2_SCR)
 #define bfin_write_UART2_SCR(val)      bfin_write16(UART2_SCR, val)
-#define pUART2_IER_SET                 ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART2_IER_SET()      bfin_read16(UART2_IER_SET)
 #define bfin_write_UART2_IER_SET(val)  bfin_write16(UART2_IER_SET, val)
-#define pUART2_IER_CLEAR               ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART2_IER_CLEAR()    bfin_read16(UART2_IER_CLEAR)
 #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define pUART2_THR                     ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */
 #define bfin_read_UART2_THR()          bfin_read16(UART2_THR)
 #define bfin_write_UART2_THR(val)      bfin_write16(UART2_THR, val)
-#define pUART2_RBR                     ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */
 #define bfin_read_UART2_RBR()          bfin_read16(UART2_RBR)
 #define bfin_write_UART2_RBR(val)      bfin_write16(UART2_RBR, val)
-#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
 #define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
-#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
 #define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
-#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
 #define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
 #define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
-#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
 #define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
 #define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
-#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
 #define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
 #define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
-#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
 #define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
 #define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
-#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
 #define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
 #define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
-#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
 #define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
 #define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
-#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
 #define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
 #define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
-#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
 #define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
 #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
 #define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
 #define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
-#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
 #define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
 #define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)
-#define pUSB_FADDR                     ((uint16_t volatile *)USB_FADDR) /* Function address register */
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define pUSB_POWER                     ((uint16_t volatile *)USB_POWER) /* Power management register */
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
 #define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define pUSB_INTRTX                    ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
 #define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
 #define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define pUSB_INTRRX                    ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */
 #define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
 #define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define pUSB_INTRTXE                   ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */
 #define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
 #define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define pUSB_INTRRXE                   ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */
 #define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
 #define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define pUSB_INTRUSB                   ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */
 #define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
 #define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define pUSB_INTRUSBE                  ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */
 #define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
 #define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define pUSB_FRAME                     ((uint16_t volatile *)USB_FRAME) /* USB frame number */
 #define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
 #define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define pUSB_INDEX                     ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */
 #define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
 #define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define pUSB_TESTMODE                  ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */
 #define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
 #define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define pUSB_GLOBINTR                  ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */
 #define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
 #define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define pUSB_GLOBAL_CTL                ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */
 #define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
 #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define pUSB_TX_MAX_PACKET             ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */
 #define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
 #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define pUSB_CSR0                      ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
 #define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define pUSB_TXCSR                     ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
 #define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
 #define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define pUSB_RX_MAX_PACKET             ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */
 #define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
 #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define pUSB_RXCSR                     ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */
 #define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
 #define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define pUSB_COUNT0                    ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
 #define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define pUSB_RXCOUNT                   ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
 #define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
 #define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define pUSB_TXTYPE                    ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
 #define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
 #define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define pUSB_NAKLIMIT0                 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
 #define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define pUSB_TXINTERVAL                ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
 #define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
 #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define pUSB_RXTYPE                    ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
 #define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
 #define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define pUSB_RXINTERVAL                ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
 #define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
 #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define pUSB_TXCOUNT                   ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */
 #define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
 #define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define pUSB_EP0_FIFO                  ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */
 #define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
 #define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define pUSB_EP1_FIFO                  ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */
 #define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
 #define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define pUSB_EP2_FIFO                  ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */
 #define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
 #define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define pUSB_EP3_FIFO                  ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */
 #define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
 #define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define pUSB_EP4_FIFO                  ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */
 #define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
 #define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define pUSB_EP5_FIFO                  ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */
 #define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
 #define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define pUSB_EP6_FIFO                  ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */
 #define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
 #define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define pUSB_EP7_FIFO                  ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */
 #define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
 #define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define pUSB_OTG_DEV_CTL               ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */
 #define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
 #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define pUSB_OTG_VBUS_IRQ              ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */
 #define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
 #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define pUSB_OTG_VBUS_MASK             ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */
 #define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
 #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define pUSB_LINKINFO                  ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */
 #define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
 #define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define pUSB_VPLEN                     ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */
 #define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
 #define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define pUSB_HS_EOF1                   ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */
 #define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
 #define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define pUSB_FS_EOF1                   ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */
 #define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
 #define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define pUSB_LS_EOF1                   ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */
 #define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
 #define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define pUSB_APHY_CNTRL                ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */
 #define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
 #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define pUSB_APHY_CALIB                ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */
 #define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
 #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define pUSB_APHY_CNTRL2               ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
 #define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
 #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define pUSB_PHY_TEST                  ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */
 #define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
 #define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define pUSB_PLLOSC_CTRL               ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */
 #define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
 #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define pUSB_SRP_CLKDIV                ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */
 #define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
 #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define pUSB_EP_NI0_TXMAXP             ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
 #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define pUSB_EP_NI0_TXCSR              ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
 #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define pUSB_EP_NI0_RXMAXP             ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
 #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define pUSB_EP_NI0_RXCSR              ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
 #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define pUSB_EP_NI0_RXCOUNT            ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */
 #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
 #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define pUSB_EP_NI0_TXTYPE             ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
 #define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
 #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define pUSB_EP_NI0_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */
 #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
 #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define pUSB_EP_NI0_RXTYPE             ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
 #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define pUSB_EP_NI0_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
 #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
 #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define pUSB_EP_NI0_TXCOUNT            ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
 #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define pUSB_EP_NI1_TXMAXP             ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
 #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define pUSB_EP_NI1_TXCSR              ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */
 #define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
 #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define pUSB_EP_NI1_RXMAXP             ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
 #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define pUSB_EP_NI1_RXCSR              ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
 #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define pUSB_EP_NI1_RXCOUNT            ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */
 #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
 #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define pUSB_EP_NI1_TXTYPE             ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
 #define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
 #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define pUSB_EP_NI1_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */
 #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
 #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define pUSB_EP_NI1_RXTYPE             ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
 #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define pUSB_EP_NI1_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
 #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
 #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define pUSB_EP_NI1_TXCOUNT            ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
 #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define pUSB_EP_NI2_TXMAXP             ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
 #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define pUSB_EP_NI2_TXCSR              ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */
 #define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
 #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define pUSB_EP_NI2_RXMAXP             ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
 #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define pUSB_EP_NI2_RXCSR              ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
 #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define pUSB_EP_NI2_RXCOUNT            ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */
 #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
 #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define pUSB_EP_NI2_TXTYPE             ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
 #define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
 #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define pUSB_EP_NI2_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */
 #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
 #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define pUSB_EP_NI2_RXTYPE             ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
 #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define pUSB_EP_NI2_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
 #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
 #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define pUSB_EP_NI2_TXCOUNT            ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
 #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define pUSB_EP_NI3_TXMAXP             ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
 #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define pUSB_EP_NI3_TXCSR              ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */
 #define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
 #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define pUSB_EP_NI3_RXMAXP             ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
 #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define pUSB_EP_NI3_RXCSR              ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
 #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define pUSB_EP_NI3_RXCOUNT            ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */
 #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
 #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define pUSB_EP_NI3_TXTYPE             ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
 #define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
 #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define pUSB_EP_NI3_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */
 #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
 #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define pUSB_EP_NI3_RXTYPE             ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
 #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define pUSB_EP_NI3_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
 #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
 #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define pUSB_EP_NI3_TXCOUNT            ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
 #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define pUSB_EP_NI4_TXMAXP             ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
 #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define pUSB_EP_NI4_TXCSR              ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */
 #define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
 #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define pUSB_EP_NI4_RXMAXP             ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
 #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define pUSB_EP_NI4_RXCSR              ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
 #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define pUSB_EP_NI4_RXCOUNT            ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */
 #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
 #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define pUSB_EP_NI4_TXTYPE             ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
 #define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
 #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define pUSB_EP_NI4_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */
 #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
 #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define pUSB_EP_NI4_RXTYPE             ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
 #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define pUSB_EP_NI4_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
 #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
 #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define pUSB_EP_NI4_TXCOUNT            ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
 #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define pUSB_EP_NI5_TXMAXP             ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
 #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define pUSB_EP_NI5_TXCSR              ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */
 #define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
 #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define pUSB_EP_NI5_RXMAXP             ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
 #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define pUSB_EP_NI5_RXCSR              ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
 #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define pUSB_EP_NI5_RXCOUNT            ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */
 #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
 #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define pUSB_EP_NI5_TXTYPE             ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
 #define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
 #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define pUSB_EP_NI5_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */
 #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
 #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define pUSB_EP_NI5_RXTYPE             ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
 #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define pUSB_EP_NI5_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
 #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
 #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define pUSB_EP_NI5_TXCOUNT            ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
 #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define pUSB_EP_NI6_TXMAXP             ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
 #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define pUSB_EP_NI6_TXCSR              ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */
 #define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
 #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define pUSB_EP_NI6_RXMAXP             ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
 #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define pUSB_EP_NI6_RXCSR              ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
 #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define pUSB_EP_NI6_RXCOUNT            ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */
 #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
 #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define pUSB_EP_NI6_TXTYPE             ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
 #define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
 #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define pUSB_EP_NI6_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */
 #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
 #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define pUSB_EP_NI6_RXTYPE             ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
 #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define pUSB_EP_NI6_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
 #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
 #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define pUSB_EP_NI6_TXCOUNT            ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
 #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define pUSB_EP_NI7_TXMAXP             ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
 #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define pUSB_EP_NI7_TXCSR              ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */
 #define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
 #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define pUSB_EP_NI7_RXMAXP             ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
 #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define pUSB_EP_NI7_RXCSR              ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
 #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define pUSB_EP_NI7_RXCOUNT            ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */
 #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
 #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define pUSB_EP_NI7_TXTYPE             ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
 #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define pUSB_EP_NI7_TXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */
 #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
 #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define pUSB_EP_NI7_RXTYPE             ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
 #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define pUSB_EP_NI7_RXINTERVAL         ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
 #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
 #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define pUSB_EP_NI7_TXCOUNT            ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */
 #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
 #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define pUSB_DMA_INTERRUPT             ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */
 #define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
 #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define pUSB_DMA0_CONTROL              ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */
 #define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
 #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define pUSB_DMA0_ADDRLOW              ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
 #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define pUSB_DMA0_ADDRHIGH             ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
 #define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
 #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define pUSB_DMA0_COUNTLOW             ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
 #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define pUSB_DMA0_COUNTHIGH            ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
 #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
 #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define pUSB_DMA1_CONTROL              ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */
 #define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
 #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define pUSB_DMA1_ADDRLOW              ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
 #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define pUSB_DMA1_ADDRHIGH             ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
 #define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
 #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define pUSB_DMA1_COUNTLOW             ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
 #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define pUSB_DMA1_COUNTHIGH            ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
 #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
 #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define pUSB_DMA2_CONTROL              ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */
 #define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
 #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define pUSB_DMA2_ADDRLOW              ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
 #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define pUSB_DMA2_ADDRHIGH             ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
 #define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
 #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define pUSB_DMA2_COUNTLOW             ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
 #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define pUSB_DMA2_COUNTHIGH            ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
 #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
 #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define pUSB_DMA3_CONTROL              ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */
 #define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
 #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define pUSB_DMA3_ADDRLOW              ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
 #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define pUSB_DMA3_ADDRHIGH             ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
 #define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
 #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define pUSB_DMA3_COUNTLOW             ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
 #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define pUSB_DMA3_COUNTHIGH            ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
 #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
 #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define pUSB_DMA4_CONTROL              ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */
 #define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
 #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define pUSB_DMA4_ADDRLOW              ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
 #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define pUSB_DMA4_ADDRHIGH             ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
 #define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
 #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define pUSB_DMA4_COUNTLOW             ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
 #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define pUSB_DMA4_COUNTHIGH            ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
 #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
 #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define pUSB_DMA5_CONTROL              ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */
 #define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
 #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define pUSB_DMA5_ADDRLOW              ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
 #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define pUSB_DMA5_ADDRHIGH             ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
 #define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
 #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define pUSB_DMA5_COUNTLOW             ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
 #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define pUSB_DMA5_COUNTHIGH            ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
 #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
 #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define pUSB_DMA6_CONTROL              ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */
 #define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
 #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define pUSB_DMA6_ADDRLOW              ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
 #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define pUSB_DMA6_ADDRHIGH             ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
 #define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
 #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define pUSB_DMA6_COUNTLOW             ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
 #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define pUSB_DMA6_COUNTHIGH            ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
 #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
 #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define pUSB_DMA7_CONTROL              ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */
 #define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
 #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define pUSB_DMA7_ADDRLOW              ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
 #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define pUSB_DMA7_ADDRHIGH             ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
 #define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
 #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define pUSB_DMA7_COUNTLOW             ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
 #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define pUSB_DMA7_COUNTHIGH            ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
 #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
 #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
index 306b5f1..c36cc9d 100644
--- a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h
@@ -10,313 +10,210 @@
 
 #include "ADSP-EDN-BF542-extended_cdef.h"
 
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
index 47ef6e1..ce1cae9 100644
--- a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h
@@ -10,313 +10,210 @@
 
 #include "ADSP-EDN-BF544-extended_cdef.h"
 
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
index 42d041a..0cc1717 100644
--- a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h
@@ -10,313 +10,210 @@
 
 #include "ADSP-EDN-BF547-extended_cdef.h"
 
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
index cf02834..2fcc05a 100644
--- a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h
@@ -10,313 +10,210 @@
 
 #include "ADSP-EDN-BF548-extended_cdef.h"
 
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
index 3514cef..0d34809 100644
--- a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h
@@ -10,313 +10,210 @@
 
 #include "ADSP-EDN-BF549-extended_cdef.h"
 
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
 
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
index e2c165a..482a750 100644
--- a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
@@ -10,454 +10,304 @@
 
 #include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
 
-#define pSRAM_BASE_ADDR                ((uint32_t volatile *)SRAM_BASE_ADDR)
 #define bfin_read_SRAM_BASE_ADDR()     bfin_read32(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL)
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS)
 #define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
 #define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((uint32_t volatile *)DCPLB_ADDR0)
 #define bfin_read_DCPLB_ADDR0()        bfin_read32(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_write32(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((uint32_t volatile *)DCPLB_ADDR1)
 #define bfin_read_DCPLB_ADDR1()        bfin_read32(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_write32(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((uint32_t volatile *)DCPLB_ADDR2)
 #define bfin_read_DCPLB_ADDR2()        bfin_read32(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_write32(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((uint32_t volatile *)DCPLB_ADDR3)
 #define bfin_read_DCPLB_ADDR3()        bfin_read32(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_write32(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((uint32_t volatile *)DCPLB_ADDR4)
 #define bfin_read_DCPLB_ADDR4()        bfin_read32(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_write32(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((uint32_t volatile *)DCPLB_ADDR5)
 #define bfin_read_DCPLB_ADDR5()        bfin_read32(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_write32(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((uint32_t volatile *)DCPLB_ADDR6)
 #define bfin_read_DCPLB_ADDR6()        bfin_read32(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_write32(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((uint32_t volatile *)DCPLB_ADDR7)
 #define bfin_read_DCPLB_ADDR7()        bfin_read32(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_write32(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((uint32_t volatile *)DCPLB_ADDR8)
 #define bfin_read_DCPLB_ADDR8()        bfin_read32(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_write32(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((uint32_t volatile *)DCPLB_ADDR9)
 #define bfin_read_DCPLB_ADDR9()        bfin_read32(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_write32(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((uint32_t volatile *)DCPLB_ADDR10)
 #define bfin_read_DCPLB_ADDR10()       bfin_read32(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_write32(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((uint32_t volatile *)DCPLB_ADDR11)
 #define bfin_read_DCPLB_ADDR11()       bfin_read32(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_write32(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((uint32_t volatile *)DCPLB_ADDR12)
 #define bfin_read_DCPLB_ADDR12()       bfin_read32(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_write32(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((uint32_t volatile *)DCPLB_ADDR13)
 #define bfin_read_DCPLB_ADDR13()       bfin_read32(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_write32(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((uint32_t volatile *)DCPLB_ADDR14)
 #define bfin_read_DCPLB_ADDR14()       bfin_read32(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_write32(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((uint32_t volatile *)DCPLB_ADDR15)
 #define bfin_read_DCPLB_ADDR15()       bfin_read32(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_write32(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0)
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1)
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2)
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3)
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4)
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5)
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6)
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7)
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8)
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9)
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10)
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11)
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12)
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13)
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14)
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15)
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND)
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0)
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1)
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL)
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
 #define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
 #define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((uint32_t volatile *)ICPLB_FAULT_ADDR)
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((uint32_t volatile *)ICPLB_ADDR0)
 #define bfin_read_ICPLB_ADDR0()        bfin_read32(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_write32(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((uint32_t volatile *)ICPLB_ADDR1)
 #define bfin_read_ICPLB_ADDR1()        bfin_read32(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_write32(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((uint32_t volatile *)ICPLB_ADDR2)
 #define bfin_read_ICPLB_ADDR2()        bfin_read32(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_write32(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((uint32_t volatile *)ICPLB_ADDR3)
 #define bfin_read_ICPLB_ADDR3()        bfin_read32(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_write32(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((uint32_t volatile *)ICPLB_ADDR4)
 #define bfin_read_ICPLB_ADDR4()        bfin_read32(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_write32(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((uint32_t volatile *)ICPLB_ADDR5)
 #define bfin_read_ICPLB_ADDR5()        bfin_read32(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_write32(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((uint32_t volatile *)ICPLB_ADDR6)
 #define bfin_read_ICPLB_ADDR6()        bfin_read32(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_write32(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((uint32_t volatile *)ICPLB_ADDR7)
 #define bfin_read_ICPLB_ADDR7()        bfin_read32(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_write32(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((uint32_t volatile *)ICPLB_ADDR8)
 #define bfin_read_ICPLB_ADDR8()        bfin_read32(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_write32(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((uint32_t volatile *)ICPLB_ADDR9)
 #define bfin_read_ICPLB_ADDR9()        bfin_read32(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_write32(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((uint32_t volatile *)ICPLB_ADDR10)
 #define bfin_read_ICPLB_ADDR10()       bfin_read32(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_write32(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((uint32_t volatile *)ICPLB_ADDR11)
 #define bfin_read_ICPLB_ADDR11()       bfin_read32(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_write32(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((uint32_t volatile *)ICPLB_ADDR12)
 #define bfin_read_ICPLB_ADDR12()       bfin_read32(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_write32(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((uint32_t volatile *)ICPLB_ADDR13)
 #define bfin_read_ICPLB_ADDR13()       bfin_read32(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_write32(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((uint32_t volatile *)ICPLB_ADDR14)
 #define bfin_read_ICPLB_ADDR14()       bfin_read32(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_write32(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((uint32_t volatile *)ICPLB_ADDR15)
 #define bfin_read_ICPLB_ADDR15()       bfin_read32(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_write32(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0)
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1)
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2)
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3)
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4)
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5)
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6)
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7)
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8)
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9)
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10)
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11)
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12)
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13)
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14)
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15)
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND)
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0)
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
 #define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
 #define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
-#define pSICA_SYSCR                    ((uint16_t volatile *)SICA_SYSCR)
 #define bfin_read_SICA_SYSCR()         bfin_read16(SICA_SYSCR)
 #define bfin_write_SICA_SYSCR(val)     bfin_write16(SICA_SYSCR, val)
-#define pSICA_RVECT                    ((uint16_t volatile *)SICA_RVECT)
 #define bfin_read_SICA_RVECT()         bfin_read16(SICA_RVECT)
 #define bfin_write_SICA_RVECT(val)     bfin_write16(SICA_RVECT, val)
-#define pSICA_IMASK0                   ((uint32_t volatile *)SICA_IMASK0)
 #define bfin_read_SICA_IMASK0()        bfin_read32(SICA_IMASK0)
 #define bfin_write_SICA_IMASK0(val)    bfin_write32(SICA_IMASK0, val)
-#define pSICA_IMASK1                   ((uint32_t volatile *)SICA_IMASK1)
 #define bfin_read_SICA_IMASK1()        bfin_read32(SICA_IMASK1)
 #define bfin_write_SICA_IMASK1(val)    bfin_write32(SICA_IMASK1, val)
-#define pSICA_ISR0                     ((uint32_t volatile *)SICA_ISR0)
 #define bfin_read_SICA_ISR0()          bfin_read32(SICA_ISR0)
 #define bfin_write_SICA_ISR0(val)      bfin_write32(SICA_ISR0, val)
-#define pSICA_ISR1                     ((uint32_t volatile *)SICA_ISR1)
 #define bfin_read_SICA_ISR1()          bfin_read32(SICA_ISR1)
 #define bfin_write_SICA_ISR1(val)      bfin_write32(SICA_ISR1, val)
-#define pSICA_IWR0                     ((uint32_t volatile *)SICA_IWR0)
 #define bfin_read_SICA_IWR0()          bfin_read32(SICA_IWR0)
 #define bfin_write_SICA_IWR0(val)      bfin_write32(SICA_IWR0, val)
-#define pSICA_IWR1                     ((uint32_t volatile *)SICA_IWR1)
 #define bfin_read_SICA_IWR1()          bfin_read32(SICA_IWR1)
 #define bfin_write_SICA_IWR1(val)      bfin_write32(SICA_IWR1, val)
-#define pSICA_IAR0                     ((uint32_t volatile *)SICA_IAR0)
 #define bfin_read_SICA_IAR0()          bfin_read32(SICA_IAR0)
 #define bfin_write_SICA_IAR0(val)      bfin_write32(SICA_IAR0, val)
-#define pSICA_IAR1                     ((uint32_t volatile *)SICA_IAR1)
 #define bfin_read_SICA_IAR1()          bfin_read32(SICA_IAR1)
 #define bfin_write_SICA_IAR1(val)      bfin_write32(SICA_IAR1, val)
-#define pSICA_IAR2                     ((uint32_t volatile *)SICA_IAR2)
 #define bfin_read_SICA_IAR2()          bfin_read32(SICA_IAR2)
 #define bfin_write_SICA_IAR2(val)      bfin_write32(SICA_IAR2, val)
-#define pSICA_IAR3                     ((uint32_t volatile *)SICA_IAR3)
 #define bfin_read_SICA_IAR3()          bfin_read32(SICA_IAR3)
 #define bfin_write_SICA_IAR3(val)      bfin_write32(SICA_IAR3, val)
-#define pSICA_IAR4                     ((uint32_t volatile *)SICA_IAR4)
 #define bfin_read_SICA_IAR4()          bfin_read32(SICA_IAR4)
 #define bfin_write_SICA_IAR4(val)      bfin_write32(SICA_IAR4, val)
-#define pSICA_IAR5                     ((uint32_t volatile *)SICA_IAR5)
 #define bfin_read_SICA_IAR5()          bfin_read32(SICA_IAR5)
 #define bfin_write_SICA_IAR5(val)      bfin_write32(SICA_IAR5, val)
-#define pSICA_IAR6                     ((uint32_t volatile *)SICA_IAR6)
 #define bfin_read_SICA_IAR6()          bfin_read32(SICA_IAR6)
 #define bfin_write_SICA_IAR6(val)      bfin_write32(SICA_IAR6, val)
-#define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
 #define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
 #define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
 #define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
 #define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
-#define pSICB_SYSCR                    ((uint16_t volatile *)SICB_SYSCR)
 #define bfin_read_SICB_SYSCR()         bfin_read16(SICB_SYSCR)
 #define bfin_write_SICB_SYSCR(val)     bfin_write16(SICB_SYSCR, val)
-#define pSICB_RVECT                    ((uint16_t volatile *)SICB_RVECT)
 #define bfin_read_SICB_RVECT()         bfin_read16(SICB_RVECT)
 #define bfin_write_SICB_RVECT(val)     bfin_write16(SICB_RVECT, val)
-#define pSICB_IMASK0                   ((uint32_t volatile *)SICB_IMASK0)
 #define bfin_read_SICB_IMASK0()        bfin_read32(SICB_IMASK0)
 #define bfin_write_SICB_IMASK0(val)    bfin_write32(SICB_IMASK0, val)
-#define pSICB_IMASK1                   ((uint32_t volatile *)SICB_IMASK1)
 #define bfin_read_SICB_IMASK1()        bfin_read32(SICB_IMASK1)
 #define bfin_write_SICB_IMASK1(val)    bfin_write32(SICB_IMASK1, val)
-#define pSICB_ISR0                     ((uint32_t volatile *)SICB_ISR0)
 #define bfin_read_SICB_ISR0()          bfin_read32(SICB_ISR0)
 #define bfin_write_SICB_ISR0(val)      bfin_write32(SICB_ISR0, val)
-#define pSICB_ISR1                     ((uint32_t volatile *)SICB_ISR1)
 #define bfin_read_SICB_ISR1()          bfin_read32(SICB_ISR1)
 #define bfin_write_SICB_ISR1(val)      bfin_write32(SICB_ISR1, val)
-#define pSICB_IWR0                     ((uint32_t volatile *)SICB_IWR0)
 #define bfin_read_SICB_IWR0()          bfin_read32(SICB_IWR0)
 #define bfin_write_SICB_IWR0(val)      bfin_write32(SICB_IWR0, val)
-#define pSICB_IWR1                     ((uint32_t volatile *)SICB_IWR1)
 #define bfin_read_SICB_IWR1()          bfin_read32(SICB_IWR1)
 #define bfin_write_SICB_IWR1(val)      bfin_write32(SICB_IWR1, val)
-#define pSICB_IAR0                     ((uint32_t volatile *)SICB_IAR0)
 #define bfin_read_SICB_IAR0()          bfin_read32(SICB_IAR0)
 #define bfin_write_SICB_IAR0(val)      bfin_write32(SICB_IAR0, val)
-#define pSICB_IAR1                     ((uint32_t volatile *)SICB_IAR1)
 #define bfin_read_SICB_IAR1()          bfin_read32(SICB_IAR1)
 #define bfin_write_SICB_IAR1(val)      bfin_write32(SICB_IAR1, val)
-#define pSICB_IAR2                     ((uint32_t volatile *)SICB_IAR2)
 #define bfin_read_SICB_IAR2()          bfin_read32(SICB_IAR2)
 #define bfin_write_SICB_IAR2(val)      bfin_write32(SICB_IAR2, val)
-#define pSICB_IAR3                     ((uint32_t volatile *)SICB_IAR3)
 #define bfin_read_SICB_IAR3()          bfin_read32(SICB_IAR3)
 #define bfin_write_SICB_IAR3(val)      bfin_write32(SICB_IAR3, val)
-#define pSICB_IAR4                     ((uint32_t volatile *)SICB_IAR4)
 #define bfin_read_SICB_IAR4()          bfin_read32(SICB_IAR4)
 #define bfin_write_SICB_IAR4(val)      bfin_write32(SICB_IAR4, val)
-#define pSICB_IAR5                     ((uint32_t volatile *)SICB_IAR5)
 #define bfin_read_SICB_IAR5()          bfin_read32(SICB_IAR5)
 #define bfin_write_SICB_IAR5(val)      bfin_write32(SICB_IAR5, val)
-#define pSICB_IAR6                     ((uint32_t volatile *)SICB_IAR6)
 #define bfin_read_SICB_IAR6()          bfin_read32(SICB_IAR6)
 #define bfin_write_SICB_IAR6(val)      bfin_write32(SICB_IAR6, val)
-#define pSICB_IAR7                     ((uint32_t volatile *)SICB_IAR7)
 #define bfin_read_SICB_IAR7()          bfin_read32(SICB_IAR7)
 #define bfin_write_SICB_IAR7(val)      bfin_write32(SICB_IAR7, val)
-#define pPPI0_CONTROL                  ((uint16_t volatile *)PPI0_CONTROL)
 #define bfin_read_PPI0_CONTROL()       bfin_read16(PPI0_CONTROL)
 #define bfin_write_PPI0_CONTROL(val)   bfin_write16(PPI0_CONTROL, val)
-#define pPPI0_STATUS                   ((uint16_t volatile *)PPI0_STATUS)
 #define bfin_read_PPI0_STATUS()        bfin_read16(PPI0_STATUS)
 #define bfin_write_PPI0_STATUS(val)    bfin_write16(PPI0_STATUS, val)
-#define pPPI0_DELAY                    ((uint16_t volatile *)PPI0_DELAY)
 #define bfin_read_PPI0_DELAY()         bfin_read16(PPI0_DELAY)
 #define bfin_write_PPI0_DELAY(val)     bfin_write16(PPI0_DELAY, val)
-#define pPPI0_COUNT                    ((uint16_t volatile *)PPI0_COUNT)
 #define bfin_read_PPI0_COUNT()         bfin_read16(PPI0_COUNT)
 #define bfin_write_PPI0_COUNT(val)     bfin_write16(PPI0_COUNT, val)
-#define pPPI0_FRAME                    ((uint16_t volatile *)PPI0_FRAME)
 #define bfin_read_PPI0_FRAME()         bfin_read16(PPI0_FRAME)
 #define bfin_write_PPI0_FRAME(val)     bfin_write16(PPI0_FRAME, val)
-#define pPPI1_CONTROL                  ((uint16_t volatile *)PPI1_CONTROL)
 #define bfin_read_PPI1_CONTROL()       bfin_read16(PPI1_CONTROL)
 #define bfin_write_PPI1_CONTROL(val)   bfin_write16(PPI1_CONTROL, val)
-#define pPPI1_STATUS                   ((uint16_t volatile *)PPI1_STATUS)
 #define bfin_read_PPI1_STATUS()        bfin_read16(PPI1_STATUS)
 #define bfin_write_PPI1_STATUS(val)    bfin_write16(PPI1_STATUS, val)
-#define pPPI1_DELAY                    ((uint16_t volatile *)PPI1_DELAY)
 #define bfin_read_PPI1_DELAY()         bfin_read16(PPI1_DELAY)
 #define bfin_write_PPI1_DELAY(val)     bfin_write16(PPI1_DELAY, val)
-#define pPPI1_COUNT                    ((uint16_t volatile *)PPI1_COUNT)
 #define bfin_read_PPI1_COUNT()         bfin_read16(PPI1_COUNT)
 #define bfin_write_PPI1_COUNT(val)     bfin_write16(PPI1_COUNT, val)
-#define pPPI1_FRAME                    ((uint16_t volatile *)PPI1_FRAME)
 #define bfin_read_PPI1_FRAME()         bfin_read16(PPI1_FRAME)
 #define bfin_write_PPI1_FRAME(val)     bfin_write16(PPI1_FRAME, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL)
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT)
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((uint32_t volatile *)TBUF)
 #define bfin_read_TBUF()               bfin_read32(TBUF)
 #define bfin_write_TBUF(val)           bfin_write32(TBUF, val)
-#define pPFCTL                         ((uint32_t volatile *)PFCTL)
 #define bfin_read_PFCTL()              bfin_read32(PFCTL)
 #define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
 #define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
 #define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
 #define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
 #define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define pSRAM_BASE_ADDR_CORE_A         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A)
 #define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
 #define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
-#define pSRAM_BASE_ADDR_CORE_B         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B)
 #define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
 #define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
-#define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pUART_THR                      ((uint16_t volatile *)UART_THR)
 #define bfin_read_UART_THR()           bfin_read16(UART_THR)
 #define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
-#define pUART_RBR                      ((uint16_t volatile *)UART_RBR)
 #define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
 #define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
-#define pUART_DLL                      ((uint16_t volatile *)UART_DLL)
 #define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
 #define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
-#define pUART_DLH                      ((uint16_t volatile *)UART_DLH)
 #define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
 #define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
-#define pUART_IER                      ((uint16_t volatile *)UART_IER)
 #define bfin_read_UART_IER()           bfin_read16(UART_IER)
 #define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
-#define pUART_IIR                      ((uint16_t volatile *)UART_IIR)
 #define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
 #define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
-#define pUART_LCR                      ((uint16_t volatile *)UART_LCR)
 #define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
 #define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
-#define pUART_MCR                      ((uint16_t volatile *)UART_MCR)
 #define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
 #define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
-#define pUART_LSR                      ((uint16_t volatile *)UART_LSR)
 #define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
 #define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
-#define pUART_MSR                      ((uint16_t volatile *)UART_MSR)
 #define bfin_read_UART_MSR()           bfin_read16(UART_MSR)
 #define bfin_write_UART_MSR(val)       bfin_write16(UART_MSR, val)
-#define pUART_SCR                      ((uint16_t volatile *)UART_SCR)
 #define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
 #define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
-#define pUART_GCTL                     ((uint16_t volatile *)UART_GCTL)
 #define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
 #define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
-#define pUART_GBL                      ((uint16_t volatile *)UART_GBL)
 #define bfin_read_UART_GBL()           bfin_read16(UART_GBL)
 #define bfin_write_UART_GBL(val)       bfin_write16(UART_GBL, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL)
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0)
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1)
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL)
 #define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 #define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL                   ((uint32_t volatile *)EBIU_SDBCTL)
 #define bfin_read_EBIU_SDBCTL()        bfin_read32(EBIU_SDBCTL)
 #define bfin_write_EBIU_SDBCTL(val)    bfin_write32(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC)
 #define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT)
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
 
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
index 43f3850..a78dfe8 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
@@ -6,1982 +6,1322 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
 #define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
 
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL)
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV)
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL)
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT)
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT)
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL)
 #define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG)
 #define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT)
 #define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR)
 #define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR)
 #define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD)
 #define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW)
 #define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define pWDOGA_CTL                     ((uint16_t volatile *)WDOGA_CTL)
 #define bfin_read_WDOGA_CTL()          bfin_read16(WDOGA_CTL)
 #define bfin_write_WDOGA_CTL(val)      bfin_write16(WDOGA_CTL, val)
-#define pWDOGA_CNT                     ((uint32_t volatile *)WDOGA_CNT)
 #define bfin_read_WDOGA_CNT()          bfin_read32(WDOGA_CNT)
 #define bfin_write_WDOGA_CNT(val)      bfin_write32(WDOGA_CNT, val)
-#define pWDOGA_STAT                    ((uint32_t volatile *)WDOGA_STAT)
 #define bfin_read_WDOGA_STAT()         bfin_read32(WDOGA_STAT)
 #define bfin_write_WDOGA_STAT(val)     bfin_write32(WDOGA_STAT, val)
-#define pWDOGB_CTL                     ((uint16_t volatile *)WDOGB_CTL)
 #define bfin_read_WDOGB_CTL()          bfin_read16(WDOGB_CTL)
 #define bfin_write_WDOGB_CTL(val)      bfin_write16(WDOGB_CTL, val)
-#define pWDOGB_CNT                     ((uint32_t volatile *)WDOGB_CNT)
 #define bfin_read_WDOGB_CNT()          bfin_read32(WDOGB_CNT)
 #define bfin_write_WDOGB_CNT(val)      bfin_write32(WDOGB_CNT, val)
-#define pWDOGB_STAT                    ((uint32_t volatile *)WDOGB_STAT)
 #define bfin_read_WDOGB_STAT()         bfin_read32(WDOGB_STAT)
 #define bfin_write_WDOGB_STAT(val)     bfin_write32(WDOGB_STAT, val)
-#define pDMA1_TC_PER                   ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */
 #define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
 #define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
-#define pDMA1_TC_CNT                   ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */
 #define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
 #define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
-#define pDMA1_0_CONFIG                 ((uint16_t volatile *)DMA1_0_CONFIG)
 #define bfin_read_DMA1_0_CONFIG()      bfin_read16(DMA1_0_CONFIG)
 #define bfin_write_DMA1_0_CONFIG(val)  bfin_write16(DMA1_0_CONFIG, val)
-#define pDMA1_0_NEXT_DESC_PTR          ((void * volatile *)DMA1_0_NEXT_DESC_PTR)
 #define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
 #define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
-#define pDMA1_0_START_ADDR             ((void * volatile *)DMA1_0_START_ADDR)
 #define bfin_read_DMA1_0_START_ADDR()  bfin_readPTR(DMA1_0_START_ADDR)
 #define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
-#define pDMA1_0_X_COUNT                ((uint16_t volatile *)DMA1_0_X_COUNT)
 #define bfin_read_DMA1_0_X_COUNT()     bfin_read16(DMA1_0_X_COUNT)
 #define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
-#define pDMA1_0_Y_COUNT                ((uint16_t volatile *)DMA1_0_Y_COUNT)
 #define bfin_read_DMA1_0_Y_COUNT()     bfin_read16(DMA1_0_Y_COUNT)
 #define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
-#define pDMA1_0_X_MODIFY               ((uint16_t volatile *)DMA1_0_X_MODIFY)
 #define bfin_read_DMA1_0_X_MODIFY()    bfin_read16(DMA1_0_X_MODIFY)
 #define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
-#define pDMA1_0_Y_MODIFY               ((uint16_t volatile *)DMA1_0_Y_MODIFY)
 #define bfin_read_DMA1_0_Y_MODIFY()    bfin_read16(DMA1_0_Y_MODIFY)
 #define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
-#define pDMA1_0_CURR_DESC_PTR          ((void * volatile *)DMA1_0_CURR_DESC_PTR)
 #define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
 #define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
-#define pDMA1_0_CURR_ADDR              ((void * volatile *)DMA1_0_CURR_ADDR)
 #define bfin_read_DMA1_0_CURR_ADDR()   bfin_readPTR(DMA1_0_CURR_ADDR)
 #define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
-#define pDMA1_0_CURR_X_COUNT           ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
 #define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
 #define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
-#define pDMA1_0_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)
 #define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
 #define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
-#define pDMA1_0_IRQ_STATUS             ((uint16_t volatile *)DMA1_0_IRQ_STATUS)
 #define bfin_read_DMA1_0_IRQ_STATUS()  bfin_read16(DMA1_0_IRQ_STATUS)
 #define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
-#define pDMA1_0_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)
 #define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
 #define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
-#define pDMA1_1_CONFIG                 ((uint16_t volatile *)DMA1_1_CONFIG)
 #define bfin_read_DMA1_1_CONFIG()      bfin_read16(DMA1_1_CONFIG)
 #define bfin_write_DMA1_1_CONFIG(val)  bfin_write16(DMA1_1_CONFIG, val)
-#define pDMA1_1_NEXT_DESC_PTR          ((void * volatile *)DMA1_1_NEXT_DESC_PTR)
 #define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
-#define pDMA1_1_START_ADDR             ((void * volatile *)DMA1_1_START_ADDR)
 #define bfin_read_DMA1_1_START_ADDR()  bfin_readPTR(DMA1_1_START_ADDR)
 #define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
-#define pDMA1_1_X_COUNT                ((uint16_t volatile *)DMA1_1_X_COUNT)
 #define bfin_read_DMA1_1_X_COUNT()     bfin_read16(DMA1_1_X_COUNT)
 #define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
-#define pDMA1_1_Y_COUNT                ((uint16_t volatile *)DMA1_1_Y_COUNT)
 #define bfin_read_DMA1_1_Y_COUNT()     bfin_read16(DMA1_1_Y_COUNT)
 #define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
-#define pDMA1_1_X_MODIFY               ((uint16_t volatile *)DMA1_1_X_MODIFY)
 #define bfin_read_DMA1_1_X_MODIFY()    bfin_read16(DMA1_1_X_MODIFY)
 #define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
-#define pDMA1_1_Y_MODIFY               ((uint16_t volatile *)DMA1_1_Y_MODIFY)
 #define bfin_read_DMA1_1_Y_MODIFY()    bfin_read16(DMA1_1_Y_MODIFY)
 #define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
-#define pDMA1_1_CURR_DESC_PTR          ((void * volatile *)DMA1_1_CURR_DESC_PTR)
 #define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
 #define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
-#define pDMA1_1_CURR_ADDR              ((void * volatile *)DMA1_1_CURR_ADDR)
 #define bfin_read_DMA1_1_CURR_ADDR()   bfin_readPTR(DMA1_1_CURR_ADDR)
 #define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
-#define pDMA1_1_CURR_X_COUNT           ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
 #define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
 #define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
-#define pDMA1_1_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)
 #define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
 #define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
-#define pDMA1_1_IRQ_STATUS             ((uint16_t volatile *)DMA1_1_IRQ_STATUS)
 #define bfin_read_DMA1_1_IRQ_STATUS()  bfin_read16(DMA1_1_IRQ_STATUS)
 #define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
-#define pDMA1_1_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)
 #define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
-#define pDMA1_2_CONFIG                 ((uint16_t volatile *)DMA1_2_CONFIG)
 #define bfin_read_DMA1_2_CONFIG()      bfin_read16(DMA1_2_CONFIG)
 #define bfin_write_DMA1_2_CONFIG(val)  bfin_write16(DMA1_2_CONFIG, val)
-#define pDMA1_2_NEXT_DESC_PTR          ((void * volatile *)DMA1_2_NEXT_DESC_PTR)
 #define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
 #define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
-#define pDMA1_2_START_ADDR             ((void * volatile *)DMA1_2_START_ADDR)
 #define bfin_read_DMA1_2_START_ADDR()  bfin_readPTR(DMA1_2_START_ADDR)
 #define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
-#define pDMA1_2_X_COUNT                ((uint16_t volatile *)DMA1_2_X_COUNT)
 #define bfin_read_DMA1_2_X_COUNT()     bfin_read16(DMA1_2_X_COUNT)
 #define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
-#define pDMA1_2_Y_COUNT                ((uint16_t volatile *)DMA1_2_Y_COUNT)
 #define bfin_read_DMA1_2_Y_COUNT()     bfin_read16(DMA1_2_Y_COUNT)
 #define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
-#define pDMA1_2_X_MODIFY               ((uint16_t volatile *)DMA1_2_X_MODIFY)
 #define bfin_read_DMA1_2_X_MODIFY()    bfin_read16(DMA1_2_X_MODIFY)
 #define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
-#define pDMA1_2_Y_MODIFY               ((uint16_t volatile *)DMA1_2_Y_MODIFY)
 #define bfin_read_DMA1_2_Y_MODIFY()    bfin_read16(DMA1_2_Y_MODIFY)
 #define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
-#define pDMA1_2_CURR_DESC_PTR          ((void * volatile *)DMA1_2_CURR_DESC_PTR)
 #define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
 #define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
-#define pDMA1_2_CURR_ADDR              ((void * volatile *)DMA1_2_CURR_ADDR)
 #define bfin_read_DMA1_2_CURR_ADDR()   bfin_readPTR(DMA1_2_CURR_ADDR)
 #define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
-#define pDMA1_2_CURR_X_COUNT           ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
 #define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
 #define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
-#define pDMA1_2_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)
 #define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
 #define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
-#define pDMA1_2_IRQ_STATUS             ((uint16_t volatile *)DMA1_2_IRQ_STATUS)
 #define bfin_read_DMA1_2_IRQ_STATUS()  bfin_read16(DMA1_2_IRQ_STATUS)
 #define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
-#define pDMA1_2_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)
 #define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
 #define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
-#define pDMA1_3_CONFIG                 ((uint16_t volatile *)DMA1_3_CONFIG)
 #define bfin_read_DMA1_3_CONFIG()      bfin_read16(DMA1_3_CONFIG)
 #define bfin_write_DMA1_3_CONFIG(val)  bfin_write16(DMA1_3_CONFIG, val)
-#define pDMA1_3_NEXT_DESC_PTR          ((void * volatile *)DMA1_3_NEXT_DESC_PTR)
 #define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
 #define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
-#define pDMA1_3_START_ADDR             ((void * volatile *)DMA1_3_START_ADDR)
 #define bfin_read_DMA1_3_START_ADDR()  bfin_readPTR(DMA1_3_START_ADDR)
 #define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
-#define pDMA1_3_X_COUNT                ((uint16_t volatile *)DMA1_3_X_COUNT)
 #define bfin_read_DMA1_3_X_COUNT()     bfin_read16(DMA1_3_X_COUNT)
 #define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
-#define pDMA1_3_Y_COUNT                ((uint16_t volatile *)DMA1_3_Y_COUNT)
 #define bfin_read_DMA1_3_Y_COUNT()     bfin_read16(DMA1_3_Y_COUNT)
 #define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
-#define pDMA1_3_X_MODIFY               ((uint16_t volatile *)DMA1_3_X_MODIFY)
 #define bfin_read_DMA1_3_X_MODIFY()    bfin_read16(DMA1_3_X_MODIFY)
 #define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
-#define pDMA1_3_Y_MODIFY               ((uint16_t volatile *)DMA1_3_Y_MODIFY)
 #define bfin_read_DMA1_3_Y_MODIFY()    bfin_read16(DMA1_3_Y_MODIFY)
 #define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
-#define pDMA1_3_CURR_DESC_PTR          ((void * volatile *)DMA1_3_CURR_DESC_PTR)
 #define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
 #define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
-#define pDMA1_3_CURR_ADDR              ((void * volatile *)DMA1_3_CURR_ADDR)
 #define bfin_read_DMA1_3_CURR_ADDR()   bfin_readPTR(DMA1_3_CURR_ADDR)
 #define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
-#define pDMA1_3_CURR_X_COUNT           ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
 #define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
 #define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
-#define pDMA1_3_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)
 #define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
 #define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
-#define pDMA1_3_IRQ_STATUS             ((uint16_t volatile *)DMA1_3_IRQ_STATUS)
 #define bfin_read_DMA1_3_IRQ_STATUS()  bfin_read16(DMA1_3_IRQ_STATUS)
 #define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
-#define pDMA1_3_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)
 #define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
 #define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
-#define pDMA1_4_CONFIG                 ((uint16_t volatile *)DMA1_4_CONFIG)
 #define bfin_read_DMA1_4_CONFIG()      bfin_read16(DMA1_4_CONFIG)
 #define bfin_write_DMA1_4_CONFIG(val)  bfin_write16(DMA1_4_CONFIG, val)
-#define pDMA1_4_NEXT_DESC_PTR          ((void * volatile *)DMA1_4_NEXT_DESC_PTR)
 #define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
 #define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
-#define pDMA1_4_START_ADDR             ((void * volatile *)DMA1_4_START_ADDR)
 #define bfin_read_DMA1_4_START_ADDR()  bfin_readPTR(DMA1_4_START_ADDR)
 #define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
-#define pDMA1_4_X_COUNT                ((uint16_t volatile *)DMA1_4_X_COUNT)
 #define bfin_read_DMA1_4_X_COUNT()     bfin_read16(DMA1_4_X_COUNT)
 #define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
-#define pDMA1_4_Y_COUNT                ((uint16_t volatile *)DMA1_4_Y_COUNT)
 #define bfin_read_DMA1_4_Y_COUNT()     bfin_read16(DMA1_4_Y_COUNT)
 #define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
-#define pDMA1_4_X_MODIFY               ((uint16_t volatile *)DMA1_4_X_MODIFY)
 #define bfin_read_DMA1_4_X_MODIFY()    bfin_read16(DMA1_4_X_MODIFY)
 #define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
-#define pDMA1_4_Y_MODIFY               ((uint16_t volatile *)DMA1_4_Y_MODIFY)
 #define bfin_read_DMA1_4_Y_MODIFY()    bfin_read16(DMA1_4_Y_MODIFY)
 #define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
-#define pDMA1_4_CURR_DESC_PTR          ((void * volatile *)DMA1_4_CURR_DESC_PTR)
 #define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
 #define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
-#define pDMA1_4_CURR_ADDR              ((void * volatile *)DMA1_4_CURR_ADDR)
 #define bfin_read_DMA1_4_CURR_ADDR()   bfin_readPTR(DMA1_4_CURR_ADDR)
 #define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
-#define pDMA1_4_CURR_X_COUNT           ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
 #define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
 #define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
-#define pDMA1_4_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)
 #define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
 #define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
-#define pDMA1_4_IRQ_STATUS             ((uint16_t volatile *)DMA1_4_IRQ_STATUS)
 #define bfin_read_DMA1_4_IRQ_STATUS()  bfin_read16(DMA1_4_IRQ_STATUS)
 #define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
-#define pDMA1_4_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)
 #define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
 #define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
-#define pDMA1_5_CONFIG                 ((uint16_t volatile *)DMA1_5_CONFIG)
 #define bfin_read_DMA1_5_CONFIG()      bfin_read16(DMA1_5_CONFIG)
 #define bfin_write_DMA1_5_CONFIG(val)  bfin_write16(DMA1_5_CONFIG, val)
-#define pDMA1_5_NEXT_DESC_PTR          ((void * volatile *)DMA1_5_NEXT_DESC_PTR)
 #define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
 #define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
-#define pDMA1_5_START_ADDR             ((void * volatile *)DMA1_5_START_ADDR)
 #define bfin_read_DMA1_5_START_ADDR()  bfin_readPTR(DMA1_5_START_ADDR)
 #define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
-#define pDMA1_5_X_COUNT                ((uint16_t volatile *)DMA1_5_X_COUNT)
 #define bfin_read_DMA1_5_X_COUNT()     bfin_read16(DMA1_5_X_COUNT)
 #define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
-#define pDMA1_5_Y_COUNT                ((uint16_t volatile *)DMA1_5_Y_COUNT)
 #define bfin_read_DMA1_5_Y_COUNT()     bfin_read16(DMA1_5_Y_COUNT)
 #define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
-#define pDMA1_5_X_MODIFY               ((uint16_t volatile *)DMA1_5_X_MODIFY)
 #define bfin_read_DMA1_5_X_MODIFY()    bfin_read16(DMA1_5_X_MODIFY)
 #define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
-#define pDMA1_5_Y_MODIFY               ((uint16_t volatile *)DMA1_5_Y_MODIFY)
 #define bfin_read_DMA1_5_Y_MODIFY()    bfin_read16(DMA1_5_Y_MODIFY)
 #define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
-#define pDMA1_5_CURR_DESC_PTR          ((void * volatile *)DMA1_5_CURR_DESC_PTR)
 #define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
 #define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
-#define pDMA1_5_CURR_ADDR              ((void * volatile *)DMA1_5_CURR_ADDR)
 #define bfin_read_DMA1_5_CURR_ADDR()   bfin_readPTR(DMA1_5_CURR_ADDR)
 #define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
-#define pDMA1_5_CURR_X_COUNT           ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
 #define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
 #define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
-#define pDMA1_5_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)
 #define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
 #define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
-#define pDMA1_5_IRQ_STATUS             ((uint16_t volatile *)DMA1_5_IRQ_STATUS)
 #define bfin_read_DMA1_5_IRQ_STATUS()  bfin_read16(DMA1_5_IRQ_STATUS)
 #define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
-#define pDMA1_5_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)
 #define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
 #define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
-#define pDMA1_6_CONFIG                 ((uint16_t volatile *)DMA1_6_CONFIG)
 #define bfin_read_DMA1_6_CONFIG()      bfin_read16(DMA1_6_CONFIG)
 #define bfin_write_DMA1_6_CONFIG(val)  bfin_write16(DMA1_6_CONFIG, val)
-#define pDMA1_6_NEXT_DESC_PTR          ((void * volatile *)DMA1_6_NEXT_DESC_PTR)
 #define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
 #define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
-#define pDMA1_6_START_ADDR             ((void * volatile *)DMA1_6_START_ADDR)
 #define bfin_read_DMA1_6_START_ADDR()  bfin_readPTR(DMA1_6_START_ADDR)
 #define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
-#define pDMA1_6_X_COUNT                ((uint16_t volatile *)DMA1_6_X_COUNT)
 #define bfin_read_DMA1_6_X_COUNT()     bfin_read16(DMA1_6_X_COUNT)
 #define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
-#define pDMA1_6_Y_COUNT                ((uint16_t volatile *)DMA1_6_Y_COUNT)
 #define bfin_read_DMA1_6_Y_COUNT()     bfin_read16(DMA1_6_Y_COUNT)
 #define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
-#define pDMA1_6_X_MODIFY               ((uint16_t volatile *)DMA1_6_X_MODIFY)
 #define bfin_read_DMA1_6_X_MODIFY()    bfin_read16(DMA1_6_X_MODIFY)
 #define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
-#define pDMA1_6_Y_MODIFY               ((uint16_t volatile *)DMA1_6_Y_MODIFY)
 #define bfin_read_DMA1_6_Y_MODIFY()    bfin_read16(DMA1_6_Y_MODIFY)
 #define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
-#define pDMA1_6_CURR_DESC_PTR          ((void * volatile *)DMA1_6_CURR_DESC_PTR)
 #define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
 #define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
-#define pDMA1_6_CURR_ADDR              ((void * volatile *)DMA1_6_CURR_ADDR)
 #define bfin_read_DMA1_6_CURR_ADDR()   bfin_readPTR(DMA1_6_CURR_ADDR)
 #define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
-#define pDMA1_6_CURR_X_COUNT           ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
 #define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
 #define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
-#define pDMA1_6_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)
 #define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
 #define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
-#define pDMA1_6_IRQ_STATUS             ((uint16_t volatile *)DMA1_6_IRQ_STATUS)
 #define bfin_read_DMA1_6_IRQ_STATUS()  bfin_read16(DMA1_6_IRQ_STATUS)
 #define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
-#define pDMA1_6_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)
 #define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
 #define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
-#define pDMA1_7_CONFIG                 ((uint16_t volatile *)DMA1_7_CONFIG)
 #define bfin_read_DMA1_7_CONFIG()      bfin_read16(DMA1_7_CONFIG)
 #define bfin_write_DMA1_7_CONFIG(val)  bfin_write16(DMA1_7_CONFIG, val)
-#define pDMA1_7_NEXT_DESC_PTR          ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
 #define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
 #define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
-#define pDMA1_7_START_ADDR             ((void * volatile *)DMA1_7_START_ADDR)
 #define bfin_read_DMA1_7_START_ADDR()  bfin_readPTR(DMA1_7_START_ADDR)
 #define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
-#define pDMA1_7_X_COUNT                ((uint16_t volatile *)DMA1_7_X_COUNT)
 #define bfin_read_DMA1_7_X_COUNT()     bfin_read16(DMA1_7_X_COUNT)
 #define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
-#define pDMA1_7_Y_COUNT                ((uint16_t volatile *)DMA1_7_Y_COUNT)
 #define bfin_read_DMA1_7_Y_COUNT()     bfin_read16(DMA1_7_Y_COUNT)
 #define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
-#define pDMA1_7_X_MODIFY               ((uint16_t volatile *)DMA1_7_X_MODIFY)
 #define bfin_read_DMA1_7_X_MODIFY()    bfin_read16(DMA1_7_X_MODIFY)
 #define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
-#define pDMA1_7_Y_MODIFY               ((uint16_t volatile *)DMA1_7_Y_MODIFY)
 #define bfin_read_DMA1_7_Y_MODIFY()    bfin_read16(DMA1_7_Y_MODIFY)
 #define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
-#define pDMA1_7_CURR_DESC_PTR          ((void * volatile *)DMA1_7_CURR_DESC_PTR)
 #define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
 #define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
-#define pDMA1_7_CURR_ADDR              ((void * volatile *)DMA1_7_CURR_ADDR)
 #define bfin_read_DMA1_7_CURR_ADDR()   bfin_readPTR(DMA1_7_CURR_ADDR)
 #define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
-#define pDMA1_7_CURR_X_COUNT           ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
 #define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
 #define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
-#define pDMA1_7_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)
 #define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
 #define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
-#define pDMA1_7_IRQ_STATUS             ((uint16_t volatile *)DMA1_7_IRQ_STATUS)
 #define bfin_read_DMA1_7_IRQ_STATUS()  bfin_read16(DMA1_7_IRQ_STATUS)
 #define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
-#define pDMA1_7_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)
 #define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
 #define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
-#define pDMA1_8_CONFIG                 ((uint16_t volatile *)DMA1_8_CONFIG)
 #define bfin_read_DMA1_8_CONFIG()      bfin_read16(DMA1_8_CONFIG)
 #define bfin_write_DMA1_8_CONFIG(val)  bfin_write16(DMA1_8_CONFIG, val)
-#define pDMA1_8_NEXT_DESC_PTR          ((void * volatile *)DMA1_8_NEXT_DESC_PTR)
 #define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
 #define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
-#define pDMA1_8_START_ADDR             ((void * volatile *)DMA1_8_START_ADDR)
 #define bfin_read_DMA1_8_START_ADDR()  bfin_readPTR(DMA1_8_START_ADDR)
 #define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
-#define pDMA1_8_X_COUNT                ((uint16_t volatile *)DMA1_8_X_COUNT)
 #define bfin_read_DMA1_8_X_COUNT()     bfin_read16(DMA1_8_X_COUNT)
 #define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
-#define pDMA1_8_Y_COUNT                ((uint16_t volatile *)DMA1_8_Y_COUNT)
 #define bfin_read_DMA1_8_Y_COUNT()     bfin_read16(DMA1_8_Y_COUNT)
 #define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
-#define pDMA1_8_X_MODIFY               ((uint16_t volatile *)DMA1_8_X_MODIFY)
 #define bfin_read_DMA1_8_X_MODIFY()    bfin_read16(DMA1_8_X_MODIFY)
 #define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
-#define pDMA1_8_Y_MODIFY               ((uint16_t volatile *)DMA1_8_Y_MODIFY)
 #define bfin_read_DMA1_8_Y_MODIFY()    bfin_read16(DMA1_8_Y_MODIFY)
 #define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
-#define pDMA1_8_CURR_DESC_PTR          ((void * volatile *)DMA1_8_CURR_DESC_PTR)
 #define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
 #define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
-#define pDMA1_8_CURR_ADDR              ((void * volatile *)DMA1_8_CURR_ADDR)
 #define bfin_read_DMA1_8_CURR_ADDR()   bfin_readPTR(DMA1_8_CURR_ADDR)
 #define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
-#define pDMA1_8_CURR_X_COUNT           ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
 #define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
 #define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
-#define pDMA1_8_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)
 #define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
 #define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
-#define pDMA1_8_IRQ_STATUS             ((uint16_t volatile *)DMA1_8_IRQ_STATUS)
 #define bfin_read_DMA1_8_IRQ_STATUS()  bfin_read16(DMA1_8_IRQ_STATUS)
 #define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
-#define pDMA1_8_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)
 #define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
 #define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
-#define pDMA1_9_CONFIG                 ((uint16_t volatile *)DMA1_9_CONFIG)
 #define bfin_read_DMA1_9_CONFIG()      bfin_read16(DMA1_9_CONFIG)
 #define bfin_write_DMA1_9_CONFIG(val)  bfin_write16(DMA1_9_CONFIG, val)
-#define pDMA1_9_NEXT_DESC_PTR          ((void * volatile *)DMA1_9_NEXT_DESC_PTR)
 #define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
 #define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
-#define pDMA1_9_START_ADDR             ((void * volatile *)DMA1_9_START_ADDR)
 #define bfin_read_DMA1_9_START_ADDR()  bfin_readPTR(DMA1_9_START_ADDR)
 #define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
-#define pDMA1_9_X_COUNT                ((uint16_t volatile *)DMA1_9_X_COUNT)
 #define bfin_read_DMA1_9_X_COUNT()     bfin_read16(DMA1_9_X_COUNT)
 #define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
-#define pDMA1_9_Y_COUNT                ((uint16_t volatile *)DMA1_9_Y_COUNT)
 #define bfin_read_DMA1_9_Y_COUNT()     bfin_read16(DMA1_9_Y_COUNT)
 #define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
-#define pDMA1_9_X_MODIFY               ((uint16_t volatile *)DMA1_9_X_MODIFY)
 #define bfin_read_DMA1_9_X_MODIFY()    bfin_read16(DMA1_9_X_MODIFY)
 #define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
-#define pDMA1_9_Y_MODIFY               ((uint16_t volatile *)DMA1_9_Y_MODIFY)
 #define bfin_read_DMA1_9_Y_MODIFY()    bfin_read16(DMA1_9_Y_MODIFY)
 #define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
-#define pDMA1_9_CURR_DESC_PTR          ((void * volatile *)DMA1_9_CURR_DESC_PTR)
 #define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
 #define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
-#define pDMA1_9_CURR_ADDR              ((void * volatile *)DMA1_9_CURR_ADDR)
 #define bfin_read_DMA1_9_CURR_ADDR()   bfin_readPTR(DMA1_9_CURR_ADDR)
 #define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
-#define pDMA1_9_CURR_X_COUNT           ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
 #define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
 #define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
-#define pDMA1_9_CURR_Y_COUNT           ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)
 #define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
 #define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
-#define pDMA1_9_IRQ_STATUS             ((uint16_t volatile *)DMA1_9_IRQ_STATUS)
 #define bfin_read_DMA1_9_IRQ_STATUS()  bfin_read16(DMA1_9_IRQ_STATUS)
 #define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
-#define pDMA1_9_PERIPHERAL_MAP         ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)
 #define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
 #define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
-#define pDMA1_10_CONFIG                ((uint16_t volatile *)DMA1_10_CONFIG)
 #define bfin_read_DMA1_10_CONFIG()     bfin_read16(DMA1_10_CONFIG)
 #define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
-#define pDMA1_10_NEXT_DESC_PTR         ((void * volatile *)DMA1_10_NEXT_DESC_PTR)
 #define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
 #define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
-#define pDMA1_10_START_ADDR            ((void * volatile *)DMA1_10_START_ADDR)
 #define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
 #define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
-#define pDMA1_10_X_COUNT               ((uint16_t volatile *)DMA1_10_X_COUNT)
 #define bfin_read_DMA1_10_X_COUNT()    bfin_read16(DMA1_10_X_COUNT)
 #define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
-#define pDMA1_10_Y_COUNT               ((uint16_t volatile *)DMA1_10_Y_COUNT)
 #define bfin_read_DMA1_10_Y_COUNT()    bfin_read16(DMA1_10_Y_COUNT)
 #define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
-#define pDMA1_10_X_MODIFY              ((uint16_t volatile *)DMA1_10_X_MODIFY)
 #define bfin_read_DMA1_10_X_MODIFY()   bfin_read16(DMA1_10_X_MODIFY)
 #define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
-#define pDMA1_10_Y_MODIFY              ((uint16_t volatile *)DMA1_10_Y_MODIFY)
 #define bfin_read_DMA1_10_Y_MODIFY()   bfin_read16(DMA1_10_Y_MODIFY)
 #define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
-#define pDMA1_10_CURR_DESC_PTR         ((void * volatile *)DMA1_10_CURR_DESC_PTR)
 #define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
 #define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
-#define pDMA1_10_CURR_ADDR             ((void * volatile *)DMA1_10_CURR_ADDR)
 #define bfin_read_DMA1_10_CURR_ADDR()  bfin_readPTR(DMA1_10_CURR_ADDR)
 #define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
-#define pDMA1_10_CURR_X_COUNT          ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
 #define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
 #define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
-#define pDMA1_10_CURR_Y_COUNT          ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)
 #define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
 #define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
-#define pDMA1_10_IRQ_STATUS            ((uint16_t volatile *)DMA1_10_IRQ_STATUS)
 #define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
 #define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
-#define pDMA1_10_PERIPHERAL_MAP        ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)
 #define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
 #define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
-#define pDMA1_11_CONFIG                ((uint16_t volatile *)DMA1_11_CONFIG)
 #define bfin_read_DMA1_11_CONFIG()     bfin_read16(DMA1_11_CONFIG)
 #define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
-#define pDMA1_11_NEXT_DESC_PTR         ((void * volatile *)DMA1_11_NEXT_DESC_PTR)
 #define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
 #define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
-#define pDMA1_11_START_ADDR            ((void * volatile *)DMA1_11_START_ADDR)
 #define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
 #define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
-#define pDMA1_11_X_COUNT               ((uint16_t volatile *)DMA1_11_X_COUNT)
 #define bfin_read_DMA1_11_X_COUNT()    bfin_read16(DMA1_11_X_COUNT)
 #define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
-#define pDMA1_11_Y_COUNT               ((uint16_t volatile *)DMA1_11_Y_COUNT)
 #define bfin_read_DMA1_11_Y_COUNT()    bfin_read16(DMA1_11_Y_COUNT)
 #define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
-#define pDMA1_11_X_MODIFY              ((uint16_t volatile *)DMA1_11_X_MODIFY)
 #define bfin_read_DMA1_11_X_MODIFY()   bfin_read16(DMA1_11_X_MODIFY)
 #define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
-#define pDMA1_11_Y_MODIFY              ((uint16_t volatile *)DMA1_11_Y_MODIFY)
 #define bfin_read_DMA1_11_Y_MODIFY()   bfin_read16(DMA1_11_Y_MODIFY)
 #define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
-#define pDMA1_11_CURR_DESC_PTR         ((void * volatile *)DMA1_11_CURR_DESC_PTR)
 #define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
 #define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
-#define pDMA1_11_CURR_ADDR             ((void * volatile *)DMA1_11_CURR_ADDR)
 #define bfin_read_DMA1_11_CURR_ADDR()  bfin_readPTR(DMA1_11_CURR_ADDR)
 #define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
-#define pDMA1_11_CURR_X_COUNT          ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
 #define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
 #define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
-#define pDMA1_11_CURR_Y_COUNT          ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)
 #define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
 #define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
-#define pDMA1_11_IRQ_STATUS            ((uint16_t volatile *)DMA1_11_IRQ_STATUS)
 #define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
 #define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
-#define pDMA1_11_PERIPHERAL_MAP        ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)
 #define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
 #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
-#define pDMA2_TC_PER                   ((uint16_t volatile *)DMA2_TC_PER)
 #define bfin_read_DMA2_TC_PER()        bfin_read16(DMA2_TC_PER)
 #define bfin_write_DMA2_TC_PER(val)    bfin_write16(DMA2_TC_PER, val)
-#define pDMA2_TC_CNT                   ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */
 #define bfin_read_DMA2_TC_CNT()        bfin_read16(DMA2_TC_CNT)
 #define bfin_write_DMA2_TC_CNT(val)    bfin_write16(DMA2_TC_CNT, val)
-#define pDMA2_0_CONFIG                 ((uint16_t volatile *)DMA2_0_CONFIG)
 #define bfin_read_DMA2_0_CONFIG()      bfin_read16(DMA2_0_CONFIG)
 #define bfin_write_DMA2_0_CONFIG(val)  bfin_write16(DMA2_0_CONFIG, val)
-#define pDMA2_0_NEXT_DESC_PTR          ((void * volatile *)DMA2_0_NEXT_DESC_PTR)
 #define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
 #define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
-#define pDMA2_0_START_ADDR             ((void * volatile *)DMA2_0_START_ADDR)
 #define bfin_read_DMA2_0_START_ADDR()  bfin_readPTR(DMA2_0_START_ADDR)
 #define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
-#define pDMA2_0_X_COUNT                ((uint16_t volatile *)DMA2_0_X_COUNT)
 #define bfin_read_DMA2_0_X_COUNT()     bfin_read16(DMA2_0_X_COUNT)
 #define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
-#define pDMA2_0_Y_COUNT                ((uint16_t volatile *)DMA2_0_Y_COUNT)
 #define bfin_read_DMA2_0_Y_COUNT()     bfin_read16(DMA2_0_Y_COUNT)
 #define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
-#define pDMA2_0_X_MODIFY               ((uint16_t volatile *)DMA2_0_X_MODIFY)
 #define bfin_read_DMA2_0_X_MODIFY()    bfin_read16(DMA2_0_X_MODIFY)
 #define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
-#define pDMA2_0_Y_MODIFY               ((uint16_t volatile *)DMA2_0_Y_MODIFY)
 #define bfin_read_DMA2_0_Y_MODIFY()    bfin_read16(DMA2_0_Y_MODIFY)
 #define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
-#define pDMA2_0_CURR_DESC_PTR          ((void * volatile *)DMA2_0_CURR_DESC_PTR)
 #define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
 #define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
-#define pDMA2_0_CURR_ADDR              ((void * volatile *)DMA2_0_CURR_ADDR)
 #define bfin_read_DMA2_0_CURR_ADDR()   bfin_readPTR(DMA2_0_CURR_ADDR)
 #define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
-#define pDMA2_0_CURR_X_COUNT           ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
 #define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
 #define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
-#define pDMA2_0_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)
 #define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
 #define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
-#define pDMA2_0_IRQ_STATUS             ((uint16_t volatile *)DMA2_0_IRQ_STATUS)
 #define bfin_read_DMA2_0_IRQ_STATUS()  bfin_read16(DMA2_0_IRQ_STATUS)
 #define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
-#define pDMA2_0_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)
 #define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
 #define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
-#define pDMA2_1_CONFIG                 ((uint16_t volatile *)DMA2_1_CONFIG)
 #define bfin_read_DMA2_1_CONFIG()      bfin_read16(DMA2_1_CONFIG)
 #define bfin_write_DMA2_1_CONFIG(val)  bfin_write16(DMA2_1_CONFIG, val)
-#define pDMA2_1_NEXT_DESC_PTR          ((void * volatile *)DMA2_1_NEXT_DESC_PTR)
 #define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
 #define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
-#define pDMA2_1_START_ADDR             ((void * volatile *)DMA2_1_START_ADDR)
 #define bfin_read_DMA2_1_START_ADDR()  bfin_readPTR(DMA2_1_START_ADDR)
 #define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
-#define pDMA2_1_X_COUNT                ((uint16_t volatile *)DMA2_1_X_COUNT)
 #define bfin_read_DMA2_1_X_COUNT()     bfin_read16(DMA2_1_X_COUNT)
 #define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
-#define pDMA2_1_Y_COUNT                ((uint16_t volatile *)DMA2_1_Y_COUNT)
 #define bfin_read_DMA2_1_Y_COUNT()     bfin_read16(DMA2_1_Y_COUNT)
 #define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
-#define pDMA2_1_X_MODIFY               ((uint16_t volatile *)DMA2_1_X_MODIFY)
 #define bfin_read_DMA2_1_X_MODIFY()    bfin_read16(DMA2_1_X_MODIFY)
 #define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
-#define pDMA2_1_Y_MODIFY               ((uint16_t volatile *)DMA2_1_Y_MODIFY)
 #define bfin_read_DMA2_1_Y_MODIFY()    bfin_read16(DMA2_1_Y_MODIFY)
 #define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
-#define pDMA2_1_CURR_DESC_PTR          ((void * volatile *)DMA2_1_CURR_DESC_PTR)
 #define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
 #define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
-#define pDMA2_1_CURR_ADDR              ((void * volatile *)DMA2_1_CURR_ADDR)
 #define bfin_read_DMA2_1_CURR_ADDR()   bfin_readPTR(DMA2_1_CURR_ADDR)
 #define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
-#define pDMA2_1_CURR_X_COUNT           ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
 #define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
 #define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
-#define pDMA2_1_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)
 #define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
 #define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
-#define pDMA2_1_IRQ_STATUS             ((uint16_t volatile *)DMA2_1_IRQ_STATUS)
 #define bfin_read_DMA2_1_IRQ_STATUS()  bfin_read16(DMA2_1_IRQ_STATUS)
 #define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
-#define pDMA2_1_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)
 #define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
 #define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
-#define pDMA2_2_CONFIG                 ((uint16_t volatile *)DMA2_2_CONFIG)
 #define bfin_read_DMA2_2_CONFIG()      bfin_read16(DMA2_2_CONFIG)
 #define bfin_write_DMA2_2_CONFIG(val)  bfin_write16(DMA2_2_CONFIG, val)
-#define pDMA2_2_NEXT_DESC_PTR          ((void * volatile *)DMA2_2_NEXT_DESC_PTR)
 #define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
-#define pDMA2_2_START_ADDR             ((void * volatile *)DMA2_2_START_ADDR)
 #define bfin_read_DMA2_2_START_ADDR()  bfin_readPTR(DMA2_2_START_ADDR)
 #define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
-#define pDMA2_2_X_COUNT                ((uint16_t volatile *)DMA2_2_X_COUNT)
 #define bfin_read_DMA2_2_X_COUNT()     bfin_read16(DMA2_2_X_COUNT)
 #define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
-#define pDMA2_2_Y_COUNT                ((uint16_t volatile *)DMA2_2_Y_COUNT)
 #define bfin_read_DMA2_2_Y_COUNT()     bfin_read16(DMA2_2_Y_COUNT)
 #define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
-#define pDMA2_2_X_MODIFY               ((uint16_t volatile *)DMA2_2_X_MODIFY)
 #define bfin_read_DMA2_2_X_MODIFY()    bfin_read16(DMA2_2_X_MODIFY)
 #define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
-#define pDMA2_2_Y_MODIFY               ((uint16_t volatile *)DMA2_2_Y_MODIFY)
 #define bfin_read_DMA2_2_Y_MODIFY()    bfin_read16(DMA2_2_Y_MODIFY)
 #define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
-#define pDMA2_2_CURR_DESC_PTR          ((void * volatile *)DMA2_2_CURR_DESC_PTR)
 #define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
 #define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
-#define pDMA2_2_CURR_ADDR              ((void * volatile *)DMA2_2_CURR_ADDR)
 #define bfin_read_DMA2_2_CURR_ADDR()   bfin_readPTR(DMA2_2_CURR_ADDR)
 #define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
-#define pDMA2_2_CURR_X_COUNT           ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
 #define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
 #define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
-#define pDMA2_2_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)
 #define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
 #define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
-#define pDMA2_2_IRQ_STATUS             ((uint16_t volatile *)DMA2_2_IRQ_STATUS)
 #define bfin_read_DMA2_2_IRQ_STATUS()  bfin_read16(DMA2_2_IRQ_STATUS)
 #define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
-#define pDMA2_2_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)
 #define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
-#define pDMA2_3_CONFIG                 ((uint16_t volatile *)DMA2_3_CONFIG)
 #define bfin_read_DMA2_3_CONFIG()      bfin_read16(DMA2_3_CONFIG)
 #define bfin_write_DMA2_3_CONFIG(val)  bfin_write16(DMA2_3_CONFIG, val)
-#define pDMA2_3_NEXT_DESC_PTR          ((void * volatile *)DMA2_3_NEXT_DESC_PTR)
 #define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
 #define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
-#define pDMA2_3_START_ADDR             ((void * volatile *)DMA2_3_START_ADDR)
 #define bfin_read_DMA2_3_START_ADDR()  bfin_readPTR(DMA2_3_START_ADDR)
 #define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
-#define pDMA2_3_X_COUNT                ((uint16_t volatile *)DMA2_3_X_COUNT)
 #define bfin_read_DMA2_3_X_COUNT()     bfin_read16(DMA2_3_X_COUNT)
 #define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
-#define pDMA2_3_Y_COUNT                ((uint16_t volatile *)DMA2_3_Y_COUNT)
 #define bfin_read_DMA2_3_Y_COUNT()     bfin_read16(DMA2_3_Y_COUNT)
 #define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
-#define pDMA2_3_X_MODIFY               ((uint16_t volatile *)DMA2_3_X_MODIFY)
 #define bfin_read_DMA2_3_X_MODIFY()    bfin_read16(DMA2_3_X_MODIFY)
 #define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
-#define pDMA2_3_Y_MODIFY               ((uint16_t volatile *)DMA2_3_Y_MODIFY)
 #define bfin_read_DMA2_3_Y_MODIFY()    bfin_read16(DMA2_3_Y_MODIFY)
 #define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
-#define pDMA2_3_CURR_DESC_PTR          ((void * volatile *)DMA2_3_CURR_DESC_PTR)
 #define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
 #define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
-#define pDMA2_3_CURR_ADDR              ((void * volatile *)DMA2_3_CURR_ADDR)
 #define bfin_read_DMA2_3_CURR_ADDR()   bfin_readPTR(DMA2_3_CURR_ADDR)
 #define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
-#define pDMA2_3_CURR_X_COUNT           ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
 #define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
 #define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
-#define pDMA2_3_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)
 #define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
 #define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
-#define pDMA2_3_IRQ_STATUS             ((uint16_t volatile *)DMA2_3_IRQ_STATUS)
 #define bfin_read_DMA2_3_IRQ_STATUS()  bfin_read16(DMA2_3_IRQ_STATUS)
 #define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
-#define pDMA2_3_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)
 #define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
 #define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
-#define pDMA2_4_CONFIG                 ((uint16_t volatile *)DMA2_4_CONFIG)
 #define bfin_read_DMA2_4_CONFIG()      bfin_read16(DMA2_4_CONFIG)
 #define bfin_write_DMA2_4_CONFIG(val)  bfin_write16(DMA2_4_CONFIG, val)
-#define pDMA2_4_NEXT_DESC_PTR          ((void * volatile *)DMA2_4_NEXT_DESC_PTR)
 #define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
 #define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
-#define pDMA2_4_START_ADDR             ((void * volatile *)DMA2_4_START_ADDR)
 #define bfin_read_DMA2_4_START_ADDR()  bfin_readPTR(DMA2_4_START_ADDR)
 #define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
-#define pDMA2_4_X_COUNT                ((uint16_t volatile *)DMA2_4_X_COUNT)
 #define bfin_read_DMA2_4_X_COUNT()     bfin_read16(DMA2_4_X_COUNT)
 #define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
-#define pDMA2_4_Y_COUNT                ((uint16_t volatile *)DMA2_4_Y_COUNT)
 #define bfin_read_DMA2_4_Y_COUNT()     bfin_read16(DMA2_4_Y_COUNT)
 #define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
-#define pDMA2_4_X_MODIFY               ((uint16_t volatile *)DMA2_4_X_MODIFY)
 #define bfin_read_DMA2_4_X_MODIFY()    bfin_read16(DMA2_4_X_MODIFY)
 #define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
-#define pDMA2_4_Y_MODIFY               ((uint16_t volatile *)DMA2_4_Y_MODIFY)
 #define bfin_read_DMA2_4_Y_MODIFY()    bfin_read16(DMA2_4_Y_MODIFY)
 #define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
-#define pDMA2_4_CURR_DESC_PTR          ((void * volatile *)DMA2_4_CURR_DESC_PTR)
 #define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
 #define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
-#define pDMA2_4_CURR_ADDR              ((void * volatile *)DMA2_4_CURR_ADDR)
 #define bfin_read_DMA2_4_CURR_ADDR()   bfin_readPTR(DMA2_4_CURR_ADDR)
 #define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
-#define pDMA2_4_CURR_X_COUNT           ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
 #define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
 #define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
-#define pDMA2_4_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)
 #define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
 #define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
-#define pDMA2_4_IRQ_STATUS             ((uint16_t volatile *)DMA2_4_IRQ_STATUS)
 #define bfin_read_DMA2_4_IRQ_STATUS()  bfin_read16(DMA2_4_IRQ_STATUS)
 #define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
-#define pDMA2_4_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)
 #define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
 #define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
-#define pDMA2_5_CONFIG                 ((uint16_t volatile *)DMA2_5_CONFIG)
 #define bfin_read_DMA2_5_CONFIG()      bfin_read16(DMA2_5_CONFIG)
 #define bfin_write_DMA2_5_CONFIG(val)  bfin_write16(DMA2_5_CONFIG, val)
-#define pDMA2_5_NEXT_DESC_PTR          ((void * volatile *)DMA2_5_NEXT_DESC_PTR)
 #define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
 #define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
-#define pDMA2_5_START_ADDR             ((void * volatile *)DMA2_5_START_ADDR)
 #define bfin_read_DMA2_5_START_ADDR()  bfin_readPTR(DMA2_5_START_ADDR)
 #define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
-#define pDMA2_5_X_COUNT                ((uint16_t volatile *)DMA2_5_X_COUNT)
 #define bfin_read_DMA2_5_X_COUNT()     bfin_read16(DMA2_5_X_COUNT)
 #define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
-#define pDMA2_5_Y_COUNT                ((uint16_t volatile *)DMA2_5_Y_COUNT)
 #define bfin_read_DMA2_5_Y_COUNT()     bfin_read16(DMA2_5_Y_COUNT)
 #define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
-#define pDMA2_5_X_MODIFY               ((uint16_t volatile *)DMA2_5_X_MODIFY)
 #define bfin_read_DMA2_5_X_MODIFY()    bfin_read16(DMA2_5_X_MODIFY)
 #define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
-#define pDMA2_5_Y_MODIFY               ((uint16_t volatile *)DMA2_5_Y_MODIFY)
 #define bfin_read_DMA2_5_Y_MODIFY()    bfin_read16(DMA2_5_Y_MODIFY)
 #define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
-#define pDMA2_5_CURR_DESC_PTR          ((void * volatile *)DMA2_5_CURR_DESC_PTR)
 #define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
 #define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
-#define pDMA2_5_CURR_ADDR              ((void * volatile *)DMA2_5_CURR_ADDR)
 #define bfin_read_DMA2_5_CURR_ADDR()   bfin_readPTR(DMA2_5_CURR_ADDR)
 #define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
-#define pDMA2_5_CURR_X_COUNT           ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
 #define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
 #define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
-#define pDMA2_5_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)
 #define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
 #define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
-#define pDMA2_5_IRQ_STATUS             ((uint16_t volatile *)DMA2_5_IRQ_STATUS)
 #define bfin_read_DMA2_5_IRQ_STATUS()  bfin_read16(DMA2_5_IRQ_STATUS)
 #define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
-#define pDMA2_5_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)
 #define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
 #define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
-#define pDMA2_6_CONFIG                 ((uint16_t volatile *)DMA2_6_CONFIG)
 #define bfin_read_DMA2_6_CONFIG()      bfin_read16(DMA2_6_CONFIG)
 #define bfin_write_DMA2_6_CONFIG(val)  bfin_write16(DMA2_6_CONFIG, val)
-#define pDMA2_6_NEXT_DESC_PTR          ((void * volatile *)DMA2_6_NEXT_DESC_PTR)
 #define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
 #define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
-#define pDMA2_6_START_ADDR             ((void * volatile *)DMA2_6_START_ADDR)
 #define bfin_read_DMA2_6_START_ADDR()  bfin_readPTR(DMA2_6_START_ADDR)
 #define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
-#define pDMA2_6_X_COUNT                ((uint16_t volatile *)DMA2_6_X_COUNT)
 #define bfin_read_DMA2_6_X_COUNT()     bfin_read16(DMA2_6_X_COUNT)
 #define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
-#define pDMA2_6_Y_COUNT                ((uint16_t volatile *)DMA2_6_Y_COUNT)
 #define bfin_read_DMA2_6_Y_COUNT()     bfin_read16(DMA2_6_Y_COUNT)
 #define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
-#define pDMA2_6_X_MODIFY               ((uint16_t volatile *)DMA2_6_X_MODIFY)
 #define bfin_read_DMA2_6_X_MODIFY()    bfin_read16(DMA2_6_X_MODIFY)
 #define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
-#define pDMA2_6_Y_MODIFY               ((uint16_t volatile *)DMA2_6_Y_MODIFY)
 #define bfin_read_DMA2_6_Y_MODIFY()    bfin_read16(DMA2_6_Y_MODIFY)
 #define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
-#define pDMA2_6_CURR_DESC_PTR          ((void * volatile *)DMA2_6_CURR_DESC_PTR)
 #define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
 #define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
-#define pDMA2_6_CURR_ADDR              ((void * volatile *)DMA2_6_CURR_ADDR)
 #define bfin_read_DMA2_6_CURR_ADDR()   bfin_readPTR(DMA2_6_CURR_ADDR)
 #define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
-#define pDMA2_6_CURR_X_COUNT           ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
 #define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
 #define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
-#define pDMA2_6_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)
 #define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
 #define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
-#define pDMA2_6_IRQ_STATUS             ((uint16_t volatile *)DMA2_6_IRQ_STATUS)
 #define bfin_read_DMA2_6_IRQ_STATUS()  bfin_read16(DMA2_6_IRQ_STATUS)
 #define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
-#define pDMA2_6_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)
 #define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
 #define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
-#define pDMA2_7_CONFIG                 ((uint16_t volatile *)DMA2_7_CONFIG)
 #define bfin_read_DMA2_7_CONFIG()      bfin_read16(DMA2_7_CONFIG)
 #define bfin_write_DMA2_7_CONFIG(val)  bfin_write16(DMA2_7_CONFIG, val)
-#define pDMA2_7_NEXT_DESC_PTR          ((void * volatile *)DMA2_7_NEXT_DESC_PTR)
 #define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
 #define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
-#define pDMA2_7_START_ADDR             ((void * volatile *)DMA2_7_START_ADDR)
 #define bfin_read_DMA2_7_START_ADDR()  bfin_readPTR(DMA2_7_START_ADDR)
 #define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
-#define pDMA2_7_X_COUNT                ((uint16_t volatile *)DMA2_7_X_COUNT)
 #define bfin_read_DMA2_7_X_COUNT()     bfin_read16(DMA2_7_X_COUNT)
 #define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
-#define pDMA2_7_Y_COUNT                ((uint16_t volatile *)DMA2_7_Y_COUNT)
 #define bfin_read_DMA2_7_Y_COUNT()     bfin_read16(DMA2_7_Y_COUNT)
 #define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
-#define pDMA2_7_X_MODIFY               ((uint16_t volatile *)DMA2_7_X_MODIFY)
 #define bfin_read_DMA2_7_X_MODIFY()    bfin_read16(DMA2_7_X_MODIFY)
 #define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
-#define pDMA2_7_Y_MODIFY               ((uint16_t volatile *)DMA2_7_Y_MODIFY)
 #define bfin_read_DMA2_7_Y_MODIFY()    bfin_read16(DMA2_7_Y_MODIFY)
 #define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
-#define pDMA2_7_CURR_DESC_PTR          ((void * volatile *)DMA2_7_CURR_DESC_PTR)
 #define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
 #define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
-#define pDMA2_7_CURR_ADDR              ((void * volatile *)DMA2_7_CURR_ADDR)
 #define bfin_read_DMA2_7_CURR_ADDR()   bfin_readPTR(DMA2_7_CURR_ADDR)
 #define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
-#define pDMA2_7_CURR_X_COUNT           ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
 #define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
 #define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
-#define pDMA2_7_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)
 #define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
 #define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
-#define pDMA2_7_IRQ_STATUS             ((uint16_t volatile *)DMA2_7_IRQ_STATUS)
 #define bfin_read_DMA2_7_IRQ_STATUS()  bfin_read16(DMA2_7_IRQ_STATUS)
 #define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
-#define pDMA2_7_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)
 #define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
 #define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
-#define pDMA2_8_CONFIG                 ((uint16_t volatile *)DMA2_8_CONFIG)
 #define bfin_read_DMA2_8_CONFIG()      bfin_read16(DMA2_8_CONFIG)
 #define bfin_write_DMA2_8_CONFIG(val)  bfin_write16(DMA2_8_CONFIG, val)
-#define pDMA2_8_NEXT_DESC_PTR          ((void * volatile *)DMA2_8_NEXT_DESC_PTR)
 #define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
 #define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
-#define pDMA2_8_START_ADDR             ((void * volatile *)DMA2_8_START_ADDR)
 #define bfin_read_DMA2_8_START_ADDR()  bfin_readPTR(DMA2_8_START_ADDR)
 #define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
-#define pDMA2_8_X_COUNT                ((uint16_t volatile *)DMA2_8_X_COUNT)
 #define bfin_read_DMA2_8_X_COUNT()     bfin_read16(DMA2_8_X_COUNT)
 #define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
-#define pDMA2_8_Y_COUNT                ((uint16_t volatile *)DMA2_8_Y_COUNT)
 #define bfin_read_DMA2_8_Y_COUNT()     bfin_read16(DMA2_8_Y_COUNT)
 #define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
-#define pDMA2_8_X_MODIFY               ((uint16_t volatile *)DMA2_8_X_MODIFY)
 #define bfin_read_DMA2_8_X_MODIFY()    bfin_read16(DMA2_8_X_MODIFY)
 #define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
-#define pDMA2_8_Y_MODIFY               ((uint16_t volatile *)DMA2_8_Y_MODIFY)
 #define bfin_read_DMA2_8_Y_MODIFY()    bfin_read16(DMA2_8_Y_MODIFY)
 #define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
-#define pDMA2_8_CURR_DESC_PTR          ((void * volatile *)DMA2_8_CURR_DESC_PTR)
 #define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
 #define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
-#define pDMA2_8_CURR_ADDR              ((void * volatile *)DMA2_8_CURR_ADDR)
 #define bfin_read_DMA2_8_CURR_ADDR()   bfin_readPTR(DMA2_8_CURR_ADDR)
 #define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
-#define pDMA2_8_CURR_X_COUNT           ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
 #define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
 #define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
-#define pDMA2_8_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)
 #define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
 #define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
-#define pDMA2_8_IRQ_STATUS             ((uint16_t volatile *)DMA2_8_IRQ_STATUS)
 #define bfin_read_DMA2_8_IRQ_STATUS()  bfin_read16(DMA2_8_IRQ_STATUS)
 #define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
-#define pDMA2_8_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)
 #define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
 #define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
-#define pDMA2_9_CONFIG                 ((uint16_t volatile *)DMA2_9_CONFIG)
 #define bfin_read_DMA2_9_CONFIG()      bfin_read16(DMA2_9_CONFIG)
 #define bfin_write_DMA2_9_CONFIG(val)  bfin_write16(DMA2_9_CONFIG, val)
-#define pDMA2_9_NEXT_DESC_PTR          ((void * volatile *)DMA2_9_NEXT_DESC_PTR)
 #define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
 #define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
-#define pDMA2_9_START_ADDR             ((void * volatile *)DMA2_9_START_ADDR)
 #define bfin_read_DMA2_9_START_ADDR()  bfin_readPTR(DMA2_9_START_ADDR)
 #define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
-#define pDMA2_9_X_COUNT                ((uint16_t volatile *)DMA2_9_X_COUNT)
 #define bfin_read_DMA2_9_X_COUNT()     bfin_read16(DMA2_9_X_COUNT)
 #define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
-#define pDMA2_9_Y_COUNT                ((uint16_t volatile *)DMA2_9_Y_COUNT)
 #define bfin_read_DMA2_9_Y_COUNT()     bfin_read16(DMA2_9_Y_COUNT)
 #define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
-#define pDMA2_9_X_MODIFY               ((uint16_t volatile *)DMA2_9_X_MODIFY)
 #define bfin_read_DMA2_9_X_MODIFY()    bfin_read16(DMA2_9_X_MODIFY)
 #define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
-#define pDMA2_9_Y_MODIFY               ((uint16_t volatile *)DMA2_9_Y_MODIFY)
 #define bfin_read_DMA2_9_Y_MODIFY()    bfin_read16(DMA2_9_Y_MODIFY)
 #define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
-#define pDMA2_9_CURR_DESC_PTR          ((void * volatile *)DMA2_9_CURR_DESC_PTR)
 #define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
 #define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
-#define pDMA2_9_CURR_ADDR              ((void * volatile *)DMA2_9_CURR_ADDR)
 #define bfin_read_DMA2_9_CURR_ADDR()   bfin_readPTR(DMA2_9_CURR_ADDR)
 #define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
-#define pDMA2_9_CURR_X_COUNT           ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
 #define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
 #define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
-#define pDMA2_9_CURR_Y_COUNT           ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)
 #define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
 #define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
-#define pDMA2_9_IRQ_STATUS             ((uint16_t volatile *)DMA2_9_IRQ_STATUS)
 #define bfin_read_DMA2_9_IRQ_STATUS()  bfin_read16(DMA2_9_IRQ_STATUS)
 #define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
-#define pDMA2_9_PERIPHERAL_MAP         ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)
 #define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
 #define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
-#define pDMA2_10_CONFIG                ((uint16_t volatile *)DMA2_10_CONFIG)
 #define bfin_read_DMA2_10_CONFIG()     bfin_read16(DMA2_10_CONFIG)
 #define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
-#define pDMA2_10_NEXT_DESC_PTR         ((void * volatile *)DMA2_10_NEXT_DESC_PTR)
 #define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
 #define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
-#define pDMA2_10_START_ADDR            ((void * volatile *)DMA2_10_START_ADDR)
 #define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
 #define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
-#define pDMA2_10_X_COUNT               ((uint16_t volatile *)DMA2_10_X_COUNT)
 #define bfin_read_DMA2_10_X_COUNT()    bfin_read16(DMA2_10_X_COUNT)
 #define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
-#define pDMA2_10_Y_COUNT               ((uint16_t volatile *)DMA2_10_Y_COUNT)
 #define bfin_read_DMA2_10_Y_COUNT()    bfin_read16(DMA2_10_Y_COUNT)
 #define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
-#define pDMA2_10_X_MODIFY              ((uint16_t volatile *)DMA2_10_X_MODIFY)
 #define bfin_read_DMA2_10_X_MODIFY()   bfin_read16(DMA2_10_X_MODIFY)
 #define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
-#define pDMA2_10_Y_MODIFY              ((uint16_t volatile *)DMA2_10_Y_MODIFY)
 #define bfin_read_DMA2_10_Y_MODIFY()   bfin_read16(DMA2_10_Y_MODIFY)
 #define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
-#define pDMA2_10_CURR_DESC_PTR         ((void * volatile *)DMA2_10_CURR_DESC_PTR)
 #define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
 #define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
-#define pDMA2_10_CURR_ADDR             ((void * volatile *)DMA2_10_CURR_ADDR)
 #define bfin_read_DMA2_10_CURR_ADDR()  bfin_readPTR(DMA2_10_CURR_ADDR)
 #define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
-#define pDMA2_10_CURR_X_COUNT          ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
 #define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
 #define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
-#define pDMA2_10_CURR_Y_COUNT          ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)
 #define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
 #define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
-#define pDMA2_10_IRQ_STATUS            ((uint16_t volatile *)DMA2_10_IRQ_STATUS)
 #define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
 #define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
-#define pDMA2_10_PERIPHERAL_MAP        ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)
 #define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
 #define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
-#define pDMA2_11_CONFIG                ((uint16_t volatile *)DMA2_11_CONFIG)
 #define bfin_read_DMA2_11_CONFIG()     bfin_read16(DMA2_11_CONFIG)
 #define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
-#define pDMA2_11_NEXT_DESC_PTR         ((void * volatile *)DMA2_11_NEXT_DESC_PTR)
 #define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
 #define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
-#define pDMA2_11_START_ADDR            ((void * volatile *)DMA2_11_START_ADDR)
 #define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
 #define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
-#define pDMA2_11_X_COUNT               ((uint16_t volatile *)DMA2_11_X_COUNT)
 #define bfin_read_DMA2_11_X_COUNT()    bfin_read16(DMA2_11_X_COUNT)
 #define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
-#define pDMA2_11_Y_COUNT               ((uint16_t volatile *)DMA2_11_Y_COUNT)
 #define bfin_read_DMA2_11_Y_COUNT()    bfin_read16(DMA2_11_Y_COUNT)
 #define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
-#define pDMA2_11_X_MODIFY              ((uint16_t volatile *)DMA2_11_X_MODIFY)
 #define bfin_read_DMA2_11_X_MODIFY()   bfin_read16(DMA2_11_X_MODIFY)
 #define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
-#define pDMA2_11_Y_MODIFY              ((uint16_t volatile *)DMA2_11_Y_MODIFY)
 #define bfin_read_DMA2_11_Y_MODIFY()   bfin_read16(DMA2_11_Y_MODIFY)
 #define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
-#define pDMA2_11_CURR_DESC_PTR         ((void * volatile *)DMA2_11_CURR_DESC_PTR)
 #define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
 #define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
-#define pDMA2_11_CURR_ADDR             ((void * volatile *)DMA2_11_CURR_ADDR)
 #define bfin_read_DMA2_11_CURR_ADDR()  bfin_readPTR(DMA2_11_CURR_ADDR)
 #define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
-#define pDMA2_11_CURR_X_COUNT          ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
 #define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
 #define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
-#define pDMA2_11_CURR_Y_COUNT          ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)
 #define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
 #define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
-#define pDMA2_11_IRQ_STATUS            ((uint16_t volatile *)DMA2_11_IRQ_STATUS)
 #define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
 #define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
-#define pDMA2_11_PERIPHERAL_MAP        ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)
 #define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
 #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
-#define pIMDMA_S0_CONFIG               ((uint16_t volatile *)IMDMA_S0_CONFIG)
 #define bfin_read_IMDMA_S0_CONFIG()    bfin_read16(IMDMA_S0_CONFIG)
 #define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
-#define pIMDMA_S0_NEXT_DESC_PTR        ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)
 #define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
-#define pIMDMA_S0_START_ADDR           ((void * volatile *)IMDMA_S0_START_ADDR)
 #define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
 #define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
-#define pIMDMA_S0_X_COUNT              ((uint16_t volatile *)IMDMA_S0_X_COUNT)
 #define bfin_read_IMDMA_S0_X_COUNT()   bfin_read16(IMDMA_S0_X_COUNT)
 #define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
-#define pIMDMA_S0_Y_COUNT              ((uint16_t volatile *)IMDMA_S0_Y_COUNT)
 #define bfin_read_IMDMA_S0_Y_COUNT()   bfin_read16(IMDMA_S0_Y_COUNT)
 #define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
-#define pIMDMA_S0_X_MODIFY             ((uint16_t volatile *)IMDMA_S0_X_MODIFY)
 #define bfin_read_IMDMA_S0_X_MODIFY()  bfin_read16(IMDMA_S0_X_MODIFY)
 #define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
-#define pIMDMA_S0_Y_MODIFY             ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)
 #define bfin_read_IMDMA_S0_Y_MODIFY()  bfin_read16(IMDMA_S0_Y_MODIFY)
 #define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
-#define pIMDMA_S0_CURR_DESC_PTR        ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)
 #define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
 #define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
-#define pIMDMA_S0_CURR_ADDR            ((void * volatile *)IMDMA_S0_CURR_ADDR)
 #define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
 #define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
-#define pIMDMA_S0_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
 #define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
 #define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
-#define pIMDMA_S0_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)
 #define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
 #define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
-#define pIMDMA_S0_IRQ_STATUS           ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)
 #define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
 #define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
-#define pIMDMA_D0_CONFIG               ((uint16_t volatile *)IMDMA_D0_CONFIG)
 #define bfin_read_IMDMA_D0_CONFIG()    bfin_read16(IMDMA_D0_CONFIG)
 #define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
-#define pIMDMA_D0_NEXT_DESC_PTR        ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)
 #define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
-#define pIMDMA_D0_START_ADDR           ((void * volatile *)IMDMA_D0_START_ADDR)
 #define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
 #define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
-#define pIMDMA_D0_X_COUNT              ((uint16_t volatile *)IMDMA_D0_X_COUNT)
 #define bfin_read_IMDMA_D0_X_COUNT()   bfin_read16(IMDMA_D0_X_COUNT)
 #define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
-#define pIMDMA_D0_Y_COUNT              ((uint16_t volatile *)IMDMA_D0_Y_COUNT)
 #define bfin_read_IMDMA_D0_Y_COUNT()   bfin_read16(IMDMA_D0_Y_COUNT)
 #define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
-#define pIMDMA_D0_X_MODIFY             ((uint16_t volatile *)IMDMA_D0_X_MODIFY)
 #define bfin_read_IMDMA_D0_X_MODIFY()  bfin_read16(IMDMA_D0_X_MODIFY)
 #define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
-#define pIMDMA_D0_Y_MODIFY             ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)
 #define bfin_read_IMDMA_D0_Y_MODIFY()  bfin_read16(IMDMA_D0_Y_MODIFY)
 #define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
-#define pIMDMA_D0_CURR_DESC_PTR        ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)
 #define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
 #define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
-#define pIMDMA_D0_CURR_ADDR            ((void * volatile *)IMDMA_D0_CURR_ADDR)
 #define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
 #define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
-#define pIMDMA_D0_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
 #define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
 #define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
-#define pIMDMA_D0_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)
 #define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
 #define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
-#define pIMDMA_D0_IRQ_STATUS           ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)
 #define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
 #define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
-#define pIMDMA_S1_CONFIG               ((uint16_t volatile *)IMDMA_S1_CONFIG)
 #define bfin_read_IMDMA_S1_CONFIG()    bfin_read16(IMDMA_S1_CONFIG)
 #define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
-#define pIMDMA_S1_NEXT_DESC_PTR        ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)
 #define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
-#define pIMDMA_S1_START_ADDR           ((void * volatile *)IMDMA_S1_START_ADDR)
 #define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
 #define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
-#define pIMDMA_S1_X_COUNT              ((uint16_t volatile *)IMDMA_S1_X_COUNT)
 #define bfin_read_IMDMA_S1_X_COUNT()   bfin_read16(IMDMA_S1_X_COUNT)
 #define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
-#define pIMDMA_S1_Y_COUNT              ((uint16_t volatile *)IMDMA_S1_Y_COUNT)
 #define bfin_read_IMDMA_S1_Y_COUNT()   bfin_read16(IMDMA_S1_Y_COUNT)
 #define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
-#define pIMDMA_S1_X_MODIFY             ((uint16_t volatile *)IMDMA_S1_X_MODIFY)
 #define bfin_read_IMDMA_S1_X_MODIFY()  bfin_read16(IMDMA_S1_X_MODIFY)
 #define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
-#define pIMDMA_S1_Y_MODIFY             ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)
 #define bfin_read_IMDMA_S1_Y_MODIFY()  bfin_read16(IMDMA_S1_Y_MODIFY)
 #define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
-#define pIMDMA_S1_CURR_DESC_PTR        ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)
 #define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
 #define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
-#define pIMDMA_S1_CURR_ADDR            ((void * volatile *)IMDMA_S1_CURR_ADDR)
 #define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
 #define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
-#define pIMDMA_S1_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
 #define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
 #define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
-#define pIMDMA_S1_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)
 #define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
 #define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
-#define pIMDMA_S1_IRQ_STATUS           ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)
 #define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
 #define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
-#define pIMDMA_D1_CONFIG               ((uint16_t volatile *)IMDMA_D1_CONFIG)
 #define bfin_read_IMDMA_D1_CONFIG()    bfin_read16(IMDMA_D1_CONFIG)
 #define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
-#define pIMDMA_D1_NEXT_DESC_PTR        ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)
 #define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
-#define pIMDMA_D1_START_ADDR           ((void * volatile *)IMDMA_D1_START_ADDR)
 #define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
 #define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
-#define pIMDMA_D1_X_COUNT              ((uint16_t volatile *)IMDMA_D1_X_COUNT)
 #define bfin_read_IMDMA_D1_X_COUNT()   bfin_read16(IMDMA_D1_X_COUNT)
 #define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
-#define pIMDMA_D1_Y_COUNT              ((uint16_t volatile *)IMDMA_D1_Y_COUNT)
 #define bfin_read_IMDMA_D1_Y_COUNT()   bfin_read16(IMDMA_D1_Y_COUNT)
 #define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
-#define pIMDMA_D1_X_MODIFY             ((uint16_t volatile *)IMDMA_D1_X_MODIFY)
 #define bfin_read_IMDMA_D1_X_MODIFY()  bfin_read16(IMDMA_D1_X_MODIFY)
 #define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
-#define pIMDMA_D1_Y_MODIFY             ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)
 #define bfin_read_IMDMA_D1_Y_MODIFY()  bfin_read16(IMDMA_D1_Y_MODIFY)
 #define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
-#define pIMDMA_D1_CURR_DESC_PTR        ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)
 #define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
 #define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
-#define pIMDMA_D1_CURR_ADDR            ((void * volatile *)IMDMA_D1_CURR_ADDR)
 #define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
 #define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
-#define pIMDMA_D1_CURR_X_COUNT         ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
 #define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
 #define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
-#define pIMDMA_D1_CURR_Y_COUNT         ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)
 #define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
 #define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
-#define pIMDMA_D1_IRQ_STATUS           ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)
 #define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
 #define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
-#define pMDMA1_S0_CONFIG               ((uint16_t volatile *)MDMA1_S0_CONFIG)
 #define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
 #define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define pMDMA1_S0_NEXT_DESC_PTR        ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
 #define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define pMDMA1_S0_START_ADDR           ((void * volatile *)MDMA1_S0_START_ADDR)
 #define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
 #define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define pMDMA1_S0_X_COUNT              ((uint16_t volatile *)MDMA1_S0_X_COUNT)
 #define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
 #define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define pMDMA1_S0_Y_COUNT              ((uint16_t volatile *)MDMA1_S0_Y_COUNT)
 #define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
 #define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define pMDMA1_S0_X_MODIFY             ((uint16_t volatile *)MDMA1_S0_X_MODIFY)
 #define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
 #define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define pMDMA1_S0_Y_MODIFY             ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)
 #define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
 #define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define pMDMA1_S0_CURR_DESC_PTR        ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
 #define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define pMDMA1_S0_CURR_ADDR            ((void * volatile *)MDMA1_S0_CURR_ADDR)
 #define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
 #define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define pMDMA1_S0_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
 #define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
 #define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define pMDMA1_S0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)
 #define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define pMDMA1_S0_IRQ_STATUS           ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)
 #define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
 #define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define pMDMA1_S0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)
 #define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define pMDMA1_D0_CONFIG               ((uint16_t volatile *)MDMA1_D0_CONFIG)
 #define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
 #define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define pMDMA1_D0_NEXT_DESC_PTR        ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
 #define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define pMDMA1_D0_START_ADDR           ((void * volatile *)MDMA1_D0_START_ADDR)
 #define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
 #define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define pMDMA1_D0_X_COUNT              ((uint16_t volatile *)MDMA1_D0_X_COUNT)
 #define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
 #define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define pMDMA1_D0_Y_COUNT              ((uint16_t volatile *)MDMA1_D0_Y_COUNT)
 #define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
 #define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define pMDMA1_D0_X_MODIFY             ((uint16_t volatile *)MDMA1_D0_X_MODIFY)
 #define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
 #define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define pMDMA1_D0_Y_MODIFY             ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)
 #define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
 #define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define pMDMA1_D0_CURR_DESC_PTR        ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
 #define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define pMDMA1_D0_CURR_ADDR            ((void * volatile *)MDMA1_D0_CURR_ADDR)
 #define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
 #define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define pMDMA1_D0_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
 #define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
 #define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define pMDMA1_D0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)
 #define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define pMDMA1_D0_IRQ_STATUS           ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
 #define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
 #define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define pMDMA1_D0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)
 #define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define pMDMA1_S1_CONFIG               ((uint16_t volatile *)MDMA1_S1_CONFIG)
 #define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
 #define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define pMDMA1_S1_NEXT_DESC_PTR        ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
 #define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define pMDMA1_S1_START_ADDR           ((void * volatile *)MDMA1_S1_START_ADDR)
 #define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
 #define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define pMDMA1_S1_X_COUNT              ((uint16_t volatile *)MDMA1_S1_X_COUNT)
 #define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
 #define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define pMDMA1_S1_Y_COUNT              ((uint16_t volatile *)MDMA1_S1_Y_COUNT)
 #define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
 #define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define pMDMA1_S1_X_MODIFY             ((uint16_t volatile *)MDMA1_S1_X_MODIFY)
 #define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
 #define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define pMDMA1_S1_Y_MODIFY             ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)
 #define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
 #define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define pMDMA1_S1_CURR_DESC_PTR        ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
 #define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define pMDMA1_S1_CURR_ADDR            ((void * volatile *)MDMA1_S1_CURR_ADDR)
 #define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
 #define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define pMDMA1_S1_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
 #define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
 #define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define pMDMA1_S1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)
 #define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define pMDMA1_S1_IRQ_STATUS           ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)
 #define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
 #define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define pMDMA1_S1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)
 #define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define pMDMA1_D1_CONFIG               ((uint16_t volatile *)MDMA1_D1_CONFIG)
 #define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
 #define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define pMDMA1_D1_NEXT_DESC_PTR        ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
 #define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define pMDMA1_D1_START_ADDR           ((void * volatile *)MDMA1_D1_START_ADDR)
 #define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
 #define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define pMDMA1_D1_X_COUNT              ((uint16_t volatile *)MDMA1_D1_X_COUNT)
 #define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
 #define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define pMDMA1_D1_Y_COUNT              ((uint16_t volatile *)MDMA1_D1_Y_COUNT)
 #define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
 #define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define pMDMA1_D1_X_MODIFY             ((uint16_t volatile *)MDMA1_D1_X_MODIFY)
 #define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
 #define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define pMDMA1_D1_Y_MODIFY             ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)
 #define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
 #define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define pMDMA1_D1_CURR_DESC_PTR        ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
 #define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define pMDMA1_D1_CURR_ADDR            ((void * volatile *)MDMA1_D1_CURR_ADDR)
 #define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
 #define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define pMDMA1_D1_CURR_X_COUNT         ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
 #define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
 #define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define pMDMA1_D1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)
 #define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define pMDMA1_D1_IRQ_STATUS           ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)
 #define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
 #define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define pMDMA1_D1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)
 #define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define pMDMA2_S0_CONFIG               ((uint16_t volatile *)MDMA2_S0_CONFIG)
 #define bfin_read_MDMA2_S0_CONFIG()    bfin_read16(MDMA2_S0_CONFIG)
 #define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
-#define pMDMA2_S0_NEXT_DESC_PTR        ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)
 #define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
-#define pMDMA2_S0_START_ADDR           ((void * volatile *)MDMA2_S0_START_ADDR)
 #define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
 #define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
-#define pMDMA2_S0_X_COUNT              ((uint16_t volatile *)MDMA2_S0_X_COUNT)
 #define bfin_read_MDMA2_S0_X_COUNT()   bfin_read16(MDMA2_S0_X_COUNT)
 #define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
-#define pMDMA2_S0_Y_COUNT              ((uint16_t volatile *)MDMA2_S0_Y_COUNT)
 #define bfin_read_MDMA2_S0_Y_COUNT()   bfin_read16(MDMA2_S0_Y_COUNT)
 #define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
-#define pMDMA2_S0_X_MODIFY             ((uint16_t volatile *)MDMA2_S0_X_MODIFY)
 #define bfin_read_MDMA2_S0_X_MODIFY()  bfin_read16(MDMA2_S0_X_MODIFY)
 #define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
-#define pMDMA2_S0_Y_MODIFY             ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)
 #define bfin_read_MDMA2_S0_Y_MODIFY()  bfin_read16(MDMA2_S0_Y_MODIFY)
 #define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
-#define pMDMA2_S0_CURR_DESC_PTR        ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)
 #define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
-#define pMDMA2_S0_CURR_ADDR            ((void * volatile *)MDMA2_S0_CURR_ADDR)
 #define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
 #define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
-#define pMDMA2_S0_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
 #define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
 #define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
-#define pMDMA2_S0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)
 #define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
-#define pMDMA2_S0_IRQ_STATUS           ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)
 #define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
 #define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
-#define pMDMA2_S0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)
 #define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
-#define pMDMA2_D0_CONFIG               ((uint16_t volatile *)MDMA2_D0_CONFIG)
 #define bfin_read_MDMA2_D0_CONFIG()    bfin_read16(MDMA2_D0_CONFIG)
 #define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
-#define pMDMA2_D0_NEXT_DESC_PTR        ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)
 #define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
-#define pMDMA2_D0_START_ADDR           ((void * volatile *)MDMA2_D0_START_ADDR)
 #define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
 #define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
-#define pMDMA2_D0_X_COUNT              ((uint16_t volatile *)MDMA2_D0_X_COUNT)
 #define bfin_read_MDMA2_D0_X_COUNT()   bfin_read16(MDMA2_D0_X_COUNT)
 #define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
-#define pMDMA2_D0_Y_COUNT              ((uint16_t volatile *)MDMA2_D0_Y_COUNT)
 #define bfin_read_MDMA2_D0_Y_COUNT()   bfin_read16(MDMA2_D0_Y_COUNT)
 #define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
-#define pMDMA2_D0_X_MODIFY             ((uint16_t volatile *)MDMA2_D0_X_MODIFY)
 #define bfin_read_MDMA2_D0_X_MODIFY()  bfin_read16(MDMA2_D0_X_MODIFY)
 #define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
-#define pMDMA2_D0_Y_MODIFY             ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)
 #define bfin_read_MDMA2_D0_Y_MODIFY()  bfin_read16(MDMA2_D0_Y_MODIFY)
 #define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
-#define pMDMA2_D0_CURR_DESC_PTR        ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)
 #define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
-#define pMDMA2_D0_CURR_ADDR            ((void * volatile *)MDMA2_D0_CURR_ADDR)
 #define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
 #define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
-#define pMDMA2_D0_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
 #define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
 #define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
-#define pMDMA2_D0_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)
 #define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
-#define pMDMA2_D0_IRQ_STATUS           ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)
 #define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
 #define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
-#define pMDMA2_D0_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)
 #define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
-#define pMDMA2_S1_CONFIG               ((uint16_t volatile *)MDMA2_S1_CONFIG)
 #define bfin_read_MDMA2_S1_CONFIG()    bfin_read16(MDMA2_S1_CONFIG)
 #define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
-#define pMDMA2_S1_NEXT_DESC_PTR        ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)
 #define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
-#define pMDMA2_S1_START_ADDR           ((void * volatile *)MDMA2_S1_START_ADDR)
 #define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
 #define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
-#define pMDMA2_S1_X_COUNT              ((uint16_t volatile *)MDMA2_S1_X_COUNT)
 #define bfin_read_MDMA2_S1_X_COUNT()   bfin_read16(MDMA2_S1_X_COUNT)
 #define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
-#define pMDMA2_S1_Y_COUNT              ((uint16_t volatile *)MDMA2_S1_Y_COUNT)
 #define bfin_read_MDMA2_S1_Y_COUNT()   bfin_read16(MDMA2_S1_Y_COUNT)
 #define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
-#define pMDMA2_S1_X_MODIFY             ((uint16_t volatile *)MDMA2_S1_X_MODIFY)
 #define bfin_read_MDMA2_S1_X_MODIFY()  bfin_read16(MDMA2_S1_X_MODIFY)
 #define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
-#define pMDMA2_S1_Y_MODIFY             ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)
 #define bfin_read_MDMA2_S1_Y_MODIFY()  bfin_read16(MDMA2_S1_Y_MODIFY)
 #define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
-#define pMDMA2_S1_CURR_DESC_PTR        ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)
 #define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
-#define pMDMA2_S1_CURR_ADDR            ((void * volatile *)MDMA2_S1_CURR_ADDR)
 #define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
 #define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
-#define pMDMA2_S1_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
 #define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
 #define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
-#define pMDMA2_S1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)
 #define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
-#define pMDMA2_S1_IRQ_STATUS           ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)
 #define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
 #define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
-#define pMDMA2_S1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)
 #define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
-#define pMDMA2_D1_CONFIG               ((uint16_t volatile *)MDMA2_D1_CONFIG)
 #define bfin_read_MDMA2_D1_CONFIG()    bfin_read16(MDMA2_D1_CONFIG)
 #define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
-#define pMDMA2_D1_NEXT_DESC_PTR        ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)
 #define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
-#define pMDMA2_D1_START_ADDR           ((void * volatile *)MDMA2_D1_START_ADDR)
 #define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
 #define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
-#define pMDMA2_D1_X_COUNT              ((uint16_t volatile *)MDMA2_D1_X_COUNT)
 #define bfin_read_MDMA2_D1_X_COUNT()   bfin_read16(MDMA2_D1_X_COUNT)
 #define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
-#define pMDMA2_D1_Y_COUNT              ((uint16_t volatile *)MDMA2_D1_Y_COUNT)
 #define bfin_read_MDMA2_D1_Y_COUNT()   bfin_read16(MDMA2_D1_Y_COUNT)
 #define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
-#define pMDMA2_D1_X_MODIFY             ((uint16_t volatile *)MDMA2_D1_X_MODIFY)
 #define bfin_read_MDMA2_D1_X_MODIFY()  bfin_read16(MDMA2_D1_X_MODIFY)
 #define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
-#define pMDMA2_D1_Y_MODIFY             ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)
 #define bfin_read_MDMA2_D1_Y_MODIFY()  bfin_read16(MDMA2_D1_Y_MODIFY)
 #define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
-#define pMDMA2_D1_CURR_DESC_PTR        ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)
 #define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
-#define pMDMA2_D1_CURR_ADDR            ((void * volatile *)MDMA2_D1_CURR_ADDR)
 #define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
 #define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
-#define pMDMA2_D1_CURR_X_COUNT         ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
 #define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
 #define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
-#define pMDMA2_D1_CURR_Y_COUNT         ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)
 #define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
-#define pMDMA2_D1_IRQ_STATUS           ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)
 #define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
 #define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
-#define pMDMA2_D1_PERIPHERAL_MAP       ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)
 #define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG)
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER)
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD)
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH)
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG)
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER)
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD)
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH)
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG)
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER)
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD)
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH)
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG)
 #define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
 #define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER)
 #define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD)
 #define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
 #define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH)
 #define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
 #define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG)
 #define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
 #define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER)
 #define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD)
 #define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
 #define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH)
 #define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
 #define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG)
 #define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
 #define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER)
 #define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD)
 #define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
 #define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH)
 #define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
 #define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG)
 #define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
 #define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER)
 #define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD)
 #define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
 #define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH)
 #define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
 #define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG)
 #define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
 #define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER)
 #define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD)
 #define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
 #define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH)
 #define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
 #define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG)
 #define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
 #define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER)
 #define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
 #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD)
 #define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
 #define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH)
 #define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
 #define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG)
 #define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
 #define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER)
 #define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
 #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD)
 #define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
 #define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH)
 #define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
 #define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG)
 #define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
 #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER)
 #define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
 #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD)
 #define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
 #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH)
 #define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
 #define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER11_CONFIG                ((uint16_t volatile *)TIMER11_CONFIG)
 #define bfin_read_TIMER11_CONFIG()     bfin_read16(TIMER11_CONFIG)
 #define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
-#define pTIMER11_COUNTER               ((uint32_t volatile *)TIMER11_COUNTER)
 #define bfin_read_TIMER11_COUNTER()    bfin_read32(TIMER11_COUNTER)
 #define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
-#define pTIMER11_PERIOD                ((uint32_t volatile *)TIMER11_PERIOD)
 #define bfin_read_TIMER11_PERIOD()     bfin_read32(TIMER11_PERIOD)
 #define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
-#define pTIMER11_WIDTH                 ((uint32_t volatile *)TIMER11_WIDTH)
 #define bfin_read_TIMER11_WIDTH()      bfin_read32(TIMER11_WIDTH)
 #define bfin_write_TIMER11_WIDTH(val)  bfin_write32(TIMER11_WIDTH, val)
-#define pTMRS4_ENABLE                  ((uint32_t volatile *)TMRS4_ENABLE)
 #define bfin_read_TMRS4_ENABLE()       bfin_read32(TMRS4_ENABLE)
 #define bfin_write_TMRS4_ENABLE(val)   bfin_write32(TMRS4_ENABLE, val)
-#define pTMRS4_DISABLE                 ((uint32_t volatile *)TMRS4_DISABLE)
 #define bfin_read_TMRS4_DISABLE()      bfin_read32(TMRS4_DISABLE)
 #define bfin_write_TMRS4_DISABLE(val)  bfin_write32(TMRS4_DISABLE, val)
-#define pTMRS4_STATUS                  ((uint32_t volatile *)TMRS4_STATUS)
 #define bfin_read_TMRS4_STATUS()       bfin_read32(TMRS4_STATUS)
 #define bfin_write_TMRS4_STATUS(val)   bfin_write32(TMRS4_STATUS, val)
-#define pTMRS8_ENABLE                  ((uint32_t volatile *)TMRS8_ENABLE)
 #define bfin_read_TMRS8_ENABLE()       bfin_read32(TMRS8_ENABLE)
 #define bfin_write_TMRS8_ENABLE(val)   bfin_write32(TMRS8_ENABLE, val)
-#define pTMRS8_DISABLE                 ((uint32_t volatile *)TMRS8_DISABLE)
 #define bfin_read_TMRS8_DISABLE()      bfin_read32(TMRS8_DISABLE)
 #define bfin_write_TMRS8_DISABLE(val)  bfin_write32(TMRS8_DISABLE, val)
-#define pTMRS8_STATUS                  ((uint32_t volatile *)TMRS8_STATUS)
 #define bfin_read_TMRS8_STATUS()       bfin_read32(TMRS8_STATUS)
 #define bfin_write_TMRS8_STATUS(val)   bfin_write32(TMRS8_STATUS, val)
-#define pFIO0_FLAG_D                   ((uint16_t volatile *)FIO0_FLAG_D)
 #define bfin_read_FIO0_FLAG_D()        bfin_read16(FIO0_FLAG_D)
 #define bfin_write_FIO0_FLAG_D(val)    bfin_write16(FIO0_FLAG_D, val)
-#define pFIO0_FLAG_C                   ((uint16_t volatile *)FIO0_FLAG_C)
 #define bfin_read_FIO0_FLAG_C()        bfin_read16(FIO0_FLAG_C)
 #define bfin_write_FIO0_FLAG_C(val)    bfin_write16(FIO0_FLAG_C, val)
-#define pFIO0_FLAG_S                   ((uint16_t volatile *)FIO0_FLAG_S)
 #define bfin_read_FIO0_FLAG_S()        bfin_read16(FIO0_FLAG_S)
 #define bfin_write_FIO0_FLAG_S(val)    bfin_write16(FIO0_FLAG_S, val)
-#define pFIO0_FLAG_T                   ((uint16_t volatile *)FIO0_FLAG_T)
 #define bfin_read_FIO0_FLAG_T()        bfin_read16(FIO0_FLAG_T)
 #define bfin_write_FIO0_FLAG_T(val)    bfin_write16(FIO0_FLAG_T, val)
-#define pFIO0_MASKA_D                  ((uint16_t volatile *)FIO0_MASKA_D)
 #define bfin_read_FIO0_MASKA_D()       bfin_read16(FIO0_MASKA_D)
 #define bfin_write_FIO0_MASKA_D(val)   bfin_write16(FIO0_MASKA_D, val)
-#define pFIO0_MASKA_C                  ((uint16_t volatile *)FIO0_MASKA_C)
 #define bfin_read_FIO0_MASKA_C()       bfin_read16(FIO0_MASKA_C)
 #define bfin_write_FIO0_MASKA_C(val)   bfin_write16(FIO0_MASKA_C, val)
-#define pFIO0_MASKA_S                  ((uint16_t volatile *)FIO0_MASKA_S)
 #define bfin_read_FIO0_MASKA_S()       bfin_read16(FIO0_MASKA_S)
 #define bfin_write_FIO0_MASKA_S(val)   bfin_write16(FIO0_MASKA_S, val)
-#define pFIO0_MASKA_T                  ((uint16_t volatile *)FIO0_MASKA_T)
 #define bfin_read_FIO0_MASKA_T()       bfin_read16(FIO0_MASKA_T)
 #define bfin_write_FIO0_MASKA_T(val)   bfin_write16(FIO0_MASKA_T, val)
-#define pFIO0_MASKB_D                  ((uint16_t volatile *)FIO0_MASKB_D)
 #define bfin_read_FIO0_MASKB_D()       bfin_read16(FIO0_MASKB_D)
 #define bfin_write_FIO0_MASKB_D(val)   bfin_write16(FIO0_MASKB_D, val)
-#define pFIO0_MASKB_C                  ((uint16_t volatile *)FIO0_MASKB_C)
 #define bfin_read_FIO0_MASKB_C()       bfin_read16(FIO0_MASKB_C)
 #define bfin_write_FIO0_MASKB_C(val)   bfin_write16(FIO0_MASKB_C, val)
-#define pFIO0_MASKB_S                  ((uint16_t volatile *)FIO0_MASKB_S)
 #define bfin_read_FIO0_MASKB_S()       bfin_read16(FIO0_MASKB_S)
 #define bfin_write_FIO0_MASKB_S(val)   bfin_write16(FIO0_MASKB_S, val)
-#define pFIO0_MASKB_T                  ((uint16_t volatile *)FIO0_MASKB_T)
 #define bfin_read_FIO0_MASKB_T()       bfin_read16(FIO0_MASKB_T)
 #define bfin_write_FIO0_MASKB_T(val)   bfin_write16(FIO0_MASKB_T, val)
-#define pFIO0_DIR                      ((uint16_t volatile *)FIO0_DIR)
 #define bfin_read_FIO0_DIR()           bfin_read16(FIO0_DIR)
 #define bfin_write_FIO0_DIR(val)       bfin_write16(FIO0_DIR, val)
-#define pFIO0_POLAR                    ((uint16_t volatile *)FIO0_POLAR)
 #define bfin_read_FIO0_POLAR()         bfin_read16(FIO0_POLAR)
 #define bfin_write_FIO0_POLAR(val)     bfin_write16(FIO0_POLAR, val)
-#define pFIO0_EDGE                     ((uint16_t volatile *)FIO0_EDGE)
 #define bfin_read_FIO0_EDGE()          bfin_read16(FIO0_EDGE)
 #define bfin_write_FIO0_EDGE(val)      bfin_write16(FIO0_EDGE, val)
-#define pFIO0_BOTH                     ((uint16_t volatile *)FIO0_BOTH)
 #define bfin_read_FIO0_BOTH()          bfin_read16(FIO0_BOTH)
 #define bfin_write_FIO0_BOTH(val)      bfin_write16(FIO0_BOTH, val)
-#define pFIO0_INEN                     ((uint16_t volatile *)FIO0_INEN)
 #define bfin_read_FIO0_INEN()          bfin_read16(FIO0_INEN)
 #define bfin_write_FIO0_INEN(val)      bfin_write16(FIO0_INEN, val)
-#define pFIO1_FLAG_D                   ((uint16_t volatile *)FIO1_FLAG_D)
 #define bfin_read_FIO1_FLAG_D()        bfin_read16(FIO1_FLAG_D)
 #define bfin_write_FIO1_FLAG_D(val)    bfin_write16(FIO1_FLAG_D, val)
-#define pFIO1_FLAG_C                   ((uint16_t volatile *)FIO1_FLAG_C)
 #define bfin_read_FIO1_FLAG_C()        bfin_read16(FIO1_FLAG_C)
 #define bfin_write_FIO1_FLAG_C(val)    bfin_write16(FIO1_FLAG_C, val)
-#define pFIO1_FLAG_S                   ((uint16_t volatile *)FIO1_FLAG_S)
 #define bfin_read_FIO1_FLAG_S()        bfin_read16(FIO1_FLAG_S)
 #define bfin_write_FIO1_FLAG_S(val)    bfin_write16(FIO1_FLAG_S, val)
-#define pFIO1_FLAG_T                   ((uint16_t volatile *)FIO1_FLAG_T)
 #define bfin_read_FIO1_FLAG_T()        bfin_read16(FIO1_FLAG_T)
 #define bfin_write_FIO1_FLAG_T(val)    bfin_write16(FIO1_FLAG_T, val)
-#define pFIO1_MASKA_D                  ((uint16_t volatile *)FIO1_MASKA_D)
 #define bfin_read_FIO1_MASKA_D()       bfin_read16(FIO1_MASKA_D)
 #define bfin_write_FIO1_MASKA_D(val)   bfin_write16(FIO1_MASKA_D, val)
-#define pFIO1_MASKA_C                  ((uint16_t volatile *)FIO1_MASKA_C)
 #define bfin_read_FIO1_MASKA_C()       bfin_read16(FIO1_MASKA_C)
 #define bfin_write_FIO1_MASKA_C(val)   bfin_write16(FIO1_MASKA_C, val)
-#define pFIO1_MASKA_S                  ((uint16_t volatile *)FIO1_MASKA_S)
 #define bfin_read_FIO1_MASKA_S()       bfin_read16(FIO1_MASKA_S)
 #define bfin_write_FIO1_MASKA_S(val)   bfin_write16(FIO1_MASKA_S, val)
-#define pFIO1_MASKA_T                  ((uint16_t volatile *)FIO1_MASKA_T)
 #define bfin_read_FIO1_MASKA_T()       bfin_read16(FIO1_MASKA_T)
 #define bfin_write_FIO1_MASKA_T(val)   bfin_write16(FIO1_MASKA_T, val)
-#define pFIO1_MASKB_D                  ((uint16_t volatile *)FIO1_MASKB_D)
 #define bfin_read_FIO1_MASKB_D()       bfin_read16(FIO1_MASKB_D)
 #define bfin_write_FIO1_MASKB_D(val)   bfin_write16(FIO1_MASKB_D, val)
-#define pFIO1_MASKB_C                  ((uint16_t volatile *)FIO1_MASKB_C)
 #define bfin_read_FIO1_MASKB_C()       bfin_read16(FIO1_MASKB_C)
 #define bfin_write_FIO1_MASKB_C(val)   bfin_write16(FIO1_MASKB_C, val)
-#define pFIO1_MASKB_S                  ((uint16_t volatile *)FIO1_MASKB_S)
 #define bfin_read_FIO1_MASKB_S()       bfin_read16(FIO1_MASKB_S)
 #define bfin_write_FIO1_MASKB_S(val)   bfin_write16(FIO1_MASKB_S, val)
-#define pFIO1_MASKB_T                  ((uint16_t volatile *)FIO1_MASKB_T)
 #define bfin_read_FIO1_MASKB_T()       bfin_read16(FIO1_MASKB_T)
 #define bfin_write_FIO1_MASKB_T(val)   bfin_write16(FIO1_MASKB_T, val)
-#define pFIO1_DIR                      ((uint16_t volatile *)FIO1_DIR)
 #define bfin_read_FIO1_DIR()           bfin_read16(FIO1_DIR)
 #define bfin_write_FIO1_DIR(val)       bfin_write16(FIO1_DIR, val)
-#define pFIO1_POLAR                    ((uint16_t volatile *)FIO1_POLAR)
 #define bfin_read_FIO1_POLAR()         bfin_read16(FIO1_POLAR)
 #define bfin_write_FIO1_POLAR(val)     bfin_write16(FIO1_POLAR, val)
-#define pFIO1_EDGE                     ((uint16_t volatile *)FIO1_EDGE)
 #define bfin_read_FIO1_EDGE()          bfin_read16(FIO1_EDGE)
 #define bfin_write_FIO1_EDGE(val)      bfin_write16(FIO1_EDGE, val)
-#define pFIO1_BOTH                     ((uint16_t volatile *)FIO1_BOTH)
 #define bfin_read_FIO1_BOTH()          bfin_read16(FIO1_BOTH)
 #define bfin_write_FIO1_BOTH(val)      bfin_write16(FIO1_BOTH, val)
-#define pFIO1_INEN                     ((uint16_t volatile *)FIO1_INEN)
 #define bfin_read_FIO1_INEN()          bfin_read16(FIO1_INEN)
 #define bfin_write_FIO1_INEN(val)      bfin_write16(FIO1_INEN, val)
-#define pFIO2_FLAG_D                   ((uint16_t volatile *)FIO2_FLAG_D)
 #define bfin_read_FIO2_FLAG_D()        bfin_read16(FIO2_FLAG_D)
 #define bfin_write_FIO2_FLAG_D(val)    bfin_write16(FIO2_FLAG_D, val)
-#define pFIO2_FLAG_C                   ((uint16_t volatile *)FIO2_FLAG_C)
 #define bfin_read_FIO2_FLAG_C()        bfin_read16(FIO2_FLAG_C)
 #define bfin_write_FIO2_FLAG_C(val)    bfin_write16(FIO2_FLAG_C, val)
-#define pFIO2_FLAG_S                   ((uint16_t volatile *)FIO2_FLAG_S)
 #define bfin_read_FIO2_FLAG_S()        bfin_read16(FIO2_FLAG_S)
 #define bfin_write_FIO2_FLAG_S(val)    bfin_write16(FIO2_FLAG_S, val)
-#define pFIO2_FLAG_T                   ((uint16_t volatile *)FIO2_FLAG_T)
 #define bfin_read_FIO2_FLAG_T()        bfin_read16(FIO2_FLAG_T)
 #define bfin_write_FIO2_FLAG_T(val)    bfin_write16(FIO2_FLAG_T, val)
-#define pFIO2_MASKA_D                  ((uint16_t volatile *)FIO2_MASKA_D)
 #define bfin_read_FIO2_MASKA_D()       bfin_read16(FIO2_MASKA_D)
 #define bfin_write_FIO2_MASKA_D(val)   bfin_write16(FIO2_MASKA_D, val)
-#define pFIO2_MASKA_C                  ((uint16_t volatile *)FIO2_MASKA_C)
 #define bfin_read_FIO2_MASKA_C()       bfin_read16(FIO2_MASKA_C)
 #define bfin_write_FIO2_MASKA_C(val)   bfin_write16(FIO2_MASKA_C, val)
-#define pFIO2_MASKA_S                  ((uint16_t volatile *)FIO2_MASKA_S)
 #define bfin_read_FIO2_MASKA_S()       bfin_read16(FIO2_MASKA_S)
 #define bfin_write_FIO2_MASKA_S(val)   bfin_write16(FIO2_MASKA_S, val)
-#define pFIO2_MASKA_T                  ((uint16_t volatile *)FIO2_MASKA_T)
 #define bfin_read_FIO2_MASKA_T()       bfin_read16(FIO2_MASKA_T)
 #define bfin_write_FIO2_MASKA_T(val)   bfin_write16(FIO2_MASKA_T, val)
-#define pFIO2_MASKB_D                  ((uint16_t volatile *)FIO2_MASKB_D)
 #define bfin_read_FIO2_MASKB_D()       bfin_read16(FIO2_MASKB_D)
 #define bfin_write_FIO2_MASKB_D(val)   bfin_write16(FIO2_MASKB_D, val)
-#define pFIO2_MASKB_C                  ((uint16_t volatile *)FIO2_MASKB_C)
 #define bfin_read_FIO2_MASKB_C()       bfin_read16(FIO2_MASKB_C)
 #define bfin_write_FIO2_MASKB_C(val)   bfin_write16(FIO2_MASKB_C, val)
-#define pFIO2_MASKB_S                  ((uint16_t volatile *)FIO2_MASKB_S)
 #define bfin_read_FIO2_MASKB_S()       bfin_read16(FIO2_MASKB_S)
 #define bfin_write_FIO2_MASKB_S(val)   bfin_write16(FIO2_MASKB_S, val)
-#define pFIO2_MASKB_T                  ((uint16_t volatile *)FIO2_MASKB_T)
 #define bfin_read_FIO2_MASKB_T()       bfin_read16(FIO2_MASKB_T)
 #define bfin_write_FIO2_MASKB_T(val)   bfin_write16(FIO2_MASKB_T, val)
-#define pFIO2_DIR                      ((uint16_t volatile *)FIO2_DIR)
 #define bfin_read_FIO2_DIR()           bfin_read16(FIO2_DIR)
 #define bfin_write_FIO2_DIR(val)       bfin_write16(FIO2_DIR, val)
-#define pFIO2_POLAR                    ((uint16_t volatile *)FIO2_POLAR)
 #define bfin_read_FIO2_POLAR()         bfin_read16(FIO2_POLAR)
 #define bfin_write_FIO2_POLAR(val)     bfin_write16(FIO2_POLAR, val)
-#define pFIO2_EDGE                     ((uint16_t volatile *)FIO2_EDGE)
 #define bfin_read_FIO2_EDGE()          bfin_read16(FIO2_EDGE)
 #define bfin_write_FIO2_EDGE(val)      bfin_write16(FIO2_EDGE, val)
-#define pFIO2_BOTH                     ((uint16_t volatile *)FIO2_BOTH)
 #define bfin_read_FIO2_BOTH()          bfin_read16(FIO2_BOTH)
 #define bfin_write_FIO2_BOTH(val)      bfin_write16(FIO2_BOTH, val)
-#define pFIO2_INEN                     ((uint16_t volatile *)FIO2_INEN)
 #define bfin_read_FIO2_INEN()          bfin_read16(FIO2_INEN)
 #define bfin_write_FIO2_INEN(val)      bfin_write16(FIO2_INEN, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1)
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2)
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV)
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV)
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX)
 #define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1)
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2)
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV)
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV)
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT)
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL)
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1)
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2)
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0                  ((uint32_t volatile *)SPORT0_MTCS0)
 #define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
 #define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1                  ((uint32_t volatile *)SPORT0_MTCS1)
 #define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
 #define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2                  ((uint32_t volatile *)SPORT0_MTCS2)
 #define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
 #define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3                  ((uint32_t volatile *)SPORT0_MTCS3)
 #define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
 #define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0                  ((uint32_t volatile *)SPORT0_MRCS0)
 #define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
 #define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1                  ((uint32_t volatile *)SPORT0_MRCS1)
 #define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
 #define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2                  ((uint32_t volatile *)SPORT0_MRCS2)
 #define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
 #define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3                  ((uint32_t volatile *)SPORT0_MRCS3)
 #define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
 #define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1)
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2)
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV)
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV)
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX)
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX)
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1)
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2)
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV)
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV)
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT)
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL)
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1)
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2)
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0)
 #define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
 #define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1)
 #define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
 #define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2)
 #define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
 #define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3)
 #define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
 #define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0)
 #define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
 #define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1)
 #define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
 #define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2)
 #define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
 #define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3)
 #define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
 #define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define pEVT0                          ((void * volatile *)EVT0)
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1)
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2)
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3)
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4)
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5)
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6)
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7)
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8)
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9)
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10)
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11)
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12)
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13)
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14)
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15)
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL)
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD)
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE)
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT)
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
index af17813..f9352ae 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
@@ -6,67 +6,46 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_core__
 #define __BFIN_CDEF_ADSP_EDN_core__
 
-#define pWPIACTL                       ((uint32_t volatile *)WPIACTL)
 #define bfin_read_WPIACTL()            bfin_read32(WPIACTL)
 #define bfin_write_WPIACTL(val)        bfin_write32(WPIACTL, val)
-#define pWPIA0                         ((void * volatile *)WPIA0)
 #define bfin_read_WPIA0()              bfin_readPTR(WPIA0)
 #define bfin_write_WPIA0(val)          bfin_writePTR(WPIA0, val)
-#define pWPIA1                         ((void * volatile *)WPIA1)
 #define bfin_read_WPIA1()              bfin_readPTR(WPIA1)
 #define bfin_write_WPIA1(val)          bfin_writePTR(WPIA1, val)
-#define pWPIA2                         ((void * volatile *)WPIA2)
 #define bfin_read_WPIA2()              bfin_readPTR(WPIA2)
 #define bfin_write_WPIA2(val)          bfin_writePTR(WPIA2, val)
-#define pWPIA3                         ((void * volatile *)WPIA3)
 #define bfin_read_WPIA3()              bfin_readPTR(WPIA3)
 #define bfin_write_WPIA3(val)          bfin_writePTR(WPIA3, val)
-#define pWPIA4                         ((void * volatile *)WPIA4)
 #define bfin_read_WPIA4()              bfin_readPTR(WPIA4)
 #define bfin_write_WPIA4(val)          bfin_writePTR(WPIA4, val)
-#define pWPIA5                         ((void * volatile *)WPIA5)
 #define bfin_read_WPIA5()              bfin_readPTR(WPIA5)
 #define bfin_write_WPIA5(val)          bfin_writePTR(WPIA5, val)
-#define pWPIACNT0                      ((uint32_t volatile *)WPIACNT0)
 #define bfin_read_WPIACNT0()           bfin_read32(WPIACNT0)
 #define bfin_write_WPIACNT0(val)       bfin_write32(WPIACNT0, val)
-#define pWPIACNT1                      ((uint32_t volatile *)WPIACNT1)
 #define bfin_read_WPIACNT1()           bfin_read32(WPIACNT1)
 #define bfin_write_WPIACNT1(val)       bfin_write32(WPIACNT1, val)
-#define pWPIACNT2                      ((uint32_t volatile *)WPIACNT2)
 #define bfin_read_WPIACNT2()           bfin_read32(WPIACNT2)
 #define bfin_write_WPIACNT2(val)       bfin_write32(WPIACNT2, val)
-#define pWPIACNT3                      ((uint32_t volatile *)WPIACNT3)
 #define bfin_read_WPIACNT3()           bfin_read32(WPIACNT3)
 #define bfin_write_WPIACNT3(val)       bfin_write32(WPIACNT3, val)
-#define pWPIACNT4                      ((uint32_t volatile *)WPIACNT4)
 #define bfin_read_WPIACNT4()           bfin_read32(WPIACNT4)
 #define bfin_write_WPIACNT4(val)       bfin_write32(WPIACNT4, val)
-#define pWPIACNT5                      ((uint32_t volatile *)WPIACNT5)
 #define bfin_read_WPIACNT5()           bfin_read32(WPIACNT5)
 #define bfin_write_WPIACNT5(val)       bfin_write32(WPIACNT5, val)
-#define pWPDACTL                       ((uint32_t volatile *)WPDACTL)
 #define bfin_read_WPDACTL()            bfin_read32(WPDACTL)
 #define bfin_write_WPDACTL(val)        bfin_write32(WPDACTL, val)
-#define pWPDA0                         ((void * volatile *)WPDA0)
 #define bfin_read_WPDA0()              bfin_readPTR(WPDA0)
 #define bfin_write_WPDA0(val)          bfin_writePTR(WPDA0, val)
-#define pWPDA1                         ((void * volatile *)WPDA1)
 #define bfin_read_WPDA1()              bfin_readPTR(WPDA1)
 #define bfin_write_WPDA1(val)          bfin_writePTR(WPDA1, val)
-#define pWPDACNT0                      ((uint32_t volatile *)WPDACNT0)
 #define bfin_read_WPDACNT0()           bfin_read32(WPDACNT0)
 #define bfin_write_WPDACNT0(val)       bfin_write32(WPDACNT0, val)
-#define pWPDACNT1                      ((uint32_t volatile *)WPDACNT1)
 #define bfin_read_WPDACNT1()           bfin_read32(WPDACNT1)
 #define bfin_write_WPDACNT1(val)       bfin_write32(WPDACNT1, val)
-#define pWPSTAT                        ((uint32_t volatile *)WPSTAT)
 #define bfin_read_WPSTAT()             bfin_read32(WPSTAT)
 #define bfin_write_WPSTAT(val)         bfin_write32(WPSTAT, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
 #define bfin_read_DSPID()              bfin_read32(DSPID)
 #define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
-#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
 #define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
 #define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
 
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
index 2e61b5f..ffa9e0a 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
@@ -6,1601 +6,1068 @@
 #ifndef __BFIN_CDEF_ADSP_EDN_extended__
 #define __BFIN_CDEF_ADSP_EDN_extended__
 
-#define pILAT                          ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
 #define bfin_read_ILAT()               bfin_read32(ILAT)
 #define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define pIMASK                         ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
 #define bfin_read_IMASK()              bfin_read32(IMASK)
 #define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define pIPEND                         ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
 #define bfin_read_IPEND()              bfin_read32(IPEND)
 #define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define pIPRIO                         ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
 #define bfin_read_IPRIO()              bfin_read32(IPRIO)
 #define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
 #define bfin_read_TCNTL()              bfin_read32(TCNTL)
 #define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
 #define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
 #define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
 #define bfin_read_TSCALE()             bfin_read32(TSCALE)
 #define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
 #define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
 #define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
-#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
 #define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
 #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
 #define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
 #define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_FAULT_STATUS            ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */
 #define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
 #define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
-#define pDCPLB_FAULT_ADDR              ((uint32_t volatile *)DCPLB_FAULT_ADDR)
 #define bfin_read_DCPLB_FAULT_ADDR()   bfin_read32(DCPLB_FAULT_ADDR)
 #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
 #define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
 #define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
 #define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
 #define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
 #define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
 #define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
 #define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
 #define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
 #define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
 #define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
 #define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
 #define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
 #define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
 #define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
 #define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
 #define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
 #define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
 #define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
 #define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
 #define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
 #define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
 #define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
 #define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
 #define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
 #define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
 #define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
 #define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
 #define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
 #define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
 #define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
 #define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
 #define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
 #define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
 #define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
 #define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
 #define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
 #define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
 #define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
 #define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
 #define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
 #define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
 #define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
 #define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
 #define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
 #define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
 #define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
 #define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
 #define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
 #define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
 #define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
 #define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
 #define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
 #define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
 #define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
 #define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
 #define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
 #define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
 #define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
 #define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
 #define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
 #define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
 #define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
 #define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
 #define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
 #define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
 #define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
 #define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
 #define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
 #define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
 #define bfin_read_EVT0()               bfin_readPTR(EVT0)
 #define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
 #define bfin_read_EVT1()               bfin_readPTR(EVT1)
 #define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
 #define bfin_read_EVT2()               bfin_readPTR(EVT2)
 #define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
 #define bfin_read_EVT3()               bfin_readPTR(EVT3)
 #define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
 #define bfin_read_EVT4()               bfin_readPTR(EVT4)
 #define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
 #define bfin_read_EVT5()               bfin_readPTR(EVT5)
 #define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
 #define bfin_read_EVT6()               bfin_readPTR(EVT6)
 #define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
 #define bfin_read_EVT7()               bfin_readPTR(EVT7)
 #define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
 #define bfin_read_EVT8()               bfin_readPTR(EVT8)
 #define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
 #define bfin_read_EVT9()               bfin_readPTR(EVT9)
 #define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
 #define bfin_read_EVT10()              bfin_readPTR(EVT10)
 #define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define pEVT11                         ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
 #define bfin_read_EVT11()              bfin_readPTR(EVT11)
 #define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define pEVT12                         ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
 #define bfin_read_EVT12()              bfin_readPTR(EVT12)
 #define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define pEVT13                         ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
 #define bfin_read_EVT13()              bfin_readPTR(EVT13)
 #define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define pEVT14                         ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
 #define bfin_read_EVT14()              bfin_readPTR(EVT14)
 #define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define pEVT15                         ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
 #define bfin_read_EVT15()              bfin_readPTR(EVT15)
 #define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
 #define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
 #define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_FAULT_STATUS            ((uint32_t volatile *)ICPLB_FAULT_STATUS)
 #define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS)
 #define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
-#define pICPLB_FAULT_ADDR              ((uint32_t volatile *)ICPLB_FAULT_ADDR)
 #define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
 #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
 #define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
 #define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
 #define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
 #define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
 #define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
 #define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
 #define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
 #define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
 #define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
 #define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
 #define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
 #define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
 #define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
 #define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
 #define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
 #define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
 #define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
 #define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
 #define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
 #define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
 #define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
 #define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
 #define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
 #define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
 #define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
 #define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
 #define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
 #define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
 #define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
 #define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
 #define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
 #define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
 #define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
 #define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
 #define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
 #define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
 #define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
 #define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
 #define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
 #define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
 #define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
 #define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
 #define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
 #define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
 #define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
 #define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
 #define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
 #define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
 #define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
 #define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
 #define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
 #define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
 #define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
 #define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
 #define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
 #define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
 #define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
 #define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
 #define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
 #define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
 #define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
 #define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
 #define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
 #define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
 #define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
 #define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
 #define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pMDMAFLX0_DMACNFG_D            ((uint16_t volatile *)MDMAFLX0_DMACNFG_D)
 #define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
 #define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define pMDMAFLX0_XCOUNT_D             ((uint16_t volatile *)MDMAFLX0_XCOUNT_D)
 #define bfin_read_MDMAFLX0_XCOUNT_D()  bfin_read16(MDMAFLX0_XCOUNT_D)
 #define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define pMDMAFLX0_XMODIFY_D            ((uint16_t volatile *)MDMAFLX0_XMODIFY_D)
 #define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
 #define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define pMDMAFLX0_YCOUNT_D             ((uint16_t volatile *)MDMAFLX0_YCOUNT_D)
 #define bfin_read_MDMAFLX0_YCOUNT_D()  bfin_read16(MDMAFLX0_YCOUNT_D)
 #define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define pMDMAFLX0_YMODIFY_D            ((uint16_t volatile *)MDMAFLX0_YMODIFY_D)
 #define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
 #define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define pMDMAFLX0_IRQSTAT_D            ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D)
 #define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
 #define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define pMDMAFLX0_PMAP_D               ((uint16_t volatile *)MDMAFLX0_PMAP_D)
 #define bfin_read_MDMAFLX0_PMAP_D()    bfin_read16(MDMAFLX0_PMAP_D)
 #define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define pMDMAFLX0_CURXCOUNT_D          ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D)
 #define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
 #define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define pMDMAFLX0_CURYCOUNT_D          ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D)
 #define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
 #define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define pMDMAFLX0_DMACNFG_S            ((uint16_t volatile *)MDMAFLX0_DMACNFG_S)
 #define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
 #define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define pMDMAFLX0_XCOUNT_S             ((uint16_t volatile *)MDMAFLX0_XCOUNT_S)
 #define bfin_read_MDMAFLX0_XCOUNT_S()  bfin_read16(MDMAFLX0_XCOUNT_S)
 #define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define pMDMAFLX0_XMODIFY_S            ((uint16_t volatile *)MDMAFLX0_XMODIFY_S)
 #define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
 #define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define pMDMAFLX0_YCOUNT_S             ((uint16_t volatile *)MDMAFLX0_YCOUNT_S)
 #define bfin_read_MDMAFLX0_YCOUNT_S()  bfin_read16(MDMAFLX0_YCOUNT_S)
 #define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define pMDMAFLX0_YMODIFY_S            ((uint16_t volatile *)MDMAFLX0_YMODIFY_S)
 #define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
 #define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define pMDMAFLX0_IRQSTAT_S            ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S)
 #define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
 #define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define pMDMAFLX0_PMAP_S               ((uint16_t volatile *)MDMAFLX0_PMAP_S)
 #define bfin_read_MDMAFLX0_PMAP_S()    bfin_read16(MDMAFLX0_PMAP_S)
 #define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define pMDMAFLX0_CURXCOUNT_S          ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S)
 #define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
 #define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define pMDMAFLX0_CURYCOUNT_S          ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S)
 #define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
 #define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define pMDMAFLX1_DMACNFG_D            ((uint16_t volatile *)MDMAFLX1_DMACNFG_D)
 #define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
 #define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define pMDMAFLX1_XCOUNT_D             ((uint16_t volatile *)MDMAFLX1_XCOUNT_D)
 #define bfin_read_MDMAFLX1_XCOUNT_D()  bfin_read16(MDMAFLX1_XCOUNT_D)
 #define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define pMDMAFLX1_XMODIFY_D            ((uint16_t volatile *)MDMAFLX1_XMODIFY_D)
 #define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
 #define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define pMDMAFLX1_YCOUNT_D             ((uint16_t volatile *)MDMAFLX1_YCOUNT_D)
 #define bfin_read_MDMAFLX1_YCOUNT_D()  bfin_read16(MDMAFLX1_YCOUNT_D)
 #define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define pMDMAFLX1_YMODIFY_D            ((uint16_t volatile *)MDMAFLX1_YMODIFY_D)
 #define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
 #define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define pMDMAFLX1_IRQSTAT_D            ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D)
 #define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
 #define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define pMDMAFLX1_PMAP_D               ((uint16_t volatile *)MDMAFLX1_PMAP_D)
 #define bfin_read_MDMAFLX1_PMAP_D()    bfin_read16(MDMAFLX1_PMAP_D)
 #define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define pMDMAFLX1_CURXCOUNT_D          ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D)
 #define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
 #define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define pMDMAFLX1_CURYCOUNT_D          ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D)
 #define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
 #define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define pMDMAFLX1_DMACNFG_S            ((uint16_t volatile *)MDMAFLX1_DMACNFG_S)
 #define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
 #define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define pMDMAFLX1_XCOUNT_S             ((uint16_t volatile *)MDMAFLX1_XCOUNT_S)
 #define bfin_read_MDMAFLX1_XCOUNT_S()  bfin_read16(MDMAFLX1_XCOUNT_S)
 #define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define pMDMAFLX1_XMODIFY_S            ((uint16_t volatile *)MDMAFLX1_XMODIFY_S)
 #define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
 #define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define pMDMAFLX1_YCOUNT_S             ((uint16_t volatile *)MDMAFLX1_YCOUNT_S)
 #define bfin_read_MDMAFLX1_YCOUNT_S()  bfin_read16(MDMAFLX1_YCOUNT_S)
 #define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define pMDMAFLX1_YMODIFY_S            ((uint16_t volatile *)MDMAFLX1_YMODIFY_S)
 #define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
 #define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define pMDMAFLX1_IRQSTAT_S            ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S)
 #define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
 #define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define pMDMAFLX1_PMAP_S               ((uint16_t volatile *)MDMAFLX1_PMAP_S)
 #define bfin_read_MDMAFLX1_PMAP_S()    bfin_read16(MDMAFLX1_PMAP_S)
 #define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define pMDMAFLX1_CURXCOUNT_S          ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S)
 #define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
 #define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define pMDMAFLX1_CURYCOUNT_S          ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S)
 #define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
 #define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define pDMAFLX0_DMACNFG               ((uint16_t volatile *)DMAFLX0_DMACNFG)
 #define bfin_read_DMAFLX0_DMACNFG()    bfin_read16(DMAFLX0_DMACNFG)
 #define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define pDMAFLX0_XCOUNT                ((uint16_t volatile *)DMAFLX0_XCOUNT)
 #define bfin_read_DMAFLX0_XCOUNT()     bfin_read16(DMAFLX0_XCOUNT)
 #define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define pDMAFLX0_XMODIFY               ((uint16_t volatile *)DMAFLX0_XMODIFY)
 #define bfin_read_DMAFLX0_XMODIFY()    bfin_read16(DMAFLX0_XMODIFY)
 #define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define pDMAFLX0_YCOUNT                ((uint16_t volatile *)DMAFLX0_YCOUNT)
 #define bfin_read_DMAFLX0_YCOUNT()     bfin_read16(DMAFLX0_YCOUNT)
 #define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define pDMAFLX0_YMODIFY               ((uint16_t volatile *)DMAFLX0_YMODIFY)
 #define bfin_read_DMAFLX0_YMODIFY()    bfin_read16(DMAFLX0_YMODIFY)
 #define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define pDMAFLX0_IRQSTAT               ((uint16_t volatile *)DMAFLX0_IRQSTAT)
 #define bfin_read_DMAFLX0_IRQSTAT()    bfin_read16(DMAFLX0_IRQSTAT)
 #define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define pDMAFLX0_PMAP                  ((uint16_t volatile *)DMAFLX0_PMAP)
 #define bfin_read_DMAFLX0_PMAP()       bfin_read16(DMAFLX0_PMAP)
 #define bfin_write_DMAFLX0_PMAP(val)   bfin_write16(DMAFLX0_PMAP, val)
-#define pDMAFLX0_CURXCOUNT             ((uint16_t volatile *)DMAFLX0_CURXCOUNT)
 #define bfin_read_DMAFLX0_CURXCOUNT()  bfin_read16(DMAFLX0_CURXCOUNT)
 #define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define pDMAFLX0_CURYCOUNT             ((uint16_t volatile *)DMAFLX0_CURYCOUNT)
 #define bfin_read_DMAFLX0_CURYCOUNT()  bfin_read16(DMAFLX0_CURYCOUNT)
 #define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define pDMAFLX1_DMACNFG               ((uint16_t volatile *)DMAFLX1_DMACNFG)
 #define bfin_read_DMAFLX1_DMACNFG()    bfin_read16(DMAFLX1_DMACNFG)
 #define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define pDMAFLX1_XCOUNT                ((uint16_t volatile *)DMAFLX1_XCOUNT)
 #define bfin_read_DMAFLX1_XCOUNT()     bfin_read16(DMAFLX1_XCOUNT)
 #define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define pDMAFLX1_XMODIFY               ((uint16_t volatile *)DMAFLX1_XMODIFY)
 #define bfin_read_DMAFLX1_XMODIFY()    bfin_read16(DMAFLX1_XMODIFY)
 #define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define pDMAFLX1_YCOUNT                ((uint16_t volatile *)DMAFLX1_YCOUNT)
 #define bfin_read_DMAFLX1_YCOUNT()     bfin_read16(DMAFLX1_YCOUNT)
 #define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define pDMAFLX1_YMODIFY               ((uint16_t volatile *)DMAFLX1_YMODIFY)
 #define bfin_read_DMAFLX1_YMODIFY()    bfin_read16(DMAFLX1_YMODIFY)
 #define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define pDMAFLX1_IRQSTAT               ((uint16_t volatile *)DMAFLX1_IRQSTAT)
 #define bfin_read_DMAFLX1_IRQSTAT()    bfin_read16(DMAFLX1_IRQSTAT)
 #define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define pDMAFLX1_PMAP                  ((uint16_t volatile *)DMAFLX1_PMAP)
 #define bfin_read_DMAFLX1_PMAP()       bfin_read16(DMAFLX1_PMAP)
 #define bfin_write_DMAFLX1_PMAP(val)   bfin_write16(DMAFLX1_PMAP, val)
-#define pDMAFLX1_CURXCOUNT             ((uint16_t volatile *)DMAFLX1_CURXCOUNT)
 #define bfin_read_DMAFLX1_CURXCOUNT()  bfin_read16(DMAFLX1_CURXCOUNT)
 #define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define pDMAFLX1_CURYCOUNT             ((uint16_t volatile *)DMAFLX1_CURYCOUNT)
 #define bfin_read_DMAFLX1_CURYCOUNT()  bfin_read16(DMAFLX1_CURYCOUNT)
 #define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define pDMAFLX2_DMACNFG               ((uint16_t volatile *)DMAFLX2_DMACNFG)
 #define bfin_read_DMAFLX2_DMACNFG()    bfin_read16(DMAFLX2_DMACNFG)
 #define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define pDMAFLX2_XCOUNT                ((uint16_t volatile *)DMAFLX2_XCOUNT)
 #define bfin_read_DMAFLX2_XCOUNT()     bfin_read16(DMAFLX2_XCOUNT)
 #define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define pDMAFLX2_XMODIFY               ((uint16_t volatile *)DMAFLX2_XMODIFY)
 #define bfin_read_DMAFLX2_XMODIFY()    bfin_read16(DMAFLX2_XMODIFY)
 #define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define pDMAFLX2_YCOUNT                ((uint16_t volatile *)DMAFLX2_YCOUNT)
 #define bfin_read_DMAFLX2_YCOUNT()     bfin_read16(DMAFLX2_YCOUNT)
 #define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define pDMAFLX2_YMODIFY               ((uint16_t volatile *)DMAFLX2_YMODIFY)
 #define bfin_read_DMAFLX2_YMODIFY()    bfin_read16(DMAFLX2_YMODIFY)
 #define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define pDMAFLX2_IRQSTAT               ((uint16_t volatile *)DMAFLX2_IRQSTAT)
 #define bfin_read_DMAFLX2_IRQSTAT()    bfin_read16(DMAFLX2_IRQSTAT)
 #define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define pDMAFLX2_PMAP                  ((uint16_t volatile *)DMAFLX2_PMAP)
 #define bfin_read_DMAFLX2_PMAP()       bfin_read16(DMAFLX2_PMAP)
 #define bfin_write_DMAFLX2_PMAP(val)   bfin_write16(DMAFLX2_PMAP, val)
-#define pDMAFLX2_CURXCOUNT             ((uint16_t volatile *)DMAFLX2_CURXCOUNT)
 #define bfin_read_DMAFLX2_CURXCOUNT()  bfin_read16(DMAFLX2_CURXCOUNT)
 #define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define pDMAFLX2_CURYCOUNT             ((uint16_t volatile *)DMAFLX2_CURYCOUNT)
 #define bfin_read_DMAFLX2_CURYCOUNT()  bfin_read16(DMAFLX2_CURYCOUNT)
 #define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define pDMAFLX3_DMACNFG               ((uint16_t volatile *)DMAFLX3_DMACNFG)
 #define bfin_read_DMAFLX3_DMACNFG()    bfin_read16(DMAFLX3_DMACNFG)
 #define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define pDMAFLX3_XCOUNT                ((uint16_t volatile *)DMAFLX3_XCOUNT)
 #define bfin_read_DMAFLX3_XCOUNT()     bfin_read16(DMAFLX3_XCOUNT)
 #define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define pDMAFLX3_XMODIFY               ((uint16_t volatile *)DMAFLX3_XMODIFY)
 #define bfin_read_DMAFLX3_XMODIFY()    bfin_read16(DMAFLX3_XMODIFY)
 #define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define pDMAFLX3_YCOUNT                ((uint16_t volatile *)DMAFLX3_YCOUNT)
 #define bfin_read_DMAFLX3_YCOUNT()     bfin_read16(DMAFLX3_YCOUNT)
 #define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define pDMAFLX3_YMODIFY               ((uint16_t volatile *)DMAFLX3_YMODIFY)
 #define bfin_read_DMAFLX3_YMODIFY()    bfin_read16(DMAFLX3_YMODIFY)
 #define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define pDMAFLX3_IRQSTAT               ((uint16_t volatile *)DMAFLX3_IRQSTAT)
 #define bfin_read_DMAFLX3_IRQSTAT()    bfin_read16(DMAFLX3_IRQSTAT)
 #define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define pDMAFLX3_PMAP                  ((uint16_t volatile *)DMAFLX3_PMAP)
 #define bfin_read_DMAFLX3_PMAP()       bfin_read16(DMAFLX3_PMAP)
 #define bfin_write_DMAFLX3_PMAP(val)   bfin_write16(DMAFLX3_PMAP, val)
-#define pDMAFLX3_CURXCOUNT             ((uint16_t volatile *)DMAFLX3_CURXCOUNT)
 #define bfin_read_DMAFLX3_CURXCOUNT()  bfin_read16(DMAFLX3_CURXCOUNT)
 #define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define pDMAFLX3_CURYCOUNT             ((uint16_t volatile *)DMAFLX3_CURYCOUNT)
 #define bfin_read_DMAFLX3_CURYCOUNT()  bfin_read16(DMAFLX3_CURYCOUNT)
 #define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define pDMAFLX4_DMACNFG               ((uint16_t volatile *)DMAFLX4_DMACNFG)
 #define bfin_read_DMAFLX4_DMACNFG()    bfin_read16(DMAFLX4_DMACNFG)
 #define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define pDMAFLX4_XCOUNT                ((uint16_t volatile *)DMAFLX4_XCOUNT)
 #define bfin_read_DMAFLX4_XCOUNT()     bfin_read16(DMAFLX4_XCOUNT)
 #define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define pDMAFLX4_XMODIFY               ((uint16_t volatile *)DMAFLX4_XMODIFY)
 #define bfin_read_DMAFLX4_XMODIFY()    bfin_read16(DMAFLX4_XMODIFY)
 #define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define pDMAFLX4_YCOUNT                ((uint16_t volatile *)DMAFLX4_YCOUNT)
 #define bfin_read_DMAFLX4_YCOUNT()     bfin_read16(DMAFLX4_YCOUNT)
 #define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define pDMAFLX4_YMODIFY               ((uint16_t volatile *)DMAFLX4_YMODIFY)
 #define bfin_read_DMAFLX4_YMODIFY()    bfin_read16(DMAFLX4_YMODIFY)
 #define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define pDMAFLX4_IRQSTAT               ((uint16_t volatile *)DMAFLX4_IRQSTAT)
 #define bfin_read_DMAFLX4_IRQSTAT()    bfin_read16(DMAFLX4_IRQSTAT)
 #define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define pDMAFLX4_PMAP                  ((uint16_t volatile *)DMAFLX4_PMAP)
 #define bfin_read_DMAFLX4_PMAP()       bfin_read16(DMAFLX4_PMAP)
 #define bfin_write_DMAFLX4_PMAP(val)   bfin_write16(DMAFLX4_PMAP, val)
-#define pDMAFLX4_CURXCOUNT             ((uint16_t volatile *)DMAFLX4_CURXCOUNT)
 #define bfin_read_DMAFLX4_CURXCOUNT()  bfin_read16(DMAFLX4_CURXCOUNT)
 #define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define pDMAFLX4_CURYCOUNT             ((uint16_t volatile *)DMAFLX4_CURYCOUNT)
 #define bfin_read_DMAFLX4_CURYCOUNT()  bfin_read16(DMAFLX4_CURYCOUNT)
 #define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define pDMAFLX5_DMACNFG               ((uint16_t volatile *)DMAFLX5_DMACNFG)
 #define bfin_read_DMAFLX5_DMACNFG()    bfin_read16(DMAFLX5_DMACNFG)
 #define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define pDMAFLX5_XCOUNT                ((uint16_t volatile *)DMAFLX5_XCOUNT)
 #define bfin_read_DMAFLX5_XCOUNT()     bfin_read16(DMAFLX5_XCOUNT)
 #define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define pDMAFLX5_XMODIFY               ((uint16_t volatile *)DMAFLX5_XMODIFY)
 #define bfin_read_DMAFLX5_XMODIFY()    bfin_read16(DMAFLX5_XMODIFY)
 #define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define pDMAFLX5_YCOUNT                ((uint16_t volatile *)DMAFLX5_YCOUNT)
 #define bfin_read_DMAFLX5_YCOUNT()     bfin_read16(DMAFLX5_YCOUNT)
 #define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define pDMAFLX5_YMODIFY               ((uint16_t volatile *)DMAFLX5_YMODIFY)
 #define bfin_read_DMAFLX5_YMODIFY()    bfin_read16(DMAFLX5_YMODIFY)
 #define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define pDMAFLX5_IRQSTAT               ((uint16_t volatile *)DMAFLX5_IRQSTAT)
 #define bfin_read_DMAFLX5_IRQSTAT()    bfin_read16(DMAFLX5_IRQSTAT)
 #define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define pDMAFLX5_PMAP                  ((uint16_t volatile *)DMAFLX5_PMAP)
 #define bfin_read_DMAFLX5_PMAP()       bfin_read16(DMAFLX5_PMAP)
 #define bfin_write_DMAFLX5_PMAP(val)   bfin_write16(DMAFLX5_PMAP, val)
-#define pDMAFLX5_CURXCOUNT             ((uint16_t volatile *)DMAFLX5_CURXCOUNT)
 #define bfin_read_DMAFLX5_CURXCOUNT()  bfin_read16(DMAFLX5_CURXCOUNT)
 #define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define pDMAFLX5_CURYCOUNT             ((uint16_t volatile *)DMAFLX5_CURYCOUNT)
 #define bfin_read_DMAFLX5_CURYCOUNT()  bfin_read16(DMAFLX5_CURYCOUNT)
 #define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define pDMAFLX6_DMACNFG               ((uint16_t volatile *)DMAFLX6_DMACNFG)
 #define bfin_read_DMAFLX6_DMACNFG()    bfin_read16(DMAFLX6_DMACNFG)
 #define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define pDMAFLX6_XCOUNT                ((uint16_t volatile *)DMAFLX6_XCOUNT)
 #define bfin_read_DMAFLX6_XCOUNT()     bfin_read16(DMAFLX6_XCOUNT)
 #define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define pDMAFLX6_XMODIFY               ((uint16_t volatile *)DMAFLX6_XMODIFY)
 #define bfin_read_DMAFLX6_XMODIFY()    bfin_read16(DMAFLX6_XMODIFY)
 #define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define pDMAFLX6_YCOUNT                ((uint16_t volatile *)DMAFLX6_YCOUNT)
 #define bfin_read_DMAFLX6_YCOUNT()     bfin_read16(DMAFLX6_YCOUNT)
 #define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define pDMAFLX6_YMODIFY               ((uint16_t volatile *)DMAFLX6_YMODIFY)
 #define bfin_read_DMAFLX6_YMODIFY()    bfin_read16(DMAFLX6_YMODIFY)
 #define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define pDMAFLX6_IRQSTAT               ((uint16_t volatile *)DMAFLX6_IRQSTAT)
 #define bfin_read_DMAFLX6_IRQSTAT()    bfin_read16(DMAFLX6_IRQSTAT)
 #define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define pDMAFLX6_PMAP                  ((uint16_t volatile *)DMAFLX6_PMAP)
 #define bfin_read_DMAFLX6_PMAP()       bfin_read16(DMAFLX6_PMAP)
 #define bfin_write_DMAFLX6_PMAP(val)   bfin_write16(DMAFLX6_PMAP, val)
-#define pDMAFLX6_CURXCOUNT             ((uint16_t volatile *)DMAFLX6_CURXCOUNT)
 #define bfin_read_DMAFLX6_CURXCOUNT()  bfin_read16(DMAFLX6_CURXCOUNT)
 #define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define pDMAFLX6_CURYCOUNT             ((uint16_t volatile *)DMAFLX6_CURYCOUNT)
 #define bfin_read_DMAFLX6_CURYCOUNT()  bfin_read16(DMAFLX6_CURYCOUNT)
 #define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define pDMAFLX7_DMACNFG               ((uint16_t volatile *)DMAFLX7_DMACNFG)
 #define bfin_read_DMAFLX7_DMACNFG()    bfin_read16(DMAFLX7_DMACNFG)
 #define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define pDMAFLX7_XCOUNT                ((uint16_t volatile *)DMAFLX7_XCOUNT)
 #define bfin_read_DMAFLX7_XCOUNT()     bfin_read16(DMAFLX7_XCOUNT)
 #define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define pDMAFLX7_XMODIFY               ((uint16_t volatile *)DMAFLX7_XMODIFY)
 #define bfin_read_DMAFLX7_XMODIFY()    bfin_read16(DMAFLX7_XMODIFY)
 #define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define pDMAFLX7_YCOUNT                ((uint16_t volatile *)DMAFLX7_YCOUNT)
 #define bfin_read_DMAFLX7_YCOUNT()     bfin_read16(DMAFLX7_YCOUNT)
 #define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define pDMAFLX7_YMODIFY               ((uint16_t volatile *)DMAFLX7_YMODIFY)
 #define bfin_read_DMAFLX7_YMODIFY()    bfin_read16(DMAFLX7_YMODIFY)
 #define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define pDMAFLX7_IRQSTAT               ((uint16_t volatile *)DMAFLX7_IRQSTAT)
 #define bfin_read_DMAFLX7_IRQSTAT()    bfin_read16(DMAFLX7_IRQSTAT)
 #define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define pDMAFLX7_PMAP                  ((uint16_t volatile *)DMAFLX7_PMAP)
 #define bfin_read_DMAFLX7_PMAP()       bfin_read16(DMAFLX7_PMAP)
 #define bfin_write_DMAFLX7_PMAP(val)   bfin_write16(DMAFLX7_PMAP, val)
-#define pDMAFLX7_CURXCOUNT             ((uint16_t volatile *)DMAFLX7_CURXCOUNT)
 #define bfin_read_DMAFLX7_CURXCOUNT()  bfin_read16(DMAFLX7_CURXCOUNT)
 #define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define pDMAFLX7_CURYCOUNT             ((uint16_t volatile *)DMAFLX7_CURYCOUNT)
 #define bfin_read_DMAFLX7_CURYCOUNT()  bfin_read16(DMAFLX7_CURYCOUNT)
 #define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG)
 #define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
 #define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER)
 #define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD)
 #define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
 #define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH)
 #define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
 #define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG)
 #define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
 #define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER)
 #define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD)
 #define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
 #define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH)
 #define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
 #define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG)
 #define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
 #define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER)
 #define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD)
 #define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
 #define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH)
 #define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
 #define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE)
 #define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
 #define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE)
 #define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
 #define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS                  ((uint16_t volatile *)TIMER_STATUS)
 #define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
 #define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
-#define pSIC_RVECT                     ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
 #define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
 #define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK                     ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
 #define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
 #define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
 #define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
 #define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
 #define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
 #define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
 #define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
 #define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
 #define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
 #define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR                       ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
 #define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
 #define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define pSIC_IWR                       ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
 #define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
 #define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define pUART_THR                      ((uint16_t volatile *)UART_THR) /* Transmit Holding */
 #define bfin_read_UART_THR()           bfin_read16(UART_THR)
 #define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
-#define pUART_DLL                      ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */
 #define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
 #define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
-#define pUART_DLH                      ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */
 #define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
 #define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
-#define pUART_IER                      ((uint16_t volatile *)UART_IER)
 #define bfin_read_UART_IER()           bfin_read16(UART_IER)
 #define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
-#define pUART_IIR                      ((uint16_t volatile *)UART_IIR)
 #define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
 #define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
-#define pUART_LCR                      ((uint16_t volatile *)UART_LCR)
 #define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
 #define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
-#define pUART_MCR                      ((uint16_t volatile *)UART_MCR)
 #define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
 #define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
-#define pUART_LSR                      ((uint16_t volatile *)UART_LSR)
 #define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
 #define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
-#define pUART_SCR                      ((uint16_t volatile *)UART_SCR)
 #define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
 #define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
-#define pUART_RBR                      ((uint16_t volatile *)UART_RBR) /* Receive Buffer */
 #define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
 #define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
-#define pUART_GCTL                     ((uint16_t volatile *)UART_GCTL)
 #define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
 #define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
-#define pSPT0_TX_CONFIG0               ((uint16_t volatile *)SPT0_TX_CONFIG0)
 #define bfin_read_SPT0_TX_CONFIG0()    bfin_read16(SPT0_TX_CONFIG0)
 #define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define pSPT0_TX_CONFIG1               ((uint16_t volatile *)SPT0_TX_CONFIG1)
 #define bfin_read_SPT0_TX_CONFIG1()    bfin_read16(SPT0_TX_CONFIG1)
 #define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define pSPT0_RX_CONFIG0               ((uint16_t volatile *)SPT0_RX_CONFIG0)
 #define bfin_read_SPT0_RX_CONFIG0()    bfin_read16(SPT0_RX_CONFIG0)
 #define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define pSPT0_RX_CONFIG1               ((uint16_t volatile *)SPT0_RX_CONFIG1)
 #define bfin_read_SPT0_RX_CONFIG1()    bfin_read16(SPT0_RX_CONFIG1)
 #define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define pSPT0_TX                       ((uint32_t volatile *)SPT0_TX)
 #define bfin_read_SPT0_TX()            bfin_read32(SPT0_TX)
 #define bfin_write_SPT0_TX(val)        bfin_write32(SPT0_TX, val)
-#define pSPT0_RX                       ((uint32_t volatile *)SPT0_RX)
 #define bfin_read_SPT0_RX()            bfin_read32(SPT0_RX)
 #define bfin_write_SPT0_RX(val)        bfin_write32(SPT0_RX, val)
-#define pSPT0_TSCLKDIV                 ((uint16_t volatile *)SPT0_TSCLKDIV)
 #define bfin_read_SPT0_TSCLKDIV()      bfin_read16(SPT0_TSCLKDIV)
 #define bfin_write_SPT0_TSCLKDIV(val)  bfin_write16(SPT0_TSCLKDIV, val)
-#define pSPT0_RSCLKDIV                 ((uint16_t volatile *)SPT0_RSCLKDIV)
 #define bfin_read_SPT0_RSCLKDIV()      bfin_read16(SPT0_RSCLKDIV)
 #define bfin_write_SPT0_RSCLKDIV(val)  bfin_write16(SPT0_RSCLKDIV, val)
-#define pSPT0_TFSDIV                   ((uint16_t volatile *)SPT0_TFSDIV)
 #define bfin_read_SPT0_TFSDIV()        bfin_read16(SPT0_TFSDIV)
 #define bfin_write_SPT0_TFSDIV(val)    bfin_write16(SPT0_TFSDIV, val)
-#define pSPT0_RFSDIV                   ((uint16_t volatile *)SPT0_RFSDIV)
 #define bfin_read_SPT0_RFSDIV()        bfin_read16(SPT0_RFSDIV)
 #define bfin_write_SPT0_RFSDIV(val)    bfin_write16(SPT0_RFSDIV, val)
-#define pSPT0_STAT                     ((uint16_t volatile *)SPT0_STAT)
 #define bfin_read_SPT0_STAT()          bfin_read16(SPT0_STAT)
 #define bfin_write_SPT0_STAT(val)      bfin_write16(SPT0_STAT, val)
-#define pSPT0_MTCS0                    ((uint32_t volatile *)SPT0_MTCS0)
 #define bfin_read_SPT0_MTCS0()         bfin_read32(SPT0_MTCS0)
 #define bfin_write_SPT0_MTCS0(val)     bfin_write32(SPT0_MTCS0, val)
-#define pSPT0_MTCS1                    ((uint32_t volatile *)SPT0_MTCS1)
 #define bfin_read_SPT0_MTCS1()         bfin_read32(SPT0_MTCS1)
 #define bfin_write_SPT0_MTCS1(val)     bfin_write32(SPT0_MTCS1, val)
-#define pSPT0_MTCS2                    ((uint32_t volatile *)SPT0_MTCS2)
 #define bfin_read_SPT0_MTCS2()         bfin_read32(SPT0_MTCS2)
 #define bfin_write_SPT0_MTCS2(val)     bfin_write32(SPT0_MTCS2, val)
-#define pSPT0_MTCS3                    ((uint32_t volatile *)SPT0_MTCS3)
 #define bfin_read_SPT0_MTCS3()         bfin_read32(SPT0_MTCS3)
 #define bfin_write_SPT0_MTCS3(val)     bfin_write32(SPT0_MTCS3, val)
-#define pSPT0_MRCS0                    ((uint32_t volatile *)SPT0_MRCS0)
 #define bfin_read_SPT0_MRCS0()         bfin_read32(SPT0_MRCS0)
 #define bfin_write_SPT0_MRCS0(val)     bfin_write32(SPT0_MRCS0, val)
-#define pSPT0_MRCS1                    ((uint32_t volatile *)SPT0_MRCS1)
 #define bfin_read_SPT0_MRCS1()         bfin_read32(SPT0_MRCS1)
 #define bfin_write_SPT0_MRCS1(val)     bfin_write32(SPT0_MRCS1, val)
-#define pSPT0_MRCS2                    ((uint32_t volatile *)SPT0_MRCS2)
 #define bfin_read_SPT0_MRCS2()         bfin_read32(SPT0_MRCS2)
 #define bfin_write_SPT0_MRCS2(val)     bfin_write32(SPT0_MRCS2, val)
-#define pSPT0_MRCS3                    ((uint32_t volatile *)SPT0_MRCS3)
 #define bfin_read_SPT0_MRCS3()         bfin_read32(SPT0_MRCS3)
 #define bfin_write_SPT0_MRCS3(val)     bfin_write32(SPT0_MRCS3, val)
-#define pSPT0_MCMC1                    ((uint16_t volatile *)SPT0_MCMC1)
 #define bfin_read_SPT0_MCMC1()         bfin_read16(SPT0_MCMC1)
 #define bfin_write_SPT0_MCMC1(val)     bfin_write16(SPT0_MCMC1, val)
-#define pSPT0_MCMC2                    ((uint16_t volatile *)SPT0_MCMC2)
 #define bfin_read_SPT0_MCMC2()         bfin_read16(SPT0_MCMC2)
 #define bfin_write_SPT0_MCMC2(val)     bfin_write16(SPT0_MCMC2, val)
-#define pSPT0_CHNL                     ((uint16_t volatile *)SPT0_CHNL)
 #define bfin_read_SPT0_CHNL()          bfin_read16(SPT0_CHNL)
 #define bfin_write_SPT0_CHNL(val)      bfin_write16(SPT0_CHNL, val)
-#define pSPT1_TX_CONFIG0               ((uint16_t volatile *)SPT1_TX_CONFIG0)
 #define bfin_read_SPT1_TX_CONFIG0()    bfin_read16(SPT1_TX_CONFIG0)
 #define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define pSPT1_TX_CONFIG1               ((uint16_t volatile *)SPT1_TX_CONFIG1)
 #define bfin_read_SPT1_TX_CONFIG1()    bfin_read16(SPT1_TX_CONFIG1)
 #define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define pSPT1_RX_CONFIG0               ((uint16_t volatile *)SPT1_RX_CONFIG0)
 #define bfin_read_SPT1_RX_CONFIG0()    bfin_read16(SPT1_RX_CONFIG0)
 #define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define pSPT1_RX_CONFIG1               ((uint16_t volatile *)SPT1_RX_CONFIG1)
 #define bfin_read_SPT1_RX_CONFIG1()    bfin_read16(SPT1_RX_CONFIG1)
 #define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define pSPT1_TX                       ((uint16_t volatile *)SPT1_TX)
 #define bfin_read_SPT1_TX()            bfin_read16(SPT1_TX)
 #define bfin_write_SPT1_TX(val)        bfin_write16(SPT1_TX, val)
-#define pSPT1_RX                       ((uint16_t volatile *)SPT1_RX)
 #define bfin_read_SPT1_RX()            bfin_read16(SPT1_RX)
 #define bfin_write_SPT1_RX(val)        bfin_write16(SPT1_RX, val)
-#define pSPT1_TSCLKDIV                 ((uint16_t volatile *)SPT1_TSCLKDIV)
 #define bfin_read_SPT1_TSCLKDIV()      bfin_read16(SPT1_TSCLKDIV)
 #define bfin_write_SPT1_TSCLKDIV(val)  bfin_write16(SPT1_TSCLKDIV, val)
-#define pSPT1_RSCLKDIV                 ((uint16_t volatile *)SPT1_RSCLKDIV)
 #define bfin_read_SPT1_RSCLKDIV()      bfin_read16(SPT1_RSCLKDIV)
 #define bfin_write_SPT1_RSCLKDIV(val)  bfin_write16(SPT1_RSCLKDIV, val)
-#define pSPT1_TFSDIV                   ((uint16_t volatile *)SPT1_TFSDIV)
 #define bfin_read_SPT1_TFSDIV()        bfin_read16(SPT1_TFSDIV)
 #define bfin_write_SPT1_TFSDIV(val)    bfin_write16(SPT1_TFSDIV, val)
-#define pSPT1_RFSDIV                   ((uint16_t volatile *)SPT1_RFSDIV)
 #define bfin_read_SPT1_RFSDIV()        bfin_read16(SPT1_RFSDIV)
 #define bfin_write_SPT1_RFSDIV(val)    bfin_write16(SPT1_RFSDIV, val)
-#define pSPT1_STAT                     ((uint16_t volatile *)SPT1_STAT)
 #define bfin_read_SPT1_STAT()          bfin_read16(SPT1_STAT)
 #define bfin_write_SPT1_STAT(val)      bfin_write16(SPT1_STAT, val)
-#define pSPT1_MTCS0                    ((uint32_t volatile *)SPT1_MTCS0)
 #define bfin_read_SPT1_MTCS0()         bfin_read32(SPT1_MTCS0)
 #define bfin_write_SPT1_MTCS0(val)     bfin_write32(SPT1_MTCS0, val)
-#define pSPT1_MTCS1                    ((uint32_t volatile *)SPT1_MTCS1)
 #define bfin_read_SPT1_MTCS1()         bfin_read32(SPT1_MTCS1)
 #define bfin_write_SPT1_MTCS1(val)     bfin_write32(SPT1_MTCS1, val)
-#define pSPT1_MTCS2                    ((uint32_t volatile *)SPT1_MTCS2)
 #define bfin_read_SPT1_MTCS2()         bfin_read32(SPT1_MTCS2)
 #define bfin_write_SPT1_MTCS2(val)     bfin_write32(SPT1_MTCS2, val)
-#define pSPT1_MTCS3                    ((uint32_t volatile *)SPT1_MTCS3)
 #define bfin_read_SPT1_MTCS3()         bfin_read32(SPT1_MTCS3)
 #define bfin_write_SPT1_MTCS3(val)     bfin_write32(SPT1_MTCS3, val)
-#define pSPT1_MRCS0                    ((uint32_t volatile *)SPT1_MRCS0)
 #define bfin_read_SPT1_MRCS0()         bfin_read32(SPT1_MRCS0)
 #define bfin_write_SPT1_MRCS0(val)     bfin_write32(SPT1_MRCS0, val)
-#define pSPT1_MRCS1                    ((uint32_t volatile *)SPT1_MRCS1)
 #define bfin_read_SPT1_MRCS1()         bfin_read32(SPT1_MRCS1)
 #define bfin_write_SPT1_MRCS1(val)     bfin_write32(SPT1_MRCS1, val)
-#define pSPT1_MRCS2                    ((uint32_t volatile *)SPT1_MRCS2)
 #define bfin_read_SPT1_MRCS2()         bfin_read32(SPT1_MRCS2)
 #define bfin_write_SPT1_MRCS2(val)     bfin_write32(SPT1_MRCS2, val)
-#define pSPT1_MRCS3                    ((uint32_t volatile *)SPT1_MRCS3)
 #define bfin_read_SPT1_MRCS3()         bfin_read32(SPT1_MRCS3)
 #define bfin_write_SPT1_MRCS3(val)     bfin_write32(SPT1_MRCS3, val)
-#define pSPT1_MCMC1                    ((uint16_t volatile *)SPT1_MCMC1)
 #define bfin_read_SPT1_MCMC1()         bfin_read16(SPT1_MCMC1)
 #define bfin_write_SPT1_MCMC1(val)     bfin_write16(SPT1_MCMC1, val)
-#define pSPT1_MCMC2                    ((uint16_t volatile *)SPT1_MCMC2)
 #define bfin_read_SPT1_MCMC2()         bfin_read16(SPT1_MCMC2)
 #define bfin_write_SPT1_MCMC2(val)     bfin_write16(SPT1_MCMC2, val)
-#define pSPT1_CHNL                     ((uint16_t volatile *)SPT1_CHNL)
 #define bfin_read_SPT1_CHNL()          bfin_read16(SPT1_CHNL)
 #define bfin_write_SPT1_CHNL(val)      bfin_write16(SPT1_CHNL, val)
-#define pPPI_CONTROL                   ((uint16_t volatile *)PPI_CONTROL)
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS                    ((uint16_t volatile *)PPI_STATUS)
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
 #define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define pPPI_DELAY                     ((uint16_t volatile *)PPI_DELAY)
 #define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
 #define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define pPPI_COUNT                     ((uint16_t volatile *)PPI_COUNT)
 #define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
 #define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define pPPI_FRAME                     ((uint16_t volatile *)PPI_FRAME)
 #define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
 #define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */
 #define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */
 #define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
 #define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */
 #define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
 #define bfin_read_SWRST()              bfin_read16(SWRST)
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
 #define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
 #define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
 #define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
 #define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define pTBUF                          ((void * volatile *)TBUF) /* Trace Buffer */
 #define bfin_read_TBUF()               bfin_readPTR(TBUF)
 #define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define pPFCTL                         ((uint32_t volatile *)PFCTL)
 #define bfin_read_PFCTL()              bfin_read32(PFCTL)
 #define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
 #define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
 #define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
 #define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
 #define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
 #define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
 #define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
 #define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
 #define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
 #define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
 #define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT)
 #define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
 #define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL)
 #define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
 #define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT)
 #define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
 #define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT)
 #define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
 #define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM)
 #define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
 #define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN)
 #define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
 #define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL)
 #define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
 #define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG)
 #define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
 #define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT)
 #define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
 #define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR)
 #define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
 #define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR)
 #define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
 #define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD)
 #define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
 #define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW)
 #define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
 #define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define pFIO_FLAG_D                    ((uint16_t volatile *)FIO_FLAG_D)
 #define bfin_read_FIO_FLAG_D()         bfin_read16(FIO_FLAG_D)
 #define bfin_write_FIO_FLAG_D(val)     bfin_write16(FIO_FLAG_D, val)
-#define pFIO_FLAG_C                    ((uint16_t volatile *)FIO_FLAG_C)
 #define bfin_read_FIO_FLAG_C()         bfin_read16(FIO_FLAG_C)
 #define bfin_write_FIO_FLAG_C(val)     bfin_write16(FIO_FLAG_C, val)
-#define pFIO_FLAG_S                    ((uint16_t volatile *)FIO_FLAG_S)
 #define bfin_read_FIO_FLAG_S()         bfin_read16(FIO_FLAG_S)
 #define bfin_write_FIO_FLAG_S(val)     bfin_write16(FIO_FLAG_S, val)
-#define pFIO_FLAG_T                    ((uint16_t volatile *)FIO_FLAG_T)
 #define bfin_read_FIO_FLAG_T()         bfin_read16(FIO_FLAG_T)
 #define bfin_write_FIO_FLAG_T(val)     bfin_write16(FIO_FLAG_T, val)
-#define pFIO_MASKA_D                   ((uint16_t volatile *)FIO_MASKA_D)
 #define bfin_read_FIO_MASKA_D()        bfin_read16(FIO_MASKA_D)
 #define bfin_write_FIO_MASKA_D(val)    bfin_write16(FIO_MASKA_D, val)
-#define pFIO_MASKA_C                   ((uint16_t volatile *)FIO_MASKA_C)
 #define bfin_read_FIO_MASKA_C()        bfin_read16(FIO_MASKA_C)
 #define bfin_write_FIO_MASKA_C(val)    bfin_write16(FIO_MASKA_C, val)
-#define pFIO_MASKA_S                   ((uint16_t volatile *)FIO_MASKA_S)
 #define bfin_read_FIO_MASKA_S()        bfin_read16(FIO_MASKA_S)
 #define bfin_write_FIO_MASKA_S(val)    bfin_write16(FIO_MASKA_S, val)
-#define pFIO_MASKA_T                   ((uint16_t volatile *)FIO_MASKA_T)
 #define bfin_read_FIO_MASKA_T()        bfin_read16(FIO_MASKA_T)
 #define bfin_write_FIO_MASKA_T(val)    bfin_write16(FIO_MASKA_T, val)
-#define pFIO_MASKB_D                   ((uint16_t volatile *)FIO_MASKB_D)
 #define bfin_read_FIO_MASKB_D()        bfin_read16(FIO_MASKB_D)
 #define bfin_write_FIO_MASKB_D(val)    bfin_write16(FIO_MASKB_D, val)
-#define pFIO_MASKB_C                   ((uint16_t volatile *)FIO_MASKB_C)
 #define bfin_read_FIO_MASKB_C()        bfin_read16(FIO_MASKB_C)
 #define bfin_write_FIO_MASKB_C(val)    bfin_write16(FIO_MASKB_C, val)
-#define pFIO_MASKB_S                   ((uint16_t volatile *)FIO_MASKB_S)
 #define bfin_read_FIO_MASKB_S()        bfin_read16(FIO_MASKB_S)
 #define bfin_write_FIO_MASKB_S(val)    bfin_write16(FIO_MASKB_S, val)
-#define pFIO_MASKB_T                   ((uint16_t volatile *)FIO_MASKB_T)
 #define bfin_read_FIO_MASKB_T()        bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)    bfin_write16(FIO_MASKB_T, val)
-#define pFIO_DIR                       ((uint16_t volatile *)FIO_DIR)
 #define bfin_read_FIO_DIR()            bfin_read16(FIO_DIR)
 #define bfin_write_FIO_DIR(val)        bfin_write16(FIO_DIR, val)
-#define pFIO_POLAR                     ((uint16_t volatile *)FIO_POLAR)
 #define bfin_read_FIO_POLAR()          bfin_read16(FIO_POLAR)
 #define bfin_write_FIO_POLAR(val)      bfin_write16(FIO_POLAR, val)
-#define pFIO_EDGE                      ((uint16_t volatile *)FIO_EDGE)
 #define bfin_read_FIO_EDGE()           bfin_read16(FIO_EDGE)
 #define bfin_write_FIO_EDGE(val)       bfin_write16(FIO_EDGE, val)
-#define pFIO_BOTH                      ((uint16_t volatile *)FIO_BOTH)
 #define bfin_read_FIO_BOTH()           bfin_read16(FIO_BOTH)
 #define bfin_write_FIO_BOTH(val)       bfin_write16(FIO_BOTH, val)
-#define pFIO_INEN                      ((uint16_t volatile *)FIO_INEN)
 #define bfin_read_FIO_INEN()           bfin_read16(FIO_INEN)
 #define bfin_write_FIO_INEN(val)       bfin_write16(FIO_INEN, val)
-#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
 #define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
 #define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
 #define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
 #define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
 #define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
 #define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2                   ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
 #define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
 #define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV                ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
 #define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
 #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV                 ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
 #define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
 #define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT                   ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
 #define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
 #define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL                   ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
 #define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
 #define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1                  ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
 #define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2                  ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
 #define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
 #define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
 #define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
 #define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
 #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
 #define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
 #define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
 #define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
 #define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
 #define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
 #define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
 #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
 #define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
 #define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
 #define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
 #define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
 #define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
 #define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
 #define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
 #define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
 #define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
 #define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define pDMA0_NEXT_DESC_PTR            ((uint32_t volatile *)DMA0_NEXT_DESC_PTR)
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR               ((uint32_t volatile *)DMA0_START_ADDR)
 #define bfin_read_DMA0_START_ADDR()    bfin_read32(DMA0_START_ADDR)
 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
 #define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT)
 #define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
 #define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY)
 #define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
 #define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT)
 #define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
 #define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY)
 #define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
 #define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR            ((uint32_t volatile *)DMA0_CURR_DESC_PTR)
 #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR                ((uint32_t volatile *)DMA0_CURR_ADDR)
 #define bfin_read_DMA0_CURR_ADDR()     bfin_read32(DMA0_CURR_ADDR)
 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS)
 #define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
 #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP)
 #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
 #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT)
 #define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
 #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT)
 #define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
 #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR            ((uint32_t volatile *)DMA1_NEXT_DESC_PTR)
 #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR               ((uint32_t volatile *)DMA1_START_ADDR)
 #define bfin_read_DMA1_START_ADDR()    bfin_read32(DMA1_START_ADDR)
 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
 #define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
 #define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT)
 #define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
 #define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY)
 #define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
 #define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT)
 #define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
 #define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY)
 #define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
 #define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR            ((uint32_t volatile *)DMA1_CURR_DESC_PTR)
 #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR                ((uint32_t volatile *)DMA1_CURR_ADDR)
 #define bfin_read_DMA1_CURR_ADDR()     bfin_read32(DMA1_CURR_ADDR)
 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS)
 #define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
 #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP)
 #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
 #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT)
 #define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
 #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT)
 #define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
 #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR            ((uint32_t volatile *)DMA2_NEXT_DESC_PTR)
 #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR               ((uint32_t volatile *)DMA2_START_ADDR)
 #define bfin_read_DMA2_START_ADDR()    bfin_read32(DMA2_START_ADDR)
 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
 #define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
 #define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT)
 #define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
 #define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY)
 #define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
 #define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT)
 #define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
 #define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY)
 #define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
 #define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR            ((uint32_t volatile *)DMA2_CURR_DESC_PTR)
 #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR                ((uint32_t volatile *)DMA2_CURR_ADDR)
 #define bfin_read_DMA2_CURR_ADDR()     bfin_read32(DMA2_CURR_ADDR)
 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS)
 #define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
 #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP)
 #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
 #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT)
 #define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
 #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT)
 #define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
 #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR            ((uint32_t volatile *)DMA3_NEXT_DESC_PTR)
 #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR               ((uint32_t volatile *)DMA3_START_ADDR)
 #define bfin_read_DMA3_START_ADDR()    bfin_read32(DMA3_START_ADDR)
 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
 #define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
 #define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT)
 #define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
 #define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY)
 #define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
 #define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT)
 #define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
 #define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY)
 #define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
 #define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR            ((uint32_t volatile *)DMA3_CURR_DESC_PTR)
 #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR                ((uint32_t volatile *)DMA3_CURR_ADDR)
 #define bfin_read_DMA3_CURR_ADDR()     bfin_read32(DMA3_CURR_ADDR)
 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS)
 #define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP)
 #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
 #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT)
 #define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
 #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT)
 #define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
 #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR            ((uint32_t volatile *)DMA4_NEXT_DESC_PTR)
 #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR               ((uint32_t volatile *)DMA4_START_ADDR)
 #define bfin_read_DMA4_START_ADDR()    bfin_read32(DMA4_START_ADDR)
 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
 #define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
 #define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT)
 #define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
 #define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY)
 #define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
 #define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT)
 #define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
 #define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY)
 #define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
 #define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR            ((uint32_t volatile *)DMA4_CURR_DESC_PTR)
 #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR                ((uint32_t volatile *)DMA4_CURR_ADDR)
 #define bfin_read_DMA4_CURR_ADDR()     bfin_read32(DMA4_CURR_ADDR)
 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS)
 #define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
 #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP)
 #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
 #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT)
 #define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
 #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT)
 #define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
 #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR            ((uint32_t volatile *)DMA5_NEXT_DESC_PTR)
 #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR               ((uint32_t volatile *)DMA5_START_ADDR)
 #define bfin_read_DMA5_START_ADDR()    bfin_read32(DMA5_START_ADDR)
 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
 #define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
 #define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT)
 #define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
 #define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY)
 #define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
 #define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT)
 #define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
 #define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY)
 #define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
 #define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR            ((uint32_t volatile *)DMA5_CURR_DESC_PTR)
 #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR                ((uint32_t volatile *)DMA5_CURR_ADDR)
 #define bfin_read_DMA5_CURR_ADDR()     bfin_read32(DMA5_CURR_ADDR)
 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS)
 #define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
 #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP)
 #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
 #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT)
 #define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
 #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT)
 #define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
 #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR            ((uint32_t volatile *)DMA6_NEXT_DESC_PTR)
 #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR               ((uint32_t volatile *)DMA6_START_ADDR)
 #define bfin_read_DMA6_START_ADDR()    bfin_read32(DMA6_START_ADDR)
 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
 #define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
 #define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT)
 #define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
 #define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY)
 #define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
 #define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT)
 #define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
 #define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY)
 #define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
 #define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR            ((uint32_t volatile *)DMA6_CURR_DESC_PTR)
 #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR                ((uint32_t volatile *)DMA6_CURR_ADDR)
 #define bfin_read_DMA6_CURR_ADDR()     bfin_read32(DMA6_CURR_ADDR)
 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS)
 #define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
 #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP)
 #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
 #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT)
 #define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
 #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT)
 #define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
 #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR            ((uint32_t volatile *)DMA7_NEXT_DESC_PTR)
 #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR               ((uint32_t volatile *)DMA7_START_ADDR)
 #define bfin_read_DMA7_START_ADDR()    bfin_read32(DMA7_START_ADDR)
 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
 #define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
 #define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT)
 #define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
 #define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY)
 #define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
 #define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT)
 #define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
 #define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY)
 #define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
 #define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR            ((uint32_t volatile *)DMA7_CURR_DESC_PTR)
 #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR                ((uint32_t volatile *)DMA7_CURR_ADDR)
 #define bfin_read_DMA7_CURR_ADDR()     bfin_read32(DMA7_CURR_ADDR)
 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS)
 #define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
 #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP)
 #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
 #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT)
 #define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT)
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR)
 #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR            ((uint32_t volatile *)MDMA_D0_START_ADDR)
 #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG)
 #define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
 #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT)
 #define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
 #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY)
 #define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
 #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT)
 #define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
 #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY)
 #define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
 #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR)
 #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR             ((uint32_t volatile *)MDMA_D0_CURR_ADDR)
 #define bfin_read_MDMA_D0_CURR_ADDR()  bfin_read32(MDMA_D0_CURR_ADDR)
 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS)
 #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
 #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP)
 #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT)
 #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
 #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT)
 #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
 #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR)
 #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR            ((uint32_t volatile *)MDMA_S0_START_ADDR)
 #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG)
 #define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
 #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT)
 #define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
 #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY)
 #define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
 #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT)
 #define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
 #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY)
 #define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
 #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR)
 #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR             ((uint32_t volatile *)MDMA_S0_CURR_ADDR)
 #define bfin_read_MDMA_S0_CURR_ADDR()  bfin_read32(MDMA_S0_CURR_ADDR)
 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS)
 #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
 #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP)
 #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT)
 #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
 #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT)
 #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
 #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR)
 #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR            ((uint32_t volatile *)MDMA_D1_START_ADDR)
 #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
 #define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
 #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT)
 #define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
 #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY)
 #define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
 #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT)
 #define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
 #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY)
 #define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
 #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR)
 #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR             ((uint32_t volatile *)MDMA_D1_CURR_ADDR)
 #define bfin_read_MDMA_D1_CURR_ADDR()  bfin_read32(MDMA_D1_CURR_ADDR)
 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS)
 #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
 #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP)
 #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT)
 #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
 #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT)
 #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
 #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR         ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR)
 #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR            ((uint32_t volatile *)MDMA_S1_START_ADDR)
 #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG)
 #define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
 #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT)
 #define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
 #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY)
 #define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
 #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT)
 #define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
 #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY)
 #define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
 #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR         ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR)
 #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR             ((uint32_t volatile *)MDMA_S1_CURR_ADDR)
 #define bfin_read_MDMA_S1_CURR_ADDR()  bfin_read32(MDMA_S1_CURR_ADDR)
 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS)
 #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
 #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP)
 #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
 #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT)
 #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
 #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT)
 #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
 #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL)
 #define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
 #define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0)
 #define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
 #define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1)
 #define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
 #define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL)
 #define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
 #define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL                   ((uint16_t volatile *)EBIU_SDBCTL)
 #define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
 #define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC)
 #define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT)
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define pDMA_TC_CNT                    ((uint16_t volatile *)DMA_TC_CNT)
 #define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
 #define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER                    ((uint16_t volatile *)DMA_TC_PER)
 #define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
 #define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)