blackfin: Move blackfin serial driver out of blackfin arch folder.

- Move blackfin serial driver to the generic driver folder.
- Move blackfin serial headers to blackfin arch head folder.
- Update the include path to blackfin serial header in start up code.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>

3 files changed, 623 insertions, 0 deletions

diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h
new file mode 100644
index 0000000..87a337d
--- /dev/null
+++ b/arch/blackfin/include/asm/serial.h
@@ -0,0 +1,131 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL_H__
+#define __BFIN_CPU_SERIAL_H__
+
+#include <asm/blackfin.h>
+#include <asm/portmux.h>
+
+#ifndef CONFIG_UART_CONSOLE
+# define CONFIG_UART_CONSOLE 0
+#endif
+
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define BFIN_DEBUG_EARLY_SERIAL 1
+#else
+# define BFIN_DEBUG_EARLY_SERIAL 0
+#endif
+
+#if defined(__ADSPBF60x__)
+# define BFIN_UART_HW_VER 4
+#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
+# define BFIN_UART_HW_VER 2
+#else
+# define BFIN_UART_HW_VER 1
+#endif
+
+#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
+#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
+#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
+#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
+
+#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
+
+#ifndef __ASSEMBLY__
+__attribute__((always_inline))
+static inline void serial_do_portmux(void);
+#endif
+
+#if BFIN_UART_HW_VER < 4
+# include "serial1.h"
+#else
+# include "serial4.h"
+#endif
+
+#ifndef __ASSEMBLY__
+
+__attribute__((always_inline))
+static inline void serial_do_portmux(void)
+{
+	if (!BFIN_DEBUG_EARLY_SERIAL) {
+		const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
+		peripheral_request_list(pins, "bfin-uart");
+		return;
+	}
+
+	serial_early_do_portmux();
+}
+
+#ifndef BFIN_IN_INITCODE
+__attribute__((always_inline))
+static inline void serial_early_puts(const char *s)
+{
+	if (BFIN_DEBUG_EARLY_SERIAL) {
+		serial_puts("Early: ");
+		serial_puts(s);
+	}
+}
+#endif
+
+#else
+
+.macro serial_early_init
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
+	call __serial_early_init;
+#endif
+.endm
+
+.macro serial_early_set_baud
+#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM)
+	R0.L = LO(CONFIG_BAUDRATE);
+	R0.H = HI(CONFIG_BAUDRATE);
+	call __serial_early_set_baud;
+#endif
+.endm
+
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+#define update_serial_early_string_addr \
+	R1.L = _start; \
+	R1.H = _start; \
+	R0 = R0 - R1; \
+	R1.L = 0; \
+	R1.H = 0x2000; \
+	R0 = R0 + R1;
+#else
+#define update_serial_early_string_addr
+#endif
+
+/* Since we embed the string right into our .text section, we need
+ * to find its address.  We do this by getting our PC and adding 2
+ * bytes (which is the length of the jump instruction).  Then we
+ * pass this address to serial_puts().
+ */
+#ifdef CONFIG_DEBUG_EARLY_SERIAL
+# define serial_early_puts(str) \
+	.section .rodata; \
+	7: \
+	.ascii "Early:"; \
+	.ascii __FILE__; \
+	.ascii ": "; \
+	.ascii str; \
+	.asciz "\n"; \
+	.previous; \
+	R0.L = 7b; \
+	R0.H = 7b; \
+	update_serial_early_string_addr \
+	call _uart_early_puts;
+#else
+# define serial_early_puts(str)
+#endif
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/serial1.h b/arch/blackfin/include/asm/serial1.h
new file mode 100644
index 0000000..467d381
--- /dev/null
+++ b/arch/blackfin/include/asm/serial1.h
@@ -0,0 +1,342 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL1_H__
+#define __BFIN_CPU_SERIAL1_H__
+
+#include <asm/mach-common/bits/uart.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/clock.h>
+
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#ifdef UART_DLL
+# define UART0_DLL UART_DLL
+# if CONFIG_UART_CONSOLE != 0
+#  error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+# endif
+#endif
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+struct bfin_mmr_serial {
+#if BFIN_UART_HW_VER == 2
+	u16 dll;
+	u16 __pad_0;
+	u16 dlh;
+	u16 __pad_1;
+	u16 gctl;
+	u16 __pad_2;
+	u16 lcr;
+	u16 __pad_3;
+	u16 mcr;
+	u16 __pad_4;
+	u16 lsr;
+	u16 __pad_5;
+	u16 msr;
+	u16 __pad_6;
+	u16 scr;
+	u16 __pad_7;
+	u16 ier_set;
+	u16 __pad_8;
+	u16 ier_clear;
+	u16 __pad_9;
+	u16 thr;
+	u16 __pad_10;
+	u16 rbr;
+	u16 __pad_11;
+#else
+	union {
+		u16 dll;
+		u16 thr;
+		const u16 rbr;
+	};
+	const u16 __spad0;
+	union {
+		u16 dlh;
+		u16 ier;
+	};
+	const u16 __spad1;
+	const u16 iir;
+	u16 __pad_0;
+	u16 lcr;
+	u16 __pad_1;
+	u16 mcr;
+	u16 __pad_2;
+	u16 lsr;
+	u16 __pad_3;
+	u16 msr;
+	u16 __pad_4;
+	u16 scr;
+	u16 __pad_5;
+	const u32 __spad2;
+	u16 gctl;
+	u16 __pad_6;
+#endif
+};
+
+#define uart_lsr_t uint32_t
+#define _lsr_read(p)     bfin_read(&p->lsr)
+#define _lsr_write(p, v) bfin_write(&p->lsr, v)
+
+#if BFIN_UART_HW_VER == 2
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+#else
+# define ACCESS_LATCH()    bfin_write_or(&pUART->lcr, DLAB)
+# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+	int mux_func, int port_pin)
+{
+	switch (port) {
+#if defined(__ADSPBF54x__)
+	case 'B':
+		bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
+		break;
+	case 'E':
+		bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
+		break;
+#endif
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
+	case 'F':
+		bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
+		break;
+	case 'G':
+		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
+		break;
+	case 'H':
+		bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF50x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
+		serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
+		break;
+	}
+#elif defined(__ADSPBF51x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
+		serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+		PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
+		break;
+	}
+#elif defined(__ADSPBF52x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+		PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+		PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
+		serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
+		break;
+	}
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+	const uint16_t func[] = { PFDE, PFTE, };
+	bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
+	bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
+			(1 << P_IDENT(P_UART(RX))) |
+			(1 << P_IDENT(P_UART(TX))));
+#elif defined(__ADSPBF54x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
+		serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
+		PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
+		PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
+		serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
+		PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
+		break;
+	case 2:
+		serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
+		PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
+		serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
+		PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
+		break;
+	case 3:
+		serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
+		PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
+		serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
+		break;
+	}
+#elif defined(__ADSPBF561__)
+	/* UART pins could be GPIO, but they aren't pin muxed.  */
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+#  error "missing portmux logic for UART"
+# endif
+#endif
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+	/* always enable UART -- avoids anomalies 05000309 and 05000350 */
+	bfin_write(&pUART->gctl, UCEN);
+
+	/* Set LCR to Word Lengh 8-bit word select */
+	bfin_write(&pUART->lcr, WLS_8);
+
+	SSYNC();
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+	/* disable the UART by clearing UCEN */
+	bfin_write(&pUART->gctl, 0);
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
+{
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+	/* Translate from baud into divisor in terms of SCLK.  The
+	 * weird multiplication is to make sure we over sample just
+	 * a little rather than under sample the incoming signals.
+	 */
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+	uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16)
+			- ANOMALY_05000230;
+#else
+	uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8),
+			baud * 16) - ANOMALY_05000230;
+#endif
+
+	serial_set_divisor(uart_base, divisor);
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->dll, LOB(divisor));
+	bfin_write(&pUART->dlh, HIB(divisor));
+	SSYNC();
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
+	uint32_t uart_base = UART_BASE;
+
+	/* Set DLAB in LCR to Access DLL and DLH */
+	ACCESS_LATCH();
+	SSYNC();
+
+	uint8_t dll = bfin_read(&pUART->dll);
+	uint8_t dlh = bfin_read(&pUART->dlh);
+	uint16_t divisor = (dlh << 8) | dll;
+
+	/* Clear DLAB in LCR to Access THR RBR IER */
+	ACCESS_PORT_IER();
+	SSYNC();
+
+	return divisor;
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/asm/serial4.h b/arch/blackfin/include/asm/serial4.h
new file mode 100644
index 0000000..6548396
--- /dev/null
+++ b/arch/blackfin/include/asm/serial4.h
@@ -0,0 +1,150 @@
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ *            any functions defined here must be always_inline since
+ *            initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL4_H__
+#define __BFIN_CPU_SERIAL4_H__
+
+#include <asm/mach-common/bits/uart4.h>
+
+#ifndef __ASSEMBLY__
+
+#include <asm/clock.h>
+
+#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+struct bfin_mmr_serial {
+	u32 revid;
+	u32 control;
+	u32 status;
+	u32 scr;
+	u32 clock;
+	u32 emask;
+	u32 emaskst;
+	u32 emaskcl;
+	u32 rbr;
+	u32 thr;
+	u32 taip;
+	u32 tsr;
+	u32 rsr;
+	u32 txdiv_cnt;
+	u32 rxdiv_cnt;
+};
+#define uart_lsr_t uint32_t
+#define _lsr_read(p)     bfin_read(&p->status)
+#define _lsr_write(p, v) bfin_write(&p->status, v)
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+	int mux_func, int port_pin)
+{
+	switch (port) {
+	case 'D':
+		bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTD_FER_SET(port_pin);
+		break;
+	case 'G':
+		bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+			~mux_mask) | mux_func);
+		bfin_write_PORTG_FER_SET(port_pin);
+		break;
+	}
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF60x__)
+	switch (CONFIG_UART_CONSOLE) {
+	case 0:
+		serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
+		PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
+		serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
+		PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
+		break;
+	case 1:
+		serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
+		PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
+		serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
+		PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
+		break;
+	}
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+#  error "missing portmux logic for UART"
+# endif
+#endif
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+	/* always enable UART to 8-bit mode */
+	bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
+
+	SSYNC();
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+	/* handle portmux crap on different Blackfins */
+	serial_do_portmux();
+
+	return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+	/* disable the UART by clearing UEN */
+	bfin_write(&pUART->control, 0);
+
+	return 0;
+}
+
+__attribute__((always_inline))
+static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor)
+{
+	/* Program the divisor to get the baud rate we want */
+	bfin_write(&pUART->clock, divisor);
+	SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+	uint16_t divisor = early_division(early_get_uart_clk(), baud * 16);
+
+	/* Program the divisor to get the baud rate we want */
+	serial_set_divisor(uart_base, divisor);
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t divisor)
+{
+	uint32_t uart_base = UART_BASE;
+	bfin_write(&pUART->clock, divisor);
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_div(void)
+{
+	uint32_t uart_base = UART_BASE;
+	return bfin_read(&pUART->clock);
+}
+
+#endif
+
+#endif