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authorSonic Zhang <sonic.zhang@analog.com>2012-11-30 17:39:32 +0800
committerSonic Zhang <sonic.zhang@analog.com>2013-05-13 15:47:24 +0800
commitab80b6595765a01f774ad2a29fde8b0c325533ac (patch)
treee3a907850eeec378960e52494c7940742f021461 /arch/blackfin/include/asm
parent79f2b3992f52334b510214c6b1b60c4200133658 (diff)
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blackfin: Correct early serial mess output in BYPASS boot mode.
The early serial should not be configured again in initcode() for BYPASS boot mode and in start() for the other LDR boot modes. In BYPASS boot mode, the start up code is located in Nor flash address other than the DRAM address defined in link script. The code embedded string can't be addressed by its compile time symbol. Calculate it according to the flash offset. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Diffstat (limited to 'arch/blackfin/include/asm')
-rw-r--r--arch/blackfin/include/asm/clock.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h
index df6cd68..f1fcd40 100644
--- a/arch/blackfin/include/asm/clock.h
+++ b/arch/blackfin/include/asm/clock.h
@@ -10,7 +10,7 @@
#include <asm/blackfin.h>
#ifdef PLL_CTL
#include <asm/mach-common/bits/pll.h>
-# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF)
+# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
#else
#include <asm/mach-common/bits/cgu.h>
# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
@@ -55,7 +55,11 @@ static inline uint32_t early_get_uart_clk(void)
if (!pll_is_bypassed()) {
div = bfin_read_PLL_DIV();
ssel = (div & SSEL) >> SSEL_P;
+#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
+ sclk = vco/ssel;
+#else
sclk = early_division(vco, ssel);
+#endif
}
uclk = sclk;
#ifdef CGU_DIV