summaryrefslogtreecommitdiff
path: root/arch/blackfin/include/asm/mach-common
diff options
context:
space:
mode:
authorMike Frysinger <vapier@gentoo.org>2010-07-25 16:39:45 -0400
committerMike Frysinger <vapier@gentoo.org>2010-10-02 16:00:38 -0400
commit94e3e444def1738aef5766e2be75fc6b776022ce (patch)
tree060f226f8ffeb8e28a2e4416b090d71d84efc410 /arch/blackfin/include/asm/mach-common
parentd56b7068ce0691aa2df2c6b6f7361fe1dff7d497 (diff)
downloadu-boot-imx-94e3e444def1738aef5766e2be75fc6b776022ce.zip
u-boot-imx-94e3e444def1738aef5766e2be75fc6b776022ce.tar.gz
u-boot-imx-94e3e444def1738aef5766e2be75fc6b776022ce.tar.bz2
Blackfin: punt old *p style volatile MMR defines
These are unused now, so punt them to clean things up. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/include/asm/mach-common')
-rw-r--r--arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h660
-rw-r--r--arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h21
-rw-r--r--arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h533
3 files changed, 0 insertions, 1214 deletions
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
index 43f3850..a78dfe8 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h
@@ -6,1982 +6,1322 @@
#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL)
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV)
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT)
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT)
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL)
#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG)
#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT)
#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR)
#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR)
#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD)
#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW)
#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pWDOGA_CTL ((uint16_t volatile *)WDOGA_CTL)
#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL)
#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val)
-#define pWDOGA_CNT ((uint32_t volatile *)WDOGA_CNT)
#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT)
#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val)
-#define pWDOGA_STAT ((uint32_t volatile *)WDOGA_STAT)
#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT)
#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val)
-#define pWDOGB_CTL ((uint16_t volatile *)WDOGB_CTL)
#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL)
#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val)
-#define pWDOGB_CNT ((uint32_t volatile *)WDOGB_CNT)
#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT)
#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val)
-#define pWDOGB_STAT ((uint32_t volatile *)WDOGB_STAT)
#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT)
#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val)
-#define pDMA1_TC_PER ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */
#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER)
#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val)
-#define pDMA1_TC_CNT ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */
#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT)
#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val)
-#define pDMA1_0_CONFIG ((uint16_t volatile *)DMA1_0_CONFIG)
#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val)
-#define pDMA1_0_NEXT_DESC_PTR ((void * volatile *)DMA1_0_NEXT_DESC_PTR)
#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR)
#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val)
-#define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR)
#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR)
#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val)
-#define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT)
#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT)
#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val)
-#define pDMA1_0_Y_COUNT ((uint16_t volatile *)DMA1_0_Y_COUNT)
#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT)
#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val)
-#define pDMA1_0_X_MODIFY ((uint16_t volatile *)DMA1_0_X_MODIFY)
#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY)
#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val)
-#define pDMA1_0_Y_MODIFY ((uint16_t volatile *)DMA1_0_Y_MODIFY)
#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY)
#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val)
-#define pDMA1_0_CURR_DESC_PTR ((void * volatile *)DMA1_0_CURR_DESC_PTR)
#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR)
#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val)
-#define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR)
#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR)
#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val)
-#define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT)
#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT)
#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val)
-#define pDMA1_0_CURR_Y_COUNT ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT)
#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT)
#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val)
-#define pDMA1_0_IRQ_STATUS ((uint16_t volatile *)DMA1_0_IRQ_STATUS)
#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS)
#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val)
-#define pDMA1_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP)
#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP)
#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val)
-#define pDMA1_1_CONFIG ((uint16_t volatile *)DMA1_1_CONFIG)
#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG)
#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val)
-#define pDMA1_1_NEXT_DESC_PTR ((void * volatile *)DMA1_1_NEXT_DESC_PTR)
#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR)
#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val)
-#define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR)
#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR)
#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val)
-#define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT)
#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT)
#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val)
-#define pDMA1_1_Y_COUNT ((uint16_t volatile *)DMA1_1_Y_COUNT)
#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT)
#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val)
-#define pDMA1_1_X_MODIFY ((uint16_t volatile *)DMA1_1_X_MODIFY)
#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY)
#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val)
-#define pDMA1_1_Y_MODIFY ((uint16_t volatile *)DMA1_1_Y_MODIFY)
#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY)
#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val)
-#define pDMA1_1_CURR_DESC_PTR ((void * volatile *)DMA1_1_CURR_DESC_PTR)
#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR)
#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val)
-#define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR)
#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR)
#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val)
-#define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT)
#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT)
#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val)
-#define pDMA1_1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT)
#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT)
#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val)
-#define pDMA1_1_IRQ_STATUS ((uint16_t volatile *)DMA1_1_IRQ_STATUS)
#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS)
#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val)
-#define pDMA1_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP)
#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP)
#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val)
-#define pDMA1_2_CONFIG ((uint16_t volatile *)DMA1_2_CONFIG)
#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG)
#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val)
-#define pDMA1_2_NEXT_DESC_PTR ((void * volatile *)DMA1_2_NEXT_DESC_PTR)
#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR)
#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val)
-#define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR)
#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR)
#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val)
-#define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT)
#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT)
#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val)
-#define pDMA1_2_Y_COUNT ((uint16_t volatile *)DMA1_2_Y_COUNT)
#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT)
#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val)
-#define pDMA1_2_X_MODIFY ((uint16_t volatile *)DMA1_2_X_MODIFY)
#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY)
#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val)
-#define pDMA1_2_Y_MODIFY ((uint16_t volatile *)DMA1_2_Y_MODIFY)
#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY)
#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val)
-#define pDMA1_2_CURR_DESC_PTR ((void * volatile *)DMA1_2_CURR_DESC_PTR)
#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR)
#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val)
-#define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR)
#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR)
#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val)
-#define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT)
#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT)
#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val)
-#define pDMA1_2_CURR_Y_COUNT ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT)
#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT)
#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val)
-#define pDMA1_2_IRQ_STATUS ((uint16_t volatile *)DMA1_2_IRQ_STATUS)
#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS)
#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val)
-#define pDMA1_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP)
#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP)
#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val)
-#define pDMA1_3_CONFIG ((uint16_t volatile *)DMA1_3_CONFIG)
#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG)
#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val)
-#define pDMA1_3_NEXT_DESC_PTR ((void * volatile *)DMA1_3_NEXT_DESC_PTR)
#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR)
#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val)
-#define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR)
#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR)
#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val)
-#define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT)
#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT)
#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val)
-#define pDMA1_3_Y_COUNT ((uint16_t volatile *)DMA1_3_Y_COUNT)
#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT)
#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val)
-#define pDMA1_3_X_MODIFY ((uint16_t volatile *)DMA1_3_X_MODIFY)
#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY)
#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val)
-#define pDMA1_3_Y_MODIFY ((uint16_t volatile *)DMA1_3_Y_MODIFY)
#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY)
#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val)
-#define pDMA1_3_CURR_DESC_PTR ((void * volatile *)DMA1_3_CURR_DESC_PTR)
#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR)
#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val)
-#define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR)
#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR)
#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val)
-#define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT)
#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT)
#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val)
-#define pDMA1_3_CURR_Y_COUNT ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT)
#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT)
#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val)
-#define pDMA1_3_IRQ_STATUS ((uint16_t volatile *)DMA1_3_IRQ_STATUS)
#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS)
#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val)
-#define pDMA1_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP)
#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP)
#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val)
-#define pDMA1_4_CONFIG ((uint16_t volatile *)DMA1_4_CONFIG)
#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG)
#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val)
-#define pDMA1_4_NEXT_DESC_PTR ((void * volatile *)DMA1_4_NEXT_DESC_PTR)
#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR)
#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val)
-#define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR)
#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR)
#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val)
-#define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT)
#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT)
#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val)
-#define pDMA1_4_Y_COUNT ((uint16_t volatile *)DMA1_4_Y_COUNT)
#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT)
#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val)
-#define pDMA1_4_X_MODIFY ((uint16_t volatile *)DMA1_4_X_MODIFY)
#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY)
#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val)
-#define pDMA1_4_Y_MODIFY ((uint16_t volatile *)DMA1_4_Y_MODIFY)
#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY)
#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val)
-#define pDMA1_4_CURR_DESC_PTR ((void * volatile *)DMA1_4_CURR_DESC_PTR)
#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR)
#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val)
-#define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR)
#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR)
#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val)
-#define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT)
#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT)
#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val)
-#define pDMA1_4_CURR_Y_COUNT ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT)
#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT)
#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val)
-#define pDMA1_4_IRQ_STATUS ((uint16_t volatile *)DMA1_4_IRQ_STATUS)
#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS)
#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val)
-#define pDMA1_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP)
#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP)
#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val)
-#define pDMA1_5_CONFIG ((uint16_t volatile *)DMA1_5_CONFIG)
#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG)
#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val)
-#define pDMA1_5_NEXT_DESC_PTR ((void * volatile *)DMA1_5_NEXT_DESC_PTR)
#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR)
#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val)
-#define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR)
#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR)
#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val)
-#define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT)
#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT)
#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val)
-#define pDMA1_5_Y_COUNT ((uint16_t volatile *)DMA1_5_Y_COUNT)
#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT)
#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val)
-#define pDMA1_5_X_MODIFY ((uint16_t volatile *)DMA1_5_X_MODIFY)
#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY)
#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val)
-#define pDMA1_5_Y_MODIFY ((uint16_t volatile *)DMA1_5_Y_MODIFY)
#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY)
#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val)
-#define pDMA1_5_CURR_DESC_PTR ((void * volatile *)DMA1_5_CURR_DESC_PTR)
#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR)
#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val)
-#define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR)
#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR)
#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val)
-#define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT)
#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT)
#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val)
-#define pDMA1_5_CURR_Y_COUNT ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT)
#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT)
#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val)
-#define pDMA1_5_IRQ_STATUS ((uint16_t volatile *)DMA1_5_IRQ_STATUS)
#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS)
#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val)
-#define pDMA1_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP)
#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP)
#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val)
-#define pDMA1_6_CONFIG ((uint16_t volatile *)DMA1_6_CONFIG)
#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG)
#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val)
-#define pDMA1_6_NEXT_DESC_PTR ((void * volatile *)DMA1_6_NEXT_DESC_PTR)
#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR)
#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val)
-#define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR)
#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR)
#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val)
-#define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT)
#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT)
#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val)
-#define pDMA1_6_Y_COUNT ((uint16_t volatile *)DMA1_6_Y_COUNT)
#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT)
#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val)
-#define pDMA1_6_X_MODIFY ((uint16_t volatile *)DMA1_6_X_MODIFY)
#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY)
#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val)
-#define pDMA1_6_Y_MODIFY ((uint16_t volatile *)DMA1_6_Y_MODIFY)
#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY)
#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val)
-#define pDMA1_6_CURR_DESC_PTR ((void * volatile *)DMA1_6_CURR_DESC_PTR)
#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR)
#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val)
-#define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR)
#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR)
#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val)
-#define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT)
#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT)
#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val)
-#define pDMA1_6_CURR_Y_COUNT ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT)
#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT)
#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val)
-#define pDMA1_6_IRQ_STATUS ((uint16_t volatile *)DMA1_6_IRQ_STATUS)
#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS)
#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val)
-#define pDMA1_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP)
#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP)
#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val)
-#define pDMA1_7_CONFIG ((uint16_t volatile *)DMA1_7_CONFIG)
#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG)
#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val)
-#define pDMA1_7_NEXT_DESC_PTR ((void * volatile *)DMA1_7_NEXT_DESC_PTR)
#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR)
#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val)
-#define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR)
#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR)
#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val)
-#define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT)
#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT)
#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val)
-#define pDMA1_7_Y_COUNT ((uint16_t volatile *)DMA1_7_Y_COUNT)
#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT)
#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val)
-#define pDMA1_7_X_MODIFY ((uint16_t volatile *)DMA1_7_X_MODIFY)
#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY)
#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val)
-#define pDMA1_7_Y_MODIFY ((uint16_t volatile *)DMA1_7_Y_MODIFY)
#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY)
#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val)
-#define pDMA1_7_CURR_DESC_PTR ((void * volatile *)DMA1_7_CURR_DESC_PTR)
#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR)
#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val)
-#define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR)
#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR)
#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val)
-#define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT)
#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT)
#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val)
-#define pDMA1_7_CURR_Y_COUNT ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT)
#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT)
#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val)
-#define pDMA1_7_IRQ_STATUS ((uint16_t volatile *)DMA1_7_IRQ_STATUS)
#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS)
#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val)
-#define pDMA1_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP)
#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP)
#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val)
-#define pDMA1_8_CONFIG ((uint16_t volatile *)DMA1_8_CONFIG)
#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG)
#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val)
-#define pDMA1_8_NEXT_DESC_PTR ((void * volatile *)DMA1_8_NEXT_DESC_PTR)
#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR)
#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val)
-#define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR)
#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR)
#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val)
-#define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT)
#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT)
#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val)
-#define pDMA1_8_Y_COUNT ((uint16_t volatile *)DMA1_8_Y_COUNT)
#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT)
#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val)
-#define pDMA1_8_X_MODIFY ((uint16_t volatile *)DMA1_8_X_MODIFY)
#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY)
#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val)
-#define pDMA1_8_Y_MODIFY ((uint16_t volatile *)DMA1_8_Y_MODIFY)
#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY)
#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val)
-#define pDMA1_8_CURR_DESC_PTR ((void * volatile *)DMA1_8_CURR_DESC_PTR)
#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR)
#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val)
-#define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR)
#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR)
#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val)
-#define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT)
#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT)
#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val)
-#define pDMA1_8_CURR_Y_COUNT ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT)
#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT)
#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val)
-#define pDMA1_8_IRQ_STATUS ((uint16_t volatile *)DMA1_8_IRQ_STATUS)
#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS)
#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val)
-#define pDMA1_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP)
#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP)
#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val)
-#define pDMA1_9_CONFIG ((uint16_t volatile *)DMA1_9_CONFIG)
#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG)
#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val)
-#define pDMA1_9_NEXT_DESC_PTR ((void * volatile *)DMA1_9_NEXT_DESC_PTR)
#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR)
#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val)
-#define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR)
#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR)
#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val)
-#define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT)
#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT)
#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val)
-#define pDMA1_9_Y_COUNT ((uint16_t volatile *)DMA1_9_Y_COUNT)
#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT)
#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val)
-#define pDMA1_9_X_MODIFY ((uint16_t volatile *)DMA1_9_X_MODIFY)
#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY)
#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val)
-#define pDMA1_9_Y_MODIFY ((uint16_t volatile *)DMA1_9_Y_MODIFY)
#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY)
#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val)
-#define pDMA1_9_CURR_DESC_PTR ((void * volatile *)DMA1_9_CURR_DESC_PTR)
#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR)
#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val)
-#define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR)
#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR)
#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val)
-#define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT)
#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT)
#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val)
-#define pDMA1_9_CURR_Y_COUNT ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT)
#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT)
#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val)
-#define pDMA1_9_IRQ_STATUS ((uint16_t volatile *)DMA1_9_IRQ_STATUS)
#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS)
#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val)
-#define pDMA1_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP)
#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP)
#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val)
-#define pDMA1_10_CONFIG ((uint16_t volatile *)DMA1_10_CONFIG)
#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG)
#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val)
-#define pDMA1_10_NEXT_DESC_PTR ((void * volatile *)DMA1_10_NEXT_DESC_PTR)
#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR)
#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val)
-#define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR)
#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR)
#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val)
-#define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT)
#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT)
#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val)
-#define pDMA1_10_Y_COUNT ((uint16_t volatile *)DMA1_10_Y_COUNT)
#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT)
#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val)
-#define pDMA1_10_X_MODIFY ((uint16_t volatile *)DMA1_10_X_MODIFY)
#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY)
#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val)
-#define pDMA1_10_Y_MODIFY ((uint16_t volatile *)DMA1_10_Y_MODIFY)
#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY)
#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val)
-#define pDMA1_10_CURR_DESC_PTR ((void * volatile *)DMA1_10_CURR_DESC_PTR)
#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR)
#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val)
-#define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR)
#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR)
#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val)
-#define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT)
#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT)
#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val)
-#define pDMA1_10_CURR_Y_COUNT ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT)
#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT)
#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val)
-#define pDMA1_10_IRQ_STATUS ((uint16_t volatile *)DMA1_10_IRQ_STATUS)
#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS)
#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val)
-#define pDMA1_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP)
#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP)
#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val)
-#define pDMA1_11_CONFIG ((uint16_t volatile *)DMA1_11_CONFIG)
#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG)
#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val)
-#define pDMA1_11_NEXT_DESC_PTR ((void * volatile *)DMA1_11_NEXT_DESC_PTR)
#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR)
#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val)
-#define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR)
#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR)
#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val)
-#define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT)
#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT)
#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val)
-#define pDMA1_11_Y_COUNT ((uint16_t volatile *)DMA1_11_Y_COUNT)
#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT)
#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val)
-#define pDMA1_11_X_MODIFY ((uint16_t volatile *)DMA1_11_X_MODIFY)
#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY)
#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val)
-#define pDMA1_11_Y_MODIFY ((uint16_t volatile *)DMA1_11_Y_MODIFY)
#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY)
#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val)
-#define pDMA1_11_CURR_DESC_PTR ((void * volatile *)DMA1_11_CURR_DESC_PTR)
#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR)
#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val)
-#define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR)
#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR)
#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val)
-#define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT)
#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT)
#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val)
-#define pDMA1_11_CURR_Y_COUNT ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT)
#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT)
#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val)
-#define pDMA1_11_IRQ_STATUS ((uint16_t volatile *)DMA1_11_IRQ_STATUS)
#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS)
#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val)
-#define pDMA1_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP)
#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP)
#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val)
-#define pDMA2_TC_PER ((uint16_t volatile *)DMA2_TC_PER)
#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER)
#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val)
-#define pDMA2_TC_CNT ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */
#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT)
#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val)
-#define pDMA2_0_CONFIG ((uint16_t volatile *)DMA2_0_CONFIG)
#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG)
#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val)
-#define pDMA2_0_NEXT_DESC_PTR ((void * volatile *)DMA2_0_NEXT_DESC_PTR)
#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR)
#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val)
-#define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR)
#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR)
#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val)
-#define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT)
#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT)
#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val)
-#define pDMA2_0_Y_COUNT ((uint16_t volatile *)DMA2_0_Y_COUNT)
#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT)
#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val)
-#define pDMA2_0_X_MODIFY ((uint16_t volatile *)DMA2_0_X_MODIFY)
#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY)
#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val)
-#define pDMA2_0_Y_MODIFY ((uint16_t volatile *)DMA2_0_Y_MODIFY)
#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY)
#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val)
-#define pDMA2_0_CURR_DESC_PTR ((void * volatile *)DMA2_0_CURR_DESC_PTR)
#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR)
#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val)
-#define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR)
#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR)
#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val)
-#define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT)
#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT)
#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val)
-#define pDMA2_0_CURR_Y_COUNT ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT)
#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT)
#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val)
-#define pDMA2_0_IRQ_STATUS ((uint16_t volatile *)DMA2_0_IRQ_STATUS)
#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS)
#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val)
-#define pDMA2_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP)
#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP)
#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val)
-#define pDMA2_1_CONFIG ((uint16_t volatile *)DMA2_1_CONFIG)
#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG)
#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val)
-#define pDMA2_1_NEXT_DESC_PTR ((void * volatile *)DMA2_1_NEXT_DESC_PTR)
#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR)
#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val)
-#define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR)
#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR)
#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val)
-#define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT)
#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT)
#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val)
-#define pDMA2_1_Y_COUNT ((uint16_t volatile *)DMA2_1_Y_COUNT)
#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT)
#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val)
-#define pDMA2_1_X_MODIFY ((uint16_t volatile *)DMA2_1_X_MODIFY)
#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY)
#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val)
-#define pDMA2_1_Y_MODIFY ((uint16_t volatile *)DMA2_1_Y_MODIFY)
#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY)
#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val)
-#define pDMA2_1_CURR_DESC_PTR ((void * volatile *)DMA2_1_CURR_DESC_PTR)
#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR)
#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val)
-#define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR)
#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR)
#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val)
-#define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT)
#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT)
#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val)
-#define pDMA2_1_CURR_Y_COUNT ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT)
#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT)
#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val)
-#define pDMA2_1_IRQ_STATUS ((uint16_t volatile *)DMA2_1_IRQ_STATUS)
#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS)
#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val)
-#define pDMA2_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP)
#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP)
#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val)
-#define pDMA2_2_CONFIG ((uint16_t volatile *)DMA2_2_CONFIG)
#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG)
#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val)
-#define pDMA2_2_NEXT_DESC_PTR ((void * volatile *)DMA2_2_NEXT_DESC_PTR)
#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR)
#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val)
-#define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR)
#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR)
#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val)
-#define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT)
#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT)
#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val)
-#define pDMA2_2_Y_COUNT ((uint16_t volatile *)DMA2_2_Y_COUNT)
#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT)
#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val)
-#define pDMA2_2_X_MODIFY ((uint16_t volatile *)DMA2_2_X_MODIFY)
#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY)
#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val)
-#define pDMA2_2_Y_MODIFY ((uint16_t volatile *)DMA2_2_Y_MODIFY)
#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY)
#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val)
-#define pDMA2_2_CURR_DESC_PTR ((void * volatile *)DMA2_2_CURR_DESC_PTR)
#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR)
#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val)
-#define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR)
#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR)
#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val)
-#define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT)
#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT)
#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val)
-#define pDMA2_2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT)
#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT)
#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val)
-#define pDMA2_2_IRQ_STATUS ((uint16_t volatile *)DMA2_2_IRQ_STATUS)
#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS)
#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val)
-#define pDMA2_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP)
#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP)
#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val)
-#define pDMA2_3_CONFIG ((uint16_t volatile *)DMA2_3_CONFIG)
#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG)
#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val)
-#define pDMA2_3_NEXT_DESC_PTR ((void * volatile *)DMA2_3_NEXT_DESC_PTR)
#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR)
#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val)
-#define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR)
#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR)
#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val)
-#define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT)
#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT)
#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val)
-#define pDMA2_3_Y_COUNT ((uint16_t volatile *)DMA2_3_Y_COUNT)
#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT)
#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val)
-#define pDMA2_3_X_MODIFY ((uint16_t volatile *)DMA2_3_X_MODIFY)
#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY)
#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val)
-#define pDMA2_3_Y_MODIFY ((uint16_t volatile *)DMA2_3_Y_MODIFY)
#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY)
#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val)
-#define pDMA2_3_CURR_DESC_PTR ((void * volatile *)DMA2_3_CURR_DESC_PTR)
#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR)
#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val)
-#define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR)
#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR)
#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val)
-#define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT)
#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT)
#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val)
-#define pDMA2_3_CURR_Y_COUNT ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT)
#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT)
#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val)
-#define pDMA2_3_IRQ_STATUS ((uint16_t volatile *)DMA2_3_IRQ_STATUS)
#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS)
#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val)
-#define pDMA2_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP)
#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP)
#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val)
-#define pDMA2_4_CONFIG ((uint16_t volatile *)DMA2_4_CONFIG)
#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG)
#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val)
-#define pDMA2_4_NEXT_DESC_PTR ((void * volatile *)DMA2_4_NEXT_DESC_PTR)
#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR)
#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val)
-#define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR)
#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR)
#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val)
-#define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT)
#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT)
#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val)
-#define pDMA2_4_Y_COUNT ((uint16_t volatile *)DMA2_4_Y_COUNT)
#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT)
#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val)
-#define pDMA2_4_X_MODIFY ((uint16_t volatile *)DMA2_4_X_MODIFY)
#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY)
#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val)
-#define pDMA2_4_Y_MODIFY ((uint16_t volatile *)DMA2_4_Y_MODIFY)
#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY)
#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val)
-#define pDMA2_4_CURR_DESC_PTR ((void * volatile *)DMA2_4_CURR_DESC_PTR)
#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR)
#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val)
-#define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR)
#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR)
#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val)
-#define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT)
#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT)
#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val)
-#define pDMA2_4_CURR_Y_COUNT ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT)
#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT)
#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val)
-#define pDMA2_4_IRQ_STATUS ((uint16_t volatile *)DMA2_4_IRQ_STATUS)
#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS)
#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val)
-#define pDMA2_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP)
#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP)
#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val)
-#define pDMA2_5_CONFIG ((uint16_t volatile *)DMA2_5_CONFIG)
#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG)
#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val)
-#define pDMA2_5_NEXT_DESC_PTR ((void * volatile *)DMA2_5_NEXT_DESC_PTR)
#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR)
#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val)
-#define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR)
#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR)
#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val)
-#define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT)
#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT)
#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val)
-#define pDMA2_5_Y_COUNT ((uint16_t volatile *)DMA2_5_Y_COUNT)
#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT)
#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val)
-#define pDMA2_5_X_MODIFY ((uint16_t volatile *)DMA2_5_X_MODIFY)
#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY)
#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val)
-#define pDMA2_5_Y_MODIFY ((uint16_t volatile *)DMA2_5_Y_MODIFY)
#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY)
#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val)
-#define pDMA2_5_CURR_DESC_PTR ((void * volatile *)DMA2_5_CURR_DESC_PTR)
#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR)
#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val)
-#define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR)
#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR)
#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val)
-#define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT)
#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT)
#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val)
-#define pDMA2_5_CURR_Y_COUNT ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT)
#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT)
#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val)
-#define pDMA2_5_IRQ_STATUS ((uint16_t volatile *)DMA2_5_IRQ_STATUS)
#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS)
#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val)
-#define pDMA2_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP)
#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP)
#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val)
-#define pDMA2_6_CONFIG ((uint16_t volatile *)DMA2_6_CONFIG)
#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG)
#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val)
-#define pDMA2_6_NEXT_DESC_PTR ((void * volatile *)DMA2_6_NEXT_DESC_PTR)
#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR)
#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val)
-#define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR)
#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR)
#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val)
-#define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT)
#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT)
#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val)
-#define pDMA2_6_Y_COUNT ((uint16_t volatile *)DMA2_6_Y_COUNT)
#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT)
#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val)
-#define pDMA2_6_X_MODIFY ((uint16_t volatile *)DMA2_6_X_MODIFY)
#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY)
#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val)
-#define pDMA2_6_Y_MODIFY ((uint16_t volatile *)DMA2_6_Y_MODIFY)
#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY)
#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val)
-#define pDMA2_6_CURR_DESC_PTR ((void * volatile *)DMA2_6_CURR_DESC_PTR)
#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR)
#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val)
-#define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR)
#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR)
#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val)
-#define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT)
#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT)
#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val)
-#define pDMA2_6_CURR_Y_COUNT ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT)
#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT)
#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val)
-#define pDMA2_6_IRQ_STATUS ((uint16_t volatile *)DMA2_6_IRQ_STATUS)
#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS)
#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val)
-#define pDMA2_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP)
#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP)
#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val)
-#define pDMA2_7_CONFIG ((uint16_t volatile *)DMA2_7_CONFIG)
#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG)
#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val)
-#define pDMA2_7_NEXT_DESC_PTR ((void * volatile *)DMA2_7_NEXT_DESC_PTR)
#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR)
#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val)
-#define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR)
#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR)
#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val)
-#define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT)
#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT)
#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val)
-#define pDMA2_7_Y_COUNT ((uint16_t volatile *)DMA2_7_Y_COUNT)
#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT)
#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val)
-#define pDMA2_7_X_MODIFY ((uint16_t volatile *)DMA2_7_X_MODIFY)
#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY)
#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val)
-#define pDMA2_7_Y_MODIFY ((uint16_t volatile *)DMA2_7_Y_MODIFY)
#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY)
#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val)
-#define pDMA2_7_CURR_DESC_PTR ((void * volatile *)DMA2_7_CURR_DESC_PTR)
#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR)
#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val)
-#define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR)
#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR)
#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val)
-#define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT)
#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT)
#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val)
-#define pDMA2_7_CURR_Y_COUNT ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT)
#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT)
#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val)
-#define pDMA2_7_IRQ_STATUS ((uint16_t volatile *)DMA2_7_IRQ_STATUS)
#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS)
#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val)
-#define pDMA2_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP)
#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP)
#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val)
-#define pDMA2_8_CONFIG ((uint16_t volatile *)DMA2_8_CONFIG)
#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG)
#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val)
-#define pDMA2_8_NEXT_DESC_PTR ((void * volatile *)DMA2_8_NEXT_DESC_PTR)
#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR)
#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val)
-#define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR)
#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR)
#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val)
-#define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT)
#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT)
#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val)
-#define pDMA2_8_Y_COUNT ((uint16_t volatile *)DMA2_8_Y_COUNT)
#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT)
#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val)
-#define pDMA2_8_X_MODIFY ((uint16_t volatile *)DMA2_8_X_MODIFY)
#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY)
#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val)
-#define pDMA2_8_Y_MODIFY ((uint16_t volatile *)DMA2_8_Y_MODIFY)
#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY)
#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val)
-#define pDMA2_8_CURR_DESC_PTR ((void * volatile *)DMA2_8_CURR_DESC_PTR)
#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR)
#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val)
-#define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR)
#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR)
#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val)
-#define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT)
#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT)
#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val)
-#define pDMA2_8_CURR_Y_COUNT ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT)
#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT)
#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val)
-#define pDMA2_8_IRQ_STATUS ((uint16_t volatile *)DMA2_8_IRQ_STATUS)
#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS)
#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val)
-#define pDMA2_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP)
#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP)
#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val)
-#define pDMA2_9_CONFIG ((uint16_t volatile *)DMA2_9_CONFIG)
#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG)
#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val)
-#define pDMA2_9_NEXT_DESC_PTR ((void * volatile *)DMA2_9_NEXT_DESC_PTR)
#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR)
#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val)
-#define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR)
#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR)
#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val)
-#define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT)
#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT)
#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val)
-#define pDMA2_9_Y_COUNT ((uint16_t volatile *)DMA2_9_Y_COUNT)
#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT)
#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val)
-#define pDMA2_9_X_MODIFY ((uint16_t volatile *)DMA2_9_X_MODIFY)
#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY)
#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val)
-#define pDMA2_9_Y_MODIFY ((uint16_t volatile *)DMA2_9_Y_MODIFY)
#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY)
#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val)
-#define pDMA2_9_CURR_DESC_PTR ((void * volatile *)DMA2_9_CURR_DESC_PTR)
#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR)
#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val)
-#define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR)
#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR)
#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val)
-#define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT)
#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT)
#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val)
-#define pDMA2_9_CURR_Y_COUNT ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT)
#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT)
#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val)
-#define pDMA2_9_IRQ_STATUS ((uint16_t volatile *)DMA2_9_IRQ_STATUS)
#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS)
#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val)
-#define pDMA2_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP)
#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP)
#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val)
-#define pDMA2_10_CONFIG ((uint16_t volatile *)DMA2_10_CONFIG)
#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG)
#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val)
-#define pDMA2_10_NEXT_DESC_PTR ((void * volatile *)DMA2_10_NEXT_DESC_PTR)
#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR)
#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val)
-#define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR)
#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR)
#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val)
-#define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT)
#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT)
#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val)
-#define pDMA2_10_Y_COUNT ((uint16_t volatile *)DMA2_10_Y_COUNT)
#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT)
#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val)
-#define pDMA2_10_X_MODIFY ((uint16_t volatile *)DMA2_10_X_MODIFY)
#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY)
#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val)
-#define pDMA2_10_Y_MODIFY ((uint16_t volatile *)DMA2_10_Y_MODIFY)
#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY)
#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val)
-#define pDMA2_10_CURR_DESC_PTR ((void * volatile *)DMA2_10_CURR_DESC_PTR)
#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR)
#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val)
-#define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR)
#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR)
#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val)
-#define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT)
#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT)
#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val)
-#define pDMA2_10_CURR_Y_COUNT ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT)
#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT)
#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val)
-#define pDMA2_10_IRQ_STATUS ((uint16_t volatile *)DMA2_10_IRQ_STATUS)
#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS)
#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val)
-#define pDMA2_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP)
#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP)
#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val)
-#define pDMA2_11_CONFIG ((uint16_t volatile *)DMA2_11_CONFIG)
#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG)
#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val)
-#define pDMA2_11_NEXT_DESC_PTR ((void * volatile *)DMA2_11_NEXT_DESC_PTR)
#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR)
#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val)
-#define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR)
#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR)
#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val)
-#define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT)
#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT)
#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val)
-#define pDMA2_11_Y_COUNT ((uint16_t volatile *)DMA2_11_Y_COUNT)
#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT)
#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val)
-#define pDMA2_11_X_MODIFY ((uint16_t volatile *)DMA2_11_X_MODIFY)
#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY)
#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val)
-#define pDMA2_11_Y_MODIFY ((uint16_t volatile *)DMA2_11_Y_MODIFY)
#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY)
#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val)
-#define pDMA2_11_CURR_DESC_PTR ((void * volatile *)DMA2_11_CURR_DESC_PTR)
#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR)
#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val)
-#define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR)
#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR)
#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val)
-#define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT)
#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT)
#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val)
-#define pDMA2_11_CURR_Y_COUNT ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT)
#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT)
#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val)
-#define pDMA2_11_IRQ_STATUS ((uint16_t volatile *)DMA2_11_IRQ_STATUS)
#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS)
#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val)
-#define pDMA2_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP)
#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP)
#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val)
-#define pIMDMA_S0_CONFIG ((uint16_t volatile *)IMDMA_S0_CONFIG)
#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG)
#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val)
-#define pIMDMA_S0_NEXT_DESC_PTR ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR)
#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR)
#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val)
-#define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR)
#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR)
#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val)
-#define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT)
#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT)
#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val)
-#define pIMDMA_S0_Y_COUNT ((uint16_t volatile *)IMDMA_S0_Y_COUNT)
#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT)
#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val)
-#define pIMDMA_S0_X_MODIFY ((uint16_t volatile *)IMDMA_S0_X_MODIFY)
#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY)
#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val)
-#define pIMDMA_S0_Y_MODIFY ((uint16_t volatile *)IMDMA_S0_Y_MODIFY)
#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY)
#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val)
-#define pIMDMA_S0_CURR_DESC_PTR ((void * volatile *)IMDMA_S0_CURR_DESC_PTR)
#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR)
#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val)
-#define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR)
#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR)
#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val)
-#define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT)
#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT)
#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val)
-#define pIMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT)
#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT)
#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val)
-#define pIMDMA_S0_IRQ_STATUS ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS)
#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS)
#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val)
-#define pIMDMA_D0_CONFIG ((uint16_t volatile *)IMDMA_D0_CONFIG)
#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG)
#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val)
-#define pIMDMA_D0_NEXT_DESC_PTR ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR)
#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR)
#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val)
-#define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR)
#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR)
#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val)
-#define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT)
#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT)
#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val)
-#define pIMDMA_D0_Y_COUNT ((uint16_t volatile *)IMDMA_D0_Y_COUNT)
#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT)
#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val)
-#define pIMDMA_D0_X_MODIFY ((uint16_t volatile *)IMDMA_D0_X_MODIFY)
#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY)
#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val)
-#define pIMDMA_D0_Y_MODIFY ((uint16_t volatile *)IMDMA_D0_Y_MODIFY)
#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY)
#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val)
-#define pIMDMA_D0_CURR_DESC_PTR ((void * volatile *)IMDMA_D0_CURR_DESC_PTR)
#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR)
#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val)
-#define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR)
#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR)
#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val)
-#define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT)
#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT)
#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val)
-#define pIMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT)
#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT)
#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val)
-#define pIMDMA_D0_IRQ_STATUS ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS)
#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS)
#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val)
-#define pIMDMA_S1_CONFIG ((uint16_t volatile *)IMDMA_S1_CONFIG)
#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG)
#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val)
-#define pIMDMA_S1_NEXT_DESC_PTR ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR)
#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR)
#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val)
-#define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR)
#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR)
#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val)
-#define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT)
#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT)
#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val)
-#define pIMDMA_S1_Y_COUNT ((uint16_t volatile *)IMDMA_S1_Y_COUNT)
#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT)
#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val)
-#define pIMDMA_S1_X_MODIFY ((uint16_t volatile *)IMDMA_S1_X_MODIFY)
#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY)
#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val)
-#define pIMDMA_S1_Y_MODIFY ((uint16_t volatile *)IMDMA_S1_Y_MODIFY)
#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY)
#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val)
-#define pIMDMA_S1_CURR_DESC_PTR ((void * volatile *)IMDMA_S1_CURR_DESC_PTR)
#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR)
#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val)
-#define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR)
#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR)
#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val)
-#define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT)
#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT)
#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val)
-#define pIMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT)
#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT)
#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val)
-#define pIMDMA_S1_IRQ_STATUS ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS)
#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS)
#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val)
-#define pIMDMA_D1_CONFIG ((uint16_t volatile *)IMDMA_D1_CONFIG)
#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG)
#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val)
-#define pIMDMA_D1_NEXT_DESC_PTR ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR)
#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR)
#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val)
-#define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR)
#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR)
#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val)
-#define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT)
#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT)
#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val)
-#define pIMDMA_D1_Y_COUNT ((uint16_t volatile *)IMDMA_D1_Y_COUNT)
#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT)
#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val)
-#define pIMDMA_D1_X_MODIFY ((uint16_t volatile *)IMDMA_D1_X_MODIFY)
#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY)
#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val)
-#define pIMDMA_D1_Y_MODIFY ((uint16_t volatile *)IMDMA_D1_Y_MODIFY)
#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY)
#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val)
-#define pIMDMA_D1_CURR_DESC_PTR ((void * volatile *)IMDMA_D1_CURR_DESC_PTR)
#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR)
#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val)
-#define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR)
#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR)
#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val)
-#define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT)
#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT)
#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val)
-#define pIMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT)
#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT)
#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val)
-#define pIMDMA_D1_IRQ_STATUS ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS)
#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS)
#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val)
-#define pMDMA1_S0_CONFIG ((uint16_t volatile *)MDMA1_S0_CONFIG)
#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG)
#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR)
#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT)
#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT)
#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define pMDMA1_S0_Y_COUNT ((uint16_t volatile *)MDMA1_S0_Y_COUNT)
#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT)
#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define pMDMA1_S0_X_MODIFY ((uint16_t volatile *)MDMA1_S0_X_MODIFY)
#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY)
#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define pMDMA1_S0_Y_MODIFY ((uint16_t volatile *)MDMA1_S0_Y_MODIFY)
#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY)
#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR)
#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT)
#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define pMDMA1_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT)
#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define pMDMA1_S0_IRQ_STATUS ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS)
#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define pMDMA1_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP)
#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define pMDMA1_D0_CONFIG ((uint16_t volatile *)MDMA1_D0_CONFIG)
#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG)
#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR)
#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT)
#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT)
#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define pMDMA1_D0_Y_COUNT ((uint16_t volatile *)MDMA1_D0_Y_COUNT)
#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT)
#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define pMDMA1_D0_X_MODIFY ((uint16_t volatile *)MDMA1_D0_X_MODIFY)
#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY)
#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define pMDMA1_D0_Y_MODIFY ((uint16_t volatile *)MDMA1_D0_Y_MODIFY)
#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY)
#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR)
#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT)
#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define pMDMA1_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT)
#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS)
#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define pMDMA1_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define pMDMA1_S1_CONFIG ((uint16_t volatile *)MDMA1_S1_CONFIG)
#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG)
#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR)
#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT)
#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT)
#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define pMDMA1_S1_Y_COUNT ((uint16_t volatile *)MDMA1_S1_Y_COUNT)
#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT)
#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define pMDMA1_S1_X_MODIFY ((uint16_t volatile *)MDMA1_S1_X_MODIFY)
#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY)
#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define pMDMA1_S1_Y_MODIFY ((uint16_t volatile *)MDMA1_S1_Y_MODIFY)
#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY)
#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR)
#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT)
#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define pMDMA1_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT)
#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-#define pMDMA1_S1_IRQ_STATUS ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS)
#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define pMDMA1_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP)
#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define pMDMA1_D1_CONFIG ((uint16_t volatile *)MDMA1_D1_CONFIG)
#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG)
#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR)
#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT)
#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT)
#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define pMDMA1_D1_Y_COUNT ((uint16_t volatile *)MDMA1_D1_Y_COUNT)
#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT)
#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define pMDMA1_D1_X_MODIFY ((uint16_t volatile *)MDMA1_D1_X_MODIFY)
#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY)
#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define pMDMA1_D1_Y_MODIFY ((uint16_t volatile *)MDMA1_D1_Y_MODIFY)
#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY)
#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR)
#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT)
#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define pMDMA1_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT)
#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define pMDMA1_D1_IRQ_STATUS ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS)
#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define pMDMA1_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define pMDMA2_S0_CONFIG ((uint16_t volatile *)MDMA2_S0_CONFIG)
#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG)
#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val)
-#define pMDMA2_S0_NEXT_DESC_PTR ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR)
#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val)
-#define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR)
#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR)
#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val)
-#define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT)
#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT)
#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val)
-#define pMDMA2_S0_Y_COUNT ((uint16_t volatile *)MDMA2_S0_Y_COUNT)
#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT)
#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val)
-#define pMDMA2_S0_X_MODIFY ((uint16_t volatile *)MDMA2_S0_X_MODIFY)
#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY)
#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val)
-#define pMDMA2_S0_Y_MODIFY ((uint16_t volatile *)MDMA2_S0_Y_MODIFY)
#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY)
#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val)
-#define pMDMA2_S0_CURR_DESC_PTR ((void * volatile *)MDMA2_S0_CURR_DESC_PTR)
#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR)
#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val)
-#define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR)
#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR)
#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val)
-#define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT)
#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT)
#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val)
-#define pMDMA2_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT)
#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT)
#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val)
-#define pMDMA2_S0_IRQ_STATUS ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS)
#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS)
#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val)
-#define pMDMA2_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP)
#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val)
-#define pMDMA2_D0_CONFIG ((uint16_t volatile *)MDMA2_D0_CONFIG)
#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG)
#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val)
-#define pMDMA2_D0_NEXT_DESC_PTR ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val)
-#define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR)
#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR)
#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val)
-#define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT)
#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT)
#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val)
-#define pMDMA2_D0_Y_COUNT ((uint16_t volatile *)MDMA2_D0_Y_COUNT)
#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT)
#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val)
-#define pMDMA2_D0_X_MODIFY ((uint16_t volatile *)MDMA2_D0_X_MODIFY)
#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY)
#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val)
-#define pMDMA2_D0_Y_MODIFY ((uint16_t volatile *)MDMA2_D0_Y_MODIFY)
#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY)
#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val)
-#define pMDMA2_D0_CURR_DESC_PTR ((void * volatile *)MDMA2_D0_CURR_DESC_PTR)
#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR)
#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val)
-#define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR)
#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR)
#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val)
-#define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT)
#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT)
#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val)
-#define pMDMA2_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT)
#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT)
#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val)
-#define pMDMA2_D0_IRQ_STATUS ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS)
#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS)
#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val)
-#define pMDMA2_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val)
-#define pMDMA2_S1_CONFIG ((uint16_t volatile *)MDMA2_S1_CONFIG)
#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG)
#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val)
-#define pMDMA2_S1_NEXT_DESC_PTR ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR)
#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val)
-#define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR)
#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR)
#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val)
-#define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT)
#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT)
#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val)
-#define pMDMA2_S1_Y_COUNT ((uint16_t volatile *)MDMA2_S1_Y_COUNT)
#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT)
#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val)
-#define pMDMA2_S1_X_MODIFY ((uint16_t volatile *)MDMA2_S1_X_MODIFY)
#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY)
#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val)
-#define pMDMA2_S1_Y_MODIFY ((uint16_t volatile *)MDMA2_S1_Y_MODIFY)
#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY)
#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val)
-#define pMDMA2_S1_CURR_DESC_PTR ((void * volatile *)MDMA2_S1_CURR_DESC_PTR)
#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR)
#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val)
-#define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR)
#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR)
#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val)
-#define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT)
#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT)
#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val)
-#define pMDMA2_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT)
#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT)
#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val)
-#define pMDMA2_S1_IRQ_STATUS ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS)
#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS)
#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val)
-#define pMDMA2_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP)
#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val)
-#define pMDMA2_D1_CONFIG ((uint16_t volatile *)MDMA2_D1_CONFIG)
#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG)
#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val)
-#define pMDMA2_D1_NEXT_DESC_PTR ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR)
#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val)
-#define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR)
#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR)
#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val)
-#define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT)
#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT)
#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val)
-#define pMDMA2_D1_Y_COUNT ((uint16_t volatile *)MDMA2_D1_Y_COUNT)
#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT)
#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val)
-#define pMDMA2_D1_X_MODIFY ((uint16_t volatile *)MDMA2_D1_X_MODIFY)
#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY)
#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val)
-#define pMDMA2_D1_Y_MODIFY ((uint16_t volatile *)MDMA2_D1_Y_MODIFY)
#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY)
#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val)
-#define pMDMA2_D1_CURR_DESC_PTR ((void * volatile *)MDMA2_D1_CURR_DESC_PTR)
#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR)
#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val)
-#define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR)
#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR)
#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val)
-#define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT)
#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT)
#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val)
-#define pMDMA2_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT)
#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT)
#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val)
-#define pMDMA2_D1_IRQ_STATUS ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS)
#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS)
#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val)
-#define pMDMA2_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG)
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER)
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD)
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH)
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG)
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER)
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD)
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH)
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG)
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER)
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD)
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH)
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG)
#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER)
#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD)
#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH)
#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG)
#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER)
#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD)
#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH)
#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG)
#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER)
#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD)
#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH)
#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG)
#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER)
#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD)
#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH)
#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG)
#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER)
#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD)
#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH)
#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG)
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
-#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER)
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
-#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD)
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
-#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH)
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
-#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG)
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
-#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER)
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
-#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD)
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
-#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH)
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
-#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG)
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
-#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER)
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD)
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
-#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH)
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
-#define pTIMER11_CONFIG ((uint16_t volatile *)TIMER11_CONFIG)
#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG)
#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val)
-#define pTIMER11_COUNTER ((uint32_t volatile *)TIMER11_COUNTER)
#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER)
#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val)
-#define pTIMER11_PERIOD ((uint32_t volatile *)TIMER11_PERIOD)
#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD)
#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val)
-#define pTIMER11_WIDTH ((uint32_t volatile *)TIMER11_WIDTH)
#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH)
#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val)
-#define pTMRS4_ENABLE ((uint32_t volatile *)TMRS4_ENABLE)
#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE)
#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val)
-#define pTMRS4_DISABLE ((uint32_t volatile *)TMRS4_DISABLE)
#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE)
#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val)
-#define pTMRS4_STATUS ((uint32_t volatile *)TMRS4_STATUS)
#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS)
#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val)
-#define pTMRS8_ENABLE ((uint32_t volatile *)TMRS8_ENABLE)
#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE)
#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val)
-#define pTMRS8_DISABLE ((uint32_t volatile *)TMRS8_DISABLE)
#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE)
#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val)
-#define pTMRS8_STATUS ((uint32_t volatile *)TMRS8_STATUS)
#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS)
#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val)
-#define pFIO0_FLAG_D ((uint16_t volatile *)FIO0_FLAG_D)
#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D)
#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val)
-#define pFIO0_FLAG_C ((uint16_t volatile *)FIO0_FLAG_C)
#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C)
#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val)
-#define pFIO0_FLAG_S ((uint16_t volatile *)FIO0_FLAG_S)
#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S)
#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val)
-#define pFIO0_FLAG_T ((uint16_t volatile *)FIO0_FLAG_T)
#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T)
#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val)
-#define pFIO0_MASKA_D ((uint16_t volatile *)FIO0_MASKA_D)
#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D)
#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val)
-#define pFIO0_MASKA_C ((uint16_t volatile *)FIO0_MASKA_C)
#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C)
#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val)
-#define pFIO0_MASKA_S ((uint16_t volatile *)FIO0_MASKA_S)
#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S)
#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val)
-#define pFIO0_MASKA_T ((uint16_t volatile *)FIO0_MASKA_T)
#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T)
#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val)
-#define pFIO0_MASKB_D ((uint16_t volatile *)FIO0_MASKB_D)
#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D)
#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val)
-#define pFIO0_MASKB_C ((uint16_t volatile *)FIO0_MASKB_C)
#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C)
#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val)
-#define pFIO0_MASKB_S ((uint16_t volatile *)FIO0_MASKB_S)
#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S)
#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val)
-#define pFIO0_MASKB_T ((uint16_t volatile *)FIO0_MASKB_T)
#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T)
#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val)
-#define pFIO0_DIR ((uint16_t volatile *)FIO0_DIR)
#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR)
#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val)
-#define pFIO0_POLAR ((uint16_t volatile *)FIO0_POLAR)
#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR)
#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val)
-#define pFIO0_EDGE ((uint16_t volatile *)FIO0_EDGE)
#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE)
#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val)
-#define pFIO0_BOTH ((uint16_t volatile *)FIO0_BOTH)
#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH)
#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val)
-#define pFIO0_INEN ((uint16_t volatile *)FIO0_INEN)
#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN)
#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val)
-#define pFIO1_FLAG_D ((uint16_t volatile *)FIO1_FLAG_D)
#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D)
#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val)
-#define pFIO1_FLAG_C ((uint16_t volatile *)FIO1_FLAG_C)
#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C)
#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val)
-#define pFIO1_FLAG_S ((uint16_t volatile *)FIO1_FLAG_S)
#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S)
#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val)
-#define pFIO1_FLAG_T ((uint16_t volatile *)FIO1_FLAG_T)
#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T)
#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val)
-#define pFIO1_MASKA_D ((uint16_t volatile *)FIO1_MASKA_D)
#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D)
#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val)
-#define pFIO1_MASKA_C ((uint16_t volatile *)FIO1_MASKA_C)
#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C)
#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val)
-#define pFIO1_MASKA_S ((uint16_t volatile *)FIO1_MASKA_S)
#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S)
#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val)
-#define pFIO1_MASKA_T ((uint16_t volatile *)FIO1_MASKA_T)
#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T)
#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val)
-#define pFIO1_MASKB_D ((uint16_t volatile *)FIO1_MASKB_D)
#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D)
#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val)
-#define pFIO1_MASKB_C ((uint16_t volatile *)FIO1_MASKB_C)
#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C)
#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val)
-#define pFIO1_MASKB_S ((uint16_t volatile *)FIO1_MASKB_S)
#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S)
#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val)
-#define pFIO1_MASKB_T ((uint16_t volatile *)FIO1_MASKB_T)
#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T)
#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val)
-#define pFIO1_DIR ((uint16_t volatile *)FIO1_DIR)
#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR)
#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val)
-#define pFIO1_POLAR ((uint16_t volatile *)FIO1_POLAR)
#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR)
#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val)
-#define pFIO1_EDGE ((uint16_t volatile *)FIO1_EDGE)
#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE)
#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val)
-#define pFIO1_BOTH ((uint16_t volatile *)FIO1_BOTH)
#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH)
#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val)
-#define pFIO1_INEN ((uint16_t volatile *)FIO1_INEN)
#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN)
#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val)
-#define pFIO2_FLAG_D ((uint16_t volatile *)FIO2_FLAG_D)
#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D)
#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val)
-#define pFIO2_FLAG_C ((uint16_t volatile *)FIO2_FLAG_C)
#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C)
#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val)
-#define pFIO2_FLAG_S ((uint16_t volatile *)FIO2_FLAG_S)
#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S)
#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val)
-#define pFIO2_FLAG_T ((uint16_t volatile *)FIO2_FLAG_T)
#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T)
#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val)
-#define pFIO2_MASKA_D ((uint16_t volatile *)FIO2_MASKA_D)
#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D)
#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val)
-#define pFIO2_MASKA_C ((uint16_t volatile *)FIO2_MASKA_C)
#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C)
#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val)
-#define pFIO2_MASKA_S ((uint16_t volatile *)FIO2_MASKA_S)
#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S)
#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val)
-#define pFIO2_MASKA_T ((uint16_t volatile *)FIO2_MASKA_T)
#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T)
#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val)
-#define pFIO2_MASKB_D ((uint16_t volatile *)FIO2_MASKB_D)
#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D)
#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val)
-#define pFIO2_MASKB_C ((uint16_t volatile *)FIO2_MASKB_C)
#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C)
#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val)
-#define pFIO2_MASKB_S ((uint16_t volatile *)FIO2_MASKB_S)
#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S)
#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val)
-#define pFIO2_MASKB_T ((uint16_t volatile *)FIO2_MASKB_T)
#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T)
#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val)
-#define pFIO2_DIR ((uint16_t volatile *)FIO2_DIR)
#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR)
#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val)
-#define pFIO2_POLAR ((uint16_t volatile *)FIO2_POLAR)
#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR)
#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val)
-#define pFIO2_EDGE ((uint16_t volatile *)FIO2_EDGE)
#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE)
#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val)
-#define pFIO2_BOTH ((uint16_t volatile *)FIO2_BOTH)
#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH)
#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val)
-#define pFIO2_INEN ((uint16_t volatile *)FIO2_INEN)
#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN)
#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1)
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2)
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV)
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX)
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV)
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV)
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT)
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL)
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1)
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2)
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0)
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1)
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2)
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3)
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0)
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1)
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2)
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3)
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1)
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2)
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV)
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV)
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX)
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX)
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1)
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2)
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV)
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV)
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT)
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL)
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1)
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2)
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0)
#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1)
#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2)
#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3)
#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0)
#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1)
#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2)
#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3)
#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define pEVT0 ((void * volatile *)EVT0)
#define bfin_read_EVT0() bfin_readPTR(EVT0)
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1)
#define bfin_read_EVT1() bfin_readPTR(EVT1)
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2)
#define bfin_read_EVT2() bfin_readPTR(EVT2)
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3)
#define bfin_read_EVT3() bfin_readPTR(EVT3)
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4)
#define bfin_read_EVT4() bfin_readPTR(EVT4)
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5)
#define bfin_read_EVT5() bfin_readPTR(EVT5)
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6)
#define bfin_read_EVT6() bfin_readPTR(EVT6)
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7)
#define bfin_read_EVT7() bfin_readPTR(EVT7)
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8)
#define bfin_read_EVT8() bfin_readPTR(EVT8)
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9)
#define bfin_read_EVT9() bfin_readPTR(EVT9)
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10)
#define bfin_read_EVT10() bfin_readPTR(EVT10)
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11)
#define bfin_read_EVT11() bfin_readPTR(EVT11)
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12)
#define bfin_read_EVT12() bfin_readPTR(EVT12)
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13)
#define bfin_read_EVT13() bfin_readPTR(EVT13)
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14)
#define bfin_read_EVT14() bfin_readPTR(EVT14)
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15)
#define bfin_read_EVT15() bfin_readPTR(EVT15)
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
#define bfin_read_ILAT() bfin_read32(ILAT)
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
#define bfin_read_IMASK() bfin_read32(IMASK)
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
#define bfin_read_IPEND() bfin_read32(IPEND)
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL)
#define bfin_read_TCNTL() bfin_read32(TCNTL)
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD)
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE)
#define bfin_read_TSCALE() bfin_read32(TSCALE)
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT)
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
index af17813..f9352ae 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h
@@ -6,67 +6,46 @@
#ifndef __BFIN_CDEF_ADSP_EDN_core__
#define __BFIN_CDEF_ADSP_EDN_core__
-#define pWPIACTL ((uint32_t volatile *)WPIACTL)
#define bfin_read_WPIACTL() bfin_read32(WPIACTL)
#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val)
-#define pWPIA0 ((void * volatile *)WPIA0)
#define bfin_read_WPIA0() bfin_readPTR(WPIA0)
#define bfin_write_WPIA0(val) bfin_writePTR(WPIA0, val)
-#define pWPIA1 ((void * volatile *)WPIA1)
#define bfin_read_WPIA1() bfin_readPTR(WPIA1)
#define bfin_write_WPIA1(val) bfin_writePTR(WPIA1, val)
-#define pWPIA2 ((void * volatile *)WPIA2)
#define bfin_read_WPIA2() bfin_readPTR(WPIA2)
#define bfin_write_WPIA2(val) bfin_writePTR(WPIA2, val)
-#define pWPIA3 ((void * volatile *)WPIA3)
#define bfin_read_WPIA3() bfin_readPTR(WPIA3)
#define bfin_write_WPIA3(val) bfin_writePTR(WPIA3, val)
-#define pWPIA4 ((void * volatile *)WPIA4)
#define bfin_read_WPIA4() bfin_readPTR(WPIA4)
#define bfin_write_WPIA4(val) bfin_writePTR(WPIA4, val)
-#define pWPIA5 ((void * volatile *)WPIA5)
#define bfin_read_WPIA5() bfin_readPTR(WPIA5)
#define bfin_write_WPIA5(val) bfin_writePTR(WPIA5, val)
-#define pWPIACNT0 ((uint32_t volatile *)WPIACNT0)
#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0)
#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val)
-#define pWPIACNT1 ((uint32_t volatile *)WPIACNT1)
#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1)
#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val)
-#define pWPIACNT2 ((uint32_t volatile *)WPIACNT2)
#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2)
#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val)
-#define pWPIACNT3 ((uint32_t volatile *)WPIACNT3)
#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3)
#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val)
-#define pWPIACNT4 ((uint32_t volatile *)WPIACNT4)
#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4)
#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val)
-#define pWPIACNT5 ((uint32_t volatile *)WPIACNT5)
#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5)
#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val)
-#define pWPDACTL ((uint32_t volatile *)WPDACTL)
#define bfin_read_WPDACTL() bfin_read32(WPDACTL)
#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val)
-#define pWPDA0 ((void * volatile *)WPDA0)
#define bfin_read_WPDA0() bfin_readPTR(WPDA0)
#define bfin_write_WPDA0(val) bfin_writePTR(WPDA0, val)
-#define pWPDA1 ((void * volatile *)WPDA1)
#define bfin_read_WPDA1() bfin_readPTR(WPDA1)
#define bfin_write_WPDA1(val) bfin_writePTR(WPDA1, val)
-#define pWPDACNT0 ((uint32_t volatile *)WPDACNT0)
#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0)
#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val)
-#define pWPDACNT1 ((uint32_t volatile *)WPDACNT1)
#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1)
#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val)
-#define pWPSTAT ((uint32_t volatile *)WPSTAT)
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
-#define pDSPID ((uint32_t volatile *)DSPID)
#define bfin_read_DSPID() bfin_read32(DSPID)
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
-#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
index 2e61b5f..ffa9e0a 100644
--- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h
@@ -6,1601 +6,1068 @@
#ifndef __BFIN_CDEF_ADSP_EDN_extended__
#define __BFIN_CDEF_ADSP_EDN_extended__
-#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */
#define bfin_read_ILAT() bfin_read32(ILAT)
#define bfin_write_ILAT(val) bfin_write32(ILAT, val)
-#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */
#define bfin_read_IMASK() bfin_read32(IMASK)
#define bfin_write_IMASK(val) bfin_write32(IMASK, val)
-#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */
#define bfin_read_IPEND() bfin_read32(IPEND)
#define bfin_write_IPEND(val) bfin_write32(IPEND, val)
-#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
-#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
#define bfin_read_TCNTL() bfin_read32(TCNTL)
#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val)
-#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
#define bfin_read_TPERIOD() bfin_read32(TPERIOD)
#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val)
-#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
#define bfin_read_TSCALE() bfin_read32(TSCALE)
#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val)
-#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
-#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */
#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR)
#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */
#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)
-#define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */
#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS)
#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val)
-#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR)
#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)
#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val)
-#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */
#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0)
#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val)
-#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */
#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1)
#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val)
-#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */
#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2)
#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val)
-#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */
#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3)
#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val)
-#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */
#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4)
#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val)
-#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */
#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5)
#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val)
-#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */
#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6)
#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val)
-#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */
#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7)
#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val)
-#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */
#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8)
#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val)
-#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */
#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9)
#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val)
-#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */
#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10)
#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val)
-#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */
#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11)
#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val)
-#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */
#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12)
#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val)
-#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */
#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13)
#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val)
-#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */
#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14)
#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val)
-#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */
#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15)
#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val)
-#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */
#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)
#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)
-#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */
#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)
#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)
-#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */
#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)
#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)
-#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */
#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)
#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)
-#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */
#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)
#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)
-#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */
#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)
#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)
-#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */
#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)
#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)
-#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */
#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)
#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)
-#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */
#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)
#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)
-#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */
#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)
#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)
-#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */
#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)
#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)
-#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */
#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)
#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)
-#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */
#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)
#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)
-#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */
#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)
#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)
-#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */
#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)
#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)
-#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */
#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)
#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)
-#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */
#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)
#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)
-#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */
#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)
#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)
-#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */
#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)
#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)
-#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */
#define bfin_read_EVT0() bfin_readPTR(EVT0)
#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val)
-#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */
#define bfin_read_EVT1() bfin_readPTR(EVT1)
#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val)
-#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */
#define bfin_read_EVT2() bfin_readPTR(EVT2)
#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val)
-#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */
#define bfin_read_EVT3() bfin_readPTR(EVT3)
#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val)
-#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */
#define bfin_read_EVT4() bfin_readPTR(EVT4)
#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val)
-#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */
#define bfin_read_EVT5() bfin_readPTR(EVT5)
#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val)
-#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */
#define bfin_read_EVT6() bfin_readPTR(EVT6)
#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val)
-#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */
#define bfin_read_EVT7() bfin_readPTR(EVT7)
#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val)
-#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */
#define bfin_read_EVT8() bfin_readPTR(EVT8)
#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val)
-#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */
#define bfin_read_EVT9() bfin_readPTR(EVT9)
#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val)
-#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */
#define bfin_read_EVT10() bfin_readPTR(EVT10)
#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val)
-#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */
#define bfin_read_EVT11() bfin_readPTR(EVT11)
#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val)
-#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */
#define bfin_read_EVT12() bfin_readPTR(EVT12)
#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val)
-#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */
#define bfin_read_EVT13() bfin_readPTR(EVT13)
#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val)
-#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */
#define bfin_read_EVT14() bfin_readPTR(EVT14)
#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val)
-#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */
#define bfin_read_EVT15() bfin_readPTR(EVT15)
#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val)
-#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */
#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)
-#define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS)
#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS)
#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val)
-#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)
#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)
#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */
#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0)
#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val)
-#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */
#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1)
#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val)
-#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */
#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2)
#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val)
-#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */
#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3)
#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val)
-#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */
#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4)
#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val)
-#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */
#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5)
#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val)
-#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */
#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6)
#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val)
-#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */
#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7)
#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val)
-#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */
#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8)
#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val)
-#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */
#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9)
#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val)
-#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */
#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10)
#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val)
-#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */
#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11)
#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val)
-#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */
#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12)
#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val)
-#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */
#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13)
#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val)
-#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */
#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14)
#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val)
-#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */
#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15)
#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val)
-#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */
#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0)
#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val)
-#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */
#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1)
#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val)
-#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */
#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2)
#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val)
-#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */
#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3)
#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val)
-#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */
#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4)
#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val)
-#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */
#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5)
#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val)
-#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */
#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6)
#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val)
-#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */
#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7)
#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val)
-#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */
#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8)
#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val)
-#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */
#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9)
#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val)
-#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */
#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10)
#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val)
-#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */
#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11)
#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val)
-#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */
#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12)
#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val)
-#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */
#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13)
#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val)
-#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */
#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14)
#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val)
-#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */
#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15)
#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val)
-#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */
#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND)
#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val)
-#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */
#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0)
#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val)
-#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
-#define pMDMAFLX0_DMACNFG_D ((uint16_t volatile *)MDMAFLX0_DMACNFG_D)
#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define pMDMAFLX0_XCOUNT_D ((uint16_t volatile *)MDMAFLX0_XCOUNT_D)
#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D)
#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define pMDMAFLX0_XMODIFY_D ((uint16_t volatile *)MDMAFLX0_XMODIFY_D)
#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define pMDMAFLX0_YCOUNT_D ((uint16_t volatile *)MDMAFLX0_YCOUNT_D)
#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D)
#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define pMDMAFLX0_YMODIFY_D ((uint16_t volatile *)MDMAFLX0_YMODIFY_D)
#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define pMDMAFLX0_IRQSTAT_D ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D)
#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define pMDMAFLX0_PMAP_D ((uint16_t volatile *)MDMAFLX0_PMAP_D)
#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D)
#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define pMDMAFLX0_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D)
#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define pMDMAFLX0_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D)
#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define pMDMAFLX0_DMACNFG_S ((uint16_t volatile *)MDMAFLX0_DMACNFG_S)
#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define pMDMAFLX0_XCOUNT_S ((uint16_t volatile *)MDMAFLX0_XCOUNT_S)
#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S)
#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define pMDMAFLX0_XMODIFY_S ((uint16_t volatile *)MDMAFLX0_XMODIFY_S)
#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define pMDMAFLX0_YCOUNT_S ((uint16_t volatile *)MDMAFLX0_YCOUNT_S)
#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S)
#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define pMDMAFLX0_YMODIFY_S ((uint16_t volatile *)MDMAFLX0_YMODIFY_S)
#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define pMDMAFLX0_IRQSTAT_S ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S)
#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define pMDMAFLX0_PMAP_S ((uint16_t volatile *)MDMAFLX0_PMAP_S)
#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S)
#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define pMDMAFLX0_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S)
#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define pMDMAFLX0_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S)
#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define pMDMAFLX1_DMACNFG_D ((uint16_t volatile *)MDMAFLX1_DMACNFG_D)
#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define pMDMAFLX1_XCOUNT_D ((uint16_t volatile *)MDMAFLX1_XCOUNT_D)
#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D)
#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define pMDMAFLX1_XMODIFY_D ((uint16_t volatile *)MDMAFLX1_XMODIFY_D)
#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define pMDMAFLX1_YCOUNT_D ((uint16_t volatile *)MDMAFLX1_YCOUNT_D)
#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D)
#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define pMDMAFLX1_YMODIFY_D ((uint16_t volatile *)MDMAFLX1_YMODIFY_D)
#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define pMDMAFLX1_IRQSTAT_D ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D)
#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define pMDMAFLX1_PMAP_D ((uint16_t volatile *)MDMAFLX1_PMAP_D)
#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D)
#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define pMDMAFLX1_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D)
#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define pMDMAFLX1_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D)
#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define pMDMAFLX1_DMACNFG_S ((uint16_t volatile *)MDMAFLX1_DMACNFG_S)
#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define pMDMAFLX1_XCOUNT_S ((uint16_t volatile *)MDMAFLX1_XCOUNT_S)
#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S)
#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define pMDMAFLX1_XMODIFY_S ((uint16_t volatile *)MDMAFLX1_XMODIFY_S)
#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define pMDMAFLX1_YCOUNT_S ((uint16_t volatile *)MDMAFLX1_YCOUNT_S)
#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S)
#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define pMDMAFLX1_YMODIFY_S ((uint16_t volatile *)MDMAFLX1_YMODIFY_S)
#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define pMDMAFLX1_IRQSTAT_S ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S)
#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define pMDMAFLX1_PMAP_S ((uint16_t volatile *)MDMAFLX1_PMAP_S)
#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S)
#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define pMDMAFLX1_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S)
#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define pMDMAFLX1_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S)
#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define pDMAFLX0_DMACNFG ((uint16_t volatile *)DMAFLX0_DMACNFG)
#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG)
#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define pDMAFLX0_XCOUNT ((uint16_t volatile *)DMAFLX0_XCOUNT)
#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT)
#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define pDMAFLX0_XMODIFY ((uint16_t volatile *)DMAFLX0_XMODIFY)
#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY)
#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define pDMAFLX0_YCOUNT ((uint16_t volatile *)DMAFLX0_YCOUNT)
#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT)
#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define pDMAFLX0_YMODIFY ((uint16_t volatile *)DMAFLX0_YMODIFY)
#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY)
#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define pDMAFLX0_IRQSTAT ((uint16_t volatile *)DMAFLX0_IRQSTAT)
#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT)
#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define pDMAFLX0_PMAP ((uint16_t volatile *)DMAFLX0_PMAP)
#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP)
#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val)
-#define pDMAFLX0_CURXCOUNT ((uint16_t volatile *)DMAFLX0_CURXCOUNT)
#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT)
#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define pDMAFLX0_CURYCOUNT ((uint16_t volatile *)DMAFLX0_CURYCOUNT)
#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT)
#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define pDMAFLX1_DMACNFG ((uint16_t volatile *)DMAFLX1_DMACNFG)
#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG)
#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define pDMAFLX1_XCOUNT ((uint16_t volatile *)DMAFLX1_XCOUNT)
#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT)
#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define pDMAFLX1_XMODIFY ((uint16_t volatile *)DMAFLX1_XMODIFY)
#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY)
#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define pDMAFLX1_YCOUNT ((uint16_t volatile *)DMAFLX1_YCOUNT)
#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT)
#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define pDMAFLX1_YMODIFY ((uint16_t volatile *)DMAFLX1_YMODIFY)
#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY)
#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define pDMAFLX1_IRQSTAT ((uint16_t volatile *)DMAFLX1_IRQSTAT)
#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT)
#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define pDMAFLX1_PMAP ((uint16_t volatile *)DMAFLX1_PMAP)
#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP)
#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val)
-#define pDMAFLX1_CURXCOUNT ((uint16_t volatile *)DMAFLX1_CURXCOUNT)
#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT)
#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define pDMAFLX1_CURYCOUNT ((uint16_t volatile *)DMAFLX1_CURYCOUNT)
#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT)
#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define pDMAFLX2_DMACNFG ((uint16_t volatile *)DMAFLX2_DMACNFG)
#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG)
#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define pDMAFLX2_XCOUNT ((uint16_t volatile *)DMAFLX2_XCOUNT)
#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT)
#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define pDMAFLX2_XMODIFY ((uint16_t volatile *)DMAFLX2_XMODIFY)
#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY)
#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define pDMAFLX2_YCOUNT ((uint16_t volatile *)DMAFLX2_YCOUNT)
#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT)
#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define pDMAFLX2_YMODIFY ((uint16_t volatile *)DMAFLX2_YMODIFY)
#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY)
#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define pDMAFLX2_IRQSTAT ((uint16_t volatile *)DMAFLX2_IRQSTAT)
#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT)
#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define pDMAFLX2_PMAP ((uint16_t volatile *)DMAFLX2_PMAP)
#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP)
#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val)
-#define pDMAFLX2_CURXCOUNT ((uint16_t volatile *)DMAFLX2_CURXCOUNT)
#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT)
#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define pDMAFLX2_CURYCOUNT ((uint16_t volatile *)DMAFLX2_CURYCOUNT)
#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT)
#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define pDMAFLX3_DMACNFG ((uint16_t volatile *)DMAFLX3_DMACNFG)
#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG)
#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define pDMAFLX3_XCOUNT ((uint16_t volatile *)DMAFLX3_XCOUNT)
#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT)
#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define pDMAFLX3_XMODIFY ((uint16_t volatile *)DMAFLX3_XMODIFY)
#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY)
#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define pDMAFLX3_YCOUNT ((uint16_t volatile *)DMAFLX3_YCOUNT)
#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT)
#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define pDMAFLX3_YMODIFY ((uint16_t volatile *)DMAFLX3_YMODIFY)
#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY)
#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define pDMAFLX3_IRQSTAT ((uint16_t volatile *)DMAFLX3_IRQSTAT)
#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT)
#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define pDMAFLX3_PMAP ((uint16_t volatile *)DMAFLX3_PMAP)
#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP)
#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val)
-#define pDMAFLX3_CURXCOUNT ((uint16_t volatile *)DMAFLX3_CURXCOUNT)
#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT)
#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define pDMAFLX3_CURYCOUNT ((uint16_t volatile *)DMAFLX3_CURYCOUNT)
#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT)
#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define pDMAFLX4_DMACNFG ((uint16_t volatile *)DMAFLX4_DMACNFG)
#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG)
#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define pDMAFLX4_XCOUNT ((uint16_t volatile *)DMAFLX4_XCOUNT)
#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT)
#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define pDMAFLX4_XMODIFY ((uint16_t volatile *)DMAFLX4_XMODIFY)
#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY)
#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define pDMAFLX4_YCOUNT ((uint16_t volatile *)DMAFLX4_YCOUNT)
#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT)
#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define pDMAFLX4_YMODIFY ((uint16_t volatile *)DMAFLX4_YMODIFY)
#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY)
#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define pDMAFLX4_IRQSTAT ((uint16_t volatile *)DMAFLX4_IRQSTAT)
#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT)
#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define pDMAFLX4_PMAP ((uint16_t volatile *)DMAFLX4_PMAP)
#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP)
#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val)
-#define pDMAFLX4_CURXCOUNT ((uint16_t volatile *)DMAFLX4_CURXCOUNT)
#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT)
#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define pDMAFLX4_CURYCOUNT ((uint16_t volatile *)DMAFLX4_CURYCOUNT)
#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT)
#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define pDMAFLX5_DMACNFG ((uint16_t volatile *)DMAFLX5_DMACNFG)
#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG)
#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define pDMAFLX5_XCOUNT ((uint16_t volatile *)DMAFLX5_XCOUNT)
#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT)
#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define pDMAFLX5_XMODIFY ((uint16_t volatile *)DMAFLX5_XMODIFY)
#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY)
#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define pDMAFLX5_YCOUNT ((uint16_t volatile *)DMAFLX5_YCOUNT)
#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT)
#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define pDMAFLX5_YMODIFY ((uint16_t volatile *)DMAFLX5_YMODIFY)
#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY)
#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define pDMAFLX5_IRQSTAT ((uint16_t volatile *)DMAFLX5_IRQSTAT)
#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT)
#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define pDMAFLX5_PMAP ((uint16_t volatile *)DMAFLX5_PMAP)
#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP)
#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val)
-#define pDMAFLX5_CURXCOUNT ((uint16_t volatile *)DMAFLX5_CURXCOUNT)
#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT)
#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define pDMAFLX5_CURYCOUNT ((uint16_t volatile *)DMAFLX5_CURYCOUNT)
#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT)
#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define pDMAFLX6_DMACNFG ((uint16_t volatile *)DMAFLX6_DMACNFG)
#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG)
#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define pDMAFLX6_XCOUNT ((uint16_t volatile *)DMAFLX6_XCOUNT)
#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT)
#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define pDMAFLX6_XMODIFY ((uint16_t volatile *)DMAFLX6_XMODIFY)
#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY)
#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define pDMAFLX6_YCOUNT ((uint16_t volatile *)DMAFLX6_YCOUNT)
#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT)
#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define pDMAFLX6_YMODIFY ((uint16_t volatile *)DMAFLX6_YMODIFY)
#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY)
#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define pDMAFLX6_IRQSTAT ((uint16_t volatile *)DMAFLX6_IRQSTAT)
#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT)
#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define pDMAFLX6_PMAP ((uint16_t volatile *)DMAFLX6_PMAP)
#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP)
#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val)
-#define pDMAFLX6_CURXCOUNT ((uint16_t volatile *)DMAFLX6_CURXCOUNT)
#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT)
#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define pDMAFLX6_CURYCOUNT ((uint16_t volatile *)DMAFLX6_CURYCOUNT)
#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT)
#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define pDMAFLX7_DMACNFG ((uint16_t volatile *)DMAFLX7_DMACNFG)
#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG)
#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define pDMAFLX7_XCOUNT ((uint16_t volatile *)DMAFLX7_XCOUNT)
#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT)
#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define pDMAFLX7_XMODIFY ((uint16_t volatile *)DMAFLX7_XMODIFY)
#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY)
#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define pDMAFLX7_YCOUNT ((uint16_t volatile *)DMAFLX7_YCOUNT)
#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT)
#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define pDMAFLX7_YMODIFY ((uint16_t volatile *)DMAFLX7_YMODIFY)
#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY)
#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define pDMAFLX7_IRQSTAT ((uint16_t volatile *)DMAFLX7_IRQSTAT)
#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT)
#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define pDMAFLX7_PMAP ((uint16_t volatile *)DMAFLX7_PMAP)
#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP)
#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val)
-#define pDMAFLX7_CURXCOUNT ((uint16_t volatile *)DMAFLX7_CURXCOUNT)
#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT)
#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define pDMAFLX7_CURYCOUNT ((uint16_t volatile *)DMAFLX7_CURYCOUNT)
#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT)
#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG)
#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER)
#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD)
#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH)
#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG)
#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER)
#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD)
#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH)
#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG)
#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER)
#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD)
#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH)
#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE)
#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE)
#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define pTIMER_STATUS ((uint16_t volatile *)TIMER_STATUS)
#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS)
#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val)
-#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */
#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */
#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
-#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */
#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
-#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */
#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
-#define pUART_THR ((uint16_t volatile *)UART_THR) /* Transmit Holding */
#define bfin_read_UART_THR() bfin_read16(UART_THR)
#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
-#define pUART_DLL ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART_DLL() bfin_read16(UART_DLL)
#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val)
-#define pUART_DLH ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART_DLH() bfin_read16(UART_DLH)
#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val)
-#define pUART_IER ((uint16_t volatile *)UART_IER)
#define bfin_read_UART_IER() bfin_read16(UART_IER)
#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val)
-#define pUART_IIR ((uint16_t volatile *)UART_IIR)
#define bfin_read_UART_IIR() bfin_read16(UART_IIR)
#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val)
-#define pUART_LCR ((uint16_t volatile *)UART_LCR)
#define bfin_read_UART_LCR() bfin_read16(UART_LCR)
#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val)
-#define pUART_MCR ((uint16_t volatile *)UART_MCR)
#define bfin_read_UART_MCR() bfin_read16(UART_MCR)
#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val)
-#define pUART_LSR ((uint16_t volatile *)UART_LSR)
#define bfin_read_UART_LSR() bfin_read16(UART_LSR)
#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val)
-#define pUART_SCR ((uint16_t volatile *)UART_SCR)
#define bfin_read_UART_SCR() bfin_read16(UART_SCR)
#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val)
-#define pUART_RBR ((uint16_t volatile *)UART_RBR) /* Receive Buffer */
#define bfin_read_UART_RBR() bfin_read16(UART_RBR)
#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val)
-#define pUART_GCTL ((uint16_t volatile *)UART_GCTL)
#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL)
#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val)
-#define pSPT0_TX_CONFIG0 ((uint16_t volatile *)SPT0_TX_CONFIG0)
#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0)
#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define pSPT0_TX_CONFIG1 ((uint16_t volatile *)SPT0_TX_CONFIG1)
#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1)
#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define pSPT0_RX_CONFIG0 ((uint16_t volatile *)SPT0_RX_CONFIG0)
#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0)
#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define pSPT0_RX_CONFIG1 ((uint16_t volatile *)SPT0_RX_CONFIG1)
#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1)
#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define pSPT0_TX ((uint32_t volatile *)SPT0_TX)
#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX)
#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val)
-#define pSPT0_RX ((uint32_t volatile *)SPT0_RX)
#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX)
#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val)
-#define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV)
#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV)
#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val)
-#define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV)
#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV)
#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val)
-#define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV)
#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV)
#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val)
-#define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV)
#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV)
#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val)
-#define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT)
#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT)
#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val)
-#define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0)
#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0)
#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val)
-#define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1)
#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1)
#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val)
-#define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2)
#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2)
#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val)
-#define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3)
#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3)
#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val)
-#define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0)
#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0)
#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val)
-#define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1)
#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1)
#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val)
-#define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2)
#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2)
#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val)
-#define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3)
#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3)
#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val)
-#define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1)
#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1)
#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val)
-#define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2)
#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2)
#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val)
-#define pSPT0_CHNL ((uint16_t volatile *)SPT0_CHNL)
#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL)
#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val)
-#define pSPT1_TX_CONFIG0 ((uint16_t volatile *)SPT1_TX_CONFIG0)
#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0)
#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define pSPT1_TX_CONFIG1 ((uint16_t volatile *)SPT1_TX_CONFIG1)
#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1)
#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define pSPT1_RX_CONFIG0 ((uint16_t volatile *)SPT1_RX_CONFIG0)
#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0)
#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define pSPT1_RX_CONFIG1 ((uint16_t volatile *)SPT1_RX_CONFIG1)
#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1)
#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define pSPT1_TX ((uint16_t volatile *)SPT1_TX)
#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX)
#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val)
-#define pSPT1_RX ((uint16_t volatile *)SPT1_RX)
#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX)
#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val)
-#define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV)
#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV)
#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val)
-#define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV)
#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV)
#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val)
-#define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV)
#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV)
#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val)
-#define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV)
#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV)
#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val)
-#define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT)
#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT)
#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val)
-#define pSPT1_MTCS0 ((uint32_t volatile *)SPT1_MTCS0)
#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0)
#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val)
-#define pSPT1_MTCS1 ((uint32_t volatile *)SPT1_MTCS1)
#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1)
#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val)
-#define pSPT1_MTCS2 ((uint32_t volatile *)SPT1_MTCS2)
#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2)
#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val)
-#define pSPT1_MTCS3 ((uint32_t volatile *)SPT1_MTCS3)
#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3)
#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val)
-#define pSPT1_MRCS0 ((uint32_t volatile *)SPT1_MRCS0)
#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0)
#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val)
-#define pSPT1_MRCS1 ((uint32_t volatile *)SPT1_MRCS1)
#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1)
#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val)
-#define pSPT1_MRCS2 ((uint32_t volatile *)SPT1_MRCS2)
#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2)
#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val)
-#define pSPT1_MRCS3 ((uint32_t volatile *)SPT1_MRCS3)
#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3)
#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val)
-#define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1)
#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1)
#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val)
-#define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2)
#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2)
#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val)
-#define pSPT1_CHNL ((uint16_t volatile *)SPT1_CHNL)
#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL)
#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val)
-#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL)
#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS)
#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY)
#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT)
#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME)
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
#define bfin_read_SWRST() bfin_read16(SWRST)
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */
#define bfin_read_SYSCR() bfin_read16(SYSCR)
#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
-#define pCHIPID ((uint32_t volatile *)CHIPID)
#define bfin_read_CHIPID() bfin_read32(CHIPID)
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
-#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */
#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT)
#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val)
-#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */
#define bfin_read_TBUF() bfin_readPTR(TBUF)
#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val)
-#define pPFCTL ((uint32_t volatile *)PFCTL)
#define bfin_read_PFCTL() bfin_read32(PFCTL)
#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val)
-#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0)
#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0)
#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val)
-#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1)
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val)
-#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define pRTC_STAT ((uint32_t volatile *)RTC_STAT)
#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
-#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL)
#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
-#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT)
#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
-#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT)
#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
-#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM)
#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
-#define pRTC_PREN ((uint16_t volatile *)RTC_PREN)
#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
-#define pSPI_CTL ((uint16_t volatile *)SPI_CTL)
#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
-#define pSPI_FLG ((uint16_t volatile *)SPI_FLG)
#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
-#define pSPI_STAT ((uint16_t volatile *)SPI_STAT)
#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
-#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR)
#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
-#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR)
#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
-#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD)
#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
-#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW)
#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
-#define pFIO_FLAG_D ((uint16_t volatile *)FIO_FLAG_D)
#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val)
-#define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C)
#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C)
#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val)
-#define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S)
#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S)
#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val)
-#define pFIO_FLAG_T ((uint16_t volatile *)FIO_FLAG_T)
#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T)
#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val)
-#define pFIO_MASKA_D ((uint16_t volatile *)FIO_MASKA_D)
#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D)
#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val)
-#define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C)
#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C)
#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val)
-#define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S)
#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S)
#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val)
-#define pFIO_MASKA_T ((uint16_t volatile *)FIO_MASKA_T)
#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T)
#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val)
-#define pFIO_MASKB_D ((uint16_t volatile *)FIO_MASKB_D)
#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D)
#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val)
-#define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C)
#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C)
#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val)
-#define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S)
#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S)
#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val)
-#define pFIO_MASKB_T ((uint16_t volatile *)FIO_MASKB_T)
#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val)
-#define pFIO_DIR ((uint16_t volatile *)FIO_DIR)
#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val)
-#define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR)
#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR)
#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val)
-#define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE)
#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE)
#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val)
-#define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH)
#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH)
#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val)
-#define pFIO_INEN ((uint16_t volatile *)FIO_INEN)
#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN)
#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val)
-#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */
#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */
#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */
#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */
#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define pDMA0_NEXT_DESC_PTR ((uint32_t volatile *)DMA0_NEXT_DESC_PTR)
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR)
#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT)
#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY)
#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT)
#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY)
#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define pDMA0_CURR_DESC_PTR ((uint32_t volatile *)DMA0_CURR_DESC_PTR)
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR)
#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS)
#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP)
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT)
#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT)
#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define pDMA1_NEXT_DESC_PTR ((uint32_t volatile *)DMA1_NEXT_DESC_PTR)
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR)
#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT)
#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY)
#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT)
#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY)
#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define pDMA1_CURR_DESC_PTR ((uint32_t volatile *)DMA1_CURR_DESC_PTR)
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR)
#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS)
#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP)
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT)
#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT)
#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define pDMA2_NEXT_DESC_PTR ((uint32_t volatile *)DMA2_NEXT_DESC_PTR)
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR)
#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT)
#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY)
#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT)
#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY)
#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define pDMA2_CURR_DESC_PTR ((uint32_t volatile *)DMA2_CURR_DESC_PTR)
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR)
#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS)
#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP)
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT)
#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT)
#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define pDMA3_NEXT_DESC_PTR ((uint32_t volatile *)DMA3_NEXT_DESC_PTR)
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR)
#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT)
#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY)
#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT)
#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY)
#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define pDMA3_CURR_DESC_PTR ((uint32_t volatile *)DMA3_CURR_DESC_PTR)
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR)
#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS)
#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP)
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT)
#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT)
#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define pDMA4_NEXT_DESC_PTR ((uint32_t volatile *)DMA4_NEXT_DESC_PTR)
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR)
#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT)
#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY)
#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT)
#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY)
#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define pDMA4_CURR_DESC_PTR ((uint32_t volatile *)DMA4_CURR_DESC_PTR)
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR)
#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS)
#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP)
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT)
#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT)
#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define pDMA5_NEXT_DESC_PTR ((uint32_t volatile *)DMA5_NEXT_DESC_PTR)
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR)
#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT)
#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY)
#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT)
#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY)
#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define pDMA5_CURR_DESC_PTR ((uint32_t volatile *)DMA5_CURR_DESC_PTR)
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR)
#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS)
#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP)
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT)
#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT)
#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR)
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR)
#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT)
#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY)
#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT)
#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY)
#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define pDMA6_CURR_DESC_PTR ((uint32_t volatile *)DMA6_CURR_DESC_PTR)
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR)
#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS)
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP)
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT)
#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT)
#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define pDMA7_NEXT_DESC_PTR ((uint32_t volatile *)DMA7_NEXT_DESC_PTR)
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR)
#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT)
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY)
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT)
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY)
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define pDMA7_CURR_DESC_PTR ((uint32_t volatile *)DMA7_CURR_DESC_PTR)
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR)
#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS)
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP)
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT)
#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT)
#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define pMDMA_D0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR)
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR)
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG)
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT)
#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY)
#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT)
#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY)
#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define pMDMA_D0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR)
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR)
#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS)
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP)
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT)
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT)
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define pMDMA_S0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR)
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR)
#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG)
#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT)
#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY)
#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT)
#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY)
#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define pMDMA_S0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR)
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR)
#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS)
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP)
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT)
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT)
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define pMDMA_D1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR)
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR)
#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT)
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY)
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT)
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY)
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define pMDMA_D1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR)
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR)
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS)
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP)
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT)
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT)
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define pMDMA_S1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR)
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR)
#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG)
#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT)
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY)
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT)
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY)
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define pMDMA_S1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR)
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR)
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS)
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP)
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT)
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT)
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL)
#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0)
#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1)
#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL)
#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
-#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL)
#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
-#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC)
#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
-#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT)
#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
-#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER)
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)