Blackfin: unify core MMRs

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

2 files changed, 0 insertions, 258 deletions

diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
index 482a750..6f21c31 100644
--- a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h
@@ -10,160 +10,6 @@
 
 #include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
 
-#define bfin_read_SRAM_BASE_ADDR()     bfin_read32(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0()        bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_write32(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1()        bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_write32(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2()        bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_write32(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3()        bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_write32(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4()        bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_write32(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5()        bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_write32(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6()        bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_write32(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7()        bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_write32(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8()        bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_write32(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9()        bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_write32(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10()       bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_write32(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11()       bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_write32(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12()       bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_write32(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13()       bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_write32(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14()       bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_write32(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15()       bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_write32(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0()        bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_write32(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1()        bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_write32(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2()        bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_write32(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3()        bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_write32(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4()        bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_write32(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5()        bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_write32(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6()        bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_write32(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7()        bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_write32(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8()        bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_write32(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9()        bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_write32(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10()       bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_write32(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11()       bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_write32(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12()       bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_write32(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13()       bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_write32(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14()       bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_write32(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15()       bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_write32(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
 #define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
 #define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
 #define bfin_read_SICA_SYSCR()         bfin_read16(SICA_SYSCR)
@@ -252,24 +98,6 @@
 #define bfin_write_PPI1_COUNT(val)     bfin_write16(PPI1_COUNT, val)
 #define bfin_read_PPI1_FRAME()         bfin_read16(PPI1_FRAME)
 #define bfin_write_PPI1_FRAME(val)     bfin_write16(PPI1_FRAME, val)
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF()               bfin_read32(TBUF)
-#define bfin_write_TBUF(val)           bfin_write32(TBUF, val)
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
-#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
-#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
-#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
-#define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
-#define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
 #define bfin_read_UART_THR()           bfin_read16(UART_THR)
 #define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
 #define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
index 8534962..1b17b51 100644
--- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
@@ -10,83 +10,6 @@
 
 #include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
 
-#define SRAM_BASE_ADDR                 0xFFE00000
-#define DMEM_CONTROL                   0xFFE00004
-#define DCPLB_STATUS                   0xFFE00008
-#define DCPLB_FAULT_ADDR               0xFFE0000C
-#define DCPLB_ADDR0                    0xFFE00100
-#define DCPLB_ADDR1                    0xFFE00104
-#define DCPLB_ADDR2                    0xFFE00108
-#define DCPLB_ADDR3                    0xFFE0010C
-#define DCPLB_ADDR4                    0xFFE00110
-#define DCPLB_ADDR5                    0xFFE00114
-#define DCPLB_ADDR6                    0xFFE00118
-#define DCPLB_ADDR7                    0xFFE0011C
-#define DCPLB_ADDR8                    0xFFE00120
-#define DCPLB_ADDR9                    0xFFE00124
-#define DCPLB_ADDR10                   0xFFE00128
-#define DCPLB_ADDR11                   0xFFE0012C
-#define DCPLB_ADDR12                   0xFFE00130
-#define DCPLB_ADDR13                   0xFFE00134
-#define DCPLB_ADDR14                   0xFFE00138
-#define DCPLB_ADDR15                   0xFFE0013C
-#define DCPLB_DATA0                    0xFFE00200
-#define DCPLB_DATA1                    0xFFE00204
-#define DCPLB_DATA2                    0xFFE00208
-#define DCPLB_DATA3                    0xFFE0020C
-#define DCPLB_DATA4                    0xFFE00210
-#define DCPLB_DATA5                    0xFFE00214
-#define DCPLB_DATA6                    0xFFE00218
-#define DCPLB_DATA7                    0xFFE0021C
-#define DCPLB_DATA8                    0xFFE00220
-#define DCPLB_DATA9                    0xFFE00224
-#define DCPLB_DATA10                   0xFFE00228
-#define DCPLB_DATA11                   0xFFE0022C
-#define DCPLB_DATA12                   0xFFE00230
-#define DCPLB_DATA13                   0xFFE00234
-#define DCPLB_DATA14                   0xFFE00238
-#define DCPLB_DATA15                   0xFFE0023C
-#define DTEST_COMMAND                  0xFFE00300
-#define DTEST_DATA0                    0xFFE00400
-#define DTEST_DATA1                    0xFFE00404
-#define IMEM_CONTROL                   0xFFE01004
-#define ICPLB_STATUS                   0xFFE01008
-#define ICPLB_FAULT_ADDR               0xFFE0100C
-#define ICPLB_ADDR0                    0xFFE01100
-#define ICPLB_ADDR1                    0xFFE01104
-#define ICPLB_ADDR2                    0xFFE01108
-#define ICPLB_ADDR3                    0xFFE0110C
-#define ICPLB_ADDR4                    0xFFE01110
-#define ICPLB_ADDR5                    0xFFE01114
-#define ICPLB_ADDR6                    0xFFE01118
-#define ICPLB_ADDR7                    0xFFE0111C
-#define ICPLB_ADDR8                    0xFFE01120
-#define ICPLB_ADDR9                    0xFFE01124
-#define ICPLB_ADDR10                   0xFFE01128
-#define ICPLB_ADDR11                   0xFFE0112C
-#define ICPLB_ADDR12                   0xFFE01130
-#define ICPLB_ADDR13                   0xFFE01134
-#define ICPLB_ADDR14                   0xFFE01138
-#define ICPLB_ADDR15                   0xFFE0113C
-#define ICPLB_DATA0                    0xFFE01200
-#define ICPLB_DATA1                    0xFFE01204
-#define ICPLB_DATA2                    0xFFE01208
-#define ICPLB_DATA3                    0xFFE0120C
-#define ICPLB_DATA4                    0xFFE01210
-#define ICPLB_DATA5                    0xFFE01214
-#define ICPLB_DATA6                    0xFFE01218
-#define ICPLB_DATA7                    0xFFE0121C
-#define ICPLB_DATA8                    0xFFE01220
-#define ICPLB_DATA9                    0xFFE01224
-#define ICPLB_DATA10                   0xFFE01228
-#define ICPLB_DATA11                   0xFFE0122C
-#define ICPLB_DATA12                   0xFFE01230
-#define ICPLB_DATA13                   0xFFE01234
-#define ICPLB_DATA14                   0xFFE01238
-#define ICPLB_DATA15                   0xFFE0123C
-#define ITEST_COMMAND                  0xFFE01300
-#define ITEST_DATA0                    0xFFE01400
-#define ITEST_DATA1                    0xFFE01404
 #define SICA_SWRST                     0xFFC00100
 #define SICA_SYSCR                     0xFFC00104
 #define SICA_RVECT                     0xFFC00108
@@ -131,15 +54,6 @@
 #define PPI1_DELAY                     0xFFC0130C
 #define PPI1_COUNT                     0xFFC01308
 #define PPI1_FRAME                     0xFFC01310
-#define TBUFCTL                        0xFFE06000
-#define TBUFSTAT                       0xFFE06004
-#define TBUF                           0xFFE06100
-#define PFCTL                          0xFFE08000
-#define PFCNTR0                        0xFFE08100
-#define PFCNTR1                        0xFFE08104
-#define SRAM_BASE_ADDR_CORE_A          0xFFE00000
-#define SRAM_BASE_ADDR_CORE_B          0xFFE00000
-#define EVT_OVERRIDE                   0xFFE02100
 #define UART_THR                       0xFFC00400
 #define UART_RBR                       0xFFC00400
 #define UART_DLL                       0xFFC00400