Blackfin: unify core MMRs

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

8 files changed, 0 insertions, 927 deletions

diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
index 6bca938..5381bf0 100644
--- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h
@@ -986,18 +986,6 @@
 #define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
 #define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
 #define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF()               bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
 #define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
 #define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
 #define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
index 0b38480..7b97aee 100644
--- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h
@@ -497,12 +497,6 @@
 #define NFC_CMD                        0xFFC03744 /* NAND Command Register */
 #define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
 #define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
-#define TBUFCTL                        0xFFE06000 /* Trace Buffer Control Register */
-#define TBUFSTAT                       0xFFE06004 /* Trace Buffer Status Register */
-#define TBUF                           0xFFE06100 /* Trace Buffer */
-#define PFCTL                          0xFFE08000
-#define PFCNTR0                        0xFFE08100
-#define PFCNTR1                        0xFFE08104
 #define DMA_TC_CNT                     0xFFC00B0C
 #define DMA_TC_PER                     0xFFC00B10
 
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
index da90346..9ce41b1 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
@@ -26,207 +26,5 @@
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 
 #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
index bc05029..a6b0787 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h
@@ -18,106 +18,5 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 
 #endif /* __BFIN_DEF_ADSP_BF522_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
index 93e1d5a..25612bf 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
@@ -26,208 +26,6 @@
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 #define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
 #define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
 #define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
index bd6aa8f..0a0056a 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h
@@ -18,107 +18,6 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 #define USB_FADDR                      0xFFC03800 /* Function address register */
 #define USB_POWER                      0xFFC03804 /* Power management register */
 #define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
index dfc4fcb..aa320ac 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
@@ -26,208 +26,6 @@
 #define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
 #define bfin_read_SYSCR()              bfin_read16(SYSCR)
 #define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)
-#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)
-#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
-#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
-#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
-#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)
-#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)
-#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)
-#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)
-#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)
-#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)
-#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)
-#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)
-#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)
-#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)
-#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)
-#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)
-#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)
-#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)
-#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)
-#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)
-#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
-#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
-#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
-#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
-#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
-#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
-#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
-#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
-#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
-#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
-#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
-#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
-#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
-#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
-#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
-#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
-#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
-#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
-#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
-#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
-#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
-#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)
-#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)
-#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)
-#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)
-#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)
-#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)
-#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)
-#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)
-#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)
-#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)
-#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)
-#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)
-#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)
-#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)
-#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)
-#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)
-#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)
-#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
-#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
-#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
-#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
-#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
-#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
-#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
-#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
-#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
-#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
-#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
-#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
-#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
-#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
-#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
-#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
-#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
-#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
-#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define bfin_read_EVT0()               bfin_readPTR(EVT0)
-#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)
-#define bfin_read_EVT1()               bfin_readPTR(EVT1)
-#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)
-#define bfin_read_EVT2()               bfin_readPTR(EVT2)
-#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)
-#define bfin_read_EVT3()               bfin_readPTR(EVT3)
-#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)
-#define bfin_read_EVT4()               bfin_readPTR(EVT4)
-#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)
-#define bfin_read_EVT5()               bfin_readPTR(EVT5)
-#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)
-#define bfin_read_EVT6()               bfin_readPTR(EVT6)
-#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)
-#define bfin_read_EVT7()               bfin_readPTR(EVT7)
-#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)
-#define bfin_read_EVT8()               bfin_readPTR(EVT8)
-#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)
-#define bfin_read_EVT9()               bfin_readPTR(EVT9)
-#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)
-#define bfin_read_EVT10()              bfin_readPTR(EVT10)
-#define bfin_write_EVT10(val)          bfin_writePTR(EVT10, val)
-#define bfin_read_EVT11()              bfin_readPTR(EVT11)
-#define bfin_write_EVT11(val)          bfin_writePTR(EVT11, val)
-#define bfin_read_EVT12()              bfin_readPTR(EVT12)
-#define bfin_write_EVT12(val)          bfin_writePTR(EVT12, val)
-#define bfin_read_EVT13()              bfin_readPTR(EVT13)
-#define bfin_write_EVT13(val)          bfin_writePTR(EVT13, val)
-#define bfin_read_EVT14()              bfin_readPTR(EVT14)
-#define bfin_write_EVT14(val)          bfin_writePTR(EVT14, val)
-#define bfin_read_EVT15()              bfin_readPTR(EVT15)
-#define bfin_write_EVT15(val)          bfin_writePTR(EVT15, val)
-#define bfin_read_ILAT()               bfin_read32(ILAT)
-#define bfin_write_ILAT(val)           bfin_write32(ILAT, val)
-#define bfin_read_IMASK()              bfin_read32(IMASK)
-#define bfin_write_IMASK(val)          bfin_write32(IMASK, val)
-#define bfin_read_IPEND()              bfin_read32(IPEND)
-#define bfin_write_IPEND(val)          bfin_write32(IPEND, val)
-#define bfin_read_IPRIO()              bfin_read32(IPRIO)
-#define bfin_write_IPRIO(val)          bfin_write32(IPRIO, val)
-#define bfin_read_TCNTL()              bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
-#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
-#define bfin_read_TSCALE()             bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
-#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
 #define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
 #define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
 #define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
index 2644abf..935d11e 100644
--- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h
+++ b/arch/blackfin/include/asm/mach-bf527/BF526_def.h
@@ -18,107 +18,6 @@
 #define CHIPID                         0xFFC00014
 #define SWRST                          0xFFC00100 /* Software Reset Register */
 #define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SRAM_BASE_ADDR                 0xFFE00000 /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL                   0xFFE00004 /* Data memory control */
-#define DCPLB_STATUS                   0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR               0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0                    0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1                    0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2                    0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3                    0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4                    0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5                    0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6                    0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7                    0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8                    0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9                    0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10                   0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11                   0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12                   0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13                   0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14                   0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15                   0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0                    0xFFE00200 /* Data Cache 0 Status */
-#define DCPLB_DATA1                    0xFFE00204 /* Data Cache 1 Status */
-#define DCPLB_DATA2                    0xFFE00208 /* Data Cache 2 Status */
-#define DCPLB_DATA3                    0xFFE0020C /* Data Cache 3 Status */
-#define DCPLB_DATA4                    0xFFE00210 /* Data Cache 4 Status */
-#define DCPLB_DATA5                    0xFFE00214 /* Data Cache 5 Status */
-#define DCPLB_DATA6                    0xFFE00218 /* Data Cache 6 Status */
-#define DCPLB_DATA7                    0xFFE0021C /* Data Cache 7 Status */
-#define DCPLB_DATA8                    0xFFE00220 /* Data Cache 8 Status */
-#define DCPLB_DATA9                    0xFFE00224 /* Data Cache 9 Status */
-#define DCPLB_DATA10                   0xFFE00228 /* Data Cache 10 Status */
-#define DCPLB_DATA11                   0xFFE0022C /* Data Cache 11 Status */
-#define DCPLB_DATA12                   0xFFE00230 /* Data Cache 12 Status */
-#define DCPLB_DATA13                   0xFFE00234 /* Data Cache 13 Status */
-#define DCPLB_DATA14                   0xFFE00238 /* Data Cache 14 Status */
-#define DCPLB_DATA15                   0xFFE0023C /* Data Cache 15 Status */
-#define DTEST_COMMAND                  0xFFE00300 /* Data Test Command Register */
-#define DTEST_DATA0                    0xFFE00400 /* Data Test Data Register */
-#define DTEST_DATA1                    0xFFE00404 /* Data Test Data Register */
-#define IMEM_CONTROL                   0xFFE01004 /* Instruction Memory Control */
-#define ICPLB_STATUS                   0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */
-#define ICPLB_FAULT_ADDR               0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */
-#define ICPLB_ADDR0                    0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1                    0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2                    0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3                    0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4                    0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5                    0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6                    0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7                    0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8                    0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9                    0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10                   0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11                   0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12                   0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13                   0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14                   0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15                   0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0                    0xFFE01200 /* Instruction Cache 0 Status */
-#define ICPLB_DATA1                    0xFFE01204 /* Instruction Cache 1 Status */
-#define ICPLB_DATA2                    0xFFE01208 /* Instruction Cache 2 Status */
-#define ICPLB_DATA3                    0xFFE0120C /* Instruction Cache 3 Status */
-#define ICPLB_DATA4                    0xFFE01210 /* Instruction Cache 4 Status */
-#define ICPLB_DATA5                    0xFFE01214 /* Instruction Cache 5 Status */
-#define ICPLB_DATA6                    0xFFE01218 /* Instruction Cache 6 Status */
-#define ICPLB_DATA7                    0xFFE0121C /* Instruction Cache 7 Status */
-#define ICPLB_DATA8                    0xFFE01220 /* Instruction Cache 8 Status */
-#define ICPLB_DATA9                    0xFFE01224 /* Instruction Cache 9 Status */
-#define ICPLB_DATA10                   0xFFE01228 /* Instruction Cache 10 Status */
-#define ICPLB_DATA11                   0xFFE0122C /* Instruction Cache 11 Status */
-#define ICPLB_DATA12                   0xFFE01230 /* Instruction Cache 12 Status */
-#define ICPLB_DATA13                   0xFFE01234 /* Instruction Cache 13 Status */
-#define ICPLB_DATA14                   0xFFE01238 /* Instruction Cache 14 Status */
-#define ICPLB_DATA15                   0xFFE0123C /* Instruction Cache 15 Status */
-#define ITEST_COMMAND                  0xFFE01300 /* Instruction Test Command Register */
-#define ITEST_DATA0                    0xFFE01400 /* Instruction Test Data Register */
-#define ITEST_DATA1                    0xFFE01404 /* Instruction Test Data Register */
-#define EVT0                           0xFFE02000 /* Event Vector 0 ESR Address */
-#define EVT1                           0xFFE02004 /* Event Vector 1 ESR Address */
-#define EVT2                           0xFFE02008 /* Event Vector 2 ESR Address */
-#define EVT3                           0xFFE0200C /* Event Vector 3 ESR Address */
-#define EVT4                           0xFFE02010 /* Event Vector 4 ESR Address */
-#define EVT5                           0xFFE02014 /* Event Vector 5 ESR Address */
-#define EVT6                           0xFFE02018 /* Event Vector 6 ESR Address */
-#define EVT7                           0xFFE0201C /* Event Vector 7 ESR Address */
-#define EVT8                           0xFFE02020 /* Event Vector 8 ESR Address */
-#define EVT9                           0xFFE02024 /* Event Vector 9 ESR Address */
-#define EVT10                          0xFFE02028 /* Event Vector 10 ESR Address */
-#define EVT11                          0xFFE0202C /* Event Vector 11 ESR Address */
-#define EVT12                          0xFFE02030 /* Event Vector 12 ESR Address */
-#define EVT13                          0xFFE02034 /* Event Vector 13 ESR Address */
-#define EVT14                          0xFFE02038 /* Event Vector 14 ESR Address */
-#define EVT15                          0xFFE0203C /* Event Vector 15 ESR Address */
-#define ILAT                           0xFFE0210C /* Interrupt Latch Register */
-#define IMASK                          0xFFE02104 /* Interrupt Mask Register */
-#define IPEND                          0xFFE02108 /* Interrupt Pending Register */
-#define IPRIO                          0xFFE02110 /* Interrupt Priority Register */
-#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
-#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
-#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
-#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
 #define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
 #define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
 #define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */