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| author | Sonic Zhang <sonic.zhang@analog.com> | 2012-08-16 11:56:14 +0800 |
|---|---|---|
| committer | sonic <sonic@sonic-linuxvm.(none)> | 2013-03-04 13:42:06 +0800 |
| commit | a2979dcdbeb39a01dc888090d2c736c2ad3f548d (patch) | |
| tree | a682537c30714af45a998e2c3cedbe495de05e52 /arch/blackfin/cpu/reset.c | |
| parent | 3ead92c571e7e17ca1c525c0fcd40e58901c5655 (diff) | |
| download | u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.zip u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.tar.gz u-boot-imx-a2979dcdbeb39a01dc888090d2c736c2ad3f548d.tar.bz2 | |
blackfin: bf60x: Port blackfin core architecture code to boot on bf60x.
Set up clocks, DDR controller, Nor flash controller, reboot,
serial port. Add new SPI boot modes.
Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
Diffstat (limited to 'arch/blackfin/cpu/reset.c')
| -rw-r--r-- | arch/blackfin/cpu/reset.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c index ff39035..b6718d3 100644 --- a/arch/blackfin/cpu/reset.c +++ b/arch/blackfin/cpu/reset.c @@ -23,6 +23,7 @@ __attribute__ ((__l1_text__, __noreturn__)) static void bfin_reset(void) { +#ifdef SWRST /* Wait for completion of "system" events such as cache line * line fills so that we avoid infinite stalls later on as * much as possible. This code is in L1, so it won't trigger @@ -66,10 +67,15 @@ static void bfin_reset(void) : "a" (15 * 1) : "LC1", "LB1", "LT1" ); +#endif while (1) +#if defined(__ADSPBF60x__) + bfin_write_RCU0_CTL(0x1); +#else /* Issue core reset */ asm("raise 1"); +#endif } /* We need to trampoline ourselves up into L1 since our linker |