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| author | Mike Frysinger <vapier@gentoo.org> | 2011-05-30 13:47:38 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-07-12 02:17:46 -0400 |
| commit | 4150cec3353b7a6d7a3ea71b2d3c62deafff353d (patch) | |
| tree | 9880d8bcdcf870b8256838f20762620390a834e1 /arch/blackfin/cpu/initcode.c | |
| parent | 27575587ba923f35356fa49a7907d88586ae1bd3 (diff) | |
| download | u-boot-imx-4150cec3353b7a6d7a3ea71b2d3c62deafff353d.zip u-boot-imx-4150cec3353b7a6d7a3ea71b2d3c62deafff353d.tar.gz u-boot-imx-4150cec3353b7a6d7a3ea71b2d3c62deafff353d.tar.bz2 | |
Blackfin: split out async setup
We really only need to tweak the async banks in the initcode if the
processor is booting out of it, otherwise we can wait until later
on in the CPU booting setup.
This also makes testing in the sim and early bring up over JTAG work
much smoother when the initcode gets bypassed.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/cpu/initcode.c')
| -rw-r--r-- | arch/blackfin/cpu/initcode.c | 47 |
1 files changed, 3 insertions, 44 deletions
diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 61dc5ab..917b7f9 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -4,7 +4,7 @@ * cannot make any function calls as it may be executed all by itself by * the Blackfin's bootrom in LDR format. * - * Copyright (c) 2004-2008 Analog Devices Inc. + * Copyright (c) 2004-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -107,6 +107,8 @@ static inline void serial_putc(char c) continue; } +#include "initcode.h" + __attribute__((always_inline)) static inline void program_nmi_handler(void) { @@ -172,21 +174,6 @@ program_nmi_handler(void) # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) #endif -#ifndef CONFIG_EBIU_RSTCTL_VAL -# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ -#endif -#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) -# error invalid EBIU_RSTCTL value: must not set reserved bits -#endif - -#ifndef CONFIG_EBIU_MBSCTL_VAL -# define CONFIG_EBIU_MBSCTL_VAL 0 -#endif - -#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) -# error invalid EBIU_DDRQUE value: must not set reserved bits -#endif - /* Make sure our voltage value is sane so we don't blow up! */ #ifndef CONFIG_VR_CTL_VAL # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) @@ -642,34 +629,6 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) serial_putc('e'); } -__attribute__((always_inline)) static inline void -program_async_controller(ADI_BOOT_DATA *bs) -{ - serial_putc('a'); - - /* Program the async banks controller. */ - bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); - bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); - bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); - - serial_putc('b'); - - /* Not all parts have these additional MMRs. */ -#ifdef EBIU_MBSCTL - bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); -#endif -#ifdef EBIU_MODE -# ifdef CONFIG_EBIU_MODE_VAL - bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); -# endif -# ifdef CONFIG_EBIU_FCTL_VAL - bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); -# endif -#endif - - serial_putc('c'); -} - BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bs) { |