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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-05 13:21:07 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-02-14 17:07:46 +0900 |
| commit | f775c09d00cc355a87cf4ba935eff86eacd0c961 (patch) | |
| tree | 03b12c19637a6bbc0f808e77a3806402db3f24b9 /arch/arm | |
| parent | c9552895a8055fed424d6817008fccd37dbfd01c (diff) | |
| download | u-boot-imx-f775c09d00cc355a87cf4ba935eff86eacd0c961.zip u-boot-imx-f775c09d00cc355a87cf4ba935eff86eacd0c961.tar.gz u-boot-imx-f775c09d00cc355a87cf4ba935eff86eacd0c961.tar.bz2 | |
ARM: uniphier: adjust DDR clock delay line for ProXstream2
It turned out that DDR channel 2 was not working on ProXstream2
Vodka board. Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-uniphier/dram/umc-proxstream2.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c index bb7acde..6e7fa88 100644 --- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c +++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c @@ -18,6 +18,8 @@ #include "ddrmphy-regs.h" #include "umc-regs.h" +#define CH_NR 3 + enum dram_freq { FREQ_1866M, FREQ_2133M, @@ -43,6 +45,9 @@ static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89}; static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125}; static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8}; +/* dependent on package and board design */ +static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009}; + static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722}; /* * The ch2 is a different generation UMC core. @@ -150,7 +155,8 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width) return dgsl_max; } -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width, + int ch) { u32 tmp; void __iomem *zq_base, *dx_base; @@ -178,6 +184,8 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width) writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3); writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4); + writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0); + writel(0x55555555, phy_base + DMPHY_ACIOCR1); writel(0x00000000, phy_base + DMPHY_ACIOCR2); writel(0x55555555, phy_base + DMPHY_ACIOCR3); @@ -528,7 +536,7 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch, writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, umc_dc_base + UMC_DIOCTLA); - ddrphy_init(phy_base, freq, width); + ddrphy_init(phy_base, freq, width, ch); ret = ddrphy_impedance_calibration(phy_base); if (ret) |