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| author | Vishnu Patekar <vishnupatekar0510@gmail.com> | 2016-01-12 01:20:58 +0800 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2016-01-26 16:20:05 +0100 |
| commit | f5fd8caf7f0e5e0c6c09eb620fc4f7564290f27b (patch) | |
| tree | b4560e3d9ac0d993d98950b60f2735f1df4d396f /arch/arm | |
| parent | 627b380f62802d06a9d47ec5407ef1cf7a751275 (diff) | |
| download | u-boot-imx-f5fd8caf7f0e5e0c6c09eb620fc4f7564290f27b.zip u-boot-imx-f5fd8caf7f0e5e0c6c09eb620fc4f7564290f27b.tar.gz u-boot-imx-f5fd8caf7f0e5e0c6c09eb620fc4f7564290f27b.tar.bz2 | |
sunxi: Groundwork to support new dram type for A83T
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.
This adds groundwork to support for new DRAM type for A83T.
Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 11 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 4 |
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c index 75e9746..35b6c5e 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c @@ -25,6 +25,7 @@ struct dram_para { u8 rank; u8 rows; u8 bus_width; + u8 dram_type; u16 page_size; }; @@ -34,7 +35,7 @@ static void mctl_set_cr(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | - MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 | + MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | (para->seq ? MCTL_CR_SEQUENCE : 0) | ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | @@ -86,6 +87,7 @@ static void auto_set_timing_para(struct dram_para *para) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + u32 reg_val; u8 tccd = 2; @@ -393,6 +395,13 @@ unsigned long sunxi_dram_init(void) .page_size = 2048, }; +#if defined(CONFIG_MACH_SUN8I_A83T) +#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7) + para.dram_type = CONFIG_DRAM_TYPE; +#else +#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) +#endif +#endif setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8); writel(0, (SUNXI_PRCM_BASE + 0x1e8)); diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h index 2891b71..05b6a89 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h @@ -186,7 +186,7 @@ struct sunxi_mctl_ctl_reg { #define MCTL_CR_BUSW8 (0 << 12) #define MCTL_CR_BUSW16 (1 << 12) #define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) +#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) #define MCTL_CR_CHANNEL_MASK (1 << 19) #define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) #define MCTL_CR_UNKNOWN (0x4 << 20) @@ -198,4 +198,6 @@ struct sunxi_mctl_ctl_reg { #define MCTL_MR2 0x18 /* CWL=8 */ #define MCTL_MR3 0x0 +#define DRAM_TYPE_DDR3 3 +#define DRAM_TYPE_LPDDR3 7 #endif /* _SUNXI_DRAM_SUN8I_A83T_H */ |