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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-06-12 14:42:04 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-24 08:33:08 -0700 |
| commit | f3acaf438de74a0b278abc71fb2aca7e7aa86ffa (patch) | |
| tree | 291b9e1bbd24d084e95938ea110d2543f3bc5d74 /arch/arm | |
| parent | b66a5c03a0870db3045be2967b85684b1887ca18 (diff) | |
| download | u-boot-imx-f3acaf438de74a0b278abc71fb2aca7e7aa86ffa.zip u-boot-imx-f3acaf438de74a0b278abc71fb2aca7e7aa86ffa.tar.gz u-boot-imx-f3acaf438de74a0b278abc71fb2aca7e7aa86ffa.tar.bz2 | |
armv8/fsl_lsch2: Correct the cores frequency initialization
The register CLKCNCSR controls the frequency of all cores in the same
cluster.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 3a77b21..d0dc58d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -11,6 +11,7 @@ #include <asm/arch/clock.h> #include <asm/arch/soc.h> #include <fsl_ifc.h> +#include "cpu.h" DECLARE_GLOBAL_DATA_PTR; @@ -47,7 +48,7 @@ void get_sys_info(struct sys_info *sys_info) [5] = 2, /* CC2 PPL / 2 */ }; - uint i; + uint i, cluster; uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -80,8 +81,9 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } - for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) { - u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) + for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) { + cluster = fsl_qoriq_core_to_cluster(cpu); + u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) & 0xf; u32 cplx_pll = core_cplx_pll[c_pll_sel]; |