diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-07-22 20:20:11 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-07-24 00:44:55 +0900 |
| commit | 29d63a59eaf1c9f3b37e249cda2a97e5e4f183f8 (patch) | |
| tree | 33a6175548430ad8e3b75838d131c58867a24fbe /arch/arm | |
| parent | be44a4679feed5a416cdce9b06514473ff82ce95 (diff) | |
| download | u-boot-imx-29d63a59eaf1c9f3b37e249cda2a97e5e4f183f8.zip u-boot-imx-29d63a59eaf1c9f3b37e249cda2a97e5e4f183f8.tar.gz u-boot-imx-29d63a59eaf1c9f3b37e249cda2a97e5e4f183f8.tar.bz2 | |
ARM: uniphier: add clock/reset settings for xHCI of ProXstream2
Deassert resets and enable clock signals of xHCI blocks if the
corresponding CONFIG is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-uniphier/clk/clk-pxs2.c | 7 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/sc-regs.h | 8 |
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 76bf856..0d92405 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/bitops.h> #include <linux/io.h> #include "../init.h" @@ -32,12 +33,16 @@ void uniphier_pxs2_clk_init(void) tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); readl(SC_RSTCTRL2); /* dummy read */ + + tmp = readl(SC_RSTCTRL6); + tmp |= 0x37; + writel(tmp, SC_RSTCTRL6); #endif /* provide clocks */ tmp = readl(SC_CLKCTRL); #ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif #ifdef CONFIG_UNIPHIER_ETH diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index a095589..ad58e10 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -1,7 +1,9 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -68,6 +70,10 @@ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ +#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) + +#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) + #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ |