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| author | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2016-06-03 18:41:26 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:12:49 -0700 |
| commit | 1e49a2318ad22ad842bf4c768398f0f5f9872dc0 (patch) | |
| tree | e216765d5b41023f78d35ae353f5e6f9532e3f5f /arch/arm | |
| parent | 3e06ba8f25521cb385c2fe9d2b312244f788a02a (diff) | |
| download | u-boot-imx-1e49a2318ad22ad842bf4c768398f0f5f9872dc0.zip u-boot-imx-1e49a2318ad22ad842bf4c768398f0f5f9872dc0.tar.gz u-boot-imx-1e49a2318ad22ad842bf4c768398f0f5f9872dc0.tar.bz2 | |
armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 04831ca..d743ffe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -94,11 +94,13 @@ ENTRY(lowlevel_init) bl ccn504_set_qos #endif +#ifdef SMMU_BASE /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */ str w0, [x1, #0x10] +#endif /* Initialize GIC Secure Bank Status */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) |