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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2016-01-06 11:26:51 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-01-25 08:24:14 -0800 |
| commit | 0d3972cfcd6dff18d110d2ee01ad99e3623bfd45 (patch) | |
| tree | cf44538dad352ebcedef94d99a03c432f6d736e8 /arch/arm | |
| parent | 12f229ea8f6c8e20f8fd07906eafc853c4c354a9 (diff) | |
| download | u-boot-imx-0d3972cfcd6dff18d110d2ee01ad99e3623bfd45.zip u-boot-imx-0d3972cfcd6dff18d110d2ee01ad99e3623bfd45.tar.gz u-boot-imx-0d3972cfcd6dff18d110d2ee01ad99e3623bfd45.tar.bz2 | |
fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.
Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..83a207c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 |