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| author | Yao Yuan <yao.yuan@freescale.com> | 2015-12-05 14:59:14 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-15 08:57:32 +0800 |
| commit | 000f4e7686f4291fbd74d8920b586caf10f9241f (patch) | |
| tree | 16b7204a1a7d5cc6ffb0383a88c627243e5bc46f /arch/arm | |
| parent | 6c4a1eba3fcc013f7d21cdb88098bdd3e7afa75b (diff) | |
| download | u-boot-imx-000f4e7686f4291fbd74d8920b586caf10f9241f.zip u-boot-imx-000f4e7686f4291fbd74d8920b586caf10f9241f.tar.gz u-boot-imx-000f4e7686f4291fbd74d8920b586caf10f9241f.tar.bz2 | |
move erratum a008336 and a008514 to soc specific file
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 8896b70..a0de4be 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,41 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * This erratum requires setting a value to eddrtqcr1 to + * optimal the DDR performance. + */ +static void erratum_a008336(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b30002); +#endif +#endif +} + +/* + * This erratum requires a register write before being Memory + * controller 3 being enabled. + */ +static void erratum_a008514(void) +{ + u32 *eddrtqcr1; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR + eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; + out_le32(eddrtqcr1, 0x63b20002); +#endif +#endif +} #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val" @@ -118,6 +153,8 @@ void fsl_lsch3_early_init_f(void) erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); + erratum_a008514(); + erratum_a008336(); } #elif defined(CONFIG_LS1043A) |