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authorCooper Jr., Franklin <fcooper@ti.com>2014-06-27 13:31:15 -0500
committerTom Rini <trini@ti.com>2014-07-07 19:42:34 -0400
commit8038b497e742af2845523ed09b560bfc8cb42089 (patch)
treebaafb8646191200cd64ad7e49faabd77b7d6fe58 /arch/arm
parent2c95211167091e543e20f4f457d3d1f1f660a6d4 (diff)
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am43xx: Tune the system to avoid DSS underflows
* This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c12
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h23
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware_am43xx.h3
-rw-r--r--arch/arm/include/asm/emif.h15
4 files changed, 49 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index bbe9d1a..fc66872 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -94,6 +94,18 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
writel(regs->emif_rd_wr_exec_thresh,
&emif_reg[nr]->emif_rd_wr_exec_thresh);
+ /*
+ * for most SOCs these registers won't need to be changed so only
+ * write to these registers if someone explicitly has set the
+ * register's value.
+ */
+ if(regs->emif_cos_config) {
+ writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+ writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+ writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+ writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+ }
+
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index aa10fab..8dd69b3 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -489,6 +489,12 @@ struct ctrl_stat {
#define OMAP_GPIO_SETDATAOUT 0x0194
/* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
+
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
unsigned int resv1[7];
@@ -502,10 +508,25 @@ struct ctrl_dev {
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
- unsigned int resv5[106];
+ unsigned int resv5[7];
+ unsigned int mreqprio_0; /* offset 0x70 */
+ unsigned int mreqprio_1; /* offset 0x74 */
+ unsigned int resv6[97];
unsigned int efuse_sma; /* offset 0x1FC */
};
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+ u32 padding0[2];
+ u32 modena_init0_bw_fractional;
+ u32 modena_init0_bw_integer;
+ u32 modena_init0_watermark_0;
+};
+
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
index 15399dc..b470319 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -13,6 +13,9 @@
/* Module base addresses */
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER 0x44005200
+
/* UART Base Address */
#define UART0_BASE 0x44E09000
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 45668ca..b8d6bdc 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -642,11 +642,16 @@ struct emif_reg_struct {
u32 emif_ddr_phy_ctrl_1;
u32 emif_ddr_phy_ctrl_1_shdw;
u32 emif_ddr_phy_ctrl_2;
- u32 padding7[12];
+ u32 padding7[4];
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 padding8[5];
u32 emif_rd_wr_exec_thresh;
- u32 padding8[7];
+ u32 emif_cos_config;
+ u32 padding9[6];
u32 emif_ddr_phy_status[21];
- u32 padding9[27];
+ u32 padding10[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@@ -1137,6 +1142,10 @@ struct emif_regs {
u32 emif_rd_wr_lvl_rmp_ctl;
u32 emif_rd_wr_lvl_ctl;
u32 emif_rd_wr_exec_thresh;
+ u32 emif_prio_class_serv_map;
+ u32 emif_connect_id_serv_1_map;
+ u32 emif_connect_id_serv_2_map;
+ u32 emif_cos_config;
};
struct lpddr2_mr_regs {