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| author | Wolfgang Denk <wd@denx.de> | 2012-07-18 10:47:03 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-07-18 10:47:03 +0200 |
| commit | 66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae (patch) | |
| tree | 946a13465467eb58f68cf8cf5e121017d380fe2a /arch/arm | |
| parent | 3a9469b5cbd467b3a7b176b4feb2073a04f294b6 (diff) | |
| parent | cf65d478ab4e0bb0247c374e6b0b40ef77eddbe8 (diff) | |
| download | u-boot-imx-66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae.zip u-boot-imx-66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae.tar.gz u-boot-imx-66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae.tar.bz2 | |
Merge branch 'next' of git://git.denx.de/u-boot-video
* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 88fb7cb..8117f4f 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -50,8 +50,6 @@ #error "CPU_TYPE not defined" #endif -#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET - #define IRAM_SIZE 0x00020000 /* 128 KB */ /* diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index e165810..5d77603 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -73,6 +73,9 @@ #define MMDC1_ARB_BASE_ADDR 0x80000000 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR +#define IPU_SOC_OFFSET 0x00200000 + /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR |