Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

27 files changed, 1342 insertions, 361 deletions

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index a0c89b7..e7839be 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -24,7 +24,7 @@
 CROSS_COMPILE ?= arm-linux-
 
 ifndef CONFIG_STANDALONE_LOAD_ADDR
-ifeq ($(SOC),omap3)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 CONFIG_STANDALONE_LOAD_ADDR = 0x80300000
 else
 CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4668b3c..7a8c2d0 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..c97e30d 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o
+COBJS-$(CONFIG_AM33XX)	+= clock_am33xx.o
+COBJS-$(CONFIG_TI814X)	+= clock_ti814x.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index e35a3e3..885fb2d 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
-		(void *)AM335X_USB0_OTG_BASE);
+		(void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
-		(void *)AM335X_USB1_OTG_BASE);
+		(void *)USB1_OTG_BASE);
 #endif
 	return 0;
 }
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index d7d98d1..afc0d92 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -1,9 +1,9 @@
 /*
- * clock.c
+ * clock_am33xx.c
  *
  * clocks for AM33XX based boards
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -42,6 +42,35 @@
 #define CPGMAC0_IDLE		0x30000
 #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
 
+#define OSC	(V_OSCK/1000000)
+
+#define MPUPLL_M	CONFIG_SYS_MPUCLK
+#define MPUPLL_N	(OSC-1)
+#define MPUPLL_M2	1
+
+/* Core PLL Fdll = 1 GHZ, */
+#define COREPLL_M	1000
+#define COREPLL_N	(OSC-1)
+
+#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
+#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
+#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
+
+/*
+ * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
+ * frequency needs to be set to 960 MHZ. Hence,
+ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
+ */
+#define PERPLL_M	960
+#define PERPLL_N	(OSC-1)
+#define PERPLL_M2	5
+
+/* DDR Freq is 266 MHZ for now */
+/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
+#define DDRPLL_M	266
+#define DDRPLL_N	(OSC-1)
+#define DDRPLL_M2	1
+
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
new file mode 100644
index 0000000..cb4210f
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -0,0 +1,406 @@
+/*
+ * clock_ti814x.c
+ *
+ * Clocks for TI814X based boards
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/* PRCM */
+#define PRCM_MOD_EN		0x2
+
+/* CLK_SRC */
+#define OSC_SRC0		0
+#define OSC_SRC1		1
+
+#define L3_OSC_SRC		OSC_SRC0
+
+#define OSC_0_FREQ		20
+
+#define DCO_HS2_MIN		500
+#define DCO_HS2_MAX		1000
+#define DCO_HS1_MIN		1000
+#define DCO_HS1_MAX		2000
+
+#define SELFREQDCO_HS2		0x00000801
+#define SELFREQDCO_HS1		0x00001001
+
+#define MPU_N			0x1
+#define MPU_M			0x3C
+#define MPU_M2			1
+#define MPU_CLKCTRL		0x1
+
+#define L3_N			19
+#define L3_M			880
+#define L3_M2			4
+#define L3_CLKCTRL		0x801
+
+#define DDR_N			19
+#define DDR_M			666
+#define DDR_M2			2
+#define DDR_CLKCTRL		0x801
+
+/* ADPLLJ register values */
+#define ADPLLJ_CLKCTRL_HS2	0x00000801 /* HS2 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_HS1	0x00001001 /* HS1 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_CLKDCOLDOEN	(1 << 29)
+#define ADPLLJ_CLKCTRL_IDLE		(1 << 23)
+#define ADPLLJ_CLKCTRL_CLKOUTEN		(1 << 20)
+#define ADPLLJ_CLKCTRL_CLKOUTLDOEN	(1 << 19)
+#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ	(1 << 17)
+#define ADPLLJ_CLKCTRL_LPMODE		(1 << 12)
+#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN	(1 << 11)
+#define ADPLLJ_CLKCTRL_REGM4XEN		(1 << 10)
+#define ADPLLJ_CLKCTRL_TINITZ		(1 << 0)
+#define ADPLLJ_CLKCTRL_CLKDCO		(ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
+					 ADPLLJ_CLKCTRL_CLKOUTEN | \
+					 ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
+					 ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
+
+#define ADPLLJ_STATUS_PHASELOCK		(1 << 10)
+#define ADPLLJ_STATUS_FREQLOCK		(1 << 9)
+#define ADPLLJ_STATUS_PHSFRQLOCK	(ADPLLJ_STATUS_PHASELOCK | \
+					 ADPLLJ_STATUS_FREQLOCK)
+#define ADPLLJ_STATUS_BYPASSACK		(1 << 8)
+#define ADPLLJ_STATUS_BYPASS		(1 << 0)
+#define ADPLLJ_STATUS_BYPASSANDACK	(ADPLLJ_STATUS_BYPASSACK | \
+					 ADPLLJ_STATUS_BYPASS)
+
+#define ADPLLJ_TENABLE_ENB		(1 << 0)
+#define ADPLLJ_TENABLEDIV_ENB		(1 << 0)
+
+#define ADPLLJ_M2NDIV_M2SHIFT		16
+
+#define MPU_PLL_BASE			(PLL_SUBSYS_BASE + 0x048)
+#define L3_PLL_BASE			(PLL_SUBSYS_BASE + 0x110)
+#define DDR_PLL_BASE			(PLL_SUBSYS_BASE + 0x290)
+
+struct ad_pll {
+	unsigned int pwrctrl;
+	unsigned int clkctrl;
+	unsigned int tenable;
+	unsigned int tenablediv;
+	unsigned int m2ndiv;
+	unsigned int mn2div;
+	unsigned int fracdiv;
+	unsigned int bwctrl;
+	unsigned int fracctrl;
+	unsigned int status;
+	unsigned int m3div;
+	unsigned int rampctrl;
+};
+
+#define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
+
+/* PRCM */
+#define CM_DEFAULT_BASE			(PRCM_BASE + 0x0500)
+
+struct cm_def {
+	unsigned int resv0[2];
+	unsigned int l3fastclkstctrl;
+	unsigned int resv1[1];
+	unsigned int pciclkstctrl;
+	unsigned int resv2[1];
+	unsigned int ducaticlkstctrl;
+	unsigned int resv3[1];
+	unsigned int emif0clkctrl;
+	unsigned int emif1clkctrl;
+	unsigned int dmmclkctrl;
+	unsigned int fwclkctrl;
+	unsigned int resv4[10];
+	unsigned int usbclkctrl;
+	unsigned int resv5[1];
+	unsigned int sataclkctrl;
+	unsigned int resv6[4];
+	unsigned int ducaticlkctrl;
+	unsigned int pciclkctrl;
+};
+
+#define CM_ALWON_BASE			(PRCM_BASE + 0x1400)
+
+struct cm_alwon {
+	unsigned int l3slowclkstctrl;
+	unsigned int ethclkstctrl;
+	unsigned int l3medclkstctrl;
+	unsigned int mmu_clkstctrl;
+	unsigned int mmucfg_clkstctrl;
+	unsigned int ocmc0clkstctrl;
+	unsigned int vcpclkstctrl;
+	unsigned int mpuclkstctrl;
+	unsigned int sysclk4clkstctrl;
+	unsigned int sysclk5clkstctrl;
+	unsigned int sysclk6clkstctrl;
+	unsigned int rtcclkstctrl;
+	unsigned int l3fastclkstctrl;
+	unsigned int resv0[67];
+	unsigned int mcasp0clkctrl;
+	unsigned int mcasp1clkctrl;
+	unsigned int mcasp2clkctrl;
+	unsigned int mcbspclkctrl;
+	unsigned int uart0clkctrl;
+	unsigned int uart1clkctrl;
+	unsigned int uart2clkctrl;
+	unsigned int gpio0clkctrl;
+	unsigned int gpio1clkctrl;
+	unsigned int i2c0clkctrl;
+	unsigned int i2c1clkctrl;
+	unsigned int mcasp345clkctrl;
+	unsigned int atlclkctrl;
+	unsigned int mlbclkctrl;
+	unsigned int pataclkctrl;
+	unsigned int resv1[1];
+	unsigned int uart3clkctrl;
+	unsigned int uart4clkctrl;
+	unsigned int uart5clkctrl;
+	unsigned int wdtimerclkctrl;
+	unsigned int spiclkctrl;
+	unsigned int mailboxclkctrl;
+	unsigned int spinboxclkctrl;
+	unsigned int mmudataclkctrl;
+	unsigned int resv2[2];
+	unsigned int mmucfgclkctrl;
+	unsigned int resv3[2];
+	unsigned int ocmc0clkctrl;
+	unsigned int vcpclkctrl;
+	unsigned int resv4[2];
+	unsigned int controlclkctrl;
+	unsigned int resv5[2];
+	unsigned int gpmcclkctrl;
+	unsigned int ethernet0clkctrl;
+	unsigned int resv6[1];
+	unsigned int mpuclkctrl;
+	unsigned int debugssclkctrl;
+	unsigned int l3clkctrl;
+	unsigned int l4hsclkctrl;
+	unsigned int l4lsclkctrl;
+	unsigned int rtcclkctrl;
+	unsigned int tpccclkctrl;
+	unsigned int tptc0clkctrl;
+	unsigned int tptc1clkctrl;
+	unsigned int tptc2clkctrl;
+	unsigned int tptc3clkctrl;
+	unsigned int resv7[4];
+	unsigned int dcan01clkctrl;
+	unsigned int mmchs0clkctrl;
+	unsigned int mmchs1clkctrl;
+	unsigned int mmchs2clkctrl;
+	unsigned int custefuseclkctrl;
+};
+
+
+const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
+const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+	/* UART0 */
+	writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
+	while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* HSMMC1 */
+	writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
+	while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
+		;
+}
+
+/*
+ * select the HS1 or HS2 for DCO Freq
+ * return : CLKCTRL
+ */
+static u32 pll_dco_freq_sel(u32 clkout_dco)
+{
+	if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
+		return SELFREQDCO_HS2;
+	else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
+		return SELFREQDCO_HS1;
+	else
+		return -1;
+}
+
+/*
+ * select the sigma delta config
+ * return: sigma delta val
+ */
+static u32 pll_sigma_delta_val(u32 clkout_dco)
+{
+	u32 sig_val = 0;
+	float frac_div;
+
+	frac_div = (float) clkout_dco / 250;
+	frac_div = frac_div + 0.90;
+	sig_val = (int)frac_div;
+	sig_val = sig_val << 24;
+
+	return sig_val;
+}
+
+/*
+ * configure individual ADPLLJ
+ */
+static void pll_config(u32 base, u32 n, u32 m, u32 m2,
+		       u32 clkctrl_val, int adpllj)
+{
+	const struct ad_pll *adpll = (struct ad_pll *)base;
+	u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
+	u32 sig_val = 0, hs_mod = 0;
+
+	m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
+	mn2val = m;
+
+	/* calculate clkout_dco */
+	clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
+
+	/* sigma delta & Hs mode selection skip for ADPLLS*/
+	if (adpllj) {
+		sig_val = pll_sigma_delta_val(clkout_dco);
+		hs_mod = pll_dco_freq_sel(clkout_dco);
+	}
+
+	/* by-pass pll */
+	read_clkctrl = readl(&adpll->clkctrl);
+	writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
+	while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
+		!= ADPLLJ_STATUS_BYPASSANDACK)
+		;
+
+	/* clear TINITZ */
+	read_clkctrl = readl(&adpll->clkctrl);
+	writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+	/*
+	 * ref_clk = 20/(n + 1);
+	 * clkout_dco = ref_clk * m;
+	 * clk_out = clkout_dco/m2;
+	*/
+	read_clkctrl = readl(&adpll->clkctrl) &
+			     ~(ADPLLJ_CLKCTRL_LPMODE |
+			     ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
+			     ADPLLJ_CLKCTRL_REGM4XEN);
+	writel(m2nval, &adpll->m2ndiv);
+	writel(mn2val, &adpll->mn2div);
+
+	/* Skip for modena(ADPLLS) */
+	if (adpllj) {
+		writel(sig_val, &adpll->fracdiv);
+		writel((read_clkctrl | hs_mod), &adpll->clkctrl);
+	}
+
+	/* Load M2, N2 dividers of ADPLL */
+	writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+	writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
+
+	/* Load M, N dividers of ADPLL */
+	writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
+	writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
+
+	/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
+	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
+	if (adpllj)
+		writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
+						&adpll->clkctrl);
+
+	/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
+	read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
+	writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
+
+	/* Wait for phase and freq lock */
+	while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
+	       ADPLLJ_STATUS_PHSFRQLOCK)
+		;
+}
+
+static void unlock_pll_control_mmr(void)
+{
+	/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
+	writel(0x1EDA4C3D, 0x481C5040);
+	writel(0x2FF1AC2B, 0x48140060);
+	writel(0xF757FDC0, 0x48140064);
+	writel(0xE2BC3A6D, 0x48140068);
+	writel(0x1EBF131D, 0x4814006c);
+	writel(0x6F361E05, 0x48140070);
+}
+
+static void mpu_pll_config(void)
+{
+	pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
+}
+
+static void l3_pll_config(void)
+{
+	u32 l3_osc_src, rd_osc_src = 0;
+
+	l3_osc_src = L3_OSC_SRC;
+	rd_osc_src = readl(OSC_SRC_CTRL);
+
+	if (OSC_SRC0 == l3_osc_src)
+		writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
+	else
+		writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
+
+	pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
+}
+
+void ddr_pll_config(unsigned int ddrpll_m)
+{
+	pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
+}
+
+void enable_emif_clocks(void) {};
+
+void enable_dmm_clocks(void)
+{
+	writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
+	writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
+	writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
+	while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
+	while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
+		;
+	while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
+		;
+	writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
+	while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
+		;
+	writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
+	while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
+		;
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void pll_init()
+{
+	unlock_pll_control_mmr();
+
+	/* Enable the control module */
+	writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+
+	mpu_pll_config();
+
+	l3_pll_config();
+
+	/* Enable the required peripherals */
+	enable_per_clocks();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 448cc40..d1e2fd3 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances
@@ -43,7 +48,7 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
 	if (regs->zq_config) {
 		/*
@@ -51,68 +56,85 @@ void config_sdram(const struct emif_regs *regs)
 		 * about 570us for a delay, which will be long enough
 		 * to configure things.
 		 */
-		writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
-		writel(regs->zq_config, &emif_reg->emif_zq_config);
+		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	}
-	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
-	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
-	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
-	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
-	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
-	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
-	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(const struct ddr_data *data, int nr)
 {
-	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
-	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
-	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
-	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
-	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
-	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
-	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
-	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
+	int i;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+		writel(data->datauserank0delay,
+			&(ddr_data_reg[nr]+i)->dt0rdelays0);
+		writel(data->datadldiff0,
+			&(ddr_data_reg[nr]+i)->dt0dldiff0);
+	}
 }
 
 void config_io_ctrl(unsigned long val)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 01e3a52..aa84e96 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,44 +44,65 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
+#ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+#endif
+
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
 
-static void config_vtp(void)
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
+static void config_vtp(int nr)
 {
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
-			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
 
 	/* Poll for READY */
-	while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
 			VTP_CTRL_READY)
 		;
 }
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs)
+		const struct emif_regs *regs, int nr)
 {
 	enable_emif_clocks();
 	ddr_pll_config(pll);
-	config_vtp();
-	config_cmd_ctrl(ctrl);
-
-	config_ddr_data(0, data);
-	config_ddr_data(1, data);
+	config_vtp(nr);
+	config_cmd_ctrl(ctrl, nr);
 
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
 	config_io_ctrl(ioctrl);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
 
 	/* Program EMIF instance */
-	config_ddr_phy(regs);
-	set_sdram_timings(regs);
-	config_sdram(regs);
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	config_sdram(regs, nr);
 }
 #endif
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index b8f54ab..b86b0de 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -83,7 +83,7 @@ void gpmc_init(void)
 	/* global settings */
 	writel(0x00000008, &gpmc_cfg->sysconfig);
 	writel(0x00000100, &gpmc_cfg->irqstatus);
-	writel(0x00000200, &gpmc_cfg->irqenable);
+	writel(0x00000100, &gpmc_cfg->irqenable);
 	writel(0x00000012, &gpmc_cfg->config);
 	/*
 	 * Disable the GPMC0 config set by ROM code
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..5fd8b47 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
 	case AM335X:
 		cpu_s = "AM335X";
 		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
 	default:
 		cpu_s = "Unknown cpu type";
 		break;
@@ -120,7 +123,7 @@ int print_cpuinfo(void)
 		sec_s = "?";
 	}
 
-	printf("AM%s-%s rev %d\n",
+	printf("%s-%s rev %d\n",
 			cpu_s, sec_s, get_cpu_rev());
 
 	/* TODO: Print ARM and DDR frequencies  */
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 0efc80d..55e82ba 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS	+= emif-common.o
 COBJS	+= vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 3581077..b933fe8 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -26,6 +26,7 @@
  * MA 02111-1307 USA
  */
 
+#include <config.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 36bea5f..507f687 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -34,6 +34,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/cpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 872ff82..ecb5901 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -3,7 +3,7 @@
  *
  * clock header
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index d748dd2..89b63d9 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -3,7 +3,7 @@
  *
  * AM33xx clock define
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,37 +19,13 @@
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
-#define OSC	(V_OSCK/1000000)
-
-/* MAIN PLL Fdll = 550 MHZ, */
-#define MPUPLL_M	550
-#define MPUPLL_N	(OSC-1)
-#define MPUPLL_M2	1
-
-/* Core PLL Fdll = 1 GHZ, */
-#define COREPLL_M	1000
-#define COREPLL_N	(OSC-1)
-
-#define COREPLL_M4	10	/* CORE_CLKOUTM4 = 200 MHZ */
-#define COREPLL_M5	8	/* CORE_CLKOUTM5 = 250 MHZ */
-#define COREPLL_M6	4	/* CORE_CLKOUTM6 = 500 MHZ */
-
-/*
- * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
- * frequency needs to be set to 960 MHZ. Hence,
- * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
- */
-#define PERPLL_M	960
-#define PERPLL_N	(OSC-1)
-#define PERPLL_M2	5
-
-/* DDR Freq is 266 MHZ for now */
-/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
-#define DDRPLL_M	266
-#define DDRPLL_N	(OSC-1)
-#define DDRPLL_M2	1
+/* MAIN PLL Fdll = 550 MHz, by default */
+#ifndef CONFIG_SYS_MPUCLK
+#define CONFIG_SYS_MPUCLK	550
+#endif
 
 extern void pll_init(void);
 extern void enable_emif_clocks(void);
+extern void enable_dmm_clocks(void);
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
 #define HS_DEVICE			0x2
 #define GP_DEVICE			0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X				0xB944
-#define DEVICE_ID			0x44E10600
+#define TI81XX				0xB81E
+#define DEVICE_ID			(CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL			0x44E00F00
-#define PRM_RSTST			0x44E00F08
+#define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET		0x01
 #define PRM_RSTST_WARM_RESET_MASK	0x232
 
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index ae43ef8..260cc34 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -28,6 +28,7 @@
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
@@ -82,6 +83,23 @@
 #define MT41J256M8HX15E_PHY_FIFO_WE		0x100
 #define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
 
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100006
+#define MT41K256M16HA125E_EMIF_TIM1		0x0888A39B
+#define MT41K256M16HA125E_EMIF_TIM2		0x26517FDA
+#define MT41K256M16HA125E_EMIF_TIM3		0x501F84EF
+#define MT41K256M16HA125E_EMIF_SDCFG		0x61C04BB2
+#define MT41K256M16HA125E_EMIF_SDREF		0x0000093B
+#define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
+#define MT41K256M16HA125E_DLL_LOCK_DIFF		0x1
+#define MT41K256M16HA125E_RATIO			0x40
+#define MT41K256M16HA125E_INVERT_CLKOUT		0x0
+#define MT41K256M16HA125E_RD_DQS		0x3C
+#define MT41K256M16HA125E_WR_DQS		0x45
+#define MT41K256M16HA125E_PHY_WR_DATA		0x7F
+#define MT41K256M16HA125E_PHY_FIFO_WE		0x9B
+#define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
+
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
 #define MT41J512M8RH125_EMIF_READ_LATENCY	0x06
 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
@@ -100,19 +118,64 @@
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs);
+void config_sdram(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs);
+void set_sdram_timings(const struct emif_regs *regs, int nr);
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs);
+void config_ddr_phy(const struct emif_regs *regs, int nr);
+
+struct ddr_cmd_regs {
+	unsigned int resv0[7];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv1[2];
+	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv2[8];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv3[2];
+	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv4[8];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv5[2];
+	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv6[3];
+};
+
+struct ddr_data_regs {
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv1[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv2[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv3;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv4;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv5[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv6[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+	unsigned int resv7[12];
+};
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
@@ -193,12 +256,12 @@ struct ddr_data {
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int data_macrono, const struct ddr_data *data);
+void config_ddr_data(const struct ddr_data *data, int nr);
 
 /**
  * This structure represents the DDR io control on AM33XX devices.
@@ -226,6 +289,6 @@ struct ddr_ctrl {
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs);
+		const struct emif_regs *regs, int nr);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 6dd3296..5a27f9c 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -3,7 +3,7 @@
  *
  * hardware specific header
  *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,10 +19,17 @@
 #ifndef __AM33XX_HARDWARE_H
 #define __AM33XX_HARDWARE_H
 
+#include <config.h>
 #include <asm/arch/omap.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/hardware_ti814x.h>
+#endif
 
-/* Module base addresses */
-#define UART0_BASE			0x44E09000
+/*
+ * Common hardware definitions
+ */
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE			0x4802C000
@@ -37,21 +44,10 @@
 /* GPIO Base address */
 #define GPIO0_BASE			0x48032000
 #define GPIO1_BASE			0x4804C000
-#define GPIO2_BASE			0x481AC000
 
 /* BCH Error Location Module */
 #define ELM_BASE			0x48080000
 
-/* Watchdog Timer */
-#define WDT_BASE			0x44E35000
-
-/* Control Module Base Address */
-#define CTRL_BASE			0x44E10000
-#define CTRL_DEVICE_BASE		0x44E10600
-
-/* PRCM Base Address */
-#define PRCM_BASE			0x44E00000
-
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE		0x4C000000
 #define EMIF4_1_CFG_BASE		0x4D000000
@@ -66,13 +62,13 @@
 #define PRM_DEVICE			0x44E00F00
 
 /* VTP Base address */
-#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
 
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
-#define DDR_PHY_BASE_ADDR		0x44E12000
-#define DDR_PHY_BASE_ADDR2		0x44E120A4
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE		UART0_BASE
@@ -84,14 +80,10 @@
 #define GPMC_BASE			0x50000000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE		0x4A100000
-#define AM335X_CPSW_MDIO_BASE		0x4A101000
-
-/* RTC base address */
-#define AM335X_RTC_BASE			0x44E3E000
+#define CPSW_BASE			0x4A100000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE		0x47401000
-#define AM335X_USB1_OTG_BASE		0x47401800
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
new file mode 100644
index 0000000..fa02f19
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -0,0 +1,54 @@
+/*
+ * hardware_am33xx.h
+ *
+ * AM33xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_AM33XX_H
+#define __AM33XX_HARDWARE_AM33XX_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44E00000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_DATA_REGS_NR		2
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
+#endif /* __AM33XX_HARDWARE_AM33XX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
new file mode 100644
index 0000000..a950ac3
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -0,0 +1,53 @@
+/*
+ * hardware_ti814x.h
+ *
+ * TI814x hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI814X_H
+#define __AM33XX_HARDWARE_TI814X_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x48020000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x481C7000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x48140000
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x48180000
+
+/* PLL Subsystem Base Address */
+#define PLL_SUBSYS_BASE			0x481C5000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48140E0C
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x47C0C400
+#define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_DATA_REGS_NR		4
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE			0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI814X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
index 33c9c83..51ba791 100644
--- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -24,4 +24,9 @@
 #define OMAP_HSMMC1_BASE		0x48060100
 #define OMAP_HSMMC2_BASE		0x481D8100
 
+#if defined(CONFIG_TI814X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#endif
+
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index 460ac1c..1c6b65f 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -1,7 +1,7 @@
 /*
  * mux.h
  *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -19,234 +19,15 @@
 #include <common.h>
 #include <asm/io.h>
 
-#define MUX_CFG(value, offset)	\
-	__raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL	(0x1 << 6)
-#define RXACTIVE	(0x1 << 5)
-#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
-#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
-#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
-#define MODE(val)	val	/* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int gpmc_ad0;
-	int gpmc_ad1;
-	int gpmc_ad2;
-	int gpmc_ad3;
-	int gpmc_ad4;
-	int gpmc_ad5;
-	int gpmc_ad6;
-	int gpmc_ad7;
-	int gpmc_ad8;
-	int gpmc_ad9;
-	int gpmc_ad10;
-	int gpmc_ad11;
-	int gpmc_ad12;
-	int gpmc_ad13;
-	int gpmc_ad14;
-	int gpmc_ad15;
-	int gpmc_a0;
-	int gpmc_a1;
-	int gpmc_a2;
-	int gpmc_a3;
-	int gpmc_a4;
-	int gpmc_a5;
-	int gpmc_a6;
-	int gpmc_a7;
-	int gpmc_a8;
-	int gpmc_a9;
-	int gpmc_a10;
-	int gpmc_a11;
-	int gpmc_wait0;
-	int gpmc_wpn;
-	int gpmc_be1n;
-	int gpmc_csn0;
-	int gpmc_csn1;
-	int gpmc_csn2;
-	int gpmc_csn3;
-	int gpmc_clk;
-	int gpmc_advn_ale;
-	int gpmc_oen_ren;
-	int gpmc_wen;
-	int gpmc_be0n_cle;
-	int lcd_data0;
-	int lcd_data1;
-	int lcd_data2;
-	int lcd_data3;
-	int lcd_data4;
-	int lcd_data5;
-	int lcd_data6;
-	int lcd_data7;
-	int lcd_data8;
-	int lcd_data9;
-	int lcd_data10;
-	int lcd_data11;
-	int lcd_data12;
-	int lcd_data13;
-	int lcd_data14;
-	int lcd_data15;
-	int lcd_vsync;
-	int lcd_hsync;
-	int lcd_pclk;
-	int lcd_ac_bias_en;
-	int mmc0_dat3;
-	int mmc0_dat2;
-	int mmc0_dat1;
-	int mmc0_dat0;
-	int mmc0_clk;
-	int mmc0_cmd;
-	int mii1_col;
-	int mii1_crs;
-	int mii1_rxerr;
-	int mii1_txen;
-	int mii1_rxdv;
-	int mii1_txd3;
-	int mii1_txd2;
-	int mii1_txd1;
-	int mii1_txd0;
-	int mii1_txclk;
-	int mii1_rxclk;
-	int mii1_rxd3;
-	int mii1_rxd2;
-	int mii1_rxd1;
-	int mii1_rxd0;
-	int rmii1_refclk;
-	int mdio_data;
-	int mdio_clk;
-	int spi0_sclk;
-	int spi0_d0;
-	int spi0_d1;
-	int spi0_cs0;
-	int spi0_cs1;
-	int ecap0_in_pwm0_out;
-	int uart0_ctsn;
-	int uart0_rtsn;
-	int uart0_rxd;
-	int uart0_txd;
-	int uart1_ctsn;
-	int uart1_rtsn;
-	int uart1_rxd;
-	int uart1_txd;
-	int i2c0_sda;
-	int i2c0_scl;
-	int mcasp0_aclkx;
-	int mcasp0_fsx;
-	int mcasp0_axr0;
-	int mcasp0_ahclkr;
-	int mcasp0_aclkr;
-	int mcasp0_fsr;
-	int mcasp0_axr1;
-	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
-	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
-	int rsvd1;
-	int tms;
-	int tdi;
-	int tdo;
-	int tck;
-	int ntrst;
-	int emu0;
-	int emu1;
-	int osc1_in;
-	int osc1_out;
-	int pmic_power_en;
-	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
-	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
-	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
-	int ddr_a0;
-	int ddr_a1;
-	int ddr_a2;
-	int ddr_a3;
-	int ddr_a4;
-	int ddr_a5;
-	int ddr_a6;
-	int ddr_a7;
-	int ddr_a8;
-	int ddr_a9;
-	int ddr_a10;
-	int ddr_a11;
-	int ddr_a12;
-	int ddr_a13;
-	int ddr_a14;
-	int ddr_a15;
-	int ddr_odt;
-	int ddr_d0;
-	int ddr_d1;
-	int ddr_d2;
-	int ddr_d3;
-	int ddr_d4;
-	int ddr_d5;
-	int ddr_d6;
-	int ddr_d7;
-	int ddr_d8;
-	int ddr_d9;
-	int ddr_d10;
-	int ddr_d11;
-	int ddr_d12;
-	int ddr_d13;
-	int ddr_d14;
-	int ddr_d15;
-	int ddr_dqm0;
-	int ddr_dqm1;
-	int ddr_dqs0;
-	int ddr_dqsn0;
-	int ddr_dqs1;
-	int ddr_dqsn1;
-	int ddr_vref;
-	int ddr_vtp;
-	int ddr_strben0;
-	int ddr_strben1;
-	int ain7;
-	int ain6;
-	int ain5;
-	int ain4;
-	int ain3;
-	int ain2;
-	int ain1;
-	int ain0;
-	int vrefp;
-	int vrefn;
-};
+#ifdef CONFIG_AM33XX
+#include <asm/arch/mux_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/mux_ti814x.h>
+#endif
 
 struct module_pin_mux {
 	short reg_offset;
-	unsigned char val;
+	unsigned int val;
 };
 
 /* Pad control register offset */
@@ -259,4 +40,4 @@ struct module_pin_mux {
  */
 void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
 
-#endif
+#endif /* endif _MUX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
new file mode 100644
index 0000000..d5cab3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
@@ -0,0 +1,247 @@
+/*
+ * mux_am33xx.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_AM33XX_H_
+#define _MUX_AM33XX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+#endif /* endif _MUX_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
new file mode 100644
index 0000000..a26e503
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
@@ -0,0 +1,311 @@
+/*
+ * mux_ti814x.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI814X_H_
+#define _MUX_TI814X_H_
+
+/* PAD Control Fields */
+#define PINCNTL_RSV_MSK	(0x3 << 18) /* Reserved bitmask */
+#define PULLUP_EN	(0x1 << 17) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 16) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+#define MUX_CFG(value, offset)				\
+{							\
+	int tmp;					\
+	tmp = __raw_readl(CTRL_BASE + offset);		\
+	tmp &= PINCNTL_RSV_MSK;				\
+	__raw_writel(tmp | value, (CTRL_BASE + offset));\
+}
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+};
+
+#endif /* endif _MUX_TI814X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 850f8a5..d28f9a8 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -28,8 +28,13 @@
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
+#ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000
+#elif defined(CONFIG_TI814X)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000
+#endif
 
 /* ROM code defines */
 /* Boot device */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index e961ce0..f60b086 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -25,8 +25,13 @@
 
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
+#ifdef CONFIG_AM33XX
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#elif defined(CONFIG_TI814X)
+#define BOOT_DEVICE_MMC1	9
+#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
+#endif
 #define BOOT_DEVICE_SPI		11
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_USBETH	68
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 97ab60d..0910a94 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -34,6 +34,8 @@ void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
 void sdelay(unsigned long);
+
+struct gpmc_cs;
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);