diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-06-24 17:41:00 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-07-10 15:29:16 +0200 |
| commit | d95b6ab87c609065e937810f04a84a16992b6f75 (patch) | |
| tree | a750660ef0f8fde05aef269508b5177920e53a20 /arch/arm | |
| parent | f5860404514aed743b6d6ca61b3b377ab751e2c6 (diff) | |
| download | u-boot-imx-d95b6ab87c609065e937810f04a84a16992b6f75.zip u-boot-imx-d95b6ab87c609065e937810f04a84a16992b6f75.tar.gz u-boot-imx-d95b6ab87c609065e937810f04a84a16992b6f75.tar.bz2 | |
mx6: clock: Do not enable sata and ipu clocks
mx6sx does not have sata nor ipu blocks, so do not handle such clocks.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index f8da94b..e1fb5ab 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -437,6 +437,7 @@ static int enable_enet_pll(uint32_t en) return 0; } +#ifndef CONFIG_MX6SX static void ungate_sata_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -445,6 +446,7 @@ static void ungate_sata_clock(void) /* Enable SATA clock. */ setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); } +#endif static void ungate_pcie_clock(void) { @@ -455,11 +457,13 @@ static void ungate_pcie_clock(void) setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); } +#ifndef CONFIG_MX6SX int enable_sata_clock(void) { ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } +#endif int enable_pcie_clock(void) { @@ -491,7 +495,9 @@ int enable_pcie_clock(void) clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); /* Party time! Ungate the clock to the PCIe. */ +#ifndef CONFIG_MX6SX ungate_sata_clock(); +#endif ungate_pcie_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | @@ -573,6 +579,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifndef CONFIG_MX6SX void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -581,6 +588,7 @@ void enable_ipu_clock(void) reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; writel(reg, &mxc_ccm->CCGR3); } +#endif /***************************************************/ U_BOOT_CMD( |