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| author | Nishanth Menon <nm@ti.com> | 2015-03-09 17:12:02 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-13 09:28:53 -0400 |
| commit | 9b4d65f918dd84a479552b86ef2cde389926738f (patch) | |
| tree | d39cc80675c8a98f672ceeec21fcd1183371dabc /arch/arm | |
| parent | 5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae (diff) | |
| download | u-boot-imx-9b4d65f918dd84a479552b86ef2cde389926738f.zip u-boot-imx-9b4d65f918dd84a479552b86ef2cde389926738f.tar.gz u-boot-imx-9b4d65f918dd84a479552b86ef2cde389926738f.tar.bz2 | |
ARM: Introduce erratum workaround for 621766
621766: Under a specific set of conditions, executing a sequence of
NEON or vfp load instructions can cause processor deadlock
Impacts: Every Cortex-A8 processors with revision lower than r2p1
Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 41fb24c..5050021 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -215,6 +215,19 @@ skip_errata_454179: skip_errata_430973: #endif +#ifdef CONFIG_ARM_ERRATA_621766 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_621766 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 5) @ Set L1NEON bit + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_621766: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) |