diff options
| author | Ye.Li <B37916@freescale.com> | 2014-09-09 10:17:00 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-09-29 10:24:07 +0200 |
| commit | 9293d7fd502ce29302fadb8b4ccb9231ec0bcc66 (patch) | |
| tree | fd8ef54e242e4c0a0607f86045a2e6c893a4728a /arch/arm | |
| parent | adca1875c8090dea9b163550d8607ccba5418819 (diff) | |
| download | u-boot-imx-9293d7fd502ce29302fadb8b4ccb9231ec0bcc66.zip u-boot-imx-9293d7fd502ce29302fadb8b4ccb9231ec0bcc66.tar.gz u-boot-imx-9293d7fd502ce29302fadb8b4ccb9231ec0bcc66.tar.bz2 | |
imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 05683a3..6352422 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -354,10 +354,10 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; - int is_6q = is_cpu_type(MXC_CPU_MX6Q); + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; u32 mask480; u32 mask528; - + u32 reg, periph1, periph2; if (is_cpu_type(MXC_CPU_MX6SX)) return; @@ -372,15 +372,23 @@ void s_init(void) ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(2) | ANATOP_PFD_CLKGATE_MASK(3); - mask528 = ANATOP_PFD_CLKGATE_MASK(0) | - ANATOP_PFD_CLKGATE_MASK(1) | + mask528 = ANATOP_PFD_CLKGATE_MASK(1) | ANATOP_PFD_CLKGATE_MASK(3); - /* - * Don't reset PFD2 on DL/S - */ - if (is_6q) + reg = readl(&ccm->cbcmr); + periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); + periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); + + /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ + if ((periph2 != 0x2) && (periph1 != 0x2)) + mask528 |= ANATOP_PFD_CLKGATE_MASK(0); + + if ((periph2 != 0x1) && (periph1 != 0x1) && + (periph2 != 0x3) && (periph1 != 0x3)) mask528 |= ANATOP_PFD_CLKGATE_MASK(2); + writel(mask480, &anatop->pfd_480_set); writel(mask528, &anatop->pfd_528_set); writel(mask480, &anatop->pfd_480_clr); |