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| author | Tom Rini <trini@ti.com> | 2012-10-30 22:23:28 -0700 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-30 22:23:28 -0700 |
| commit | 57f588be60eac8135cdfb366237fbf6e6dc2d316 (patch) | |
| tree | e57ea33a2786f4d3db452a90e626c12c5c5a2278 /arch/arm | |
| parent | 9cd7b4cdca2500608b218fb4de215eddd8e66111 (diff) | |
| download | u-boot-imx-57f588be60eac8135cdfb366237fbf6e6dc2d316.zip u-boot-imx-57f588be60eac8135cdfb366237fbf6e6dc2d316.tar.gz u-boot-imx-57f588be60eac8135cdfb366237fbf6e6dc2d316.tar.bz2 | |
omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF
When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings
currently. Re-order functions so that we don't have that anymore.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/board.c | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9cee1d9..f3cd81a 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; static void omap3_setup_aux_cr(void); +#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); +#endif static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - static void omap3_setup_aux_cr(void) { /* Workaround for Cortex-A8 errata: #454179 #430973 @@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void) } #ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) { |