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authorAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>2016-05-17 16:49:01 +0530
committerMichal Simek <michal.simek@xilinx.com>2016-11-15 15:30:40 +0100
commitdb6c62e1b945364295812c7be46ea1a630f9bcd3 (patch)
treea232d67ad6acba5bfe463b0bbb9e1dd57bc474e7 /arch/arm
parent571f53179656bdb31c25497f33dcd6c37b5585fc (diff)
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ARM64: zynqmp: Add device tree properties for ZynqMP GT core
This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/dts/zynqmp.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b796c34..edfa03a 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -688,6 +688,29 @@
interrupt-names = "alarm", "sec";
};
+ serdes: zynqmp_phy@fd400000 {
+ compatible = "xlnx,zynqmp-psgtr";
+ status = "disabled";
+ reg = <0x0 0xfd400000 0x40000>,
+ <0x0 0xfd3d0000 0x1000>,
+ <0x0 0xfd1a0000 0x1000>,
+ <0x0 0xff5e0000 0x1000>;
+ reg-names = "serdes", "siou", "fpd", "lpd";
+ xlnx,tx_termination_fix;
+ lane0: lane0 {
+ #phy-cells = <4>;
+ };
+ lane1: lane1 {
+ #phy-cells = <4>;
+ };
+ lane2: lane2 {
+ #phy-cells = <4>;
+ };
+ lane3: lane3 {
+ #phy-cells = <4>;
+ };
+ };
+
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";