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authorStefan Agner <stefan.agner@toradex.com>2016-08-14 21:33:00 -0700
committerTom Rini <trini@konsulko.com>2016-08-26 17:04:56 -0400
commitc5b3cabf4a2f78b126a7da92c20b781a52d5307f (patch)
treedec0fdd2a500c7cd5249cd3c2a4eb46444fd0569 /arch/arm
parente009bfa4f980c3a94a00b3a379f3b4e377b1c880 (diff)
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arm: cache: add support for LPAE for region D$ behavior
Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/lib/cache-cp15.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3..3aabda1 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,7 +61,11 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
+#ifdef CONFIG_ARMV7_LPAE
+ u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;