diff options
author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-08-02 19:03:27 +0800 |
---|---|---|
committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:07:13 -0700 |
commit | b392a6d4b05b7409283cd75b4ac6bd12018d187a (patch) | |
tree | 272b0b5b8780f23ed8fc102d09c97d94c9dbe7e6 /arch/arm | |
parent | 664b6520582fcea7e150f57258c7a63627837318 (diff) | |
download | u-boot-imx-b392a6d4b05b7409283cd75b4ac6bd12018d187a.zip u-boot-imx-b392a6d4b05b7409283cd75b4ac6bd12018d187a.tar.gz u-boot-imx-b392a6d4b05b7409283cd75b4ac6bd12018d187a.tar.bz2 |
fsl-layerscape: Add workaround for PCIe erratum A010315
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/armv7/ls102xa/soc.c | 14 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 4 |
6 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 4c93ab7..31f00cb 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -7,6 +7,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/io.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/immap_ls102xa.h> #include <asm/arch/ls102xa_soc.h> #include <asm/arch/ls102xa_stream_id.h> @@ -59,6 +60,19 @@ unsigned int get_soc_major_rev(void) return major; } +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE2; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2b39a02..43c4aa5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -8,11 +8,14 @@ #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> +#include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include <fsl_csu.h> +#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr_sdram.h> #include <fsl_ddr.h> @@ -301,6 +304,19 @@ void erratum_a008850_post(void) #endif } +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void) +{ + int i; + + for (i = PCIE1; i <= PCIE4; i++) + if (!is_serdes_configured(i)) { + debug("PCIe%d: disabled all R/W permission!\n", i); + set_pcie_ns_access(i, 0); + } +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 5279981..9ccdcfa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -165,6 +165,8 @@ #define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SRDS_1 + +#define CONFIG_SYS_FSL_ERRATUM_A010315 /* SoC related */ #ifdef CONFIG_LS1043A #define CONFIG_MAX_CPUS 4 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8d4a7ad..4512732 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -100,6 +100,10 @@ void cpu_name(char *name); void erratum_a009635(void); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + bool soc_has_dp_ddr(void); bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 56d8f32..b0bf92e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -129,6 +129,7 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 #define CONFIG_SYS_FSL_ERRATUM_A009663 +#define CONFIG_SYS_FSL_ERRATUM_A010315 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index a354684..9c91354 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -11,4 +11,8 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); int ls102xa_smmu_stream_id_init(void); +#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 +void erratum_a010315(void); +#endif + #endif /* __FSL_LS102XA_SOC_H */ |