summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
authorArun Mankuzhi <arun.m@samsung.com>2012-11-30 13:01:14 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-01-10 22:21:27 +0100
commit44df5e8d30a276985b40bb32a69584f5a7fac9a0 (patch)
tree33c840cacf79d611780e143c891c318f6f87e925 /arch/arm
parent612404c28a64a6df300642a1550a65dcc8e01f82 (diff)
downloadu-boot-imx-44df5e8d30a276985b40bb32a69584f5a7fac9a0.zip
u-boot-imx-44df5e8d30a276985b40bb32a69584f5a7fac9a0.tar.gz
u-boot-imx-44df5e8d30a276985b40bb32a69584f5a7fac9a0.tar.bz2
arm: move flush_dcache_all() to just before disable cache
In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/lib/cache-cp15.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 6edf815..1cab27c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit)
return;
/* if disabling data cache, disable mmu too */
cache_bit |= CR_M;
- flush_dcache_all();
}
+ reg = get_cr();
+ cp_delay();
+ if (cache_bit == (CR_C | CR_M))
+ flush_dcache_all();
set_cr(reg & ~cache_bit);
}
#endif