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author | Tom Rini <trini@konsulko.com> | 2016-04-06 14:17:22 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-04-06 14:17:22 -0400 |
commit | 43d3fb5c0609a76409e7859a2a5800670c7b5bd2 (patch) | |
tree | 562ebcc0e6a22077140b10efce77f44340b819ac /arch/arm | |
parent | 46a16bd895144617575c788d9c2554aeef76ac44 (diff) | |
parent | 3c1d218a1d3048fb576677c47eab43049d0b7778 (diff) | |
download | u-boot-imx-43d3fb5c0609a76409e7859a2a5800670c7b5bd2.zip u-boot-imx-43d3fb5c0609a76409e7859a2a5800670c7b5bd2.tar.gz u-boot-imx-43d3fb5c0609a76409e7859a2a5800670c7b5bd2.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/ns_access.h | 6 | ||||
-rw-r--r-- | arch/arm/include/asm/fsl_secure_boot.h | 12 |
12 files changed, 62 insertions, 35 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index cce7405..5f86ef9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -25,10 +25,6 @@ ifneq ($(CONFIG_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif -ifneq ($(CONFIG_LS2085A),) -obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o -endif - ifneq ($(CONFIG_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 4b9e209..d939900 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -538,12 +538,12 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type, rcw; + u32 type, rcw, svr = gur_in32(&gur->svr); puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); + printf(" %s (0x%x)\n", buf, svr); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); get_sys_info(&sysinfo); puts("Clock Configuration:"); @@ -564,7 +564,10 @@ int print_cpuinfo(void) printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); #endif #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); + if (soc_has_dp_ddr()) { + printf(" DP-DDR: %-4s MT/s", + strmhz(buf, sysinfo.freq_ddrbus2)); + } #endif puts("\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 81cf470..d580a43 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -97,9 +97,13 @@ void get_sys_info(struct sys_info *sys_info) FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> + if (soc_has_dp_ddr()) { + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; + } else { + sys_info->freq_ddrbus2 = 0; + } #endif for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 9c69ed1..04831ca 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -20,7 +20,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_FSL_LSCH3 /* Set Wuo bit for RN-I 20 */ -#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) +#ifdef CONFIG_LS2080A ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a76447e..0cb0100 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -18,7 +18,31 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +bool soc_has_dp_ddr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + /* LS2085A has DP_DDR */ + if (SVR_SOC_VER(svr) == SVR_LS2085) + return true; + + return false; +} + +bool soc_has_aiop(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); + + /* LS2085A has AIOP */ + if (SVR_SOC_VER(svr) == SVR_LS2085) + return true; + + return false; +} + +#ifdef CONFIG_LS2080A /* * This erratum requires setting a value to eddrtqcr1 to * optimal the DDR performance. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index f434c44..c1229c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC @@ -54,7 +54,7 @@ void board_init_f(ulong dummy) #endif board_early_init_f(); timer_init(); -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A env_init(); #endif get_clocks(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ceefe43..10d17b2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -23,16 +23,11 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 2 -#endif -#ifdef CONFIG_LS2085A #define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR -#endif +#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index f75faa6..702b9fa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -157,9 +157,11 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif }; @@ -204,7 +206,7 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -245,7 +247,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -256,7 +259,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif }; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index d1fbde7..f71c2c1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A enum srds_prtcl { NONE = 0, PCIE1, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 56989e1..831d817 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -94,4 +94,7 @@ void cpu_name(char *name); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif + +bool soc_has_dp_ddr(void); +bool soc_has_aiop(void); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h index a921fb6..44acfd2 100644 --- a/arch/arm/include/asm/arch-ls102xa/ns_access.h +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -82,12 +82,12 @@ enum csu_cslx_ind { CSU_CSLX_FTM5, CSU_CSLX_FTM8, CSU_CSLX_FTM7, - CSU_CSLX_COP_DCSR, CSU_CSLX_EPU, - CSU_CSLX_GDI, + CSU_CSLX_COP_DCSR, CSU_CSLX_DDI, + CSU_CSLX_GDI, CSU_CSLX_RESERVED1, - CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_USB3_PHY = 116, CSU_CSLX_RESERVED2, CSU_CSLX_MAX, }; diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d576f2e..53cd755 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -44,15 +44,14 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit - * Similiarly for LS2080 and LS2085 + * Similiarly for LS2080 */ #define CONFIG_ESBC_ADDR_64BIT #endif -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ @@ -66,12 +65,11 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) ||\ - defined(CONFIG_LS2085A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR and DDR memory map */ -#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#ifdef CONFIG_LS2080A #define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 #define CONFIG_BS_ADDR_FLASH 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 |