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authorShengzhou Liu <Shengzhou.Liu@nxp.com>2016-11-11 18:11:05 +0800
committerYork Sun <york.sun@nxp.com>2016-11-21 09:20:32 -0800
commit40836e215a06d435333422b2c64fa1c01f0c4f82 (patch)
treea41521e70f92eff86fcc647f2ba9090180d317b5 /arch/arm
parentc3aa1df28d0938259b44af24c15d50e126a1fbbc (diff)
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armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..5a4dd39 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -50,16 +50,16 @@ bool soc_has_aiop(void)
return false;
}
-#ifdef CONFIG_LS2080A
+#if defined(CONFIG_FSL_LSCH3)
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
*/
static void erratum_a008336(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
@@ -79,9 +79,9 @@ static void erratum_a008336(void)
*/
static void erratum_a008514(void)
{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
@@ -176,6 +176,7 @@ static void erratum_a009203(void)
#endif
#endif
}
+
void bypass_smmu(void)
{
u32 val;