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authorRuss Dill <Russ.Dill@ti.com>2016-07-21 04:28:32 -0700
committerTom Rini <trini@konsulko.com>2016-07-25 12:00:06 -0400
commit335b4e53c9c5310c36f5178d2f66a13c4b1c8592 (patch)
tree139507bd5709732c4c048bedaf6c1806f1cbaf22 /arch/arm
parent3325b06556b78a2afdaaa781765b505f7d1f8ae4 (diff)
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ARM: am33xx: Always inhibit init/refresh during DDR phy init
A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv7/am33xx/ddr.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ef1fc4d..6acf30c 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -292,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
- * Disable initialization and refreshes for now until we
- * finish programming EMIF regs.
- * Also set time between rising edge of DDR_RESET to rising
- * edge of DDR_CKE to > 500us per memory spec.
+ * Disable initialization and refreshes for now until we finish
+ * programming EMIF regs and set time between rising edge of
+ * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
+ * We currently hardcode a value based on a max expected frequency
+ * of 400MHz.
*/
-#ifndef CONFIG_AM43XX
- setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
- EMIF_REG_INITREF_DIS_MASK);
-#endif
- if (regs->zq_config)
- /* Set time between rising edge of DDR_RESET to rising
- * edge of DDR_CKE to > 500us per memory spec. */
- writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
+ writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
+ &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);