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author | Simon Glass <sjg@chromium.org> | 2016-11-13 14:22:14 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2016-11-25 17:59:31 -0700 |
commit | 20b13e8d7ef1b5ac93e4f1c0addae126b05eaf90 (patch) | |
tree | 206a2982ff799487f1cbef07ecfd8d30ea07140a /arch/arm | |
parent | 3a8a42d9550cf6779495037ce19c5357eed5ff88 (diff) | |
download | u-boot-imx-20b13e8d7ef1b5ac93e4f1c0addae126b05eaf90.zip u-boot-imx-20b13e8d7ef1b5ac93e4f1c0addae126b05eaf90.tar.gz u-boot-imx-20b13e8d7ef1b5ac93e4f1c0addae126b05eaf90.tar.bz2 |
rockchip: veyron: Adjust ARM clock after relocation
Update board_init() to increase the ARM clock to the maximum speed on
veyron boards. This makes quite a large difference in performance. With
this change, speed goes from about 750 DMIPS to 2720 DMIPs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-rockchip/rk3288-board.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index baf9522..bca6075 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -16,6 +16,8 @@ #include <asm/arch/boot_mode.h> #include <asm/gpio.h> #include <dm/pinctrl.h> +#include <dt-bindings/clock/rk3288-cru.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,6 +58,39 @@ int board_late_init(void) return rk_board_late_init(); } +#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +static int veyron_init(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = regulator_get_by_platname("vdd_arm", &dev); + if (ret) + return ret; + + /* Slowly raise to max CPU voltage to prevent overshoot */ + ret = regulator_set_value(dev, 1200000); + if (ret) + return ret; + udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ + ret = regulator_set_value(dev, 1400000); + if (ret) + return ret; + udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ + + ret = rockchip_get_clk(&clk.dev); + if (ret) + return ret; + clk.id = PLL_APLL; + ret = clk_set_rate(&clk, 1800000000); + if (IS_ERR_VALUE(ret)) + return ret; + + return 0; +} +#endif + int board_init(void) { #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM @@ -87,6 +122,15 @@ err: return -1; #else + int ret; + + /* We do some SoC one time setting here */ + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { + ret = veyron_init(); + if (ret) + return ret; + } + return 0; #endif } |