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| author | York Sun <york.sun@nxp.com> | 2016-08-03 12:33:00 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:07:19 -0700 |
| commit | b63a9506296b10b9730c3ff4a0e9611f6f98e7db (patch) | |
| tree | 15cae8f7890f62c2a3e80aebbe957b85e2de56b9 /arch/arm | |
| parent | b392a6d4b05b7409283cd75b4ac6bd12018d187a (diff) | |
| download | u-boot-imx-b63a9506296b10b9730c3ff4a0e9611f6f98e7db.zip u-boot-imx-b63a9506296b10b9730c3ff4a0e9611f6f98e7db.tar.gz u-boot-imx-b63a9506296b10b9730c3ff4a0e9611f6f98e7db.tar.bz2 | |
armv8: ls2080a: Remove debug server support
Debug server feature has been dropped from roadmap.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 |
2 files changed, 0 insertions, 14 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index e12b773..5fbd848 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -18,7 +18,6 @@ #include <asm/arch/mp.h> #endif #include <fm_eth.h> -#include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -457,10 +456,6 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) #ifdef CONFIG_SYS_MEM_TOP_HIDE #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function #endif -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - ram_top -= debug_server_get_dram_block_size(); -#endif /* Carve the MC private DRAM block from the end of DRAM */ #ifdef CONFIG_FSL_MC_ENET diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 93e26c1..7acba27 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,15 +33,6 @@ #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) -/* SP (Cortex-A5) related */ -#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000) -#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR) -#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \ - (CONFIG_SYS_FSL_SP_ADDR + 0x0008) -#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \ - (CONFIG_SYS_FSL_SP_ADDR + 0x1000) - #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL |