ARM: zynq: DT: Update zc770 dtses

Platform DTSes are missing content needed for platform to be able to use
OF binding and DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

3 files changed, 176 insertions, 12 deletions

diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts
index bf107e3..da3a182 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -1,7 +1,7 @@
 /*
  * Xilinx ZC770 XM010 board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,20 +9,85 @@
 #include "zynq-7000.dtsi"
 
 / {
-	model = "Zynq ZC770 XM010 Board";
 	compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
 
 	aliases {
+		ethernet0 = &gem0;
+		i2c0 = &i2c0;
 		serial0 = &uart1;
-		spi1 = &spi1;
+		spi0 = &spi1;
 	};
 
-	memory {
+	chosen {
+		bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+		linux,stdout-path = &uart1;
+		stdout-path = &uart1;
+	};
+
+	memory@0 {
 		device_type = "memory";
-		reg = <0 0x40000000>;
+		reg = <0x0 0x40000000>;
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
 &spi1 {
 	status = "okay";
+	num-cs = <4>;
+	is-decoded-cs = <0>;
+	flash@0 {
+		compatible = "sst25wf080";
+		reg = <1>;
+		spi-max-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@test {
+			label = "spi-flash";
+			reg = <0x0 0x100000>;
+		};
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@7 {
+		reg = <7>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	m24c02_eeprom@52 {
+		compatible = "at,24c02";
+		reg = <0x52>;
+	};
+
+};
+
+&sdhci0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
 };
diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts
index 127a661..f8cc503 100644
--- a/arch/arm/dts/zynq-zc770-xm012.dts
+++ b/arch/arm/dts/zynq-zc770-xm012.dts
@@ -1,7 +1,7 @@
 /*
  * Xilinx ZC770 XM012 board DTS
  *
- * Copyright (C) 2013 Xilinx, Inc.
+ * Copyright (C) 2013 - 2015 Xilinx, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,15 +9,58 @@
 #include "zynq-7000.dtsi"
 
 / {
-	model = "Zynq ZC770 XM012 Board";
 	compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
 
 	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 		serial0 = &uart1;
+		spi0 = &spi1;
 	};
 
-	memory {
+	chosen {
+		bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+		linux,stdout-path = &uart1;
+		stdout-path = &uart1;
+	};
+
+	memory@0 {
 		device_type = "memory";
-		reg = <0 0x40000000>;
+		reg = <0x0 0x40000000>;
+	};
+};
+
+&spi1 {
+	status = "okay";
+	num-cs = <4>;
+	is-decoded-cs = <0>;
+};
+
+&can1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	m24c02_eeprom@52 {
+		compatible = "at,24c02";
+		reg = <0x52>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	m24c02_eeprom@52 {
+		compatible = "at,24c02";
+		reg = <0x52>;
 	};
 };
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts
index c61c7e7..436a8cd 100644
--- a/arch/arm/dts/zynq-zc770-xm013.dts
+++ b/arch/arm/dts/zynq-zc770-xm013.dts
@@ -9,15 +9,71 @@
 #include "zynq-7000.dtsi"
 
 / {
-	model = "Zynq ZC770 XM013 Board";
 	compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+	model = "Xilinx Zynq";
 
 	aliases {
+		ethernet0 = &gem1;
+		i2c0 = &i2c1;
 		serial0 = &uart0;
+		spi0 = &spi0;
 	};
 
-	memory {
+	chosen {
+		bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+		linux,stdout-path = &uart0;
+		stdout-path = &uart0;
+	};
+
+	memory@0 {
 		device_type = "memory";
-		reg = <0 0x40000000>;
+		reg = <0x0 0x40000000>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	num-cs = <4>;
+	is-decoded-cs = <0>;
+	eeprom: at25@0 {
+		at25,byte-len = <8192>;
+		at25,addr-mode = <2>;
+		at25,page-size = <32>;
+
+		compatible = "atmel,at25";
+		reg = <2>;
+		spi-max-frequency = <1000000>;
+	};
+};
+
+&can1 {
+	status = "okay";
+};
+
+&gem1 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	ethernet_phy: ethernet-phy@7 {
+		reg = <7>;
 	};
 };
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	si570: clock-generator@55 {
+		#clock-cells = <0>;
+		compatible = "silabs,si570";
+		temperature-stability = <50>;
+		reg = <0x55>;
+		factory-fout = <156250000>;
+		clock-frequency = <148500000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};