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| author | Ye Li <ye.li@nxp.com> | 2016-04-13 10:00:56 +0800 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2016-04-13 12:57:42 +0800 |
| commit | f965b951ad6ea362c93d52f5eeda97119cfbff62 (patch) | |
| tree | 64f3455ea2adce5c8b5b332f101d01f8c4a2256a /arch/arm | |
| parent | 194b587b89a2945e8740b29c1ef531fc5e8eb016 (diff) | |
| download | u-boot-imx-f965b951ad6ea362c93d52f5eeda97119cfbff62.zip u-boot-imx-f965b951ad6ea362c93d52f5eeda97119cfbff62.tar.gz u-boot-imx-f965b951ad6ea362c93d52f5eeda97119cfbff62.tar.bz2 | |
MLK-12616-9 mx6ull: Update memory map address
Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5154e0c15965019602a7c128abe00d58b6e26ff1)
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index d09ec47..4ed7b37 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -170,7 +170,11 @@ #endif #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #if defined(CONFIG_MX6UL) +#if defined(CONFIG_MX6ULL) +#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#else #define UART8_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#endif #define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) @@ -231,6 +235,7 @@ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #elif CONFIG_MX6SX #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) @@ -250,8 +255,8 @@ #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#endif #define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#endif #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) @@ -315,6 +320,7 @@ #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #endif #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #else @@ -378,6 +384,14 @@ #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#elif defined(CONFIG_MX6ULL) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #endif /* Only for i.MX6SX */ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) @@ -401,7 +415,9 @@ #define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) #define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ - MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) + MX6UL_LCDIF1_BASE_ADDR : \ + ((is_cpu_type(MXC_CPU_MX6ULL)) ? \ + MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) #define UART6_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) |